From 39a8a2645470e22073d1da41fb1ee9dbc35364e6 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 3 Aug 2025 01:32:44 +0530
Subject: [PATCH 01/73] feat: added the skeleton structure of the x86 module

---
 crates/intrinsic-test/Cargo.toml            |  2 +
 crates/intrinsic-test/src/main.rs           |  2 +
 crates/intrinsic-test/src/x86/intrinsic.rs  | 43 ++++++++++++++++++++
 crates/intrinsic-test/src/x86/mod.rs        | 31 ++++++++++++++
 crates/intrinsic-test/src/x86/types.rs      | 37 +++++++++++++++++
 crates/intrinsic-test/src/x86/xml_parser.rs | 45 +++++++++++++++++++++
 6 files changed, 160 insertions(+)
 create mode 100644 crates/intrinsic-test/src/x86/intrinsic.rs
 create mode 100644 crates/intrinsic-test/src/x86/mod.rs
 create mode 100644 crates/intrinsic-test/src/x86/types.rs
 create mode 100644 crates/intrinsic-test/src/x86/xml_parser.rs

diff --git a/crates/intrinsic-test/Cargo.toml b/crates/intrinsic-test/Cargo.toml
index fbbf90e140..df4f7fe706 100644
--- a/crates/intrinsic-test/Cargo.toml
+++ b/crates/intrinsic-test/Cargo.toml
@@ -19,3 +19,5 @@ pretty_env_logger = "0.5.0"
 rayon = "1.5.0"
 diff = "0.1.12"
 itertools = "0.14.0"
+quick-xml = { version = "0.37.5", features = ["serialize", "overlapped-lists"] }
+serde-xml-rs = "0.8.0"
diff --git a/crates/intrinsic-test/src/main.rs b/crates/intrinsic-test/src/main.rs
index 44d7aafd82..d780e35160 100644
--- a/crates/intrinsic-test/src/main.rs
+++ b/crates/intrinsic-test/src/main.rs
@@ -3,10 +3,12 @@ extern crate log;
 
 mod arm;
 mod common;
+mod x86;
 
 use arm::ArmArchitectureTest;
 use common::SupportedArchitectureTest;
 use common::cli::{Cli, ProcessedCli};
+use x86::X86ArchitectureTest;
 
 fn main() {
     pretty_env_logger::init();
diff --git a/crates/intrinsic-test/src/x86/intrinsic.rs b/crates/intrinsic-test/src/x86/intrinsic.rs
new file mode 100644
index 0000000000..27eca89406
--- /dev/null
+++ b/crates/intrinsic-test/src/x86/intrinsic.rs
@@ -0,0 +1,43 @@
+use crate::common::argument::ArgumentList;
+use crate::common::indentation::Indentation;
+use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
+use crate::common::intrinsic_helpers::IntrinsicType;
+use std::ops::{Deref, DerefMut};
+
+#[derive(Debug, Clone, PartialEq)]
+pub struct X86IntrinsicType(pub IntrinsicType);
+
+impl Deref for X86IntrinsicType {
+    type Target = IntrinsicType;
+
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+
+impl DerefMut for X86IntrinsicType {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+
+impl IntrinsicDefinition<X86IntrinsicType> for Intrinsic<X86IntrinsicType> {
+    fn arguments(&self) -> ArgumentList<X86IntrinsicType> {
+        self.arguments.clone()
+    }
+
+    fn results(&self) -> X86IntrinsicType {
+        self.results.clone()
+    }
+
+    fn name(&self) -> String {
+        self.name.clone()
+    }
+
+    /// Generates a std::cout for the intrinsics results that will match the
+    /// rust debug output format for the return type. The generated line assumes
+    /// there is an int i in scope which is the current pass number.
+    fn print_result_c(&self, _indentation: Indentation, _additional: &str) -> String {
+        todo!("print_result_c in Intrinsic<X86IntrinsicType> needs to be implemented!");
+    }
+}
\ No newline at end of file
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
new file mode 100644
index 0000000000..84499b5c4b
--- /dev/null
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -0,0 +1,31 @@
+mod intrinsic;
+mod types;
+mod xml_parser;
+
+use crate::common::SupportedArchitectureTest;
+use crate::common::cli::ProcessedCli;
+use crate::common::intrinsic::Intrinsic;
+use intrinsic::X86IntrinsicType;
+
+pub struct X86ArchitectureTest {
+    intrinsics: Vec<Intrinsic<X86IntrinsicType>>,
+    cli_options: ProcessedCli,
+}
+
+impl SupportedArchitectureTest for X86ArchitectureTest {
+    fn create(cli_options: ProcessedCli) -> Box<Self> {
+        todo!("create in X86ArchitectureTest is not implemented")
+    }
+
+    fn build_c_file(&self) -> bool {
+        todo!("build_c_file in X86ArchitectureTest is not implemented")
+    }
+
+    fn build_rust_file(&self) -> bool {
+        todo!("build_rust_file in X86ArchitectureTest is not implemented")
+    }
+
+    fn compare_outputs(&self) -> bool {
+        todo!("compare_outputs in X86ArchitectureTest is not implemented")
+    }
+}
\ No newline at end of file
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
new file mode 100644
index 0000000000..3dd205c9cb
--- /dev/null
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -0,0 +1,37 @@
+use super::intrinsic::X86IntrinsicType;
+use crate::common::cli::Language;
+use crate::common::intrinsic_helpers::IntrinsicTypeDefinition;
+use crate::x86::xml_parser::Parameter;
+
+impl IntrinsicTypeDefinition for X86IntrinsicType {
+    /// Gets a string containing the type in C format.
+    /// This function assumes that this value is present in the metadata hashmap.
+    fn c_type(&self) -> String {
+        todo!("c_type from IntrinsicTypeDefinition is not defined!")
+    }
+
+    fn c_single_vector_type(&self) -> String {
+        // matches __m128, __m256 and similar types
+        todo!("c_type from IntrinsicTypeDefinition is not defined!")
+    }
+
+    /// Determines the load function for this type.
+    fn get_load_function(&self, _language: Language) -> String {
+        todo!("get_load_function from IntrinsicTypeDefinition is not defined!")
+    }
+
+    /// Determines the get lane function for this type.
+    fn get_lane_function(&self) -> String {
+        todo!("get_lane_function for X86IntrinsicType needs to be implemented!");
+    }
+
+    fn from_c(s: &str, target: &str) -> Result<Self, String> {
+        todo!("from_c from IntrinsicTypeDefinition is not defined!")
+    }
+}
+
+impl X86IntrinsicType {
+    pub fn from_param(param: &Parameter) -> Result<Self, String> {
+        todo!("from_param from X86IntrinsicType is not defined!")
+    }
+}
\ No newline at end of file
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
new file mode 100644
index 0000000000..a6b4eb8382
--- /dev/null
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -0,0 +1,45 @@
+use serde::{Deserialize, Deserializer};
+
+
+// Custom deserializer function to convert strings to u32
+fn string_to_u32<'de, D>(deserializer: D) -> Result<u32, D::Error>
+where
+    D: Deserializer<'de>,
+{
+    let s = String::deserialize(deserializer)?;
+    return s.as_str().parse::<u32>().or(Ok(0u32));
+}
+
+#[derive(Deserialize)]
+struct Data {
+    #[serde(rename = "intrinsic", default)]
+    intrinsics: Vec<XMLIntrinsic>,
+}
+
+#[derive(Deserialize)]
+struct XMLIntrinsic {
+    #[serde(rename = "return")]
+    return_data: Parameter,
+    #[serde(rename = "@name")]
+    name: String,
+    // #[serde(rename = "@tech")]
+    // tech: String,
+    #[serde(rename = "CPUID", default)]
+    cpuid: Vec<String>,
+    #[serde(rename = "parameter", default)]
+    parameters: Vec<Parameter>,
+}
+
+#[derive(Deserialize)]
+pub struct Parameter {
+    #[serde(rename = "@varname")]
+    pub var_name: String,
+    #[serde(rename = "@type")]
+    pub type_data: String,
+    #[serde(rename = "@etype", default)]
+    pub etype: String,
+    #[serde(rename = "@memwidth", default, deserialize_with = "string_to_u32")]
+    pub memwidth: u32,
+    #[serde(rename = "@immtype", default)]
+    pub imm_type: String,
+}

From acf67c2a2b0b4d6dc559b7c15299e93ce3c6d59e Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 3 Aug 2025 01:35:52 +0530
Subject: [PATCH 02/73] feat: added the XML intrinsic parser for x86

---
 crates/intrinsic-test/src/x86/constraint.rs | 20 ++++++
 crates/intrinsic-test/src/x86/mod.rs        |  1 +
 crates/intrinsic-test/src/x86/xml_parser.rs | 70 +++++++++++++++++++++
 3 files changed, 91 insertions(+)
 create mode 100644 crates/intrinsic-test/src/x86/constraint.rs

diff --git a/crates/intrinsic-test/src/x86/constraint.rs b/crates/intrinsic-test/src/x86/constraint.rs
new file mode 100644
index 0000000000..321ee89b6c
--- /dev/null
+++ b/crates/intrinsic-test/src/x86/constraint.rs
@@ -0,0 +1,20 @@
+use crate::common::constraint::Constraint;
+
+pub fn map_constraints(imm_type: &String) -> Option<Constraint> {
+    match imm_type.as_str() {
+        "_MM_FROUND" => Some(Constraint::Range(0..4)),
+        "_MM_INDEX_SCALE" => Some(Constraint::Set(vec![1, 2, 4, 8])),
+        "_MM_CMPINT" => Some(Constraint::Range(0..8)),
+        "_MM_REDUCE" => Some(Constraint::Range(0..8)),
+        "_MM_FROUND_SAE" => Some(Constraint::Range(0..8)),
+        "_MM_MANTISSA_NORM" => Some(Constraint::Range(0..4)),
+        "_MM_MANTISSA_NORM_ENUM" => Some(Constraint::Range(0..4)),
+        "_MM_MANTISSA_SIGN" => Some(Constraint::Range(0..3)),
+        "_MM_PERM" => Some(Constraint::Range(0..256)),
+        "_MM_PERM_ENUM" => Some(Constraint::Range(0..256)),
+        "_MM_CMPINT_ENUM" => Some(Constraint::Range(0..8)),
+        "_MM_ROUND_MODE" => Some(Constraint::Set(vec![0, 0x2000, 0x4000, 0x6000])),
+        "_CMP_" => Some(Constraint::Range(0..32)),
+        _ => None,
+    }
+}
\ No newline at end of file
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 84499b5c4b..ac613643bd 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -1,3 +1,4 @@
+mod constraint;
 mod intrinsic;
 mod types;
 mod xml_parser;
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index a6b4eb8382..55bc33ca7c 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -1,5 +1,12 @@
+use crate::common::argument::{Argument, ArgumentList};
+use crate::common::intrinsic::Intrinsic;
+use crate::common::intrinsic_helpers::TypeKind;
+use crate::x86::constraint::map_constraints;
+
 use serde::{Deserialize, Deserializer};
+use std::path::Path;
 
+use super::intrinsic::X86IntrinsicType;
 
 // Custom deserializer function to convert strings to u32
 fn string_to_u32<'de, D>(deserializer: D) -> Result<u32, D::Error>
@@ -43,3 +50,66 @@ pub struct Parameter {
     #[serde(rename = "@immtype", default)]
     pub imm_type: String,
 }
+
+pub fn get_xml_intrinsics(
+    filename: &Path,
+) -> Result<Vec<Intrinsic<X86IntrinsicType>>, Box<dyn std::error::Error>> {
+    let file = std::fs::File::open(filename)?;
+    let reader = std::io::BufReader::new(file);
+    let data: Data =
+        quick_xml::de::from_reader(reader).expect("failed to deserialize the source XML file");
+
+    let parsed_intrinsics: Vec<Intrinsic<X86IntrinsicType>> = data
+        .intrinsics
+        .into_iter()
+        .filter_map(|intr| {
+            // Some(xml_to_intrinsic(intr, target).expect("Couldn't parse XML properly!"))
+            xml_to_intrinsic(intr).ok()
+        })
+        .collect();
+
+    Ok(parsed_intrinsics)
+}
+
+fn xml_to_intrinsic(
+    intr: XMLIntrinsic,
+) -> Result<Intrinsic<X86IntrinsicType>, Box<dyn std::error::Error>> {
+    let name = intr.name;
+    let result = X86IntrinsicType::from_param(&intr.return_data);
+    let args_check = intr.parameters.into_iter().enumerate().map(|(i, param)| {
+        let ty = X86IntrinsicType::from_param(&param);
+        if ty.is_err() {
+            None
+        } else {
+            let constraint = map_constraints(&param.imm_type);
+            let arg = Argument::<X86IntrinsicType>::new(
+                i,
+                param.var_name.clone(),
+                ty.unwrap(),
+                constraint,
+            );
+            Some(arg)
+        }
+    });
+
+    let args = args_check.collect::<Vec<_>>();
+    if args.iter().any(|elem| elem.is_none()) {
+        return Err(Box::from("intrinsic isn't fully supported in this test!"));
+    }
+    let args = args
+        .into_iter()
+        .map(|e| e.unwrap())
+        .filter(|arg| arg.ty.ptr || arg.ty.kind != TypeKind::Void)
+        .collect::<Vec<_>>();
+    let arguments = ArgumentList::<X86IntrinsicType> { args };
+
+    if let Err(message) = result {
+        return Err(Box::from(message));
+    }
+    Ok(Intrinsic {
+        name,
+        arguments,
+        results: result.unwrap(),
+        arch_tags: intr.cpuid,
+    })
+}
\ No newline at end of file

From 21798b1ce91b549d9901c4761f79b57a36bbd17e Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 3 Aug 2025 18:00:34 +0530
Subject: [PATCH 03/73] feat: updated intrinsics creation

---
 Cargo.lock                                  | 53 ++++++++++++++++++++-
 crates/intrinsic-test/src/x86/mod.rs        | 29 +++++++++--
 crates/intrinsic-test/src/x86/xml_parser.rs |  4 +-
 3 files changed, 80 insertions(+), 6 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index ff503f3035..97bdfd5368 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -347,8 +347,10 @@ dependencies = [
  "itertools",
  "log",
  "pretty_env_logger",
+ "quick-xml 0.37.5",
  "rayon",
  "serde",
+ "serde-xml-rs",
  "serde_json",
 ]
 
@@ -452,6 +454,16 @@ dependencies = [
  "serde",
 ]
 
+[[package]]
+name = "quick-xml"
+version = "0.37.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "331e97a1af0bf59823e6eadffe373d7b27f485be8748f71471c662c1f269b7fb"
+dependencies = [
+ "memchr",
+ "serde",
+]
+
 [[package]]
 name = "quickcheck"
 version = "1.0.3"
@@ -587,6 +599,18 @@ dependencies = [
  "serde_derive",
 ]
 
+[[package]]
+name = "serde-xml-rs"
+version = "0.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "53630160a98edebde0123eb4dfd0fce6adff091b2305db3154a9e920206eb510"
+dependencies = [
+ "log",
+ "serde",
+ "thiserror",
+ "xml-rs",
+]
+
 [[package]]
 name = "serde_derive"
 version = "1.0.219"
@@ -698,7 +722,7 @@ name = "stdarch-verify"
 version = "0.1.0"
 dependencies = [
  "proc-macro2",
- "quick-xml",
+ "quick-xml 0.33.0",
  "quote",
  "serde",
  "serde_json",
@@ -746,6 +770,26 @@ dependencies = [
  "winapi-util",
 ]
 
+[[package]]
+name = "thiserror"
+version = "1.0.69"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b6aaf5339b578ea85b50e080feb250a3e8ae8cfcdff9a461c9ec2904bc923f52"
+dependencies = [
+ "thiserror-impl",
+]
+
+[[package]]
+name = "thiserror-impl"
+version = "1.0.69"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "4fee6c4efc90059e10f81e6d42c60a18f76588c3d74cb83a0b242a2b6c7504c1"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "unicode-ident"
 version = "1.0.18"
@@ -953,10 +997,17 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
 
 [[package]]
+<<<<<<< HEAD
 name = "windows_x86_64_msvc"
 version = "0.53.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486"
+=======
+name = "xml-rs"
+version = "0.8.27"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6fd8403733700263c6eb89f192880191f1b83e332f7a20371ddcf421c4a337c7"
+>>>>>>> 3283a857 (feat: updated intrinsics creation)
 
 [[package]]
 name = "yaml-rust"
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index ac613643bd..d1c23b8a94 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -3,10 +3,12 @@ mod intrinsic;
 mod types;
 mod xml_parser;
 
-use crate::common::SupportedArchitectureTest;
 use crate::common::cli::ProcessedCli;
-use crate::common::intrinsic::Intrinsic;
+use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
+use crate::common::intrinsic_helpers::TypeKind;
+use crate::common::SupportedArchitectureTest;
 use intrinsic::X86IntrinsicType;
+use xml_parser::get_xml_intrinsics;
 
 pub struct X86ArchitectureTest {
     intrinsics: Vec<Intrinsic<X86IntrinsicType>>,
@@ -15,7 +17,28 @@ pub struct X86ArchitectureTest {
 
 impl SupportedArchitectureTest for X86ArchitectureTest {
     fn create(cli_options: ProcessedCli) -> Box<Self> {
-        todo!("create in X86ArchitectureTest is not implemented")
+        let intrinsics =
+            get_xml_intrinsics(&cli_options.filename).expect("Error parsing input file");
+
+        let mut intrinsics = intrinsics
+            .into_iter()
+            // Not sure how we would compare intrinsic that returns void.
+            .filter(|i| i.results.kind() != TypeKind::Void)
+            .filter(|i| i.results.kind() != TypeKind::BFloat)
+            .filter(|i| i.arguments().args.len() > 0)
+            .filter(|i| !i.arguments.iter().any(|a| a.ty.kind() == TypeKind::BFloat))
+            // Skip pointers for now, we would probably need to look at the return
+            // type to work out how many elements we need to point to.
+            .filter(|i| !i.arguments.iter().any(|a| a.is_ptr()))
+            .filter(|i| !i.arguments.iter().any(|a| a.ty.inner_size() == 128))
+            .filter(|i| !cli_options.skip.contains(&i.name))
+            .collect::<Vec<_>>();
+
+        intrinsics.sort_by(|a, b| a.name.cmp(&b.name));
+        Box::new(Self {
+            intrinsics: intrinsics,
+            cli_options: cli_options,
+        })
     }
 
     fn build_c_file(&self) -> bool {
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index 55bc33ca7c..7f76cbc40a 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -26,9 +26,9 @@ struct Data {
 #[derive(Deserialize)]
 struct XMLIntrinsic {
     #[serde(rename = "return")]
-    return_data: Parameter,
+    pub return_data: Parameter,
     #[serde(rename = "@name")]
-    name: String,
+    pub name: String,
     // #[serde(rename = "@tech")]
     // tech: String,
     #[serde(rename = "CPUID", default)]

From bdc580139b1b12667740c23afe48842ed373d927 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 3 Aug 2025 18:25:44 +0530
Subject: [PATCH 04/73] feat: update building C code for x86 architecture.

Notes: 1. chunk_info has been moved to `common/mod.rs` since it will be
needed for all architectures
---
 crates/intrinsic-test/src/x86/compile.rs | 38 +++++++++++++
 crates/intrinsic-test/src/x86/config.rs  | 25 ++++++++
 crates/intrinsic-test/src/x86/mod.rs     | 72 +++++++++++++++++++++++-
 3 files changed, 133 insertions(+), 2 deletions(-)
 create mode 100644 crates/intrinsic-test/src/x86/compile.rs
 create mode 100644 crates/intrinsic-test/src/x86/config.rs

diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
new file mode 100644
index 0000000000..170e40927f
--- /dev/null
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -0,0 +1,38 @@
+use crate::common::cli::ProcessedCli;
+use crate::common::compile_c::{CompilationCommandBuilder, CppCompilation};
+
+pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
+    let cpp_compiler = config.cpp_compiler.as_ref()?;
+
+    // -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations
+    let mut command = CompilationCommandBuilder::new()
+        .add_arch_flags(vec![
+            "avx",
+            "avx2",
+            "avx512f",
+            "avx512cd",
+            "avx512dq",
+            "avx512vl",
+            "avx512bw",
+            "avx512bf16",
+            "avx512bitalg",
+            "lzcnt",
+            "popcnt",
+            "adx",
+            "aes",
+        ])
+        .set_compiler(cpp_compiler)
+        .set_target(&config.target)
+        .set_opt_level("2")
+        .set_cxx_toolchain_dir(config.cxx_toolchain_dir.as_deref())
+        .set_project_root("c_programs")
+        .add_extra_flags(vec!["-ffp-contract=off", "-Wno-narrowing"]);
+
+    if !cpp_compiler.contains("clang") {
+        command = command.add_extra_flag("-flax-vector-conversions");
+    }
+
+    let mut cpp_compiler = command.into_cpp_compilation();
+
+    Some(cpp_compiler)
+}
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
new file mode 100644
index 0000000000..5a07dd745f
--- /dev/null
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -0,0 +1,25 @@
+pub fn build_notices(line_prefix: &str) -> String {
+    format!(
+        "\
+{line_prefix}This is a transient test file, not intended for distribution. Some aspects of the
+{line_prefix}test are derived from an XML specification, published under the same license as the
+{line_prefix}`intrinsic-test` crate.\n
+"
+    )
+}
+
+// Format f16 values (and vectors containing them) in a way that is consistent with C.
+pub const F16_FORMATTING_DEF: &str = r#"
+#[repr(transparent)]
+struct Hex<T>(T);
+ "#;
+
+pub const X86_CONFIGURATIONS: &str = r#"
+#![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_bf16))]
+#![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_f16))]
+#![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))]
+#![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))]
+#![cfg_attr(target_arch = "x86_64", feature(x86_amx_intrinsics))]
+#![cfg_attr(target_arch = "x86_64", feature(stdarch_x86_avx512_f16))]
+#![feature(fmt_helpers_for_derive)]
+"#;
\ No newline at end of file
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index d1c23b8a94..c7b4a9d4aa 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -1,14 +1,21 @@
+mod compile;
+mod config;
 mod constraint;
 mod intrinsic;
 mod types;
 mod xml_parser;
 
+use std::fs::{self, File};
+use rayon::prelude::*;
+
 use crate::common::cli::ProcessedCli;
 use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
 use crate::common::intrinsic_helpers::TypeKind;
-use crate::common::SupportedArchitectureTest;
+use crate::common::{SupportedArchitectureTest, chunk_info};
+use crate::common::gen_c::{write_main_cpp, write_mod_cpp};
 use intrinsic::X86IntrinsicType;
 use xml_parser::get_xml_intrinsics;
+use config::build_notices;
 
 pub struct X86ArchitectureTest {
     intrinsics: Vec<Intrinsic<X86IntrinsicType>>,
@@ -42,7 +49,68 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
     }
 
     fn build_c_file(&self) -> bool {
-        todo!("build_c_file in X86ArchitectureTest is not implemented")
+        let c_target = "x86_64";
+        let platform_headers = &["immintrin.h"];
+
+        let (chunk_size, chunk_count) = chunk_info(self.intrinsics.len());
+
+        let cpp_compiler_wrapped = compile::build_cpp_compilation(&self.cli_options);
+
+        let notice = &build_notices("// ");
+        fs::create_dir_all("c_programs").unwrap();
+        self.intrinsics
+            .par_chunks(chunk_size)
+            .enumerate()
+            .map(|(i, chunk)| {
+                let c_filename = format!("c_programs/mod_{i}.cpp");
+                let mut file = File::create(&c_filename).unwrap();
+                write_mod_cpp(&mut file, notice, c_target, platform_headers, chunk).unwrap();
+
+                // compile this cpp file into a .o file.
+                //
+                // This is done because `cpp_compiler_wrapped` is None when
+                // the --generate-only flag is passed
+                if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
+                    let output = cpp_compiler
+                        .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"))?;
+                    assert!(output.status.success(), "{output:?}");
+                }
+
+                Ok(())
+            })
+            .collect::<Result<(), std::io::Error>>()
+            .unwrap();
+
+        let mut file = File::create("c_programs/main.cpp").unwrap();
+        write_main_cpp(
+            &mut file,
+            c_target,
+            "\n",
+            self.intrinsics.iter().map(|i| i.name.as_str()),
+        )
+        .unwrap();
+
+        // This is done because `cpp_compiler_wrapped` is None when
+        // the --generate-only flag is passed
+        if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
+            // compile this cpp file into a .o file
+            info!("compiling main.cpp");
+            let output = cpp_compiler
+                .compile_object_file("main.cpp", "intrinsic-test-programs.o")
+                .unwrap();
+            assert!(output.status.success(), "{output:?}");
+
+            let object_files = (0..chunk_count)
+                .map(|i| format!("mod_{i}.o"))
+                .chain(["intrinsic-test-programs.o".to_owned()]);
+
+            let output = cpp_compiler
+                .link_executable(object_files, "intrinsic-test-programs")
+                .unwrap();
+            assert!(output.status.success(), "{output:?}");
+        }
+
+        true
     }
 
     fn build_rust_file(&self) -> bool {

From adcd62969748dddae7999e9f153253487feb3583 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 3 Aug 2025 19:01:00 +0530
Subject: [PATCH 05/73] fix: code cleanup

---
 crates/intrinsic-test/src/x86/config.rs     |   2 +-
 crates/intrinsic-test/src/x86/constraint.rs |   2 +-
 crates/intrinsic-test/src/x86/intrinsic.rs  |   2 +-
 crates/intrinsic-test/src/x86/mod.rs        |   8 +-
 crates/intrinsic-test/src/x86/types.rs      | 230 +++++++++++++++++++-
 crates/intrinsic-test/src/x86/xml_parser.rs |   2 +-
 6 files changed, 230 insertions(+), 16 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 5a07dd745f..427ec183a9 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -22,4 +22,4 @@ pub const X86_CONFIGURATIONS: &str = r#"
 #![cfg_attr(target_arch = "x86_64", feature(x86_amx_intrinsics))]
 #![cfg_attr(target_arch = "x86_64", feature(stdarch_x86_avx512_f16))]
 #![feature(fmt_helpers_for_derive)]
-"#;
\ No newline at end of file
+"#;
diff --git a/crates/intrinsic-test/src/x86/constraint.rs b/crates/intrinsic-test/src/x86/constraint.rs
index 321ee89b6c..1f06988388 100644
--- a/crates/intrinsic-test/src/x86/constraint.rs
+++ b/crates/intrinsic-test/src/x86/constraint.rs
@@ -17,4 +17,4 @@ pub fn map_constraints(imm_type: &String) -> Option<Constraint> {
         "_CMP_" => Some(Constraint::Range(0..32)),
         _ => None,
     }
-}
\ No newline at end of file
+}
diff --git a/crates/intrinsic-test/src/x86/intrinsic.rs b/crates/intrinsic-test/src/x86/intrinsic.rs
index 27eca89406..1dedcb59a5 100644
--- a/crates/intrinsic-test/src/x86/intrinsic.rs
+++ b/crates/intrinsic-test/src/x86/intrinsic.rs
@@ -40,4 +40,4 @@ impl IntrinsicDefinition<X86IntrinsicType> for Intrinsic<X86IntrinsicType> {
     fn print_result_c(&self, _indentation: Indentation, _additional: &str) -> String {
         todo!("print_result_c in Intrinsic<X86IntrinsicType> needs to be implemented!");
     }
-}
\ No newline at end of file
+}
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index c7b4a9d4aa..7f30a220f3 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -5,17 +5,17 @@ mod intrinsic;
 mod types;
 mod xml_parser;
 
-use std::fs::{self, File};
 use rayon::prelude::*;
+use std::fs::{self, File};
 
 use crate::common::cli::ProcessedCli;
+use crate::common::gen_c::{write_main_cpp, write_mod_cpp};
 use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
 use crate::common::intrinsic_helpers::TypeKind;
 use crate::common::{SupportedArchitectureTest, chunk_info};
-use crate::common::gen_c::{write_main_cpp, write_mod_cpp};
+use config::build_notices;
 use intrinsic::X86IntrinsicType;
 use xml_parser::get_xml_intrinsics;
-use config::build_notices;
 
 pub struct X86ArchitectureTest {
     intrinsics: Vec<Intrinsic<X86IntrinsicType>>,
@@ -120,4 +120,4 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
     fn compare_outputs(&self) -> bool {
         todo!("compare_outputs in X86ArchitectureTest is not implemented")
     }
-}
\ No newline at end of file
+}
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 3dd205c9cb..e27a182370 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -1,23 +1,125 @@
+use std::collections::HashMap;
+use std::str::FromStr;
+
+use itertools::Itertools;
+use regex::Regex;
+
 use super::intrinsic::X86IntrinsicType;
 use crate::common::cli::Language;
-use crate::common::intrinsic_helpers::IntrinsicTypeDefinition;
+use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind};
 use crate::x86::xml_parser::Parameter;
 
 impl IntrinsicTypeDefinition for X86IntrinsicType {
     /// Gets a string containing the type in C format.
     /// This function assumes that this value is present in the metadata hashmap.
     fn c_type(&self) -> String {
-        todo!("c_type from IntrinsicTypeDefinition is not defined!")
+        self.metadata
+            .get("type")
+            .expect("Failed to extract the C typename in X86!")
+            .to_string()
     }
 
     fn c_single_vector_type(&self) -> String {
         // matches __m128, __m256 and similar types
-        todo!("c_type from IntrinsicTypeDefinition is not defined!")
+        let re = Regex::new(r"\__m\d+\").unwrap();
+        match self.metadata.get("type") {
+            Some(type_data) if re.is_match(type_data) => type_data.to_string(),
+            _ => unreachable!("Shouldn't be called on this type"),
+        }
     }
 
+    // fn rust_type(&self) -> String {
+    //     // handling edge cases first
+    //     // the general handling is implemented below
+    //     if let Some(val) = self.metadata.get("type") {
+    //         match val.as_str() {
+    //             "__m128 const *" => {
+    //                 return "&__m128".to_string();
+    //             }
+    //             "__m128d const *" => {
+    //                 return "&__m128d".to_string();
+    //             }
+    //             "const void*" => {
+    //                 return "&__m128d".to_string();
+    //             }
+    //             _ => {}
+    //         }
+    //     }
+
+    //     if self.kind() == TypeKind::Void && self.ptr {
+    //         // this has been handled by default settings in
+    //         // the from_param function of X86IntrinsicType
+    //         unreachable!()
+    //     }
+
+    //     // general handling cases
+    //     let core_part = if self.kind() == TypeKind::Mask {
+    //         // all types of __mmask<int> are handled here
+    //         format!("__mask{}", self.bit_len.unwrap())
+    //     } else if self.simd_len.is_some() {
+    //         // all types of __m<int> vector types are handled here
+    //         let re = Regex::new(r"\__m\d+[a-z]*").unwrap();
+    //         let rust_type = self
+    //             .metadata
+    //             .get("type")
+    //             .map(|val| re.find(val).unwrap().as_str());
+    //         rust_type.unwrap().to_string()
+    //     } else {
+    //         format!(
+    //             "{}{}",
+    //             self.kind.rust_prefix().to_string(),
+    //             self.bit_len.unwrap()
+    //         )
+    //     };
+
+    //     // extracting "memsize" so that even vector types can be involved
+    //     let memwidth = self
+    //         .metadata
+    //         .get("memwidth")
+    //         .map(|n| str::parse::<u32>(n).unwrap());
+    //     let prefix_part = if self.ptr && self.constant && self.bit_len.eq(&memwidth) {
+    //         "&"
+    //     } else if self.ptr && self.bit_len.eq(&memwidth) {
+    //         "&mut "
+    //     } else if self.ptr && self.constant {
+    //         "*const "
+    //     } else if self.ptr {
+    //         "*mut "
+    //     } else {
+    //         ""
+    //     };
+
+    //     return prefix_part.to_string() + core_part.as_str();
+    // }
+
     /// Determines the load function for this type.
     fn get_load_function(&self, _language: Language) -> String {
-        todo!("get_load_function from IntrinsicTypeDefinition is not defined!")
+        if let Some(type_value) = self.metadata.get("type") {
+            if type_value.starts_with("__mmask") {
+                // no need of loads, since they work directly
+                // with hex constants
+                String::from("*")
+            } else if type_value.starts_with("__m") {
+                // the structure is like the follows:
+                // if "type" starts with __m<num>{h/i/<null>},
+                // then use either _mm_set1_epi64,
+                // _mm256_set1_epi64 or _mm512_set1_epi64
+                let type_val_filtered = type_value
+                    .chars()
+                    .filter(|c| c.is_numeric())
+                    .join("")
+                    .replace("128", "");
+                format!("_mm{type_val_filtered}_set1_epi64")
+            } else {
+                // if it is a pointer, then rely on type conversion
+                // If it is not any of the above type (__int<num>, __bfloat16, unsigned short, etc)
+                // then typecast it.
+                format!("({type_value})")
+            }
+            // Look for edge cases (constexpr, literal, etc)
+        } else {
+            unimplemented!("the value for key 'type' is not present!");
+        }
     }
 
     /// Determines the get lane function for this type.
@@ -25,13 +127,125 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
         todo!("get_lane_function for X86IntrinsicType needs to be implemented!");
     }
 
-    fn from_c(s: &str, target: &str) -> Result<Self, String> {
-        todo!("from_c from IntrinsicTypeDefinition is not defined!")
+    fn from_c(s: &str) -> Result<Self, String> {
+        let mut s_copy = s.to_string();
+        let mut metadata: HashMap<String, String> = HashMap::new();
+        metadata.insert("type".to_string(), s.to_string());
+        s_copy = s_copy
+            .replace("*", "")
+            .replace("_", "")
+            .replace("constexpr", "")
+            .replace("const", "")
+            .replace("literal", "");
+
+        let s_split = s_copy
+            .split(" ")
+            .filter_map(|s| if s.len() == 0 { None } else { Some(s) })
+            .last();
+
+        let s_split = s_split.map(|s| s.chars().filter(|c| !c.is_numeric()).join(""));
+
+        // TODO: make the unwrapping safe
+        let kind = TypeKind::from_str(s_split.unwrap().trim()).unwrap_or(TypeKind::Void);
+
+        let kind = if s.find("unsigned").is_some() {
+            match kind {
+                TypeKind::Int(_) => TypeKind::Int(Sign::Unsigned),
+                TypeKind::Char(_) => TypeKind::Char(Sign::Unsigned),
+                a => a,
+            }
+        } else {
+            kind
+        };
+
+        let ptr_constant = false;
+        let constant = s.matches("const").next().is_some();
+        let ptr = s.matches("*").next().is_some();
+
+        Ok(X86IntrinsicType(IntrinsicType {
+            ptr,
+            ptr_constant,
+            constant,
+            kind,
+            bit_len: None,
+            simd_len: None,
+            vec_len: None,
+            metadata,
+        }))
     }
 }
 
 impl X86IntrinsicType {
     pub fn from_param(param: &Parameter) -> Result<Self, String> {
-        todo!("from_param from X86IntrinsicType is not defined!")
+        match Self::from_c(param.type_data.as_str()) {
+            Err(message) => Err(message),
+            Ok(mut ret) => {
+                // First correct the type of the parameter using param.etype.
+                // The assumption is that the parameter of type void may have param.type
+                // as "__m128i", "__mmask8" and the like.
+                ret.set_metadata("etype".to_string(), param.etype.clone());
+                ret.set_metadata("memwidth".to_string(), param.memwidth.to_string());
+                if !param.etype.is_empty() {
+                    match TypeKind::from_str(param.etype.as_str()) {
+                        Ok(value) => {
+                            ret.kind = value;
+                        }
+                        Err(_) => {}
+                    };
+                }
+
+                // check for param.etype.
+                // extract the numeric part and set as bit-len
+                // If param.etype is not present, guess the default bit-len
+
+                let mut etype_processed = param.etype.clone();
+                etype_processed.retain(|c| c.is_numeric());
+
+                match str::parse::<u32>(etype_processed.as_str()) {
+                    Ok(value) => ret.bit_len = Some(value),
+                    Err(_) => {
+                        ret.bit_len = match ret.kind() {
+                            TypeKind::Char(_) => Some(8),
+                            TypeKind::BFloat => Some(16),
+                            TypeKind::Int(_) => Some(32),
+                            TypeKind::Float => Some(32),
+                            _ => None,
+                        };
+                    }
+                }
+
+                // then check the param.type and extract numeric part if there are double
+                // underscores. divide this number with bit-len and set this as simd-len.
+                // Only __m<int> types can have a simd-len.
+                if param.type_data.matches("__m").next().is_some()
+                    && param.type_data.matches("__mmask").next().is_none()
+                {
+                    let mut type_processed = param.type_data.clone();
+                    type_processed.retain(|c| c.is_numeric());
+                    ret.vec_len = match str::parse::<u32>(type_processed.as_str()) {
+                        // If bit_len is None, vec_len will be None.
+                        // Else vec_len will be (num_bits / bit_len).
+                        Ok(num_bits) => ret.bit_len.and(Some(num_bits / ret.bit_len.unwrap())),
+                        Err(_) => None,
+                    };
+                }
+
+                // default settings for "void *" parameters
+                // often used by intrinsics to denote memory address or so.
+                if ret.kind == TypeKind::Void && ret.ptr {
+                    ret.kind = TypeKind::Int(Sign::Unsigned);
+                    ret.bit_len = Some(8);
+                }
+
+                // if param.etype == IMM, then it is a constant.
+                // else it stays unchanged.
+                ret.constant |= param.etype == "IMM";
+
+                Ok(ret)
+            }
+        }
+        // Tile types won't currently reach here, since the intrinsic that involve them
+        // often return "null" type. Such intrinsics are not tested in `intrinsic-test`
+        // currently and are filtered out at `mod.rs`.
     }
-}
\ No newline at end of file
+}
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index 7f76cbc40a..b26e18840d 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -112,4 +112,4 @@ fn xml_to_intrinsic(
         results: result.unwrap(),
         arch_tags: intr.cpuid,
     })
-}
\ No newline at end of file
+}

From 23b3ff9af04371900475371d239c50c777c4b6c5 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 5 Aug 2025 15:46:01 +0530
Subject: [PATCH 06/73] chore: added Regex crate, updated the structure of
 X86IntrinsicType struct

---
 Cargo.lock                                  |  1 +
 crates/intrinsic-test/Cargo.toml            |  1 +
 crates/intrinsic-test/src/x86/compile.rs    |  2 +-
 crates/intrinsic-test/src/x86/intrinsic.rs  | 10 ++-
 crates/intrinsic-test/src/x86/types.rs      | 98 ++++++++++-----------
 crates/intrinsic-test/src/x86/xml_parser.rs |  2 +-
 6 files changed, 59 insertions(+), 55 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 97bdfd5368..26a4223271 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -349,6 +349,7 @@ dependencies = [
  "pretty_env_logger",
  "quick-xml 0.37.5",
  "rayon",
+ "regex",
  "serde",
  "serde-xml-rs",
  "serde_json",
diff --git a/crates/intrinsic-test/Cargo.toml b/crates/intrinsic-test/Cargo.toml
index df4f7fe706..2c0f53897e 100644
--- a/crates/intrinsic-test/Cargo.toml
+++ b/crates/intrinsic-test/Cargo.toml
@@ -21,3 +21,4 @@ diff = "0.1.12"
 itertools = "0.14.0"
 quick-xml = { version = "0.37.5", features = ["serialize", "overlapped-lists"] }
 serde-xml-rs = "0.8.0"
+regex = "1.11.1"
diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index 170e40927f..e8c2262b85 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -32,7 +32,7 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
         command = command.add_extra_flag("-flax-vector-conversions");
     }
 
-    let mut cpp_compiler = command.into_cpp_compilation();
+    let cpp_compiler = command.into_cpp_compilation();
 
     Some(cpp_compiler)
 }
diff --git a/crates/intrinsic-test/src/x86/intrinsic.rs b/crates/intrinsic-test/src/x86/intrinsic.rs
index 1dedcb59a5..0261a2df85 100644
--- a/crates/intrinsic-test/src/x86/intrinsic.rs
+++ b/crates/intrinsic-test/src/x86/intrinsic.rs
@@ -2,22 +2,26 @@ use crate::common::argument::ArgumentList;
 use crate::common::indentation::Indentation;
 use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
 use crate::common::intrinsic_helpers::IntrinsicType;
+use crate::x86::xml_parser::Parameter;
 use std::ops::{Deref, DerefMut};
 
 #[derive(Debug, Clone, PartialEq)]
-pub struct X86IntrinsicType(pub IntrinsicType);
+pub struct X86IntrinsicType {
+    pub data: IntrinsicType,
+    pub param: Parameter,
+}
 
 impl Deref for X86IntrinsicType {
     type Target = IntrinsicType;
 
     fn deref(&self) -> &Self::Target {
-        &self.0
+        &self.data
     }
 }
 
 impl DerefMut for X86IntrinsicType {
     fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.0
+        &mut self.data
     }
 }
 
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index e27a182370..542d1ad3fa 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -13,18 +13,16 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
     /// Gets a string containing the type in C format.
     /// This function assumes that this value is present in the metadata hashmap.
     fn c_type(&self) -> String {
-        self.metadata
-            .get("type")
-            .expect("Failed to extract the C typename in X86!")
-            .to_string()
+        self.param.type_data.clone()
     }
 
     fn c_single_vector_type(&self) -> String {
         // matches __m128, __m256 and similar types
         let re = Regex::new(r"\__m\d+\").unwrap();
-        match self.metadata.get("type") {
-            Some(type_data) if re.is_match(type_data) => type_data.to_string(),
-            _ => unreachable!("Shouldn't be called on this type"),
+        if re.is_match(self.param.type_data.as_str()) {
+            self.param.type_data.clone()
+        } else {
+            unreachable!("Shouldn't be called on this type")
         }
     }
 
@@ -94,40 +92,42 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
 
     /// Determines the load function for this type.
     fn get_load_function(&self, _language: Language) -> String {
-        if let Some(type_value) = self.metadata.get("type") {
-            if type_value.starts_with("__mmask") {
-                // no need of loads, since they work directly
-                // with hex constants
-                String::from("*")
-            } else if type_value.starts_with("__m") {
-                // the structure is like the follows:
-                // if "type" starts with __m<num>{h/i/<null>},
-                // then use either _mm_set1_epi64,
-                // _mm256_set1_epi64 or _mm512_set1_epi64
-                let type_val_filtered = type_value
-                    .chars()
-                    .filter(|c| c.is_numeric())
-                    .join("")
-                    .replace("128", "");
-                format!("_mm{type_val_filtered}_set1_epi64")
-            } else {
-                // if it is a pointer, then rely on type conversion
-                // If it is not any of the above type (__int<num>, __bfloat16, unsigned short, etc)
-                // then typecast it.
-                format!("({type_value})")
-            }
-            // Look for edge cases (constexpr, literal, etc)
-        } else {
+        let type_value = self.param.type_data.clone();
+        if type_value.len() == 0 {
             unimplemented!("the value for key 'type' is not present!");
         }
+        if type_value.starts_with("__mmask") {
+            // no need of loads, since they work directly
+            // with hex constants
+            String::from("*")
+        } else if type_value.starts_with("__m") {
+            // the structure is like the follows:
+            // if "type" starts with __m<num>{h/i/<null>},
+            // then use either _mm_set1_epi64,
+            // _mm256_set1_epi64 or _mm512_set1_epi64
+            let type_val_filtered = type_value
+                .chars()
+                .filter(|c| c.is_numeric())
+                .join("")
+                .replace("128", "");
+            format!("_mm{type_val_filtered}_set1_epi64")
+        } else {
+            // if it is a pointer, then rely on type conversion
+            // If it is not any of the above type (__int<num>, __bfloat16, unsigned short, etc)
+            // then typecast it.
+            format!("({type_value})")
+        }
+        // Look for edge cases (constexpr, literal, etc)
     }
 
     /// Determines the get lane function for this type.
     fn get_lane_function(&self) -> String {
         todo!("get_lane_function for X86IntrinsicType needs to be implemented!");
     }
+}
 
-    fn from_c(s: &str) -> Result<Self, String> {
+impl X86IntrinsicType {
+    fn from_c(s: &str) -> Result<IntrinsicType, String> {
         let mut s_copy = s.to_string();
         let mut metadata: HashMap<String, String> = HashMap::new();
         metadata.insert("type".to_string(), s.to_string());
@@ -162,7 +162,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
         let constant = s.matches("const").next().is_some();
         let ptr = s.matches("*").next().is_some();
 
-        Ok(X86IntrinsicType(IntrinsicType {
+        Ok(IntrinsicType {
             ptr,
             ptr_constant,
             constant,
@@ -170,25 +170,20 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             bit_len: None,
             simd_len: None,
             vec_len: None,
-            metadata,
-        }))
+        })
     }
-}
 
-impl X86IntrinsicType {
     pub fn from_param(param: &Parameter) -> Result<Self, String> {
         match Self::from_c(param.type_data.as_str()) {
             Err(message) => Err(message),
-            Ok(mut ret) => {
+            Ok(mut data) => {
                 // First correct the type of the parameter using param.etype.
                 // The assumption is that the parameter of type void may have param.type
                 // as "__m128i", "__mmask8" and the like.
-                ret.set_metadata("etype".to_string(), param.etype.clone());
-                ret.set_metadata("memwidth".to_string(), param.memwidth.to_string());
                 if !param.etype.is_empty() {
                     match TypeKind::from_str(param.etype.as_str()) {
                         Ok(value) => {
-                            ret.kind = value;
+                            data.kind = value;
                         }
                         Err(_) => {}
                     };
@@ -202,9 +197,9 @@ impl X86IntrinsicType {
                 etype_processed.retain(|c| c.is_numeric());
 
                 match str::parse::<u32>(etype_processed.as_str()) {
-                    Ok(value) => ret.bit_len = Some(value),
+                    Ok(value) => data.bit_len = Some(value),
                     Err(_) => {
-                        ret.bit_len = match ret.kind() {
+                        data.bit_len = match data.kind() {
                             TypeKind::Char(_) => Some(8),
                             TypeKind::BFloat => Some(16),
                             TypeKind::Int(_) => Some(32),
@@ -222,26 +217,29 @@ impl X86IntrinsicType {
                 {
                     let mut type_processed = param.type_data.clone();
                     type_processed.retain(|c| c.is_numeric());
-                    ret.vec_len = match str::parse::<u32>(type_processed.as_str()) {
+                    data.vec_len = match str::parse::<u32>(type_processed.as_str()) {
                         // If bit_len is None, vec_len will be None.
                         // Else vec_len will be (num_bits / bit_len).
-                        Ok(num_bits) => ret.bit_len.and(Some(num_bits / ret.bit_len.unwrap())),
+                        Ok(num_bits) => data.bit_len.and(Some(num_bits / data.bit_len.unwrap())),
                         Err(_) => None,
                     };
                 }
 
                 // default settings for "void *" parameters
                 // often used by intrinsics to denote memory address or so.
-                if ret.kind == TypeKind::Void && ret.ptr {
-                    ret.kind = TypeKind::Int(Sign::Unsigned);
-                    ret.bit_len = Some(8);
+                if data.kind == TypeKind::Void && data.ptr {
+                    data.kind = TypeKind::Int(Sign::Unsigned);
+                    data.bit_len = Some(8);
                 }
 
                 // if param.etype == IMM, then it is a constant.
                 // else it stays unchanged.
-                ret.constant |= param.etype == "IMM";
+                data.constant |= param.etype == "IMM";
 
-                Ok(ret)
+                Ok(X86IntrinsicType {
+                    data,
+                    param: param.clone(),
+                })
             }
         }
         // Tile types won't currently reach here, since the intrinsic that involve them
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index b26e18840d..0b422bddb5 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -37,7 +37,7 @@ struct XMLIntrinsic {
     parameters: Vec<Parameter>,
 }
 
-#[derive(Deserialize)]
+#[derive(Debug, PartialEq, Clone, Deserialize)]
 pub struct Parameter {
     #[serde(rename = "@varname")]
     pub var_name: String,

From b3292c3bc5d77ced3014f49763f9edd80349373d Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 5 Aug 2025 15:56:09 +0530
Subject: [PATCH 07/73] feat: implemented build_rust_file of `x86` module

---
 crates/intrinsic-test/src/x86/mod.rs | 59 +++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 7f30a220f3..9030205c78 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -10,9 +10,13 @@ use std::fs::{self, File};
 
 use crate::common::cli::ProcessedCli;
 use crate::common::gen_c::{write_main_cpp, write_mod_cpp};
+use crate::common::gen_rust::{
+    compile_rust_programs, write_bin_cargo_toml, write_lib_cargo_toml, write_lib_rs, write_main_rs,
+};
 use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
 use crate::common::intrinsic_helpers::TypeKind;
 use crate::common::{SupportedArchitectureTest, chunk_info};
+use crate::x86::config::{F16_FORMATTING_DEF, X86_CONFIGURATIONS};
 use config::build_notices;
 use intrinsic::X86IntrinsicType;
 use xml_parser::get_xml_intrinsics;
@@ -114,7 +118,60 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
     }
 
     fn build_rust_file(&self) -> bool {
-        todo!("build_rust_file in X86ArchitectureTest is not implemented")
+        std::fs::create_dir_all("rust_programs/src").unwrap();
+
+        let architecture = if self.cli_options.target.contains("v7") {
+            "arm"
+        } else {
+            "aarch64"
+        };
+
+        let (chunk_size, chunk_count) = chunk_info(self.intrinsics.len());
+
+        let mut cargo = File::create("rust_programs/Cargo.toml").unwrap();
+        write_bin_cargo_toml(&mut cargo, chunk_count).unwrap();
+
+        let mut main_rs = File::create("rust_programs/src/main.rs").unwrap();
+        write_main_rs(
+            &mut main_rs,
+            chunk_count,
+            X86_CONFIGURATIONS,
+            "",
+            self.intrinsics.iter().map(|i| i.name.as_str()),
+        )
+        .unwrap();
+
+        let target = &self.cli_options.target;
+        let toolchain = self.cli_options.toolchain.as_deref();
+        let linker = self.cli_options.linker.as_deref();
+
+        let notice = &build_notices("// ");
+        self.intrinsics
+            .par_chunks(chunk_size)
+            .enumerate()
+            .map(|(i, chunk)| {
+                std::fs::create_dir_all(format!("rust_programs/mod_{i}/src"))?;
+
+                let rust_filename = format!("rust_programs/mod_{i}/src/lib.rs");
+                trace!("generating `{rust_filename}`");
+                let mut file = File::create(rust_filename)?;
+
+                let cfg = X86_CONFIGURATIONS;
+                let definitions = F16_FORMATTING_DEF;
+                write_lib_rs(&mut file, architecture, notice, cfg, definitions, chunk)?;
+
+                let toml_filename = format!("rust_programs/mod_{i}/Cargo.toml");
+                trace!("generating `{toml_filename}`");
+                let mut file = File::create(toml_filename).unwrap();
+
+                write_lib_cargo_toml(&mut file, &format!("mod_{i}"))?;
+
+                Ok(())
+            })
+            .collect::<Result<(), std::io::Error>>()
+            .unwrap();
+
+        compile_rust_programs(toolchain, target, linker)
     }
 
     fn compare_outputs(&self) -> bool {

From 75ff3134ab322cea06fe1f9a17d0c655dd2bbb11 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 5 Aug 2025 15:57:55 +0530
Subject: [PATCH 08/73] feat: implemented compare_outputs of `x86` module

---
 crates/intrinsic-test/src/x86/mod.rs | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 9030205c78..5515e68385 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -9,6 +9,7 @@ use rayon::prelude::*;
 use std::fs::{self, File};
 
 use crate::common::cli::ProcessedCli;
+use crate::common::compare::compare_outputs;
 use crate::common::gen_c::{write_main_cpp, write_mod_cpp};
 use crate::common::gen_rust::{
     compile_rust_programs, write_bin_cargo_toml, write_lib_cargo_toml, write_lib_rs, write_main_rs,
@@ -175,6 +176,20 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
     }
 
     fn compare_outputs(&self) -> bool {
-        todo!("compare_outputs in X86ArchitectureTest is not implemented")
+        if self.cli_options.toolchain.is_some() {
+            let intrinsics_name_list = self
+                .intrinsics
+                .iter()
+                .map(|i| i.name.clone())
+                .collect::<Vec<_>>();
+
+            compare_outputs(
+                &intrinsics_name_list,
+                &self.cli_options.runner,
+                &self.cli_options.target,
+            )
+        } else {
+            true
+        }
     }
 }

From 1c82e7f5d59464d9335bd0b4174a716981c1f8eb Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 5 Aug 2025 16:16:26 +0530
Subject: [PATCH 09/73] feat: implement `print_result_c` for
 `Intrinsic<X86IntrinsicType>`

---
 crates/intrinsic-test/src/x86/intrinsic.rs | 68 +++++++++++++++++++++-
 1 file changed, 65 insertions(+), 3 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/intrinsic.rs b/crates/intrinsic-test/src/x86/intrinsic.rs
index 0261a2df85..169394b793 100644
--- a/crates/intrinsic-test/src/x86/intrinsic.rs
+++ b/crates/intrinsic-test/src/x86/intrinsic.rs
@@ -1,7 +1,7 @@
 use crate::common::argument::ArgumentList;
 use crate::common::indentation::Indentation;
 use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
-use crate::common::intrinsic_helpers::IntrinsicType;
+use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, TypeKind};
 use crate::x86::xml_parser::Parameter;
 use std::ops::{Deref, DerefMut};
 
@@ -41,7 +41,69 @@ impl IntrinsicDefinition<X86IntrinsicType> for Intrinsic<X86IntrinsicType> {
     /// Generates a std::cout for the intrinsics results that will match the
     /// rust debug output format for the return type. The generated line assumes
     /// there is an int i in scope which is the current pass number.
-    fn print_result_c(&self, _indentation: Indentation, _additional: &str) -> String {
-        todo!("print_result_c in Intrinsic<X86IntrinsicType> needs to be implemented!");
+    fn print_result_c(&self, indentation: Indentation, additional: &str) -> String {
+        let lanes = if self.results().num_vectors() > 1 {
+            (0..self.results().num_vectors())
+                .map(|vector| {
+                    format!(
+                        r#""{ty}(" << {lanes} << ")""#,
+                        ty = self.results().c_single_vector_type(),
+                        lanes = (0..self.results().num_lanes())
+                            .map(move |idx| -> std::string::String {
+                                format!(
+                                    "{cast}{lane_fn}(__return_value.val[{vector}], {lane})",
+                                    cast = self.results().c_promotion(),
+                                    lane_fn = self.results().get_lane_function(),
+                                    lane = idx,
+                                    vector = vector,
+                                )
+                            })
+                            .collect::<Vec<_>>()
+                            .join(r#" << ", " << "#)
+                    )
+                })
+                .collect::<Vec<_>>()
+                .join(r#" << ", " << "#)
+        } else if self.results().num_lanes() > 1 {
+            (0..self.results().num_lanes())
+                .map(|idx| -> std::string::String {
+                    format!(
+                        "{cast}{lane_fn}(__return_value, {lane})",
+                        cast = self.results().c_promotion(),
+                        lane_fn = self.results().get_lane_function(),
+                        lane = idx
+                    )
+                })
+                .collect::<Vec<_>>()
+                .join(r#" << ", " << "#)
+        } else {
+            format!(
+                "{promote}cast<{cast}>(__return_value)",
+                cast = match self.results.kind() {
+                    TypeKind::Void => "void".to_string(),
+                    TypeKind::Float if self.results().inner_size() == 64 => "double".to_string(),
+                    TypeKind::Float if self.results().inner_size() == 32 => "float".to_string(),
+                    // TypeKind::Float if self.results().inner_size() == 16 => "float16_t".to_string(),
+                    // TypeKind::Int(true) if self.results().inner_size() == 64 => "long".to_string(),
+                    // TypeKind::Int(false) if self.results().inner_size() == 64 => "unsigned long".to_string(),
+                    // TypeKind::Int(true) if self.results().inner_size() == 32 => "int".to_string(),
+                    // TypeKind::Int(false) if self.results().inner_size() == 32 => "unsigned int".to_string(),
+                    // TypeKind::Int(true) if self.results().inner_size() == 16 => "short".to_string(),
+                    // TypeKind::Int(false) if self.results().inner_size() == 16 => "unsigned short".to_string(),
+                    _ => self.results.c_scalar_type(),
+                },
+                promote = self.results().c_promotion(),
+            )
+        };
+
+        format!(
+            r#"{indentation}std::cout << "Result {additional}-" << i+1 << ": {ty}" << std::fixed << std::setprecision(150) <<  {lanes} << "{close}" << std::endl;"#,
+            ty = if self.results().is_simd() {
+                format!("{}(", self.results().c_type())
+            } else {
+                String::from("")
+            },
+            close = if self.results.is_simd() { ")" } else { "" },
+        )
     }
 }

From 3fddae0889000f1d993c3059c8423fc72ae37cac Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 5 Aug 2025 21:45:22 +0530
Subject: [PATCH 10/73] feat: Added x86 to CI pipeline

---
 ci/run.sh                     |      3 +
 intrinsics_data/x86-intel.xml | 158422 +++++++++++++++++++++++++++++++
 2 files changed, 158425 insertions(+)
 create mode 100644 intrinsics_data/x86-intel.xml

diff --git a/ci/run.sh b/ci/run.sh
index 2bb77bae25..d8af9b7697 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -90,6 +90,9 @@ fi
 # Test targets compiled with extra features.
 case ${TARGET} in
     x86_64-unknown-linux-gnu)
+        TEST_CPPFLAGS="-fuse-ld=lld -I/usr/include/x86_64-linux-gnu/"
+        TEST_CXX_COMPILER="clang++-19"
+        TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
         export STDARCH_DISABLE_ASSERT_INSTR=1
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
diff --git a/intrinsics_data/x86-intel.xml b/intrinsics_data/x86-intel.xml
new file mode 100644
index 0000000000..41f2119e68
--- /dev/null
+++ b/intrinsics_data/x86-intel.xml
@@ -0,0 +1,158422 @@
+<intrinsics_list version="3.6.9" date="07/12/2024">
+<intrinsic name="_addcarryx_u32" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="unsigned char" varname="c_in" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<parameter etype="UI32" memwidth="32" type="unsigned int *" varname="out" />
+	<description>Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
+	<operation>
+tmp[32:0] := a[31:0] + b[31:0] + (c_in &gt; 0 ? 1 : 0)
+MEM[out+31:out] := tmp[31:0]
+dst[0] := tmp[32]
+dst[7:1] := 0
+	</operation>
+	<instruction form="r32, r32" name="ADCX" xed="ADCX_GPR32d_GPR32d" />
+	<instruction form="r32, r32" name="ADOX" xed="ADOX_GPR32d_GPR32d" />
+	<CPUID>ADX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_addcarryx_u64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="unsigned char" varname="c_in" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<parameter etype="UI64" memwidth="64" type="unsigned __int64 *" varname="out" />
+	<description>Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
+	<operation>
+tmp[64:0] := a[63:0] + b[63:0] + (c_in &gt; 0 ? 1 : 0)
+MEM[out+63:out] := tmp[63:0]
+dst[0] := tmp[64]
+dst[7:1] := 0
+	</operation>
+	<instruction form="r64, r64" name="ADCX" xed="ADCX_GPR64q_GPR64q" />
+	<instruction form="r64, r64" name="ADOX" xed="ADOX_GPR64q_GPR64q" />
+	<CPUID>ADX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+<intrinsic name="_mm_aesenc_si128" vexEq="TRUE" tech="Other">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="RoundKey" />
+	<description>Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"."</description>
+	<operation>a[127:0] := ShiftRows(a[127:0])
+a[127:0] := SubBytes(a[127:0])
+a[127:0] := MixColumns(a[127:0])
+dst[127:0] := a[127:0] XOR RoundKey[127:0]
+	</operation>
+	<instruction form="xmm, xmm" name="AESENC" xed="AESENC_XMMdq_XMMdq" />
+	<CPUID>AES</CPUID>
+	<header>wmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesenclast_si128" vexEq="TRUE" tech="Other">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="RoundKey" />
+	<description>Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"."</description>
+	<operation>a[127:0] := ShiftRows(a[127:0])
+a[127:0] := SubBytes(a[127:0])
+dst[127:0] := a[127:0] XOR RoundKey[127:0]
+	</operation>
+	<instruction form="xmm, xmm" name="AESENCLAST" xed="AESENCLAST_XMMdq_XMMdq" />
+	<CPUID>AES</CPUID>
+	<header>wmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesdec_si128" vexEq="TRUE" tech="Other">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="RoundKey" />
+	<description>Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst".</description>
+	<operation>a[127:0] := InvShiftRows(a[127:0])
+a[127:0] := InvSubBytes(a[127:0])
+a[127:0] := InvMixColumns(a[127:0])
+dst[127:0] := a[127:0] XOR RoundKey[127:0]
+	</operation>
+	<instruction form="xmm, xmm" name="AESDEC" xed="AESDEC_XMMdq_XMMdq" />
+	<CPUID>AES</CPUID>
+	<header>wmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesdeclast_si128" vexEq="TRUE" tech="Other">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="RoundKey" />
+	<description>Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst".</description>
+	<operation>a[127:0] := InvShiftRows(a[127:0])
+a[127:0] := InvSubBytes(a[127:0])
+dst[127:0] := a[127:0] XOR RoundKey[127:0]
+	</operation>
+	<instruction form="xmm, xmm" name="AESDECLAST" xed="AESDECLAST_XMMdq_XMMdq" />
+	<CPUID>AES</CPUID>
+	<header>wmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesimc_si128" vexEq="TRUE" tech="Other">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Perform the InvMixColumns transformation on "a" and store the result in "dst".</description>
+	<operation>dst[127:0] := InvMixColumns(a[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="AESIMC" xed="AESIMC_XMMdq_XMMdq" />
+	<CPUID>AES</CPUID>
+	<header>wmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aeskeygenassist_si128" vexEq="TRUE" tech="Other">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from "a" and an 8-bit round constant specified in "imm8", and store the result in "dst"."</description>
+	<operation>X3[31:0] := a[127:96]
+X2[31:0] := a[95:64]
+X1[31:0] := a[63:32]
+X0[31:0] := a[31:0]
+RCON[31:0] := ZeroExtend32(imm8[7:0])
+dst[31:0] := SubWord(X1)
+dst[63:32] := RotWord(SubWord(X1)) XOR RCON
+dst[95:64] := SubWord(X3)
+dst[127:96] := RotWord(SubWord(X3)) XOR RCON
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="AESKEYGENASSIST" xed="AESKEYGENASSIST_XMMdq_XMMdq_IMMb" />
+	<CPUID>AES</CPUID>
+	<header>wmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_tile_dpbf16ps" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="dst" />
+	<parameter type="constexpr int" varname="a" />
+	<parameter type="constexpr int" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in tiles "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst".</description>
+	<operation>FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (a.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.fp32[n] += FP32(a.row[m].bf16[2*k+0]) * FP32(b.row[k].bf16[2*n+0])
+			tmp.fp32[n] += FP32(a.row[m].bf16[2*k+1]) * FP32(b.row[k].bf16[2*n+1])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, tmm, tmm" name="TDPBF16PS" xed="TDPBF16PS_TMMf32_TMMu32_TMMu32" />
+	<CPUID>AMX-BF16</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_dpbf16ps" tech="AMX">
+	<return type="void" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in tiles "src0" and "src1", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm, tmm, tmm" name="TDPBF16PS" xed="TDPBF16PS_TMMf32_TMMu32_TMMu32" />
+	<operation>FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (src0.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.fp32[n] += FP32(src0.row[m].bf16[2*k+0]) * FP32(src1.row[k].bf16[2*n+0])
+			tmp.fp32[n] += FP32(src0.row[m].bf16[2*k+1]) * FP32(src1.row[k].bf16[2*n+1])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="__tile1024i" varname="src0" />
+	<parameter type="__tile1024i" varname="src1" />
+	<CPUID>AMX-BF16</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	
+<intrinsic name="_tile_cmmimfp16ps" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" etype="FP32" varname="dst" />
+	<parameter type="constexpr int" etype="FP16" varname="a" />
+	<parameter type="constexpr int" etype="FP16" varname="b" />
+	<description>Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. Each dword element in input tiles "a" and "b" is interpreted as a complex number with FP16 real part and FP16 imaginary part. Calculates the imaginary part of the result. For each possible combination of (row of "a", column of "b"), it performs a set of multiplication and accumulations on all corresponding complex numbers (one from "a" and one from "b"). The imaginary part of the "a" element is multiplied with the real part of the corresponding "b" element, and the real part of the "a" element is multiplied with the imaginary part of the corresponding "b" elements. The two accumulated results are added, and then accumulated into the corresponding row and column of "dst".</description>
+	<operation>FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (a.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+1])
+			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+0])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, tmm, tmm" name="TCMMIMFP16PS" xed="TCMMIMFP16PS_TMMf32_TMMf16_TMMf16" />
+	<CPUID>AMX-COMPLEX</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_cmmrlfp16ps" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" etype="FP32" varname="dst" />
+	<parameter type="constexpr int" etype="FP16" varname="a" />
+	<parameter type="constexpr int" etype="FP16" varname="b" />
+	<description>Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. Each dword element in input tiles "a" and "b" is interpreted as a complex number with FP16 real part and FP16 imaginary part. Calculates the real part of the result. For each possible combination of (row of "a", column of "b"), it performs a set of multiplication and accumulations on all corresponding complex numbers (one from "a" and one from "b"). The real part of the "a" element is multiplied with the real part of the corresponding "b" element, and the negated imaginary part of the "a" element is multiplied with the imaginary part of the corresponding "b" elements. The two accumulated results are added, and then accumulated into the corresponding row and column of "dst".</description>
+	<operation>FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (a.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+0])
+			tmp.fp32[n] += FP32(-a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+1])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<instruction form="tmm, tmm, tmm" name="TCMMRLFP16PS" xed="TCMMRLFP16PS_TMMf32_TMMf16_TMMf16" />
+	<CPUID>AMX-COMPLEX</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_cmmimfp16ps" tech="AMX">
+	<return type="void" />
+	<description>Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. Each dword element in input tiles "src0" and "src1" is interpreted as a complex number with FP16 real part and FP16 imaginary part. This function calculates the imaginary part of the result.</description>
+	<instruction form="tmm, tmm, tmm" name="TCMMIMFP16PS" xed="TCMMIMFP16PS_TMMf32_TMMf16_TMMf16" />
+	<operation>FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (src0.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+0]) * FP32(src1.row[k].fp16[2*n+1])
+			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+1]) * FP32(src1.row[k].fp16[2*n+0])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="__tile1024i" varname="src0" />
+	<parameter type="__tile1024i" varname="src1" />
+	<CPUID>AMX-COMPLEX</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_cmmrlfp16ps" tech="AMX">
+	<return type="void" />
+	<description>Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. Each dword element in input tiles src0 and src1 is interpreted as a complex number with FP16 real part and FP16 imaginary part. This function calculates the real part of the result.</description>
+	<instruction form="tmm, tmm, tmm" name="TCMMRLFP16PS" xed="TCMMRLFP16PS_TMMf32_TMMf16_TMMf16" />
+	<operation>FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (src0.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+0]) * FP32(src1.row[k].fp16[2*n+0])
+			tmp.fp32[n] += FP32(-src0.row[m].fp16[2*k+1]) * FP32(src1.row[k].fp16[2*n+1])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="__tile1024i" varname="src0" />
+	<parameter type="__tile1024i" varname="src1" />
+	<CPUID>AMX-COMPLEX</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	
+<intrinsic name="_tile_dpfp16ps" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" etype="FP32" varname="dst" />
+	<parameter type="constexpr int" etype="FP16" varname="a" />
+	<parameter type="constexpr int" etype="FP16" varname="b" />
+	<description>Compute dot-product of FP16 (16-bit) floating-point pairs in tiles "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst".</description>
+	<operation>FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (a.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+0])
+			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+1])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, tmm, tmm" name="TDPFP16PS" xed="TDPFP16PS_TMMf32_TMM2f16_TMM2f16" />
+	<CPUID>AMX-FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_dpfp16ps" tech="AMX">
+	<return type="void" />
+	<description>Compute dot-product of FP16 (16-bit) floating-point pairs in tiles "src0" and "src1", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm, tmm, tmm" name="TDPBF16PS" xed="TDPBF16PS_TMMf32_TMMu32_TMMu32" />
+	<operation>FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (src0.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+0]) * FP32(src1.row[k].fp16[2*n+0])
+			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+1]) * FP32(src1.row[k].fp16[2*n+1])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="__tile1024i" varname="src0" />
+	<parameter type="__tile1024i" varname="src1" />
+	<CPUID>AMX-FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	
+<intrinsic name="_tile_dpbsud" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="dst" />
+	<parameter type="constexpr int" varname="a" />
+	<parameter type="constexpr int" varname="b" />
+	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "a" with corresponding unsigned 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst".</description>
+	<operation>DEFINE DPBD(c, x, y) {
+	tmp1 := SignExtend32(x.byte[0]) * ZeroExtend32(y.byte[0])
+	tmp2 := SignExtend32(x.byte[1]) * ZeroExtend32(y.byte[1])
+	tmp3 := SignExtend32(x.byte[2]) * ZeroExtend32(y.byte[2])
+	tmp4 := SignExtend32(x.byte[3]) * ZeroExtend32(y.byte[3])
+	
+	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
+}
+FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (a.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, tmm, tmm" name="TDPBSUD" xed="TDPBSUD_TMMi32_TMMu32_TMMu32" />
+	<CPUID>AMX-INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_dpbusd" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="dst" />
+	<parameter type="constexpr int" varname="a" />
+	<parameter type="constexpr int" varname="b" />
+	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst".</description>
+	<operation>DEFINE DPBD(c, x, y) {
+	tmp1 := ZeroExtend32(x.byte[0]) * SignExtend32(y.byte[0])
+	tmp2 := ZeroExtend32(x.byte[1]) * SignExtend32(y.byte[1])
+	tmp3 := ZeroExtend32(x.byte[2]) * SignExtend32(y.byte[2])
+	tmp4 := ZeroExtend32(x.byte[3]) * SignExtend32(y.byte[3])
+	
+	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
+}
+FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (a.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, tmm, tmm" name="TDPBUSD" xed="TDPBUSD_TMMi32_TMMu32_TMMu32" />
+	<CPUID>AMX-INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_dpbuud" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="dst" />
+	<parameter type="constexpr int" varname="a" />
+	<parameter type="constexpr int" varname="b" />
+	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding unsigned 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst".</description>
+	<operation>DEFINE DPBD(c, x, y) {
+	tmp1 := ZeroExtend32(x.byte[0]) * ZeroExtend32(y.byte[0])
+	tmp2 := ZeroExtend32(x.byte[1]) * ZeroExtend32(y.byte[1])
+	tmp3 := ZeroExtend32(x.byte[2]) * ZeroExtend32(y.byte[2])
+	tmp4 := ZeroExtend32(x.byte[3]) * ZeroExtend32(y.byte[3])
+	
+	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
+}
+FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (a.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, tmm, tmm" name="TDPBUUD" xed="TDPBUUD_TMMu32_TMMu32_TMMu32" />
+	<CPUID>AMX-INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_dpbssd" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="dst" />
+	<parameter type="constexpr int" varname="a" />
+	<parameter type="constexpr int" varname="b" />
+	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst".</description>
+	<operation>DEFINE DPBD(c, x, y) {
+	tmp1 := SignExtend32(x.byte[0]) * SignExtend32(y.byte[0])
+	tmp2 := SignExtend32(x.byte[1]) * SignExtend32(y.byte[1])
+	tmp3 := SignExtend32(x.byte[2]) * SignExtend32(y.byte[2])
+	tmp4 := SignExtend32(x.byte[3]) * SignExtend32(y.byte[3])
+	
+	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
+}
+FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (a.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, tmm, tmm" name="TDPBSSD" xed="TDPBSSD_TMMi32_TMMu32_TMMu32" />
+	<CPUID>AMX-INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_dpbssd" tech="AMX">
+	<return type="void" />
+	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "src0" with corresponding signed 8-bit integers in "src1", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm, tmm, tmm" name="TDPBSSD" xed="TDPBSSD_TMMi32_TMMu32_TMMu32" />
+	<operation>DEFINE DPBD(c, x, y) {
+	tmp1 := SignExtend32(x.byte[0]) * SignExtend32(y.byte[0])
+	tmp2 := SignExtend32(x.byte[1]) * SignExtend32(y.byte[1])
+	tmp3 := SignExtend32(x.byte[2]) * SignExtend32(y.byte[2])
+	tmp4 := SignExtend32(x.byte[3]) * SignExtend32(y.byte[3])
+	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
+}
+FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (src0.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.dword[n] := DPBD(tmp.dword[n], src0.row[m].dword[k], src1.row[k].dword[n])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="__tile1024i" varname="src0" />
+	<parameter type="__tile1024i" varname="src1" />
+	<CPUID>AMX-INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_dpbsud" tech="AMX">
+	<return type="void" />
+	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "src0" with corresponding unsigned 8-bit integers in "src1", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm, tmm, tmm" name="TDPBSUD" xed="TDPBSUD_TMMi32_TMMu32_TMMu32" />
+	<operation>DEFINE DPBD(c, x, y) {
+	tmp1 := SignExtend32(x.byte[0]) * ZeroExtend32(y.byte[0])
+	tmp2 := SignExtend32(x.byte[1]) * ZeroExtend32(y.byte[1])
+	tmp3 := SignExtend32(x.byte[2]) * ZeroExtend32(y.byte[2])
+	tmp4 := SignExtend32(x.byte[3]) * ZeroExtend32(y.byte[3])
+	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
+}
+FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (src0.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.dword[n] := DPBD(tmp.dword[n], src0.row[m].dword[k], src1.row[k].dword[n])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="__tile1024i" varname="src0" />
+	<parameter type="__tile1024i" varname="src1" />
+	<CPUID>AMX-INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_dpbusd" tech="AMX">
+	<return type="void" />
+	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "src0" with corresponding signed 8-bit integers in "src1", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm, tmm, tmm" name="TDPBUSD" xed="TDPBUSD_TMMi32_TMMu32_TMMu32" />
+	<operation>DEFINE DPBD(c, x, y) {
+	tmp1 := ZeroExtend32(x.byte[0]) * SignExtend32(y.byte[0])
+	tmp2 := ZeroExtend32(x.byte[1]) * SignExtend32(y.byte[1])
+	tmp3 := ZeroExtend32(x.byte[2]) * SignExtend32(y.byte[2])
+	tmp4 := ZeroExtend32(x.byte[3]) * SignExtend32(y.byte[3])
+	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
+}
+FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (src0.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.dword[n] := DPBD(tmp.dword[n], src0.row[m].dword[k], src1.row[k].dword[n])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="__tile1024i" varname="src0" />
+	<parameter type="__tile1024i" varname="src1" />
+	<CPUID>AMX-INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_dpbuud" tech="AMX">
+	<return type="void" />
+	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "src0" with corresponding unsigned 8-bit integers in "src1", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm, tmm, tmm" name="TDPBUUD" xed="TDPBUUD_TMMu32_TMMu32_TMMu32" />
+	<operation>DEFINE DPBD(c, x, y) {
+	tmp1 := ZeroExtend32(x.byte[0]) * ZeroExtend32(y.byte[0])
+	tmp2 := ZeroExtend32(x.byte[1]) * ZeroExtend32(y.byte[1])
+	tmp3 := ZeroExtend32(x.byte[2]) * ZeroExtend32(y.byte[2])
+	tmp4 := ZeroExtend32(x.byte[3]) * ZeroExtend32(y.byte[3])
+	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
+}
+FOR m := 0 TO dst.rows - 1
+	tmp := dst.row[m]
+	FOR k := 0 TO (src0.colsb / 4) - 1
+		FOR n := 0 TO (dst.colsb / 4) - 1
+			tmp.dword[n] := DPBD(tmp.dword[n], src0.row[m].dword[k], src1.row[k].dword[n])
+		ENDFOR
+	ENDFOR
+	write_row_and_zero(dst, m, tmp, dst.colsb)
+ENDFOR
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="__tile1024i" varname="src0" />
+	<parameter type="__tile1024i" varname="src1" />
+	<CPUID>AMX-INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	
+<intrinsic name="_tile_loadconfig" tech="AMX">
+	<return type="void" />
+	<parameter memwidth="512" type="const void *" varname="mem_addr" />
+	<description>Load tile configuration from a 64-byte memory location specified by "mem_addr". The tile configuration format is specified below, and includes the tile type pallette, the number of bytes per row, and the number of rows. If the specified pallette_id is zero, that signifies the init state for both the tile config and the tile data, and the tiles are zeroed. Any invalid configurations will result in #GP fault.</description>
+	<operation>
+//	format of memory payload. each field is a byte.
+//		 0: palette
+//		 1: start_row
+//	 2-15: reserved, must be zero
+//	16-17: tile0.colsb
+//	18-19: tile1.colsb
+//	20-21: tile2.colsb
+//			...
+//	30-31: tile7.colsb
+//	32-47: reserved, must be zero
+//		48: tile0.rows
+//		49: tile1.rows
+//		50: tile2.rows
+//			 ...
+//		55: tile7.rows
+//	56-63: reserved, must be zero
+	</operation>
+	<instruction form="m512" name="LDTILECFG" xed="LDTILECFG_MEM" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_storeconfig" tech="AMX">
+	<return type="void" />
+	<parameter memwidth="512" type="void *" varname="mem_addr" />
+	<description>Stores the current tile configuration to a 64-byte memory location specified by "mem_addr". The tile configuration format is specified below, and includes the tile type pallette, the number of bytes per row, and the number of rows. If tiles are not configured, all zeroes will be stored to memory.</description>
+	<operation>
+//	format of memory payload. each field is a byte.
+//		 0: palette
+//		 1: start_row
+//	 2-15: reserved, must be zero
+//	16-17: tile0.colsb
+//	18-19: tile1.colsb
+//	20-21: tile2.colsb
+//			...
+//	30-31: tile7.colsb
+//	32-47: reserved, must be zero
+//		48: tile0.rows
+//		49: tile1.rows
+//		50: tile2.rows
+//			 ...
+//		55: tile7.rows
+//	56-63: reserved, must be zero
+	</operation>
+	<instruction form="m512" name="STTILECFG" xed="STTILECFG_MEM" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_loadd" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="dst" />
+	<parameter type="const void *" varname="base" />
+	<parameter etype="UI32" type="size_t" varname="stride" />
+	<description>Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst" using the tile configuration previously configured via "_tile_loadconfig".</description>
+	<operation>start := tileconfig.startRow
+IF start == 0 // not restarting, zero incoming state
+	tilezero(dst)
+FI
+nbytes := dst.colsb
+DO WHILE start &lt; dst.rows
+	memptr := base + start * stride
+	write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes)
+	start := start + 1
+OD
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, sibmem" name="TILELOADD" xed="TILELOADD_TMMu32_MEMu32" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_stream_loadd" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="dst" />
+	<parameter type="const void *" varname="base" />
+	<parameter etype="UI32" type="size_t" varname="stride" />
+	<description>Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst" using the tile configuration previously configured via "_tile_loadconfig". This intrinsic provides a hint to the implementation that the data will likely not be reused in the near future and the data caching can be optimized accordingly.</description>
+	<operation>start := tileconfig.startRow
+IF start == 0 // not restarting, zero incoming state
+	tilezero(dst)
+FI
+nbytes := dst.colsb
+DO WHILE start &lt; dst.rows
+	memptr := base + start * stride
+	write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes)
+	start := start + 1
+OD
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+	</operation>
+	<instruction form="tmm, sibmem" name="TILELOADDT1" xed="TILELOADDT1_TMMu32_MEMu32" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_release" tech="AMX">
+	<return type="void" />
+	<description>Release the tile configuration to return to the init state, which releases all storage it currently holds.</description>
+	<instruction name="TILERELEASE" xed="TILERELEASE" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_stored" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="src" />
+	<parameter type="void *" varname="base" />
+	<parameter etype="UI32" type="size_t" varname="stride" />
+	<description>Store the tile specified by "src" to memory specifieid by "base" address and "stride" using the tile configuration previously configured via "_tile_loadconfig".</description>
+	<operation>start := tileconfig.startRow
+DO WHILE start &lt; src.rows
+	memptr := base + start * stride
+	write_memory(memptr, src.colsb, src.row[start])
+	start := start + 1
+OD
+zero_tileconfig_start()
+	</operation>
+	<instruction form="sibmem, tmm" name="TILESTORED" xed="TILESTORED_MEMu32_TMMu32" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_tile_zero" tech="AMX">
+	<return type="void" />
+	<parameter type="constexpr int" varname="tdest" />
+	<description>Zero the tile specified by "tdest".</description>
+	<operation>nbytes := palette_table[tileconfig.palette_id].bytes_per_row
+FOR i := 0 TO palette_table[tileconfig.palette_id].max_rows-1
+	FOR j := 0 TO nbytes-1
+		tdest.row[i].byte[j] := 0
+	ENDFOR
+ENDFOR
+	</operation>
+	<instruction form="tmm" name="TILEZERO" xed="TILEZERO_TMMu32" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_loadd" tech="AMX">
+	<return type="void" />
+	<description>Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm, sibmem" name="TILELOADD" xed="TILELOADD_TMMu32_MEMu32" />
+	<operation>start := tileconfig.startRow
+IF start == 0 // not restarting, zero incoming state
+	tilezero(dst)
+FI
+nbytes := dst.colsb
+DO WHILE start &lt; dst.rows
+	memptr := base + start * stride
+	write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes)
+	start := start + 1
+OD
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="const void*" varname="base" />
+	<parameter type="size_t" varname="stride" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_stored" tech="AMX">
+	<return type="void" />
+	<description>Store the tile specified by "src" to memory specifieid by "base" address and "stride". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="sibmem, tmm" name="TILESTORED" xed="TILESTORED_MEMu32_TMMu32" />
+	<operation>start := tileconfig.startRow
+DO WHILE start &lt; src.rows
+	memptr := base + start * stride
+	write_memory(memptr, src.colsb, src.row[start])
+	start := start + 1
+OD
+zero_tileconfig_start()
+</operation>
+	<parameter type="void*" varname="base" />
+	<parameter type="size_t" varname="stride" />
+	<parameter type="__tile1024i" varname="src" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_stream_loadd" tech="AMX">
+	<return type="void" />
+	<description>Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst". This intrinsic provides a hint to the implementation that the data will likely not be reused in the near future and the data caching can be optimized accordingly. The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm, sibmem" name="TILELOADDT1" xed="TILELOADDT1_TMMu32_MEMu32" />
+	<operation>start := tileconfig.startRow
+IF start == 0 // not restarting, zero incoming state
+	tilezero(dst)
+FI
+nbytes := dst.colsb
+DO WHILE start &lt; dst.rows
+	memptr := base + start * stride
+	write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes)
+	start := start + 1
+OD
+zero_upper_rows(dst, dst.rows)
+zero_tileconfig_start()
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<parameter type="const void*" varname="base" />
+	<parameter type="size_t" varname="stride" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	<intrinsic name="__tile_zero" tech="AMX">
+	<return type="void" />
+	<description>Zero the tile specified by "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
+	<instruction form="tmm" name="TILEZERO" xed="TILEZERO_TMMu32" />
+	<operation>nbytes := palette_table[tileconfig.palette_id].bytes_per_row
+FOR i := 0 TO palette_table[tileconfig.palette_id].max_rows-1
+	FOR j := 0 TO nbytes-1
+		tdest.row[i].byte[j] := 0
+	ENDFOR
+ENDFOR
+</operation>
+	<parameter type="__tile1024i*" varname="dst" />
+	<CPUID>AMX-TILE</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	
+<intrinsic name="_mm256_acos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ACOS(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_acos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ACOS(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_acosh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ACOSH(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_acosh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ACOSH(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_asin_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ASIN(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_asin_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ASIN(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_asinh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ASINH(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_asinh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ASINH(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_atan_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ATAN(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_atan_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ATAN(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_atan2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_atan2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_atanh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ATANH(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_atanh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ATANH(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := COS(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := COS(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cosd_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := COSD(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cosd_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := COSD(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cosh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := COSH(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cosh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := COSH(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hypot_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hypot_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sin_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SIN(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sin_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SIN(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sincos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" memwidth="256" type="__m256d *" varname="mem_addr" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SIN(a[i+63:i])
+	MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sincos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" memwidth="256" type="__m256 *" varname="mem_addr" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SIN(a[i+31:i])
+	MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sind_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SIND(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sind_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SIND(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sinh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SINH(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sinh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SINH(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_tan_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := TAN(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_tan_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := TAN(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_tand_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := TAND(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_tand_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := TAND(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_tanh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := TANH(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_tanh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := TANH(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cbrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := CubeRoot(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cbrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := CubeRoot(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cexp_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+	<operation>
+DEFINE CEXP(a[31:0], b[31:0]) {
+	result[31:0]  := POW(FP32(e), a[31:0]) * COS(b[31:0])
+	result[63:32] := POW(FP32(e), a[31:0]) * SIN(b[31:0])
+	RETURN result
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := CEXP(a[i+31:i], a[i+63:i+32])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_clog_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the natural logarithm of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+	<operation>
+DEFINE CLOG(a[31:0], b[31:0]) {
+	result[31:0]  := LOG(SQRT(POW(a, 2.0) + POW(b, 2.0)))
+	result[63:32] := ATAN2(b, a)
+	RETURN result
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := CLOG(a[i+31:i], a[i+63:i+32])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_csqrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the square root of packed complex snumbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+	<operation>
+DEFINE CSQRT(a[31:0], b[31:0]) {
+	sign[31:0] := (b &lt; 0.0) ? -FP32(1.0) : FP32(1.0)
+	result[31:0]  := SQRT((a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
+	result[63:32] := sign * SQRT((-a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
+	RETURN result
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := CSQRT(a[i+31:i], a[i+63:i+32])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_exp_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := POW(e, a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_exp_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := POW(FP32(e), a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_exp10_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := POW(10.0, a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_exp10_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_exp2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := POW(2.0, a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_exp2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_expm1_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_expm1_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_invcbrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := InvCubeRoot(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_invcbrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := InvCubeRoot(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_invsqrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := InvSQRT(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_invsqrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := InvSQRT(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_log_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_log_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_log10_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_log10_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_log1p_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := LOG(1.0 + a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_log1p_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := LOG(1.0 + a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_log2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_log2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_logb_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_logb_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_pow_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_pow_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_svml_sqrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SQRT(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_svml_sqrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SQRT(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cdfnorm_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := CDFNormal(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cdfnorm_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := CDFNormal(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cdfnorminv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := InverseCDFNormal(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cdfnorminv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := InverseCDFNormal(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_erf_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ERF(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_erf_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ERF(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_erfc_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := 1.0 - ERF(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_erfc_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+63:i] := 1.0 - ERF(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_erfcinv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_erfcinv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_erfinv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := 1.0 / ERF(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_erfinv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+63:i] := 1.0 / ERF(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_epi8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 8*j
+	IF b[i+7:i] == 0
+		#DE
+	FI
+	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_epi16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	IF b[i+15:i] == 0
+		#DE
+	FI
+	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF b[i+31:i] == 0
+		#DE
+	FI
+	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_epi64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	IF b[i+63:i] == 0
+		#DE
+	FI
+	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_epu8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 8*j
+	IF b[i+7:i] == 0
+		#DE
+	FI
+	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_epu16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	IF b[i+15:i] == 0
+		#DE
+	FI
+	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_epu32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF b[i+31:i] == 0
+		#DE
+	FI
+	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_epu64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	IF b[i+63:i] == 0
+		#DE
+	FI
+	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_idiv_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_idivrem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" memwidth="256" type="__m256i *" varname="mem_addr" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr".</description>
+	<operation>FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_irem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rem_epi8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 31
+	i := 8*j
+	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rem_epi16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := 16*j
+	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rem_epi64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := 64*j
+	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rem_epu8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 31
+	i := 8*j
+	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rem_epu16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := 16*j
+	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rem_epu32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rem_epu64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := 64*j
+	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_udiv_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_udivrem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" memwidth="256" type="__m256i *" varname="mem_addr" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr".</description>
+	<operation>FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_urem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_svml_ceil_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := CEIL(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_svml_ceil_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := CEIL(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_svml_floor_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := FLOOR(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_svml_floor_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := FLOOR(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_svml_round_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ROUND(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_svml_round_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ROUND(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_trunc_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := TRUNCATE(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_trunc_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := TRUNCATE(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_add_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VADDPD" xed="VADDPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_add_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VADDPS" xed="VADDPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_addsub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF ((j &amp; 1) == 0)
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VADDSUBPD" xed="VADDSUBPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_addsub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF ((j &amp; 1) == 0)
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VADDSUBPS" xed="VADDSUBPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VDIVPD" xed="VDIVPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VDIVPS" xed="VDIVPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dp_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".</description>
+	<operation>
+DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
+	FOR j := 0 to 3
+		i := j*32
+		IF imm8[(4+j)%8]
+			temp[i+31:i] := a[i+31:i] * b[i+31:i]
+		ELSE
+			temp[i+31:i] := FP32(0.0)
+		FI
+	ENDFOR
+	
+	sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0])
+	
+	FOR j := 0 to 3
+		i := j*32
+		IF imm8[j%8]
+			tmpdst[i+31:i] := sum[31:0]
+		ELSE
+			tmpdst[i+31:i] := FP32(0.0)
+		FI
+	ENDFOR
+	RETURN tmpdst[127:0]
+}
+dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])
+dst[255:128] := DP(a[255:128], b[255:128], imm8[7:0])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VDPPS" xed="VDPPS_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hadd_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+	<operation>
+dst[63:0] := a[127:64] + a[63:0]
+dst[127:64] := b[127:64] + b[63:0]
+dst[191:128] := a[255:192] + a[191:128]
+dst[255:192] := b[255:192] + b[191:128]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VHADDPD" xed="VHADDPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hadd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32] + a[31:0]
+dst[63:32] := a[127:96] + a[95:64]
+dst[95:64] := b[63:32] + b[31:0]
+dst[127:96] := b[127:96] + b[95:64]
+dst[159:128] := a[191:160] + a[159:128]
+dst[191:160] := a[255:224] + a[223:192]
+dst[223:192] := b[191:160] + b[159:128]
+dst[255:224] := b[255:224] + b[223:192]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VHADDPS" xed="VHADDPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hsub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+	<operation>
+dst[63:0] := a[63:0] - a[127:64]
+dst[127:64] := b[63:0] - b[127:64]
+dst[191:128] := a[191:128] - a[255:192]
+dst[255:192] := b[191:128] - b[255:192]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VHSUBPD" xed="VHSUBPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hsub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Horizontally subtract adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] - a[63:32]
+dst[63:32] := a[95:64] - a[127:96]
+dst[95:64] := b[31:0] - b[63:32]
+dst[127:96] := b[95:64] - b[127:96]
+dst[159:128] := a[159:128] - a[191:160]
+dst[191:160] := a[223:192] - a[255:224]
+dst[223:192] := b[159:128] - b[191:160]
+dst[255:224] := b[223:192] - b[255:224]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VHSUBPS" xed="VHSUBPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mul_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMULPD" xed="VMULPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mul_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMULPS" xed="VMULPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VSUBPD" xed="VSUBPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VSUBPS" xed="VSUBPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_and_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VANDPD" xed="VANDPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_and_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VANDPS" xed="VANDPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_andnot_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VANDNPD" xed="VANDNPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_andnot_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VANDNPS" xed="VANDNPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_or_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VORPD" xed="VORPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_or_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VORPS" xed="VORPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_xor_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VXORPD" xed="VXORPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_xor_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VXORPS" xed="VXORPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testz_si256" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+	<operation>
+IF ((a[255:0] AND b[255:0]) == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+IF (((NOT a[255:0]) AND b[255:0]) == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+RETURN ZF
+	</operation>
+	<instruction form="ymm, ymm" name="VPTEST" xed="VPTEST_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testc_si256" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+	<operation>
+IF ((a[255:0] AND b[255:0]) == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+IF (((NOT a[255:0]) AND b[255:0]) == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+RETURN CF
+	</operation>
+	<instruction form="ymm, ymm" name="VPTEST" xed="VPTEST_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testnzc_si256" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+	<operation>
+IF ((a[255:0] AND b[255:0]) == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+IF (((NOT a[255:0]) AND b[255:0]) == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+IF (ZF == 0 &amp;&amp; CF == 0)
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="ymm, ymm" name="VPTEST" xed="VPTEST_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testz_pd" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+	<operation>
+tmp[255:0] := a[255:0] AND b[255:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := ZF
+	</operation>
+	<instruction form="ymm, ymm" name="VTESTPD" xed="VTESTPD_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testc_pd" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+	<operation>
+tmp[255:0] := a[255:0] AND b[255:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := CF
+	</operation>
+	<instruction form="ymm, ymm" name="VTESTPD" xed="VTESTPD_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testnzc_pd" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+	<operation>
+tmp[255:0] := a[255:0] AND b[255:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+IF (ZF == 0 &amp;&amp; CF == 0)
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="ymm, ymm" name="VTESTPD" xed="VTESTPD_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_testz_pd" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+	<operation>
+tmp[127:0] := a[127:0] AND b[127:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := ZF
+	</operation>
+	<instruction form="xmm, xmm" name="VTESTPD" xed="VTESTPD_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_testc_pd" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+	<operation>
+tmp[127:0] := a[127:0] AND b[127:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := CF
+	</operation>
+	<instruction form="xmm, xmm" name="VTESTPD" xed="VTESTPD_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_testnzc_pd" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+	<operation>
+tmp[127:0] := a[127:0] AND b[127:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+IF (ZF == 0 &amp;&amp; CF == 0)
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="xmm, xmm" name="VTESTPD" xed="VTESTPD_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testz_ps" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+	<operation>
+tmp[255:0] := a[255:0] AND b[255:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := ZF
+	</operation>
+	<instruction form="ymm, ymm" name="VTESTPS" xed="VTESTPS_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testc_ps" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+	<operation>
+tmp[255:0] := a[255:0] AND b[255:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := CF
+	</operation>
+	<instruction form="ymm, ymm" name="VTESTPS" xed="VTESTPS_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testnzc_ps" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+	<operation>
+tmp[255:0] := a[255:0] AND b[255:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[255:0] := (NOT a[255:0]) AND b[255:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
+    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+IF (ZF == 0 &amp;&amp; CF == 0)
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="ymm, ymm" name="VTESTPS" xed="VTESTPS_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_testz_ps" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+	<operation>
+tmp[127:0] := a[127:0] AND b[127:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := ZF
+	</operation>
+	<instruction form="xmm, xmm" name="VTESTPS" xed="VTESTPS_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_testc_ps" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+	<operation>
+tmp[127:0] := a[127:0] AND b[127:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := CF
+	</operation>
+	<instruction form="xmm, xmm" name="VTESTPS" xed="VTESTPS_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_testnzc_ps" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+	<operation>
+tmp[127:0] := a[127:0] AND b[127:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+tmp[127:0] := (NOT a[127:0]) AND b[127:0]
+IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+IF (ZF == 0 &amp;&amp; CF == 0)
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="xmm, xmm" name="VTESTPS" xed="VTESTPS_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_blend_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF imm8[j]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VBLENDPD" xed="VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_blend_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF imm8[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VBLENDPS" xed="VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_blendv_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="MASK" type="__m256d" varname="mask" />
+	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF mask[i+63]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, ymm" name="VBLENDVPD" xed="VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_blendv_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="MASK" type="__m256" varname="mask" />
+	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF mask[i+31]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, ymm" name="VBLENDVPS" xed="VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shuffle_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFPD" xed="VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shuffle_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFPS" xed="VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extractf128_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VEXTRACTF128" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extractf128_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VEXTRACTF128" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extractf128_si256" tech="AVX_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VEXTRACTF128" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extract_epi32" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI32" type="__int32" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="3" type="const int" varname="index" />
+	<description>Extract a 32-bit integer from "a", selected with "index", and store the result in "dst".</description>
+	<operation>
+dst[31:0] := (a[255:0] &gt;&gt; (index[2:0] * 32))[31:0]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extract_epi64" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="index" />
+	<description>Extract a 64-bit integer from "a", selected with "index", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := (a[255:0] &gt;&gt; (index[1:0] * 64))[63:0]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutevar_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], b[1:0])
+dst[63:32] := SELECT4(a[127:0], b[33:32])
+dst[95:64] := SELECT4(a[127:0], b[65:64])
+dst[127:96] := SELECT4(a[127:0], b[97:96])
+dst[159:128] := SELECT4(a[255:128], b[129:128])
+dst[191:160] := SELECT4(a[255:128], b[161:160])
+dst[223:192] := SELECT4(a[255:128], b[193:192])
+dst[255:224] := SELECT4(a[255:128], b[225:224])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMILPS" xed="VPERMILPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutevar_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], b[1:0])
+dst[63:32] := SELECT4(a[127:0], b[33:32])
+dst[95:64] := SELECT4(a[127:0], b[65:64])
+dst[127:96] := SELECT4(a[127:0], b[97:96])
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMILPS" xed="VPERMILPS_XMMdq_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permute_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPERMILPS" xed="VPERMILPS_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_permute_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VPERMILPS" xed="VPERMILPS_XMMdq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutevar_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
+	<operation>
+IF (b[1] == 0) dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) dst[127:64] := a[127:64]; FI
+IF (b[129] == 0) dst[191:128] := a[191:128]; FI
+IF (b[129] == 1) dst[191:128] := a[255:192]; FI
+IF (b[193] == 0) dst[255:192] := a[191:128]; FI
+IF (b[193] == 1) dst[255:192] := a[255:192]; FI
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMILPD" xed="VPERMILPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutevar_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst".</description>
+	<operation>
+IF (b[1] == 0) dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) dst[127:64] := a[127:64]; FI
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMILPD" xed="VPERMILPD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permute_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
+IF (imm8[2] == 0) dst[191:128] := a[191:128]; FI
+IF (imm8[2] == 1) dst[191:128] := a[255:192]; FI
+IF (imm8[3] == 0) dst[255:192] := a[191:128]; FI
+IF (imm8[3] == 1) dst[255:192] := a[255:192]; FI
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPERMILPD" xed="VPERMILPD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_permute_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VPERMILPD" xed="VPERMILPD_XMMdq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permute2f128_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src1, src2, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src1[127:0]
+	1:	tmp[127:0] := src1[255:128]
+	2:	tmp[127:0] := src2[127:0]
+	3:	tmp[127:0] := src2[255:128]
+	ESAC
+	IF control[3]
+		tmp[127:0] := 0
+	FI
+	RETURN tmp[127:0]
+}
+dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
+dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPERM2F128" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permute2f128_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src1, src2, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src1[127:0]
+	1:	tmp[127:0] := src1[255:128]
+	2:	tmp[127:0] := src2[127:0]
+	3:	tmp[127:0] := src2[255:128]
+	ESAC
+	IF control[3]
+		tmp[127:0] := 0
+	FI
+	RETURN tmp[127:0]
+}
+dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
+dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPERM2F128" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permute2f128_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src1, src2, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src1[127:0]
+	1:	tmp[127:0] := src1[255:128]
+	2:	tmp[127:0] := src2[127:0]
+	3:	tmp[127:0] := src2[255:128]
+	ESAC
+	IF control[3]
+		tmp[127:0] := 0
+	FI
+	RETURN tmp[127:0]
+}
+dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
+dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPERM2F128" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insertf128_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insertf128_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[255:0] := a[255:0]
+CASE imm8[0] OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insertf128_si256" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insert_epi8" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__int8" varname="i" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="index" />
+	<description>Copy "a" to "dst", and insert the 8-bit integer "i" into "dst" at the location specified by "index".</description>
+	<operation>
+dst[255:0] := a[255:0]
+sel := index[4:0]*8
+dst[sel+7:sel] := i[7:0]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insert_epi16" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__int16" varname="i" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="index" />
+	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "index".</description>
+	<operation>
+dst[255:0] := a[255:0]
+sel := index[3:0]*16
+dst[sel+15:sel] := i[15:0]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insert_epi32" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__int32" varname="i" />
+	<parameter etype="IMM" immwidth="3" type="const int" varname="index" />
+	<description>Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "index".</description>
+	<operation>
+dst[255:0] := a[255:0]
+sel := index[2:0]*32
+dst[sel+31:sel] := i[31:0]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insert_epi64" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__int64" varname="i" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="index" />
+	<description>Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "index".</description>
+	<operation>
+dst[255:0] := a[255:0]
+sel := index[1:0]*64
+dst[sel+63:sel] := i[63:0]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpackhi_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VUNPCKHPD" xed="VUNPCKHPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpackhi_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VUNPCKHPS" xed="VUNPCKHPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpacklo_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VUNPCKLPD" xed="VUNPCKLPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpacklo_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VUNPCKLPS" xed="VUNPCKLPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMAXPD" xed="VMAXPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMAXPS" xed="VMAXPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMINPD" xed="VMINPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMINPS" xed="VMINPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_round_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ROUND(a[i+63:i], rounding)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VROUNDPD" xed="VROUNDPD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_round_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ROUND(a[i+31:i], rounding)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VROUNDPS" xed="VROUNDPS_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_floor_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := FLOOR(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VROUNDPS" xed="VROUNDPS_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_ceil_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := CEIL(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VROUNDPS" xed="VROUNDPS_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_floor_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := FLOOR(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VROUNDPD" xed="VROUNDPD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_ceil_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := CEIL(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VROUNDPD" xed="VROUNDPD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VCMPPD" xed="VCMPPD_XMMdq_XMMdq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VCMPPD" xed="VCMPPD_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VCMPPS" xed="VCMPPS_XMMdq_XMMdq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VCMPPS" xed="VCMPPS_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_sd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+dst[63:0] := ( a[63:0] OP b[63:0] ) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VCMPSD" xed="VCMPSD_XMMdq_XMMdq_XMMq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_ss" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+dst[31:0] := ( a[31:0] OP b[31:0] ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VCMPSS" xed="VCMPSS_XMMdq_XMMdq_XMMd_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi32_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_YMMqq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi32_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTDQ2PS" xed="VCVTDQ2PS_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtpd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMdq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtps_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTPS2DQ" xed="VCVTPS2DQ_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtps_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPS2PD" xed="VCVTPS2PD_YMMqq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttpd_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMdq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtpd_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMdq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttps_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtss_f32" vexEq="TRUE" tech="AVX_ALL">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+	</operation>
+	<instruction form="m32, xmm" name="VMOVSS" xed="VMOVSS_MEMd_XMMd" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsd_f64" vexEq="TRUE" tech="AVX_ALL">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="m64, xmm" name="VMOVSD" xed="VMOVSD_MEMq_XMMq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsi256_si32" vexEq="TRUE" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+	</operation>
+	<instruction form="r32, xmm" name="VMOVD" xed="VMOVD_GPR32d_XMMd" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_zeroall" tech="AVX_ALL">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Zero the contents of all XMM or YMM registers.</description>
+	<operation>YMM0[MAX:0] := 0
+YMM1[MAX:0] := 0
+YMM2[MAX:0] := 0
+YMM3[MAX:0] := 0
+YMM4[MAX:0] := 0
+YMM5[MAX:0] := 0
+YMM6[MAX:0] := 0
+YMM7[MAX:0] := 0
+IF _64_BIT_MODE
+	YMM8[MAX:0] := 0
+	YMM9[MAX:0] := 0
+	YMM10[MAX:0] := 0
+	YMM11[MAX:0] := 0
+	YMM12[MAX:0] := 0
+	YMM13[MAX:0] := 0
+	YMM14[MAX:0] := 0
+	YMM15[MAX:0] := 0
+FI
+	</operation>
+	<instruction name="VZEROALL" xed="VZEROALL" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm256_zeroupper" tech="AVX_ALL">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Zero the upper 128 bits of all YMM registers; the lower 128-bits of the registers are unmodified.</description>
+	<operation>YMM0[MAX:128] := 0
+YMM1[MAX:128] := 0
+YMM2[MAX:128] := 0
+YMM3[MAX:128] := 0
+YMM4[MAX:128] := 0
+YMM5[MAX:128] := 0
+YMM6[MAX:128] := 0
+YMM7[MAX:128] := 0
+IF _64_BIT_MODE
+	YMM8[MAX:128] := 0
+	YMM9[MAX:128] := 0
+	YMM10[MAX:128] := 0
+	YMM11[MAX:128] := 0
+	YMM12[MAX:128] := 0
+	YMM13[MAX:128] := 0
+	YMM14[MAX:128] := 0
+	YMM15[MAX:128] := 0
+FI
+	</operation>
+	<instruction name="VZEROUPPER" xed="VZEROUPPER" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm256_undefined_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m256 with undefined elements.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm256_undefined_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m256d with undefined elements.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm256_undefined_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m256i with undefined elements.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_ss" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" memwidth="32" type="float const *" varname="mem_addr" />
+	<description>Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst".</description>
+	<operation>
+tmp[31:0] := MEM[mem_addr+31:mem_addr]
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := tmp[31:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m32" name="VBROADCASTSS" xed="VBROADCASTSS_YMMqq_MEMd" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcast_ss" tech="AVX_ALL">
+	<category>Swizzle</category>
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="32" type="float const *" varname="mem_addr" />
+	<description>Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst".</description>
+	<operation>
+tmp[31:0] := MEM[mem_addr+31:mem_addr]
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := tmp[31:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m32" name="VBROADCASTSS" xed="VBROADCASTSS_XMMdq_MEMd" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_sd" tech="AVX_ALL">
+	<category>Swizzle</category>
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" memwidth="64" type="double const *" varname="mem_addr" />
+	<description>Broadcast a double-precision (64-bit) floating-point element from memory to all elements of "dst".</description>
+	<operation>
+tmp[63:0] := MEM[mem_addr+63:mem_addr]
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := tmp[63:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m64" name="VBROADCASTSD" xed="VBROADCASTSD_YMMqq_MEMq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_ps" tech="AVX_ALL">
+	<category>Swizzle</category>
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" memwidth="128" type="__m128 const *" varname="mem_addr" />
+	<description>Broadcast 128 bits from memory (composed of 4 packed single-precision (32-bit) floating-point elements) to all elements of "dst".</description>
+	<operation>
+tmp[127:0] := MEM[mem_addr+127:mem_addr]
+dst[127:0] := tmp[127:0]
+dst[255:128] := tmp[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m128" name="VBROADCASTF128" xed="VBROADCASTF128_YMMqq_MEMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_pd" tech="AVX_ALL">
+	<category>Swizzle</category>
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" memwidth="128" type="__m128d const *" varname="mem_addr" />
+	<description>Broadcast 128 bits from memory (composed of 2 packed double-precision (64-bit) floating-point elements) to all elements of "dst".</description>
+	<operation>
+tmp[127:0] := MEM[mem_addr+127:mem_addr]
+dst[127:0] := tmp[127:0]
+dst[255:128] := tmp[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m128" name="VBROADCASTF128" xed="VBROADCASTF128_YMMqq_MEMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_load_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" memwidth="256" type="double const *" varname="mem_addr" />
+	<description>Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst".
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVAPD" xed="VMOVAPD_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_load_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" memwidth="256" type="float const *" varname="mem_addr" />
+	<description>Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst".
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVAPS" xed="VMOVAPS_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" memwidth="256" type="double const *" varname="mem_addr" />
+	<description>Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVUPD" xed="VMOVUPD_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" memwidth="256" type="float const *" varname="mem_addr" />
+	<description>Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVUPS" xed="VMOVUPS_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_load_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" memwidth="256" type="__m256i const *" varname="mem_addr" />
+	<description>Load 256-bits of integer data from memory into "dst".
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVDQA" xed="VMOVDQA_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" memwidth="256" type="__m256i const *" varname="mem_addr" />
+	<description>Load 256-bits of integer data from memory into "dst".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVDQU" xed="VMOVDQU_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskload_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" memwidth="256" type="double const *" varname="mem_addr" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF mask[i+63]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, m256" name="VMASKMOVPD" xed="VMASKMOVPD_YMMqq_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskload_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="128" type="double const *" varname="mem_addr" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF mask[i+63]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, m128" name="VMASKMOVPD" xed="VMASKMOVPD_XMMdq_XMMdq_MEMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskload_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" memwidth="256" type="float const *" varname="mem_addr" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF mask[i+31]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, m256" name="VMASKMOVPS" xed="VMASKMOVPS_YMMqq_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskload_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="128" type="float const *" varname="mem_addr" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF mask[i+31]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, m128" name="VMASKMOVPS" xed="VMASKMOVPS_XMMdq_XMMdq_MEMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_lddqu_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" memwidth="256" type="__m256i const *" varname="mem_addr" />
+	<description>Load 256-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm256_loadu_si256" when the data crosses a cache line boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VLDDQU" xed="VLDDQU_YMMqq_MEMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu2_m128" sequence="TRUE" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" memwidth="128" type="float const*" varname="hiaddr" />
+	<parameter etype="FP32" memwidth="128" type="float const*" varname="loaddr" />
+	<description>Load two 128-bit values (composed of 4 packed single-precision (32-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst".
+	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[loaddr+127:loaddr]
+dst[255:128] := MEM[hiaddr+127:hiaddr]
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu2_m128d" sequence="TRUE" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" memwidth="128" type="double const*" varname="hiaddr" />
+	<parameter etype="FP64" memwidth="128" type="double const*" varname="loaddr" />
+	<description>Load two 128-bit values (composed of 2 packed double-precision (64-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst".
+	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[loaddr+127:loaddr]
+dst[255:128] := MEM[hiaddr+127:hiaddr]
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu2_m128i" sequence="TRUE" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="hiaddr" />
+	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="loaddr" />
+	<description>Load two 128-bit values (composed of integer data) from memory, and combine them into a 256-bit value in "dst".
+	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[loaddr+127:loaddr]
+dst[255:128] := MEM[hiaddr+127:hiaddr]
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_store_pd" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="256" type="double *" varname="mem_addr" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory.
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVAPD" xed="VMOVAPD_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_store_ps" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="256" type="float *" varname="mem_addr" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory.
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVAPS" xed="VMOVAPS_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu_pd" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="256" type="double *" varname="mem_addr" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory.
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVUPD" xed="VMOVUPD_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu_ps" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="256" type="float *" varname="mem_addr" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory.
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVUPS" xed="VMOVUPS_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_store_si256" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="M256" memwidth="256" type="__m256i *" varname="mem_addr" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<description>Store 256-bits of integer data from "a" into memory.
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVDQA" xed="VMOVDQA_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu_si256" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="M256" memwidth="256" type="__m256i *" varname="mem_addr" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<description>Store 256-bits of integer data from "a" into memory.
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVDQU" xed="VMOVDQU_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskstore_pd" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="256" type="double *" varname="mem_addr" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF mask[i+63]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256, ymm, ymm" name="VMASKMOVPD" xed="VMASKMOVPD_MEMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskstore_pd" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="double *" varname="mem_addr" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF mask[i+63]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128, xmm, xmm" name="VMASKMOVPD" xed="VMASKMOVPD_MEMdq_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskstore_ps" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="256" type="float *" varname="mem_addr" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF mask[i+31]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256, ymm, ymm" name="VMASKMOVPS" xed="VMASKMOVPS_MEMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskstore_ps" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="float *" varname="mem_addr" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF mask[i+31]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128, xmm, xmm" name="VMASKMOVPS" xed="VMASKMOVPS_MEMdq_XMMdq_XMMdq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_stream_si256" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="M256" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<description>Store 256-bits of integer data from "a" into memory using a non-temporal memory hint.
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVNTDQ" xed="VMOVNTDQ_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_stream_pd" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVNTPD" xed="VMOVNTPD_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_stream_ps" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVNTPS" xed="VMOVNTPS_MEMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu2_m128" sequence="TRUE" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="float*" varname="hiaddr" />
+	<parameter etype="FP32" memwidth="128" type="float*" varname="loaddr" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Store the high and low 128-bit halves (each composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory two different 128-bit locations.
+	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[loaddr+127:loaddr] := a[127:0]
+MEM[hiaddr+127:hiaddr] := a[255:128]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu2_m128d" sequence="TRUE" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="double*" varname="hiaddr" />
+	<parameter etype="FP64" memwidth="128" type="double*" varname="loaddr" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Store the high and low 128-bit halves (each composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory two different 128-bit locations.
+	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[loaddr+127:loaddr] := a[127:0]
+MEM[hiaddr+127:hiaddr] := a[255:128]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu2_m128i" sequence="TRUE" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="M128" memwidth="128" type="__m128i*" varname="hiaddr" />
+	<parameter etype="M128" memwidth="128" type="__m128i*" varname="loaddr" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<description>Store the high and low 128-bit halves (each composed of integer data) from "a" into memory two different 128-bit locations.
+	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[loaddr+127:loaddr] := a[127:0]
+MEM[hiaddr+127:hiaddr] := a[255:128]
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movehdup_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32] 
+dst[63:32] := a[63:32] 
+dst[95:64] := a[127:96] 
+dst[127:96] := a[127:96]
+dst[159:128] := a[191:160] 
+dst[191:160] := a[191:160] 
+dst[223:192] := a[255:224] 
+dst[255:224] := a[255:224]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VMOVSHDUP" xed="VMOVSHDUP_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_moveldup_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] 
+dst[63:32] := a[31:0] 
+dst[95:64] := a[95:64] 
+dst[127:96] := a[95:64]
+dst[159:128] := a[159:128] 
+dst[191:160] := a[159:128] 
+dst[223:192] := a[223:192] 
+dst[255:224] := a[223:192]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VMOVSLDUP" xed="VMOVSLDUP_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movedup_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := a[63:0]
+dst[191:128] := a[191:128]
+dst[255:192] := a[191:128]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VMOVDDUP" xed="VMOVDDUP_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rcp_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := 1.0 / a[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VRCPPS" xed="VRCPPS_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rsqrt_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VRSQRTPS" xed="VRSQRTPS_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sqrt_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SQRT(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VSQRTPD" xed="VSQRTPD_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sqrt_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SQRT(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VSQRTPS" xed="VSQRTPS_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movemask_pd" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF a[i+63]
+		dst[j] := 1
+	ELSE
+		dst[j] := 0
+	FI
+ENDFOR
+dst[MAX:4] := 0
+	</operation>
+	<instruction form="r32, ymm" name="VMOVMSKPD" xed="VMOVMSKPD_GPR32d_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movemask_ps" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF a[i+31]
+		dst[j] := 1
+	ELSE
+		dst[j] := 0
+	FI
+ENDFOR
+dst[MAX:8] := 0
+	</operation>
+	<instruction form="r32, ymm" name="VMOVMSKPS" xed="VMOVMSKPS_GPR32d_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setzero_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m256d with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VXORPD" xed="VXORPD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setzero_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m256 with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VXORPS" xed="VXORPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setzero_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m256i with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPXOR" xed="VPXOR_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_pd" sequence="TRUE" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="e3" />
+	<parameter etype="FP64" type="double" varname="e2" />
+	<parameter etype="FP64" type="double" varname="e1" />
+	<parameter etype="FP64" type="double" varname="e0" />
+	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst[63:0] := e0
+dst[127:64] := e1
+dst[191:128] := e2
+dst[255:192] := e3
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_ps" sequence="TRUE" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="float" varname="e7" />
+	<parameter etype="FP32" type="float" varname="e6" />
+	<parameter etype="FP32" type="float" varname="e5" />
+	<parameter etype="FP32" type="float" varname="e4" />
+	<parameter etype="FP32" type="float" varname="e3" />
+	<parameter etype="FP32" type="float" varname="e2" />
+	<parameter etype="FP32" type="float" varname="e1" />
+	<parameter etype="FP32" type="float" varname="e0" />
+	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst[31:0] := e0
+dst[63:32] := e1
+dst[95:64] := e2
+dst[127:96] := e3
+dst[159:128] := e4
+dst[191:160] := e5
+dst[223:192] := e6
+dst[255:224] := e7
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_epi8" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="char" varname="e31" />
+	<parameter etype="UI8" type="char" varname="e30" />
+	<parameter etype="UI8" type="char" varname="e29" />
+	<parameter etype="UI8" type="char" varname="e28" />
+	<parameter etype="UI8" type="char" varname="e27" />
+	<parameter etype="UI8" type="char" varname="e26" />
+	<parameter etype="UI8" type="char" varname="e25" />
+	<parameter etype="UI8" type="char" varname="e24" />
+	<parameter etype="UI8" type="char" varname="e23" />
+	<parameter etype="UI8" type="char" varname="e22" />
+	<parameter etype="UI8" type="char" varname="e21" />
+	<parameter etype="UI8" type="char" varname="e20" />
+	<parameter etype="UI8" type="char" varname="e19" />
+	<parameter etype="UI8" type="char" varname="e18" />
+	<parameter etype="UI8" type="char" varname="e17" />
+	<parameter etype="UI8" type="char" varname="e16" />
+	<parameter etype="UI8" type="char" varname="e15" />
+	<parameter etype="UI8" type="char" varname="e14" />
+	<parameter etype="UI8" type="char" varname="e13" />
+	<parameter etype="UI8" type="char" varname="e12" />
+	<parameter etype="UI8" type="char" varname="e11" />
+	<parameter etype="UI8" type="char" varname="e10" />
+	<parameter etype="UI8" type="char" varname="e9" />
+	<parameter etype="UI8" type="char" varname="e8" />
+	<parameter etype="UI8" type="char" varname="e7" />
+	<parameter etype="UI8" type="char" varname="e6" />
+	<parameter etype="UI8" type="char" varname="e5" />
+	<parameter etype="UI8" type="char" varname="e4" />
+	<parameter etype="UI8" type="char" varname="e3" />
+	<parameter etype="UI8" type="char" varname="e2" />
+	<parameter etype="UI8" type="char" varname="e1" />
+	<parameter etype="UI8" type="char" varname="e0" />
+	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[7:0] := e0
+dst[15:8] := e1
+dst[23:16] := e2
+dst[31:24] := e3
+dst[39:32] := e4
+dst[47:40] := e5
+dst[55:48] := e6
+dst[63:56] := e7
+dst[71:64] := e8
+dst[79:72] := e9
+dst[87:80] := e10
+dst[95:88] := e11
+dst[103:96] := e12
+dst[111:104] := e13
+dst[119:112] := e14
+dst[127:120] := e15
+dst[135:128] := e16
+dst[143:136] := e17
+dst[151:144] := e18
+dst[159:152] := e19
+dst[167:160] := e20
+dst[175:168] := e21
+dst[183:176] := e22
+dst[191:184] := e23
+dst[199:192] := e24
+dst[207:200] := e25
+dst[215:208] := e26
+dst[223:216] := e27
+dst[231:224] := e28
+dst[239:232] := e29
+dst[247:240] := e30
+dst[255:248] := e31
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_epi16" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="e15" />
+	<parameter etype="UI16" type="short" varname="e14" />
+	<parameter etype="UI16" type="short" varname="e13" />
+	<parameter etype="UI16" type="short" varname="e12" />
+	<parameter etype="UI16" type="short" varname="e11" />
+	<parameter etype="UI16" type="short" varname="e10" />
+	<parameter etype="UI16" type="short" varname="e9" />
+	<parameter etype="UI16" type="short" varname="e8" />
+	<parameter etype="UI16" type="short" varname="e7" />
+	<parameter etype="UI16" type="short" varname="e6" />
+	<parameter etype="UI16" type="short" varname="e5" />
+	<parameter etype="UI16" type="short" varname="e4" />
+	<parameter etype="UI16" type="short" varname="e3" />
+	<parameter etype="UI16" type="short" varname="e2" />
+	<parameter etype="UI16" type="short" varname="e1" />
+	<parameter etype="UI16" type="short" varname="e0" />
+	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[15:0] := e0
+dst[31:16] := e1
+dst[47:32] := e2
+dst[63:48] := e3
+dst[79:64] := e4
+dst[95:80] := e5
+dst[111:96] := e6
+dst[127:112] := e7
+dst[143:128] := e8
+dst[159:144] := e9
+dst[175:160] := e10
+dst[191:176] := e11
+dst[207:192] := e12
+dst[223:208] := e13
+dst[239:224] := e14
+dst[255:240] := e15
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_epi32" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="e7" />
+	<parameter etype="UI32" type="int" varname="e6" />
+	<parameter etype="UI32" type="int" varname="e5" />
+	<parameter etype="UI32" type="int" varname="e4" />
+	<parameter etype="UI32" type="int" varname="e3" />
+	<parameter etype="UI32" type="int" varname="e2" />
+	<parameter etype="UI32" type="int" varname="e1" />
+	<parameter etype="UI32" type="int" varname="e0" />
+	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[31:0] := e0
+dst[63:32] := e1
+dst[95:64] := e2
+dst[127:96] := e3
+dst[159:128] := e4
+dst[191:160] := e5
+dst[223:192] := e6
+dst[255:224] := e7
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_epi64x" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="e3" />
+	<parameter etype="UI64" type="__int64" varname="e2" />
+	<parameter etype="UI64" type="__int64" varname="e1" />
+	<parameter etype="UI64" type="__int64" varname="e0" />
+	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[63:0] := e0
+dst[127:64] := e1
+dst[191:128] := e2
+dst[255:192] := e3
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_pd" sequence="TRUE" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="e3" />
+	<parameter etype="FP64" type="double" varname="e2" />
+	<parameter etype="FP64" type="double" varname="e1" />
+	<parameter etype="FP64" type="double" varname="e0" />
+	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[63:0] := e3
+dst[127:64] := e2
+dst[191:128] := e1
+dst[255:192] := e0
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_ps" sequence="TRUE" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="float" varname="e7" />
+	<parameter etype="FP32" type="float" varname="e6" />
+	<parameter etype="FP32" type="float" varname="e5" />
+	<parameter etype="FP32" type="float" varname="e4" />
+	<parameter etype="FP32" type="float" varname="e3" />
+	<parameter etype="FP32" type="float" varname="e2" />
+	<parameter etype="FP32" type="float" varname="e1" />
+	<parameter etype="FP32" type="float" varname="e0" />
+	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[31:0] := e7
+dst[63:32] := e6
+dst[95:64] := e5
+dst[127:96] := e4
+dst[159:128] := e3
+dst[191:160] := e2
+dst[223:192] := e1
+dst[255:224] := e0
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_epi8" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="char" varname="e31" />
+	<parameter etype="UI8" type="char" varname="e30" />
+	<parameter etype="UI8" type="char" varname="e29" />
+	<parameter etype="UI8" type="char" varname="e28" />
+	<parameter etype="UI8" type="char" varname="e27" />
+	<parameter etype="UI8" type="char" varname="e26" />
+	<parameter etype="UI8" type="char" varname="e25" />
+	<parameter etype="UI8" type="char" varname="e24" />
+	<parameter etype="UI8" type="char" varname="e23" />
+	<parameter etype="UI8" type="char" varname="e22" />
+	<parameter etype="UI8" type="char" varname="e21" />
+	<parameter etype="UI8" type="char" varname="e20" />
+	<parameter etype="UI8" type="char" varname="e19" />
+	<parameter etype="UI8" type="char" varname="e18" />
+	<parameter etype="UI8" type="char" varname="e17" />
+	<parameter etype="UI8" type="char" varname="e16" />
+	<parameter etype="UI8" type="char" varname="e15" />
+	<parameter etype="UI8" type="char" varname="e14" />
+	<parameter etype="UI8" type="char" varname="e13" />
+	<parameter etype="UI8" type="char" varname="e12" />
+	<parameter etype="UI8" type="char" varname="e11" />
+	<parameter etype="UI8" type="char" varname="e10" />
+	<parameter etype="UI8" type="char" varname="e9" />
+	<parameter etype="UI8" type="char" varname="e8" />
+	<parameter etype="UI8" type="char" varname="e7" />
+	<parameter etype="UI8" type="char" varname="e6" />
+	<parameter etype="UI8" type="char" varname="e5" />
+	<parameter etype="UI8" type="char" varname="e4" />
+	<parameter etype="UI8" type="char" varname="e3" />
+	<parameter etype="UI8" type="char" varname="e2" />
+	<parameter etype="UI8" type="char" varname="e1" />
+	<parameter etype="UI8" type="char" varname="e0" />
+	<description>Set packed 8-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[7:0] := e31
+dst[15:8] := e30
+dst[23:16] := e29
+dst[31:24] := e28
+dst[39:32] := e27
+dst[47:40] := e26
+dst[55:48] := e25
+dst[63:56] := e24
+dst[71:64] := e23
+dst[79:72] := e22
+dst[87:80] := e21
+dst[95:88] := e20
+dst[103:96] := e19
+dst[111:104] := e18
+dst[119:112] := e17
+dst[127:120] := e16
+dst[135:128] := e15
+dst[143:136] := e14
+dst[151:144] := e13
+dst[159:152] := e12
+dst[167:160] := e11
+dst[175:168] := e10
+dst[183:176] := e9
+dst[191:184] := e8
+dst[199:192] := e7
+dst[207:200] := e6
+dst[215:208] := e5
+dst[223:216] := e4
+dst[231:224] := e3
+dst[239:232] := e2
+dst[247:240] := e1
+dst[255:248] := e0
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_epi16" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="e15" />
+	<parameter etype="UI16" type="short" varname="e14" />
+	<parameter etype="UI16" type="short" varname="e13" />
+	<parameter etype="UI16" type="short" varname="e12" />
+	<parameter etype="UI16" type="short" varname="e11" />
+	<parameter etype="UI16" type="short" varname="e10" />
+	<parameter etype="UI16" type="short" varname="e9" />
+	<parameter etype="UI16" type="short" varname="e8" />
+	<parameter etype="UI16" type="short" varname="e7" />
+	<parameter etype="UI16" type="short" varname="e6" />
+	<parameter etype="UI16" type="short" varname="e5" />
+	<parameter etype="UI16" type="short" varname="e4" />
+	<parameter etype="UI16" type="short" varname="e3" />
+	<parameter etype="UI16" type="short" varname="e2" />
+	<parameter etype="UI16" type="short" varname="e1" />
+	<parameter etype="UI16" type="short" varname="e0" />
+	<description>Set packed 16-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[15:0] := e15
+dst[31:16] := e14
+dst[47:32] := e13
+dst[63:48] := e12
+dst[79:64] := e11
+dst[95:80] := e10
+dst[111:96] := e9
+dst[127:112] := e8
+dst[143:128] := e7
+dst[159:144] := e6
+dst[175:160] := e5
+dst[191:176] := e4
+dst[207:192] := e3
+dst[223:208] := e2
+dst[239:224] := e1
+dst[255:240] := e0
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_epi32" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="e7" />
+	<parameter etype="UI32" type="int" varname="e6" />
+	<parameter etype="UI32" type="int" varname="e5" />
+	<parameter etype="UI32" type="int" varname="e4" />
+	<parameter etype="UI32" type="int" varname="e3" />
+	<parameter etype="UI32" type="int" varname="e2" />
+	<parameter etype="UI32" type="int" varname="e1" />
+	<parameter etype="UI32" type="int" varname="e0" />
+	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[31:0] := e7
+dst[63:32] := e6
+dst[95:64] := e5
+dst[127:96] := e4
+dst[159:128] := e3
+dst[191:160] := e2
+dst[223:192] := e1
+dst[255:224] := e0
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_epi64x" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="e3" />
+	<parameter etype="UI64" type="__int64" varname="e2" />
+	<parameter etype="UI64" type="__int64" varname="e1" />
+	<parameter etype="UI64" type="__int64" varname="e0" />
+	<description>Set packed 64-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[63:0] := e3
+dst[127:64] := e2
+dst[191:128] := e1
+dst[255:192] := e0
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set1_pd" sequence="TRUE" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="a" />
+	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set1_ps" sequence="TRUE" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set1_epi8" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastb".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := a[7:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set1_epi16" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate the "vpbroadcastw".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := a[15:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set1_epi32" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastd".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set1_epi64x" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="long long" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_m128" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="hi" />
+	<parameter etype="FP32" type="__m128" varname="lo" />
+	<description>Set packed __m256 vector "dst" with the supplied values.</description>
+	<operation>
+dst[127:0] := lo[127:0]
+dst[255:128] := hi[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_m128d" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="hi" />
+	<parameter etype="FP64" type="__m128d" varname="lo" />
+	<description>Set packed __m256d vector "dst" with the supplied values.</description>
+	<operation>
+dst[127:0] := lo[127:0]
+dst[255:128] := hi[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_m128i" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="hi" />
+	<parameter etype="M128" type="__m128i" varname="lo" />
+	<description>Set packed __m256i vector "dst" with the supplied values.</description>
+	<operation>
+dst[127:0] := lo[127:0]
+dst[255:128] := hi[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_m128" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="lo" />
+	<parameter etype="FP32" type="__m128" varname="hi" />
+	<description>Set packed __m256 vector "dst" with the supplied values.</description>
+	<operation>
+dst[127:0] := lo[127:0]
+dst[255:128] := hi[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_m128d" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="lo" />
+	<parameter etype="FP64" type="__m128d" varname="hi" />
+	<description>Set packed __m256d vector "dst" with the supplied values.</description>
+	<operation>
+dst[127:0] := lo[127:0]
+dst[255:128] := hi[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_m128i" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="lo" />
+	<parameter etype="M128" type="__m128i" varname="hi" />
+	<description>Set packed __m256i vector "dst" with the supplied values.</description>
+	<operation>
+dst[127:0] := lo[127:0]
+dst[255:128] := hi[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castpd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Cast vector of type __m256d to type __m256.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castps_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Cast vector of type __m256 to type __m256d.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castps_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Cast vector of type __m256 to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castpd_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Cast vector of type __m256d to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castsi256_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Cast vector of type __m256i to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castsi256_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Cast vector of type __m256i to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castps256_ps128" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Cast vector of type __m256 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castpd256_pd128" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Cast vector of type __m256d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castsi256_si128" tech="AVX_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<description>Cast vector of type __m256i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castps128_ps256" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Cast vector of type __m128 to type __m256; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castpd128_pd256" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Cast vector of type __m128d to type __m256d; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castsi128_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m128i" varname="a" />
+	<description>Cast vector of type __m128i to type __m256i; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_zextps128_ps256" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Cast vector of type __m128 to type __m256; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_zextpd128_pd256" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Cast vector of type __m128d to type __m256d; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_zextsi128_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m128i" varname="a" />
+	<description>Cast vector of type __m128i to type __m256i; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_extract_epi8" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI8" type="int" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="index" />
+	<description>Extract an 8-bit integer from "a", selected with "index", and store the result in "dst".</description>
+	<operation>
+dst[7:0] := (a[255:0] &gt;&gt; (index[4:0] * 8))[7:0]
+	</operation>
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extract_epi16" sequence="TRUE" tech="AVX_ALL">
+	<return etype="UI16" type="int" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="index" />
+	<description>Extract a 16-bit integer from "a", selected with "index", and store the result in "dst".</description>
+	<operation>
+dst[15:0] := (a[255:0] &gt;&gt; (index[3:0] * 16))[15:0]
+	</operation>
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_blend_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Blend packed 16-bit integers from "a" and "b" within 128-bit lanes using control mask "imm8", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF imm8[j%8]
+		dst[i+15:i] := b[i+15:i]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPBLENDW" xed="VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_blend_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF imm8[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPBLENDD" xed="VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_blend_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF imm8[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPBLENDD" xed="VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_blendv_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<description>Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF mask[i+7]
+		dst[i+7:i] := b[i+7:i]
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, ymm" name="VPBLENDVB" xed="VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastb_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := a[7:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_XMMdq_XMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcastb_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := a[7:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_YMMqq_XMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastd_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_XMMdq_XMMd" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcastd_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_YMMqq_XMMd" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastq_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMdq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcastq_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastsd_pd" vexEq="TRUE" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="MOVDDUP" xed="MOVDDUP_XMMdq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcastsd_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_YMMqq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastsi128_si256" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst".</description>
+	<operation>
+dst[127:0] := a[127:0]
+dst[255:128] := a[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m128" name="VBROADCASTI128" xed="VBROADCASTI128_YMMqq_MEMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcastsi128_si256" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst".</description>
+	<operation>
+dst[127:0] := a[127:0]
+dst[255:128] := a[127:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m128" name="VBROADCASTI128" xed="VBROADCASTI128_YMMqq_MEMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastss_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_XMMdq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcastss_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_YMMqq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastw_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := a[15:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_XMMdq_XMMw" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcastw_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := a[15:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_YMMqq_XMMw" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extracti128_si256" tech="AVX_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VEXTRACTI128" xed="VEXTRACTI128_XMMdq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_inserti128_si256" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of integer data) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTI128" xed="VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permute2x128_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src1, src2, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src1[127:0]
+	1:	tmp[127:0] := src1[255:128]
+	2:	tmp[127:0] := src2[127:0]
+	3:	tmp[127:0] := src2[255:128]
+	ESAC
+	IF control[3]
+		tmp[127:0] := 0
+	FI
+	RETURN tmp[127:0]
+}
+dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
+dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPERM2I128" xed="VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permute4x64_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPERMQ" xed="VPERMQ_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permute4x64_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPERMPD" xed="VPERMPD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutevar8x32_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	id := idx[i+2:i]*32
+	dst[i+31:i] := a[id+31:id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMD" xed="VPERMD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutevar8x32_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	id := idx[i+2:i]*32
+	dst[i+31:i] := a[id+31:id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMPS" xed="VPERMPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shuffle_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSHUFD" xed="VPSHUFD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shuffle_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF b[i+7] == 1
+		dst[i+7:i] := 0
+	ELSE
+		index[3:0] := b[i+3:i]
+		dst[i+7:i] := a[index*8+7:index*8]
+	FI
+	IF b[128+i+7] == 1
+		dst[128+i+7:128+i] := 0
+	ELSE
+		index[3:0] := b[128+i+3:128+i]
+		dst[128+i+7:128+i] := a[128+index*8+7:128+index*8]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSHUFB" xed="VPSHUFB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shufflehi_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+dst[191:128] := a[191:128]
+dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSHUFHW" xed="VPSHUFHW_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shufflelo_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
+	<operation>
+dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+dst[127:64] := a[127:64]
+dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+dst[255:192] := a[255:192]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSHUFLW" xed="VPSHUFLW_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpackhi_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPUNPCKHBW" xed="VPUNPCKHBW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpackhi_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPUNPCKHWD" xed="VPUNPCKHWD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpackhi_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpackhi_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpacklo_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPUNPCKLBW" xed="VPUNPCKLBW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpacklo_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPUNPCKLWD" xed="VPUNPCKLWD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpacklo_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_unpacklo_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_abs_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := ABS(a[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPABSB" xed="VPABSB_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_abs_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ABS(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPABSW" xed="VPABSW_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_abs_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ABS(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPABSD" xed="VPABSD_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMAXSB" xed="VPMAXSB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMAXSW" xed="VPMAXSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMAXSD" xed="VPMAXSD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_epu8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMAXUB" xed="VPMAXUB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_epu16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMAXUW" xed="VPMAXUW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_epu32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMAXUD" xed="VPMAXUD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMINSB" xed="VPMINSB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMINSW" xed="VPMINSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMINSD" xed="VPMINSD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_epu8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMINUB" xed="VPMINUB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_epu16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMINUW" xed="VPMINUW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_epu32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMINUD" xed="VPMINUD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_add_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPADDB" xed="VPADDB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_add_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPADDW" xed="VPADDW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_add_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPADDD" xed="VPADDD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_add_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPADDQ" xed="VPADDQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_adds_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPADDSB" xed="VPADDSB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_adds_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPADDSW" xed="VPADDSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_adds_epu8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPADDUSB" xed="VPADDUSB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_adds_epu16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPADDUSW" xed="VPADDUSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hadd_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := a[31:16] + a[15:0]
+dst[31:16] := a[63:48] + a[47:32]
+dst[47:32] := a[95:80] + a[79:64]
+dst[63:48] := a[127:112] + a[111:96]
+dst[79:64] := b[31:16] + b[15:0]
+dst[95:80] := b[63:48] + b[47:32]
+dst[111:96] := b[95:80] + b[79:64]
+dst[127:112] := b[127:112] + b[111:96]
+dst[143:128] := a[159:144] + a[143:128]
+dst[159:144] := a[191:176] + a[175:160]
+dst[175:160] := a[223:208] + a[207:192]
+dst[191:176] := a[255:240] + a[239:224]
+dst[207:192] := b[159:144] + b[143:128]
+dst[223:208] := b[191:176] + b[175:160]
+dst[239:224] := b[223:208] + b[207:192]
+dst[255:240] := b[255:240] + b[239:224]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPHADDW" xed="VPHADDW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hadd_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32] + a[31:0]
+dst[63:32] := a[127:96] + a[95:64]
+dst[95:64] := b[63:32] + b[31:0]
+dst[127:96] := b[127:96] + b[95:64]
+dst[159:128] := a[191:160] + a[159:128]
+dst[191:160] := a[255:224] + a[223:192]
+dst[223:192] := b[191:160] + b[159:128]
+dst[255:224] := b[255:224] + b[223:192]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPHADDD" xed="VPHADDD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hadds_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[31:16] + a[15:0])
+dst[31:16] := Saturate16(a[63:48] + a[47:32])
+dst[47:32] := Saturate16(a[95:80] + a[79:64])
+dst[63:48] := Saturate16(a[127:112] + a[111:96])
+dst[79:64] := Saturate16(b[31:16] + b[15:0])
+dst[95:80] := Saturate16(b[63:48] + b[47:32])
+dst[111:96] := Saturate16(b[95:80] + b[79:64])
+dst[127:112] := Saturate16(b[127:112] + b[111:96])
+dst[143:128] := Saturate16(a[159:144] + a[143:128])
+dst[159:144] := Saturate16(a[191:176] + a[175:160])
+dst[175:160] := Saturate16(a[223:208] + a[207:192])
+dst[191:176] := Saturate16(a[255:240] + a[239:224])
+dst[207:192] := Saturate16(b[159:144] + b[143:128])
+dst[223:208] := Saturate16(b[191:176] + b[175:160])
+dst[239:224] := Saturate16(b[223:208] + b[207:192])
+dst[255:240] := Saturate16(b[255:240] + b[239:224])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPHADDSW" xed="VPHADDSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hsub_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := a[15:0] - a[31:16]
+dst[31:16] := a[47:32] - a[63:48]
+dst[47:32] := a[79:64] - a[95:80]
+dst[63:48] := a[111:96] - a[127:112]
+dst[79:64] := b[15:0] - b[31:16]
+dst[95:80] := b[47:32] - b[63:48]
+dst[111:96] := b[79:64] - b[95:80]
+dst[127:112] := b[111:96] - b[127:112]
+dst[143:128] := a[143:128] - a[159:144]
+dst[159:144] := a[175:160] - a[191:176]
+dst[175:160] := a[207:192] - a[223:208]
+dst[191:176] := a[239:224] - a[255:240]
+dst[207:192] := b[143:128] - b[159:144]
+dst[223:208] := b[175:160] - b[191:176]
+dst[239:224] := b[207:192] - b[223:208]
+dst[255:240] := b[239:224] - b[255:240]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPHSUBW" xed="VPHSUBW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hsub_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] - a[63:32]
+dst[63:32] := a[95:64] - a[127:96]
+dst[95:64] := b[31:0] - b[63:32]
+dst[127:96] := b[95:64] - b[127:96]
+dst[159:128] := a[159:128] - a[191:160]
+dst[191:160] := a[223:192] - a[255:224]
+dst[223:192] := b[159:128] - b[191:160]
+dst[255:224] := b[223:192] - b[255:224]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPHSUBD" xed="VPHSUBD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_hsubs_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[15:0] - a[31:16])
+dst[31:16] := Saturate16(a[47:32] - a[63:48])
+dst[47:32] := Saturate16(a[79:64] - a[95:80])
+dst[63:48] := Saturate16(a[111:96] - a[127:112])
+dst[79:64] := Saturate16(b[15:0] - b[31:16])
+dst[95:80] := Saturate16(b[47:32] - b[63:48])
+dst[111:96] := Saturate16(b[79:64] - b[95:80])
+dst[127:112] := Saturate16(b[111:96] - b[127:112])
+dst[143:128] := Saturate16(a[143:128] - a[159:144])
+dst[159:144] := Saturate16(a[175:160] - a[191:176])
+dst[175:160] := Saturate16(a[207:192] - a[223:208])
+dst[191:176] := Saturate16(a[239:224] - a[255:240])
+dst[207:192] := Saturate16(b[143:128] - b[159:144])
+dst[223:208] := Saturate16(b[175:160] - b[191:176])
+dst[239:224] := Saturate16(b[207:192] - b[223:208])
+dst[255:240] := Saturate16(b[239:224] - b[255:240])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPHSUBSW" xed="VPHSUBSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_madd_epi16" tech="AVX_ALL">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMADDWD" xed="VPMADDWD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maddubs_epi16" tech="AVX_ALL">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMADDUBSW" xed="VPMADDUBSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mul_epi32" tech="AVX_ALL">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULDQ" xed="VPMULDQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mul_epu32" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+31:i] * b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULUDQ" xed="VPMULUDQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mulhi_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULHW" xed="VPMULHW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mulhi_epu16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	tmp[31:0] := a[i+15:i] * b[i+15:i]
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULHUW" xed="VPMULHUW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mulhrs_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+	dst[i+15:i] := tmp[16:1]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULHRSW" xed="VPMULHRSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mullo_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+	dst[i+15:i] := tmp[15:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULLW" xed="VPMULLW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mullo_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Multiply the packed signed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	tmp[63:0] := a[i+31:i] * b[i+31:i]
+	dst[i+31:i] := tmp[31:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULLD" xed="VPMULLD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sad_epu8" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
+ENDFOR
+FOR j := 0 to 3
+	i := j*64
+	dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
+	               tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
+	dst[i+63:i+16] := 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSADBW" xed="VPSADBW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sign_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Negate packed signed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF b[i+7:i] &lt; 0
+		dst[i+7:i] := -(a[i+7:i])
+	ELSE IF b[i+7:i] == 0
+		dst[i+7:i] := 0
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSIGNB" xed="VPSIGNB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sign_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Negate packed signed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF b[i+15:i] &lt; 0
+		dst[i+15:i] := -(a[i+15:i])
+	ELSE IF b[i+15:i] == 0
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSIGNW" xed="VPSIGNW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sign_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Negate packed signed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF b[i+31:i] &lt; 0
+		dst[i+31:i] := -(a[i+31:i])
+	ELSE IF b[i+31:i] == 0
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSIGND" xed="VPSIGND_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sub_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSUBB" xed="VPSUBB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sub_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSUBW" xed="VPSUBW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sub_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSUBD" xed="VPSUBD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sub_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSUBQ" xed="VPSUBQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_subs_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSUBSB" xed="VPSUBSB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_subs_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSUBSW" xed="VPSUBSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_subs_epu8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSUBUSB" xed="VPSUBUSB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_subs_epu16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSUBUSW" xed="VPSUBUSW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_alignr_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*128
+	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+	dst[i+127:i] := tmp[127:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPALIGNR" xed="VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movemask_epi8" tech="AVX_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[j] := a[i+7]
+ENDFOR
+	</operation>
+	<instruction form="r32, ymm" name="VPMOVMSKB" xed="VPMOVMSKB_GPR32d_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mpsadbw_epu8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+	Eight SADs are performed for each 128-bit lane using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8".</description>
+	<operation>
+DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) {
+	a_offset := imm8[2]*32
+	b_offset := imm8[1:0]*32
+	FOR j := 0 to 7
+		i := j*8
+		k := a_offset+i
+		l := b_offset
+		tmp[i*2+15:i*2] := ABS(Signed(a[k+7:k] - b[l+7:l])) + ABS(Signed(a[k+15:k+8] - b[l+15:l+8])) + \
+		                   ABS(Signed(a[k+23:k+16] - b[l+23:l+16])) + ABS(Signed(a[k+31:k+24] - b[l+31:l+24]))
+	ENDFOR
+	RETURN tmp[127:0]
+}
+dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0])
+dst[255:128] := MPSADBW(a[255:128], b[255:128], imm8[5:3])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VMPSADBW" xed="VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_packs_epi16" tech="AVX_ALL">
+	<return etype="SI8" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := Saturate8(a[15:0])
+dst[15:8] := Saturate8(a[31:16])
+dst[23:16] := Saturate8(a[47:32])
+dst[31:24] := Saturate8(a[63:48])
+dst[39:32] := Saturate8(a[79:64])
+dst[47:40] := Saturate8(a[95:80])
+dst[55:48] := Saturate8(a[111:96])
+dst[63:56] := Saturate8(a[127:112])
+dst[71:64] := Saturate8(b[15:0])
+dst[79:72] := Saturate8(b[31:16])
+dst[87:80] := Saturate8(b[47:32])
+dst[95:88] := Saturate8(b[63:48])
+dst[103:96] := Saturate8(b[79:64])
+dst[111:104] := Saturate8(b[95:80])
+dst[119:112] := Saturate8(b[111:96])
+dst[127:120] := Saturate8(b[127:112])
+dst[135:128] := Saturate8(a[143:128])
+dst[143:136] := Saturate8(a[159:144])
+dst[151:144] := Saturate8(a[175:160])
+dst[159:152] := Saturate8(a[191:176])
+dst[167:160] := Saturate8(a[207:192])
+dst[175:168] := Saturate8(a[223:208])
+dst[183:176] := Saturate8(a[239:224])
+dst[191:184] := Saturate8(a[255:240])
+dst[199:192] := Saturate8(b[143:128])
+dst[207:200] := Saturate8(b[159:144])
+dst[215:208] := Saturate8(b[175:160])
+dst[223:216] := Saturate8(b[191:176])
+dst[231:224] := Saturate8(b[207:192])
+dst[239:232] := Saturate8(b[223:208])
+dst[247:240] := Saturate8(b[239:224])
+dst[255:248] := Saturate8(b[255:240])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPACKSSWB" xed="VPACKSSWB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_packs_epi32" tech="AVX_ALL">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[31:0])
+dst[31:16] := Saturate16(a[63:32])
+dst[47:32] := Saturate16(a[95:64])
+dst[63:48] := Saturate16(a[127:96])
+dst[79:64] := Saturate16(b[31:0])
+dst[95:80] := Saturate16(b[63:32])
+dst[111:96] := Saturate16(b[95:64])
+dst[127:112] := Saturate16(b[127:96])
+dst[143:128] := Saturate16(a[159:128])
+dst[159:144] := Saturate16(a[191:160])
+dst[175:160] := Saturate16(a[223:192])
+dst[191:176] := Saturate16(a[255:224])
+dst[207:192] := Saturate16(b[159:128])
+dst[223:208] := Saturate16(b[191:160])
+dst[239:224] := Saturate16(b[223:192])
+dst[255:240] := Saturate16(b[255:224])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPACKSSDW" xed="VPACKSSDW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_packus_epi16" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := SaturateU8(a[15:0])
+dst[15:8] := SaturateU8(a[31:16])
+dst[23:16] := SaturateU8(a[47:32])
+dst[31:24] := SaturateU8(a[63:48])
+dst[39:32] := SaturateU8(a[79:64])
+dst[47:40] := SaturateU8(a[95:80])
+dst[55:48] := SaturateU8(a[111:96])
+dst[63:56] := SaturateU8(a[127:112])
+dst[71:64] := SaturateU8(b[15:0])
+dst[79:72] := SaturateU8(b[31:16])
+dst[87:80] := SaturateU8(b[47:32])
+dst[95:88] := SaturateU8(b[63:48])
+dst[103:96] := SaturateU8(b[79:64])
+dst[111:104] := SaturateU8(b[95:80])
+dst[119:112] := SaturateU8(b[111:96])
+dst[127:120] := SaturateU8(b[127:112])
+dst[135:128] := SaturateU8(a[143:128])
+dst[143:136] := SaturateU8(a[159:144])
+dst[151:144] := SaturateU8(a[175:160])
+dst[159:152] := SaturateU8(a[191:176])
+dst[167:160] := SaturateU8(a[207:192])
+dst[175:168] := SaturateU8(a[223:208])
+dst[183:176] := SaturateU8(a[239:224])
+dst[191:184] := SaturateU8(a[255:240])
+dst[199:192] := SaturateU8(b[143:128])
+dst[207:200] := SaturateU8(b[159:144])
+dst[215:208] := SaturateU8(b[175:160])
+dst[223:216] := SaturateU8(b[191:176])
+dst[231:224] := SaturateU8(b[207:192])
+dst[239:232] := SaturateU8(b[223:208])
+dst[247:240] := SaturateU8(b[239:224])
+dst[255:248] := SaturateU8(b[255:240])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPACKUSWB" xed="VPACKUSWB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_packus_epi32" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".</description>
+	<operation>
+dst[15:0] := SaturateU16(a[31:0])
+dst[31:16] := SaturateU16(a[63:32])
+dst[47:32] := SaturateU16(a[95:64])
+dst[63:48] := SaturateU16(a[127:96])
+dst[79:64] := SaturateU16(b[31:0])
+dst[95:80] := SaturateU16(b[63:32])
+dst[111:96] := SaturateU16(b[95:64])
+dst[127:112] := SaturateU16(b[127:96])
+dst[143:128] := SaturateU16(a[159:128])
+dst[159:144] := SaturateU16(a[191:160])
+dst[175:160] := SaturateU16(a[223:192])
+dst[191:176] := SaturateU16(a[255:224])
+dst[207:192] := SaturateU16(b[159:128])
+dst[223:208] := SaturateU16(b[191:160])
+dst[239:224] := SaturateU16(b[223:192])
+dst[255:240] := SaturateU16(b[255:224])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPACKUSDW" xed="VPACKUSDW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_and_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[255:0] := (a[255:0] AND b[255:0])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPAND" xed="VPAND_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_andnot_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<description>Compute the bitwise NOT of 256 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
+	<operation>
+dst[255:0] := ((NOT a[255:0]) AND b[255:0])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPANDN" xed="VPANDN_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_or_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<description>Compute the bitwise OR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[255:0] := (a[255:0] OR b[255:0])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPOR" xed="VPOR_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_xor_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m256i" varname="a" />
+	<parameter etype="M256" type="__m256i" varname="b" />
+	<description>Compute the bitwise XOR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[255:0] := (a[255:0] XOR b[255:0])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPXOR" xed="VPXOR_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_avg_epu8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPAVGB" xed="VPAVGB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_avg_epu16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPAVGW" xed="VPAVGW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPCMPEQB" xed="VPCMPEQB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPCMPEQW" xed="VPCMPEQW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPCMPEQD" xed="VPCMPEQD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPCMPEQQ" xed="VPCMPEQQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epi8" tech="AVX_ALL">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPCMPGTB" xed="VPCMPGTB_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPCMPGTW" xed="VPCMPGTW_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPCMPGTD" xed="VPCMPGTD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ( a[i+63:i] &gt; b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPCMPGTQ" xed="VPCMPGTQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi16_epi32" tech="AVX_ALL">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j:= 0 to 7
+	i := 32*j
+	k := 16*j
+	dst[i+31:i] := SignExtend32(a[k+15:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_YMMqq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi16_epi64" tech="AVX_ALL">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j:= 0 to 3
+	i := 64*j
+	k := 16*j
+	dst[i+63:i] := SignExtend64(a[k+15:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi32_epi64" tech="AVX_ALL">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j:= 0 to 3
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := SignExtend64(a[k+31:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_YMMqq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi8_epi16" tech="AVX_ALL">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	l := j*16
+	dst[l+15:l] := SignExtend16(a[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_YMMqq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi8_epi32" tech="AVX_ALL">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 8*j
+	dst[i+31:i] := SignExtend32(a[k+7:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi8_epi64" tech="AVX_ALL">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 8*j
+	dst[i+63:i] := SignExtend64(a[k+7:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_YMMqq_XMMd" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu16_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 16*j
+	dst[i+31:i] := ZeroExtend32(a[k+15:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_YMMqq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu16_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j:= 0 to 3
+	i := 64*j
+	k := 16*j
+	dst[i+63:i] := ZeroExtend64(a[k+15:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu32_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j:= 0 to 3
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := ZeroExtend64(a[k+31:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_YMMqq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu8_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	l := j*16
+	dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_YMMqq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu8_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 8*j
+	dst[i+31:i] := ZeroExtend32(a[k+7:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu8_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 8*j
+	dst[i+63:i] := ZeroExtend64(a[k+7:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_YMMqq_XMMd" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_i32gather_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="double const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm32x, xmm" name="VGATHERDPD" xed="VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i32gather_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="double const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm32x, ymm" name="VGATHERDPD" xed="VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_i32gather_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="float const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm32x, xmm" name="VGATHERDPS" xed="VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i32gather_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="float const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm32x, ymm" name="VGATHERDPS" xed="VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_i32gather_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="int const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm32x, xmm" name="VPGATHERDD" xed="VPGATHERDD_XMMu32_MEMd_XMMi32_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i32gather_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="int const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm32x, ymm" name="VPGATHERDD" xed="VPGATHERDD_YMMu32_MEMd_YMMi32_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_i32gather_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm32x, xmm" name="VPGATHERDQ" xed="VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i32gather_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm32x, ymm" name="VPGATHERDQ" xed="VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_i64gather_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="double const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm64x, xmm" name="VGATHERQPD" xed="VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i64gather_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="double const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm64x, ymm" name="VGATHERQPD" xed="VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_i64gather_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="float const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, vm64x, xmm" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i64gather_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="float const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm64y, xmm" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_i64gather_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="int const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, vm64x, xmm" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i64gather_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="int const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm64y, xmm" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_i64gather_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm64x, xmm" name="VPGATHERQQ" xed="VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i64gather_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm64x, ymm" name="VPGATHERQQ" xed="VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i32gather_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="FP64" type="double const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m128d" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	IF mask[i+63]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+mask[MAX:128] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm32x, xmm" name="VGATHERDPD" xed="VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i32gather_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="FP64" type="double const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m256d" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	IF mask[i+63]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+mask[MAX:256] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm32x, ymm" name="VGATHERDPD" xed="VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i32gather_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="FP32" type="float const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m128" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	IF mask[i+31]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+mask[MAX:128] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm32x, xmm" name="VGATHERDPS" xed="VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i32gather_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="FP32" type="float const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="MASK" type="__m256" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	IF mask[i+31]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+mask[MAX:256] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm32x, ymm" name="VGATHERDPS" xed="VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i32gather_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="UI32" type="int const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	IF mask[i+31]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+mask[MAX:128] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm32x, xmm" name="VPGATHERDD" xed="VPGATHERDD_XMMu32_MEMd_XMMi32_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i32gather_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="UI32" type="int const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	IF mask[i+31]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+mask[MAX:256] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm32x, ymm" name="VPGATHERDD" xed="VPGATHERDD_YMMu32_MEMd_YMMi32_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i32gather_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	IF mask[i+63]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+mask[MAX:128] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm32x, xmm" name="VPGATHERDQ" xed="VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i32gather_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	IF mask[i+63]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+mask[MAX:256] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm32x, ymm" name="VPGATHERDQ" xed="VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i64gather_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="FP64" type="double const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m128d" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	IF mask[i+63]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+mask[MAX:128] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm64x, xmm" name="VGATHERQPD" xed="VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i64gather_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="FP64" type="double const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="MASK" type="__m256d" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	IF mask[i+63]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+mask[MAX:256] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm64x, ymm" name="VGATHERQPD" xed="VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i64gather_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="FP32" type="float const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m128" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	IF mask[i+31]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+mask[MAX:64] := 0
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, vm64x, xmm" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i64gather_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="FP32" type="float const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="MASK" type="__m128" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	IF mask[i+31]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+mask[MAX:128] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm64y, xmm" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i64gather_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="UI32" type="int const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	IF mask[i+31]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+mask[MAX:64] := 0
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, vm64x, xmm" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i64gather_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="UI32" type="int const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	IF mask[i+31]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+mask[MAX:128] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm64y, xmm" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i64gather_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	IF mask[i+63]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+mask[MAX:128] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, vm64x, xmm" name="VPGATHERQQ" xed="VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i64gather_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	IF mask[i+63]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+mask[MAX:256] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm64x, ymm" name="VPGATHERQQ" xed="VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskload_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" memwidth="128" type="int const*" varname="mem_addr" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<description>Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF mask[i+31]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, m128" name="VPMASKMOVD" xed="VPMASKMOVD_XMMdq_XMMdq_MEMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskload_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" memwidth="256" type="int const*" varname="mem_addr" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<description>Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF mask[i+31]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, m256" name="VPMASKMOVD" xed="VPMASKMOVD_YMMqq_YMMqq_MEMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskload_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" memwidth="128" type="__int64 const*" varname="mem_addr" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<description>Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF mask[i+63]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, m128" name="VPMASKMOVQ" xed="VPMASKMOVQ_XMMdq_XMMdq_MEMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskload_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" memwidth="256" type="__int64 const*" varname="mem_addr" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<description>Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF mask[i+63]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, m256" name="VPMASKMOVQ" xed="VPMASKMOVQ_YMMqq_YMMqq_MEMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_stream_load_si256" tech="AVX_ALL">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits of integer data from memory into "dst" using a non-temporal memory hint.
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVNTDQA" xed="VMOVNTDQA_YMMqq_MEMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskstore_epi32" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="128" type="int*" varname="mem_addr" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF mask[i+31]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128, xmm, xmm" name="VPMASKMOVD" xed="VPMASKMOVD_MEMdq_XMMdq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskstore_epi32" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="256" type="int*" varname="mem_addr" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF mask[i+31]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256, ymm, ymm" name="VPMASKMOVD" xed="VPMASKMOVD_MEMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskstore_epi64" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="128" type="__int64*" varname="mem_addr" />
+	<parameter etype="MASK" type="__m128i" varname="mask" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF mask[i+63]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128, xmm, xmm" name="VPMASKMOVQ" xed="VPMASKMOVQ_MEMdq_XMMdq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskstore_epi64" tech="AVX_ALL">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="256" type="__int64*" varname="mem_addr" />
+	<parameter etype="MASK" type="__m256i" varname="mask" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF mask[i+63]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256, ymm, ymm" name="VPMASKMOVQ" xed="VPMASKMOVQ_MEMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_slli_si256" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
+dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSLLDQ" xed="VPSLLDQ_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_bslli_epi128" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
+dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSLLDQ" xed="VPSLLDQ_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sll_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSLLW" xed="VPSLLW_YMMqq_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_slli_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSLLW" xed="VPSLLW_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sll_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSLLD" xed="VPSLLD_YMMqq_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_slli_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSLLD" xed="VPSLLD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sll_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSLLQ" xed="VPSLLQ_YMMqq_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_slli_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSLLQ" xed="VPSLLQ_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sllv_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSLLVD" xed="VPSLLVD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sllv_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSLLVD" xed="VPSLLVD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sllv_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSLLVQ" xed="VPSLLVQ_XMMdq_XMMdq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sllv_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSLLVQ" xed="VPSLLVQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sra_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSRAW" xed="VPSRAW_YMMqq_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srai_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSRAW" xed="VPSRAW_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sra_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSRAD" xed="VPSRAD_YMMqq_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srai_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSRAD" xed="VPSRAD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srav_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSRAVD" xed="VPSRAVD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srav_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSRAVD" xed="VPSRAVD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srli_si256" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
+dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSRLDQ" xed="VPSRLDQ_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_bsrli_epi128" tech="AVX_ALL">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
+dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSRLDQ" xed="VPSRLDQ_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srl_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSRLW" xed="VPSRLW_YMMqq_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srli_epi16" tech="AVX_ALL">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSRLW" xed="VPSRLW_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srl_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSRLD" xed="VPSRLD_YMMqq_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srli_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSRLD" xed="VPSRLD_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srl_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSRLQ" xed="VPSRLQ_YMMqq_YMMqq_XMMq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srli_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSRLQ" xed="VPSRLQ_YMMqq_YMMqq_IMMb" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srlv_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSRLVD" xed="VPSRLVD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srlv_epi32" tech="AVX_ALL">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSRLVD" xed="VPSRLVD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srlv_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSRLVQ" xed="VPSRLVQ_XMMdq_XMMdq_XMMdq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srlv_epi64" tech="AVX_ALL">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSRLVQ" xed="VPSRLVQ_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+FOR i := 0 to 1
+	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ENDFOR
+FOR j := 0 to 3
+	i := j*64
+	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VDBPSADBW" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+FOR i := 0 to 1
+	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ENDFOR
+FOR j := 0 to 3
+	i := j*64
+	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VDBPSADBW" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+FOR i := 0 to 1
+	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ENDFOR
+FOR j := 0 to 3
+	i := j*64
+	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VDBPSADBW" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+tmp.dword[0] := b.dword[ imm8[1:0] ]
+tmp.dword[1] := b.dword[ imm8[3:2] ]
+tmp.dword[2] := b.dword[ imm8[5:4] ]
+tmp.dword[3] := b.dword[ imm8[7:6] ]
+FOR j := 0 to 1
+	i := j*64
+	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+tmp.dword[0] := b.dword[ imm8[1:0] ]
+tmp.dword[1] := b.dword[ imm8[3:2] ]
+tmp.dword[2] := b.dword[ imm8[5:4] ]
+tmp.dword[3] := b.dword[ imm8[7:6] ]
+FOR j := 0 to 1
+	i := j*64
+	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+tmp.dword[0] := b.dword[ imm8[1:0] ]
+tmp.dword[1] := b.dword[ imm8[3:2] ]
+tmp.dword[2] := b.dword[ imm8[5:4] ]
+tmp.dword[3] := b.dword[ imm8[7:6] ]
+FOR j := 0 to 1
+	i := j*64
+	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_alignr_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*128
+	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+	tmp_dst[i+127:i] := tmp[127:0]
+ENDFOR
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPALIGNR" xed="VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_alignr_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*128
+	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+	tmp_dst[i+127:i] := tmp[127:0]
+ENDFOR
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPALIGNR" xed="VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_alignr_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[255:0] := ((a[127:0] &lt;&lt; 128)[255:0] OR b[127:0]) &gt;&gt; (imm8*8)
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPALIGNR" xed="VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_alignr_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[255:0] := ((a[127:0] &lt;&lt; 128)[255:0] OR b[127:0]) &gt;&gt; (imm8*8)
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPALIGNR" xed="VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_blend_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := b[i+7:i]
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMB" xed="VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_blend_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := b[i+7:i]
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMB" xed="VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_blend_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := b[i+15:i]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMW" xed="VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_blend_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := b[i+15:i]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMW" xed="VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcastb_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcastb_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_broadcastb_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_broadcastb_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcastw_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcastw_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_broadcastw_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_broadcastw_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask2_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+3:i]
+		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := idx[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2W" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+3:i]
+		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2W" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+3:i]
+		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2W" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2W" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	off := 16*idx[i+3:i]
+	dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMI2W" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VPERMT2W" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask2_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+2:i]
+		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := idx[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2W" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+2:i]
+		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2W" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+2:i]
+		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2W" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2W" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	off := 16*idx[i+2:i]
+	dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMI2W" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VPERMT2W" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	id := idx[i+3:i]*16
+	IF k[j]
+		dst[i+15:i] := a[id+15:id]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMW" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	id := idx[i+3:i]*16
+	IF k[j]
+		dst[i+15:i] := a[id+15:id]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMW" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	id := idx[i+3:i]*16
+	dst[i+15:i] := a[id+15:id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMW" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	id := idx[i+2:i]*16
+	IF k[j]
+		dst[i+15:i] := a[id+15:id]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMW" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	id := idx[i+2:i]*16
+	IF k[j]
+		dst[i+15:i] := a[id+15:id]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMW" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	id := idx[i+2:i]*16
+	dst[i+15:i] := a[id+15:id]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMW" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movepi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF a[i+7]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm" name="VPMOVB2M" xed="VPMOVB2M_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movepi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF a[i+7]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm" name="VPMOVB2M" xed="VPMOVB2M_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movm_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := 0xFF
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm" name="VPMOVM2B" xed="VPMOVM2B_YMMu8_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movm_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := 0xFF
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm" name="VPMOVM2B" xed="VPMOVM2B_XMMu8_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movm_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := 0xFFFF
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm" name="VPMOVM2W" xed="VPMOVM2W_YMMu16_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movm_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := 0xFFFF
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm" name="VPMOVM2W" xed="VPMOVM2W_XMMu16_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movepi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF a[i+15]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm" name="VPMOVW2M" xed="VPMOVW2M_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movepi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF a[i+15]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm" name="VPMOVW2M" xed="VPMOVW2M_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shuffle_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		IF b[i+7] == 1
+			dst[i+7:i] := 0
+		ELSE
+			index[4:0] := b[i+3:i] + (j &amp; 0x10)
+			dst[i+7:i] := a[index*8+7:index*8]
+		FI
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSHUFB" xed="VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shuffle_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		IF b[i+7] == 1
+			dst[i+7:i] := 0
+		ELSE
+			index[4:0] := b[i+3:i] + (j &amp; 0x10)
+			dst[i+7:i] := a[index*8+7:index*8]
+		FI
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSHUFB" xed="VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shuffle_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		IF b[i+7] == 1
+			dst[i+7:i] := 0
+		ELSE
+			index[3:0] := b[i+3:i]
+			dst[i+7:i] := a[index*8+7:index*8]
+		FI
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSHUFB" xed="VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shuffle_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		IF b[i+7] == 1
+			dst[i+7:i] := 0
+		ELSE
+			index[3:0] := b[i+3:i]
+			dst[i+7:i] := a[index*8+7:index*8]
+		FI
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSHUFB" xed="VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shufflehi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := a[63:0]
+tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+tmp_dst[191:128] := a[191:128]
+tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSHUFHW" xed="VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shufflehi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := a[63:0]
+tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+tmp_dst[191:128] := a[191:128]
+tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSHUFHW" xed="VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shufflehi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := a[63:0]
+tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shufflehi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := a[63:0]
+tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shufflelo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+tmp_dst[127:64] := a[127:64]
+tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+tmp_dst[255:192] := a[255:192]
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSHUFLW" xed="VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shufflelo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+tmp_dst[127:64] := a[127:64]
+tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+tmp_dst[255:192] := a[255:192]
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSHUFLW" xed="VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shufflelo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+tmp_dst[127:64] := a[127:64]
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shufflelo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+tmp_dst[127:64] := a[127:64]
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpackhi_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKHBW" xed="VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpackhi_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKHBW" xed="VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpackhi_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpackhi_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpackhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKHWD" xed="VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpackhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKHWD" xed="VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpackhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpackhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpacklo_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKLBW" xed="VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpacklo_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKLBW" xed="VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpacklo_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpacklo_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpacklo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKLWD" xed="VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpacklo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKLWD" xed="VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpacklo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpacklo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m256" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m256" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m128" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m128" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m256" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m256" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m128" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m128" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits (composed of 16 packed 16-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits (composed of 32 packed 8-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 8 packed 16-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m128" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 16 packed 8-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m128" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mov_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mov_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mov_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mov_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mov_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mov_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mov_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mov_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_storeu_epi16" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI16" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_storeu_epi16" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI16" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_storeu_epi8" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI8" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_storeu_epi8" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI8" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu_epi16" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI16" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Store 256-bits (composed of 16 packed 16-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu_epi8" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI8" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Store 256-bits (composed of 32 packed 8-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_epi16" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI16" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Store 128-bits (composed of 8 packed 16-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_epi8" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI8" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Store 128-bits (composed of 16 packed 8-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_abs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := ABS(a[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPABSB" xed="VPABSB_YMMi8_MASKmskw_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_abs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := ABS(a[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPABSB" xed="VPABSB_YMMi8_MASKmskw_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_abs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := ABS(a[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPABSB" xed="VPABSB_XMMi8_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_abs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := ABS(a[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPABSB" xed="VPABSB_XMMi8_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_abs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ABS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPABSW" xed="VPABSW_YMMi16_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_abs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ABS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPABSW" xed="VPABSW_YMMi16_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_abs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ABS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPABSW" xed="VPABSW_XMMi16_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_abs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ABS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPABSW" xed="VPABSW_XMMi16_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_add_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPADDB" xed="VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_add_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPADDB" xed="VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPADDB" xed="VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPADDB" xed="VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_adds_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPADDSB" xed="VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_adds_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPADDSB" xed="VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_adds_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPADDSB" xed="VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_adds_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPADDSB" xed="VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_adds_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPADDSW" xed="VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_adds_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPADDSW" xed="VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_adds_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPADDSW" xed="VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_adds_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPADDSW" xed="VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_adds_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPADDUSB" xed="VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_adds_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPADDUSB" xed="VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_adds_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPADDUSB" xed="VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_adds_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPADDUSB" xed="VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_adds_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPADDUSW" xed="VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_adds_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPADDUSW" xed="VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_adds_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPADDUSW" xed="VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_adds_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPADDUSW" xed="VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_add_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPADDW" xed="VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_add_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPADDW" xed="VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPADDW" xed="VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPADDW" xed="VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_avg_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPAVGB" xed="VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_avg_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPAVGB" xed="VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_avg_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPAVGB" xed="VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_avg_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPAVGB" xed="VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_avg_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPAVGW" xed="VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_avg_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPAVGW" xed="VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_avg_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPAVGW" xed="VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_avg_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPAVGW" xed="VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_maddubs_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMADDUBSW" xed="VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_maddubs_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMADDUBSW" xed="VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_maddubs_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMADDUBSW" xed="VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_maddubs_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMADDUBSW" xed="VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_madd_epi16" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMADDWD" xed="VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_madd_epi16" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMADDWD" xed="VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_madd_epi16" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMADDWD" xed="VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_madd_epi16" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMADDWD" xed="VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMAXSB" xed="VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMAXSB" xed="VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMAXSB" xed="VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMAXSB" xed="VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMAXSW" xed="VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMAXSW" xed="VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMAXSW" xed="VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMAXSW" xed="VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMAXUB" xed="VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMAXUB" xed="VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMAXUB" xed="VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMAXUB" xed="VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMAXUW" xed="VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMAXUW" xed="VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMAXUW" xed="VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMAXUW" xed="VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMINSB" xed="VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMINSB" xed="VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMINSB" xed="VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMINSB" xed="VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMINSW" xed="VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMINSW" xed="VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMINSW" xed="VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMINSW" xed="VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMINUB" xed="VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMINUB" xed="VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMINUB" xed="VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMINUB" xed="VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMINUW" xed="VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMINUW" xed="VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMINUW" xed="VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMINUW" xed="VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mulhrs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+		dst[i+15:i] := tmp[16:1]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULHRSW" xed="VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mulhrs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+		dst[i+15:i] := tmp[16:1]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULHRSW" xed="VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mulhrs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+		dst[i+15:i] := tmp[16:1]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULHRSW" xed="VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mulhrs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+		dst[i+15:i] := tmp[16:1]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULHRSW" xed="VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mulhi_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := a[i+15:i] * b[i+15:i]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULHUW" xed="VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mulhi_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := a[i+15:i] * b[i+15:i]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULHUW" xed="VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mulhi_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := a[i+15:i] * b[i+15:i]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULHUW" xed="VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mulhi_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := a[i+15:i] * b[i+15:i]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULHUW" xed="VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mulhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULHW" xed="VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mulhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULHW" xed="VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mulhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULHW" xed="VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mulhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULHW" xed="VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mullo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULLW" xed="VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mullo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULLW" xed="VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mullo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULLW" xed="VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mullo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULLW" xed="VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sub_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSUBB" xed="VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sub_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSUBB" xed="VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSUBB" xed="VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSUBB" xed="VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_subs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSUBSB" xed="VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_subs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSUBSB" xed="VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_subs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSUBSB" xed="VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_subs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSUBSB" xed="VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_subs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSUBSW" xed="VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_subs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSUBSW" xed="VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_subs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSUBSW" xed="VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_subs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSUBSW" xed="VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_subs_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSUBUSB" xed="VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_subs_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSUBUSB" xed="VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_subs_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSUBUSB" xed="VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_subs_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSUBUSB" xed="VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_subs_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSUBUSW" xed="VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_subs_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSUBUSW" xed="VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_subs_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSUBUSW" xed="VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_subs_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSUBUSW" xed="VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sub_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSUBW" xed="VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sub_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSUBW" xed="VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSUBW" xed="VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSUBW" xed="VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_packs_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := Saturate16(a[31:0])
+tmp_dst[31:16] := Saturate16(a[63:32])
+tmp_dst[47:32] := Saturate16(a[95:64])
+tmp_dst[63:48] := Saturate16(a[127:96])
+tmp_dst[79:64] := Saturate16(b[31:0])
+tmp_dst[95:80] := Saturate16(b[63:32])
+tmp_dst[111:96] := Saturate16(b[95:64])
+tmp_dst[127:112] := Saturate16(b[127:96])
+tmp_dst[143:128] := Saturate16(a[159:128])
+tmp_dst[159:144] := Saturate16(a[191:160])
+tmp_dst[175:160] := Saturate16(a[223:192])
+tmp_dst[191:176] := Saturate16(a[255:224])
+tmp_dst[207:192] := Saturate16(b[159:128])
+tmp_dst[223:208] := Saturate16(b[191:160])
+tmp_dst[239:224] := Saturate16(b[223:192])
+tmp_dst[255:240] := Saturate16(b[255:224])
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPACKSSDW" xed="VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_packs_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := Saturate16(a[31:0])
+tmp_dst[31:16] := Saturate16(a[63:32])
+tmp_dst[47:32] := Saturate16(a[95:64])
+tmp_dst[63:48] := Saturate16(a[127:96])
+tmp_dst[79:64] := Saturate16(b[31:0])
+tmp_dst[95:80] := Saturate16(b[63:32])
+tmp_dst[111:96] := Saturate16(b[95:64])
+tmp_dst[127:112] := Saturate16(b[127:96])
+tmp_dst[143:128] := Saturate16(a[159:128])
+tmp_dst[159:144] := Saturate16(a[191:160])
+tmp_dst[175:160] := Saturate16(a[223:192])
+tmp_dst[191:176] := Saturate16(a[255:224])
+tmp_dst[207:192] := Saturate16(b[159:128])
+tmp_dst[223:208] := Saturate16(b[191:160])
+tmp_dst[239:224] := Saturate16(b[223:192])
+tmp_dst[255:240] := Saturate16(b[255:224])
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPACKSSDW" xed="VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_packs_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := Saturate16(a[31:0])
+tmp_dst[31:16] := Saturate16(a[63:32])
+tmp_dst[47:32] := Saturate16(a[95:64])
+tmp_dst[63:48] := Saturate16(a[127:96])
+tmp_dst[79:64] := Saturate16(b[31:0])
+tmp_dst[95:80] := Saturate16(b[63:32])
+tmp_dst[111:96] := Saturate16(b[95:64])
+tmp_dst[127:112] := Saturate16(b[127:96])
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPACKSSDW" xed="VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_packs_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := Saturate16(a[31:0])
+tmp_dst[31:16] := Saturate16(a[63:32])
+tmp_dst[47:32] := Saturate16(a[95:64])
+tmp_dst[63:48] := Saturate16(a[127:96])
+tmp_dst[79:64] := Saturate16(b[31:0])
+tmp_dst[95:80] := Saturate16(b[63:32])
+tmp_dst[111:96] := Saturate16(b[95:64])
+tmp_dst[127:112] := Saturate16(b[127:96])
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPACKSSDW" xed="VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_packs_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := Saturate8(a[15:0])
+tmp_dst[15:8] := Saturate8(a[31:16])
+tmp_dst[23:16] := Saturate8(a[47:32])
+tmp_dst[31:24] := Saturate8(a[63:48])
+tmp_dst[39:32] := Saturate8(a[79:64])
+tmp_dst[47:40] := Saturate8(a[95:80])
+tmp_dst[55:48] := Saturate8(a[111:96])
+tmp_dst[63:56] := Saturate8(a[127:112])
+tmp_dst[71:64] := Saturate8(b[15:0])
+tmp_dst[79:72] := Saturate8(b[31:16])
+tmp_dst[87:80] := Saturate8(b[47:32])
+tmp_dst[95:88] := Saturate8(b[63:48])
+tmp_dst[103:96] := Saturate8(b[79:64])
+tmp_dst[111:104] := Saturate8(b[95:80])
+tmp_dst[119:112] := Saturate8(b[111:96])
+tmp_dst[127:120] := Saturate8(b[127:112])
+tmp_dst[135:128] := Saturate8(a[143:128])
+tmp_dst[143:136] := Saturate8(a[159:144])
+tmp_dst[151:144] := Saturate8(a[175:160])
+tmp_dst[159:152] := Saturate8(a[191:176])
+tmp_dst[167:160] := Saturate8(a[207:192])
+tmp_dst[175:168] := Saturate8(a[223:208])
+tmp_dst[183:176] := Saturate8(a[239:224])
+tmp_dst[191:184] := Saturate8(a[255:240])
+tmp_dst[199:192] := Saturate8(b[143:128])
+tmp_dst[207:200] := Saturate8(b[159:144])
+tmp_dst[215:208] := Saturate8(b[175:160])
+tmp_dst[223:216] := Saturate8(b[191:176])
+tmp_dst[231:224] := Saturate8(b[207:192])
+tmp_dst[239:232] := Saturate8(b[223:208])
+tmp_dst[247:240] := Saturate8(b[239:224])
+tmp_dst[255:248] := Saturate8(b[255:240])
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPACKSSWB" xed="VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_packs_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := Saturate8(a[15:0])
+tmp_dst[15:8] := Saturate8(a[31:16])
+tmp_dst[23:16] := Saturate8(a[47:32])
+tmp_dst[31:24] := Saturate8(a[63:48])
+tmp_dst[39:32] := Saturate8(a[79:64])
+tmp_dst[47:40] := Saturate8(a[95:80])
+tmp_dst[55:48] := Saturate8(a[111:96])
+tmp_dst[63:56] := Saturate8(a[127:112])
+tmp_dst[71:64] := Saturate8(b[15:0])
+tmp_dst[79:72] := Saturate8(b[31:16])
+tmp_dst[87:80] := Saturate8(b[47:32])
+tmp_dst[95:88] := Saturate8(b[63:48])
+tmp_dst[103:96] := Saturate8(b[79:64])
+tmp_dst[111:104] := Saturate8(b[95:80])
+tmp_dst[119:112] := Saturate8(b[111:96])
+tmp_dst[127:120] := Saturate8(b[127:112])
+tmp_dst[135:128] := Saturate8(a[143:128])
+tmp_dst[143:136] := Saturate8(a[159:144])
+tmp_dst[151:144] := Saturate8(a[175:160])
+tmp_dst[159:152] := Saturate8(a[191:176])
+tmp_dst[167:160] := Saturate8(a[207:192])
+tmp_dst[175:168] := Saturate8(a[223:208])
+tmp_dst[183:176] := Saturate8(a[239:224])
+tmp_dst[191:184] := Saturate8(a[255:240])
+tmp_dst[199:192] := Saturate8(b[143:128])
+tmp_dst[207:200] := Saturate8(b[159:144])
+tmp_dst[215:208] := Saturate8(b[175:160])
+tmp_dst[223:216] := Saturate8(b[191:176])
+tmp_dst[231:224] := Saturate8(b[207:192])
+tmp_dst[239:232] := Saturate8(b[223:208])
+tmp_dst[247:240] := Saturate8(b[239:224])
+tmp_dst[255:248] := Saturate8(b[255:240])
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPACKSSWB" xed="VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_packs_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := Saturate8(a[15:0])
+tmp_dst[15:8] := Saturate8(a[31:16])
+tmp_dst[23:16] := Saturate8(a[47:32])
+tmp_dst[31:24] := Saturate8(a[63:48])
+tmp_dst[39:32] := Saturate8(a[79:64])
+tmp_dst[47:40] := Saturate8(a[95:80])
+tmp_dst[55:48] := Saturate8(a[111:96])
+tmp_dst[63:56] := Saturate8(a[127:112])
+tmp_dst[71:64] := Saturate8(b[15:0])
+tmp_dst[79:72] := Saturate8(b[31:16])
+tmp_dst[87:80] := Saturate8(b[47:32])
+tmp_dst[95:88] := Saturate8(b[63:48])
+tmp_dst[103:96] := Saturate8(b[79:64])
+tmp_dst[111:104] := Saturate8(b[95:80])
+tmp_dst[119:112] := Saturate8(b[111:96])
+tmp_dst[127:120] := Saturate8(b[127:112])
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPACKSSWB" xed="VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_packs_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := Saturate8(a[15:0])
+tmp_dst[15:8] := Saturate8(a[31:16])
+tmp_dst[23:16] := Saturate8(a[47:32])
+tmp_dst[31:24] := Saturate8(a[63:48])
+tmp_dst[39:32] := Saturate8(a[79:64])
+tmp_dst[47:40] := Saturate8(a[95:80])
+tmp_dst[55:48] := Saturate8(a[111:96])
+tmp_dst[63:56] := Saturate8(a[127:112])
+tmp_dst[71:64] := Saturate8(b[15:0])
+tmp_dst[79:72] := Saturate8(b[31:16])
+tmp_dst[87:80] := Saturate8(b[47:32])
+tmp_dst[95:88] := Saturate8(b[63:48])
+tmp_dst[103:96] := Saturate8(b[79:64])
+tmp_dst[111:104] := Saturate8(b[95:80])
+tmp_dst[119:112] := Saturate8(b[111:96])
+tmp_dst[127:120] := Saturate8(b[127:112])
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPACKSSWB" xed="VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_packus_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := SaturateU16(a[31:0])
+tmp_dst[31:16] := SaturateU16(a[63:32])
+tmp_dst[47:32] := SaturateU16(a[95:64])
+tmp_dst[63:48] := SaturateU16(a[127:96])
+tmp_dst[79:64] := SaturateU16(b[31:0])
+tmp_dst[95:80] := SaturateU16(b[63:32])
+tmp_dst[111:96] := SaturateU16(b[95:64])
+tmp_dst[127:112] := SaturateU16(b[127:96])
+tmp_dst[143:128] := SaturateU16(a[159:128])
+tmp_dst[159:144] := SaturateU16(a[191:160])
+tmp_dst[175:160] := SaturateU16(a[223:192])
+tmp_dst[191:176] := SaturateU16(a[255:224])
+tmp_dst[207:192] := SaturateU16(b[159:128])
+tmp_dst[223:208] := SaturateU16(b[191:160])
+tmp_dst[239:224] := SaturateU16(b[223:192])
+tmp_dst[255:240] := SaturateU16(b[255:224])
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPACKUSDW" xed="VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_packus_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := SaturateU16(a[31:0])
+tmp_dst[31:16] := SaturateU16(a[63:32])
+tmp_dst[47:32] := SaturateU16(a[95:64])
+tmp_dst[63:48] := SaturateU16(a[127:96])
+tmp_dst[79:64] := SaturateU16(b[31:0])
+tmp_dst[95:80] := SaturateU16(b[63:32])
+tmp_dst[111:96] := SaturateU16(b[95:64])
+tmp_dst[127:112] := SaturateU16(b[127:96])
+tmp_dst[143:128] := SaturateU16(a[159:128])
+tmp_dst[159:144] := SaturateU16(a[191:160])
+tmp_dst[175:160] := SaturateU16(a[223:192])
+tmp_dst[191:176] := SaturateU16(a[255:224])
+tmp_dst[207:192] := SaturateU16(b[159:128])
+tmp_dst[223:208] := SaturateU16(b[191:160])
+tmp_dst[239:224] := SaturateU16(b[223:192])
+tmp_dst[255:240] := SaturateU16(b[255:224])
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPACKUSDW" xed="VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_packus_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := SaturateU16(a[31:0])
+tmp_dst[31:16] := SaturateU16(a[63:32])
+tmp_dst[47:32] := SaturateU16(a[95:64])
+tmp_dst[63:48] := SaturateU16(a[127:96])
+tmp_dst[79:64] := SaturateU16(b[31:0])
+tmp_dst[95:80] := SaturateU16(b[63:32])
+tmp_dst[111:96] := SaturateU16(b[95:64])
+tmp_dst[127:112] := SaturateU16(b[127:96])
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPACKUSDW" xed="VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_packus_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := SaturateU16(a[31:0])
+tmp_dst[31:16] := SaturateU16(a[63:32])
+tmp_dst[47:32] := SaturateU16(a[95:64])
+tmp_dst[63:48] := SaturateU16(a[127:96])
+tmp_dst[79:64] := SaturateU16(b[31:0])
+tmp_dst[95:80] := SaturateU16(b[63:32])
+tmp_dst[111:96] := SaturateU16(b[95:64])
+tmp_dst[127:112] := SaturateU16(b[127:96])
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPACKUSDW" xed="VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_packus_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := SaturateU8(a[15:0])
+tmp_dst[15:8] := SaturateU8(a[31:16])
+tmp_dst[23:16] := SaturateU8(a[47:32])
+tmp_dst[31:24] := SaturateU8(a[63:48])
+tmp_dst[39:32] := SaturateU8(a[79:64])
+tmp_dst[47:40] := SaturateU8(a[95:80])
+tmp_dst[55:48] := SaturateU8(a[111:96])
+tmp_dst[63:56] := SaturateU8(a[127:112])
+tmp_dst[71:64] := SaturateU8(b[15:0])
+tmp_dst[79:72] := SaturateU8(b[31:16])
+tmp_dst[87:80] := SaturateU8(b[47:32])
+tmp_dst[95:88] := SaturateU8(b[63:48])
+tmp_dst[103:96] := SaturateU8(b[79:64])
+tmp_dst[111:104] := SaturateU8(b[95:80])
+tmp_dst[119:112] := SaturateU8(b[111:96])
+tmp_dst[127:120] := SaturateU8(b[127:112])
+tmp_dst[135:128] := SaturateU8(a[143:128])
+tmp_dst[143:136] := SaturateU8(a[159:144])
+tmp_dst[151:144] := SaturateU8(a[175:160])
+tmp_dst[159:152] := SaturateU8(a[191:176])
+tmp_dst[167:160] := SaturateU8(a[207:192])
+tmp_dst[175:168] := SaturateU8(a[223:208])
+tmp_dst[183:176] := SaturateU8(a[239:224])
+tmp_dst[191:184] := SaturateU8(a[255:240])
+tmp_dst[199:192] := SaturateU8(b[143:128])
+tmp_dst[207:200] := SaturateU8(b[159:144])
+tmp_dst[215:208] := SaturateU8(b[175:160])
+tmp_dst[223:216] := SaturateU8(b[191:176])
+tmp_dst[231:224] := SaturateU8(b[207:192])
+tmp_dst[239:232] := SaturateU8(b[223:208])
+tmp_dst[247:240] := SaturateU8(b[239:224])
+tmp_dst[255:248] := SaturateU8(b[255:240])
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPACKUSWB" xed="VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_packus_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := SaturateU8(a[15:0])
+tmp_dst[15:8] := SaturateU8(a[31:16])
+tmp_dst[23:16] := SaturateU8(a[47:32])
+tmp_dst[31:24] := SaturateU8(a[63:48])
+tmp_dst[39:32] := SaturateU8(a[79:64])
+tmp_dst[47:40] := SaturateU8(a[95:80])
+tmp_dst[55:48] := SaturateU8(a[111:96])
+tmp_dst[63:56] := SaturateU8(a[127:112])
+tmp_dst[71:64] := SaturateU8(b[15:0])
+tmp_dst[79:72] := SaturateU8(b[31:16])
+tmp_dst[87:80] := SaturateU8(b[47:32])
+tmp_dst[95:88] := SaturateU8(b[63:48])
+tmp_dst[103:96] := SaturateU8(b[79:64])
+tmp_dst[111:104] := SaturateU8(b[95:80])
+tmp_dst[119:112] := SaturateU8(b[111:96])
+tmp_dst[127:120] := SaturateU8(b[127:112])
+tmp_dst[135:128] := SaturateU8(a[143:128])
+tmp_dst[143:136] := SaturateU8(a[159:144])
+tmp_dst[151:144] := SaturateU8(a[175:160])
+tmp_dst[159:152] := SaturateU8(a[191:176])
+tmp_dst[167:160] := SaturateU8(a[207:192])
+tmp_dst[175:168] := SaturateU8(a[223:208])
+tmp_dst[183:176] := SaturateU8(a[239:224])
+tmp_dst[191:184] := SaturateU8(a[255:240])
+tmp_dst[199:192] := SaturateU8(b[143:128])
+tmp_dst[207:200] := SaturateU8(b[159:144])
+tmp_dst[215:208] := SaturateU8(b[175:160])
+tmp_dst[223:216] := SaturateU8(b[191:176])
+tmp_dst[231:224] := SaturateU8(b[207:192])
+tmp_dst[239:232] := SaturateU8(b[223:208])
+tmp_dst[247:240] := SaturateU8(b[239:224])
+tmp_dst[255:248] := SaturateU8(b[255:240])
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPACKUSWB" xed="VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_packus_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := SaturateU8(a[15:0])
+tmp_dst[15:8] := SaturateU8(a[31:16])
+tmp_dst[23:16] := SaturateU8(a[47:32])
+tmp_dst[31:24] := SaturateU8(a[63:48])
+tmp_dst[39:32] := SaturateU8(a[79:64])
+tmp_dst[47:40] := SaturateU8(a[95:80])
+tmp_dst[55:48] := SaturateU8(a[111:96])
+tmp_dst[63:56] := SaturateU8(a[127:112])
+tmp_dst[71:64] := SaturateU8(b[15:0])
+tmp_dst[79:72] := SaturateU8(b[31:16])
+tmp_dst[87:80] := SaturateU8(b[47:32])
+tmp_dst[95:88] := SaturateU8(b[63:48])
+tmp_dst[103:96] := SaturateU8(b[79:64])
+tmp_dst[111:104] := SaturateU8(b[95:80])
+tmp_dst[119:112] := SaturateU8(b[111:96])
+tmp_dst[127:120] := SaturateU8(b[127:112])
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPACKUSWB" xed="VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_packus_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := SaturateU8(a[15:0])
+tmp_dst[15:8] := SaturateU8(a[31:16])
+tmp_dst[23:16] := SaturateU8(a[47:32])
+tmp_dst[31:24] := SaturateU8(a[63:48])
+tmp_dst[39:32] := SaturateU8(a[79:64])
+tmp_dst[47:40] := SaturateU8(a[95:80])
+tmp_dst[55:48] := SaturateU8(a[111:96])
+tmp_dst[63:56] := SaturateU8(a[127:112])
+tmp_dst[71:64] := SaturateU8(b[15:0])
+tmp_dst[79:72] := SaturateU8(b[31:16])
+tmp_dst[87:80] := SaturateU8(b[47:32])
+tmp_dst[95:88] := SaturateU8(b[63:48])
+tmp_dst[103:96] := SaturateU8(b[79:64])
+tmp_dst[111:104] := SaturateU8(b[95:80])
+tmp_dst[119:112] := SaturateU8(b[111:96])
+tmp_dst[127:120] := SaturateU8(b[127:112])
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPACKUSWB" xed="VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := Saturate8(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVSWB" xed="VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := Saturate8(a[i+15:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVSWB" xed="VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi8_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := SignExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi8_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := SignExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi8_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := SignExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi8_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := SignExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := SaturateU8(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVUSWB" xed="VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := SaturateU8(a[i+15:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVUSWB" xed="VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := Truncate8(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVWB" xed="VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := Truncate8(a[i+15:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVWB" xed="VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu8_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu8_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu8_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu8_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_set1_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_set1_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_set1_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_set1_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_set1_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_set1_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast 16-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_set1_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_set1_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpge_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmple_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmplt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpneq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpeq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpge_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpgt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmple_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmplt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpneq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpeq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpge_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpgt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmple_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmplt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpneq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpge_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmple_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmplt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpneq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpeq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpge_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpgt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmple_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmplt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpneq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpeq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpge_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpgt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmple_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmplt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpneq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpge_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmple_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmplt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpneq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpeq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpge_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpgt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmple_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmplt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpneq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpeq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpge_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpgt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmple_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmplt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpneq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpge_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmple_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmplt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpneq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpeq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpge_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpgt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmple_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmplt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpneq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpeq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpge_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpgt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmple_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmplt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpneq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_test_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_test_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_test_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_test_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_test_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_test_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_test_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_test_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_testn_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k1[j]
+		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testn_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_testn_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k1[j]
+		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_testn_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_testn_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k1[j]
+		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testn_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_testn_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k1[j]
+		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_testn_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSLLVW" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSLLVW" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSLLVW" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSLLVW" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSLLVW" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSLLVW" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sll_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSLLW" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_slli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSLLW" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sll_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSLLW" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_slli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSLLW" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sll_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSLLW" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_slli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSLLW" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sll_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSLLW" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_slli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSLLW" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSRAVW" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSRAVW" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSRAVW" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRAVW" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRAVW" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSRAVW" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sra_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSRAW" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srai_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSRAW" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sra_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSRAW" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srai_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSRAW" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sra_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRAW" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srai_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSRAW" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sra_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRAW" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srai_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSRAW" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSRLVW" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSRLVW" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSRLVW" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRLVW" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRLVW" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSRLVW" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srl_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSRLW" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSRLW" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srl_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSRLW" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSRLW" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srl_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRLW" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSRLW" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srl_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRLW" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSRLW" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_add_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[15:0] + src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] + src[i+16*len+31:i+16*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_ADD(a, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_add_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[15:0] + src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] + src[i+16*len+15:i+16*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0
+	FI
+ENDFOR
+dst[15:0] := REDUCE_ADD(tmp, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_add_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[15:0] + src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] + src[i+16*len+31:i+16*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_ADD(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_add_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[15:0] + src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] + src[i+16*len+15:i+16*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0
+	FI
+ENDFOR
+dst[15:0] := REDUCE_ADD(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_add_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[7:0] + src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] + src[i+8*len+15:i+8*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_ADD(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_add_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[7:0] + src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] + src[i+8*len+7:i+8*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0
+	FI
+ENDFOR
+dst[7:0] := REDUCE_ADD(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_add_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[7:0] + src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] + src[i+8*len+15:i+8*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_ADD(a, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_add_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[7:0] + src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] + src[i+8*len+7:i+8*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0
+	FI
+ENDFOR
+dst[7:0] := REDUCE_ADD(tmp, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_mul_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[15:0] * src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] * src[i+16*len+31:i+16*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MUL(a, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_mul_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[15:0] * src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] * src[i+16*len+15:i+16*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 1
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MUL(tmp, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_mul_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[15:0] * src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] * src[i+16*len+31:i+16*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MUL(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_mul_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[15:0] * src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] * src[i+16*len+15:i+16*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 1
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MUL(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_mul_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[7:0] * src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] * src[i+8*len+15:i+8*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MUL(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_mul_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[7:0] * src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] * src[i+8*len+7:i+8*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 1
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MUL(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_mul_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[7:0] * src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] * src[i+8*len+15:i+8*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MUL(a, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_mul_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[7:0] * src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] * src[i+8*len+7:i+8*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 1
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MUL(tmp, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_or_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[15:0] OR src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] OR src[i+16*len+31:i+16*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_OR(a, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_or_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[15:0] OR src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] OR src[i+16*len+15:i+16*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0
+	FI
+ENDFOR
+dst[15:0] := REDUCE_OR(tmp, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_or_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[15:0] OR src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] OR src[i+16*len+31:i+16*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_OR(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_or_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[15:0] OR src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] OR src[i+16*len+15:i+16*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0
+	FI
+ENDFOR
+dst[15:0] := REDUCE_OR(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_or_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[7:0] OR src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] OR src[i+8*len+15:i+8*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_OR(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_or_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[7:0] OR src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] OR src[i+8*len+7:i+8*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0
+	FI
+ENDFOR
+dst[7:0] := REDUCE_OR(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_or_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[7:0] OR src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] OR src[i+8*len+15:i+8*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_OR(a, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_or_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[7:0] OR src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] OR src[i+8*len+7:i+8*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0
+	FI
+ENDFOR
+dst[7:0] := REDUCE_OR(tmp, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_and_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[15:0] AND src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] AND src[i+16*len+31:i+16*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_AND(a, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_and_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[15:0] AND src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] AND src[i+16*len+15:i+16*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0xFFFF
+	FI
+ENDFOR
+dst[15:0] := REDUCE_AND(tmp, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_and_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[15:0] AND src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] AND src[i+16*len+31:i+16*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_AND(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_and_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[15:0] AND src[31:16]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := src[i+15:i] AND src[i+16*len+15:i+16*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0xFFFF
+	FI
+ENDFOR
+dst[15:0] := REDUCE_AND(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_and_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[7:0] AND src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] AND src[i+8*len+15:i+8*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_AND(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_and_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[7:0] AND src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] AND src[i+8*len+7:i+8*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0xFF
+	FI
+ENDFOR
+dst[7:0] := REDUCE_AND(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_and_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[7:0] AND src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] AND src[i+8*len+15:i+8*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_AND(a, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_and_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[7:0] AND src[15:8]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := src[i+7:i] AND src[i+8*len+7:i+8*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0xFF
+	FI
+ENDFOR
+dst[7:0] := REDUCE_AND(tmp, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_max_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed signed 16-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MAX(a, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_max_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed signed 16-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := Int16(-0x8000)
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MAX(tmp, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_max_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed signed 16-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MAX(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_max_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed signed 16-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := Int16(-0x8000)
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MAX(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_max_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed signed 8-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MAX(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_max_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed signed 8-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := Int8(-0x80)
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MAX(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_max_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed signed 8-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MAX(a, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_max_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed signed 8-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := Int8(-0x80)
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MAX(tmp, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_max_epu16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Reduce the packed unsigned 16-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MAX(a, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_max_epu16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Reduce the packed unsigned 16-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MAX(tmp, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_max_epu16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Reduce the packed unsigned 16-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MAX(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_max_epu16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Reduce the packed unsigned 16-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MAX(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_max_epu8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Reduce the packed unsigned 8-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MAX(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_max_epu8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Reduce the packed unsigned 8-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MAX(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_max_epu8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Reduce the packed unsigned 8-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MAX(a, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_max_epu8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Reduce the packed unsigned 8-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MAX(tmp, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_min_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed signed 16-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MIN(a, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_min_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Reduce the packed signed 16-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := Int16(0x7FFF)
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MIN(tmp, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_min_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed signed 16-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MIN(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_min_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="SI16" type="short" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Reduce the packed signed 16-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := Int16(0x7FFF)
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MIN(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_min_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed signed 8-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MIN(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_min_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Reduce the packed signed 8-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := Int8(0x7F)
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MIN(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_min_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed signed 8-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MIN(a, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_min_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="SI8" type="char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Reduce the packed signed 8-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := Int8(0x7F)
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MIN(tmp, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_min_epu16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Reduce the packed unsigned 16-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MIN(a, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_min_epu16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Reduce the packed unsigned 16-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0xFFFF
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MIN(tmp, 8)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_min_epu16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Reduce the packed unsigned 16-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[16*len-1:0], len)
+}
+dst[15:0] := REDUCE_MIN(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_min_epu16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Reduce the packed unsigned 16-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*16
+		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[16*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[i+15:i] := a[i+15:i]
+	ELSE
+		tmp[i+15:i] := 0xFFFF
+	FI
+ENDFOR
+dst[15:0] := REDUCE_MIN(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_min_epu8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Reduce the packed unsigned 8-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MIN(a, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_min_epu8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Reduce the packed unsigned 8-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0xFF
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MIN(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_min_epu8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Reduce the packed unsigned 8-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[8*len-1:0], len)
+}
+dst[7:0] := REDUCE_MIN(a, 32)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_min_epu8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Reduce the packed unsigned 8-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*8
+		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[8*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		tmp[i+7:i] := a[i+7:i]
+	ELSE
+		tmp[i+7:i] := 0xFF
+	FI
+ENDFOR
+dst[7:0] := REDUCE_MIN(tmp, 16)
+	</operation>
+	<CPUID>AVX512BW</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	
+<intrinsic name="_mm512_kunpackd" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Unpack and interleave 32 bits from masks "a" and "b", and store the 64-bit result in "dst".</description>
+	<operation>
+dst[31:0] := b[31:0]
+dst[63:32] := a[31:0]
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="k, k, k" name="KUNPCKDQ" xed="KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kunpackw" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Unpack and interleave 16 bits from masks "a" and "b", and store the 32-bit result in "dst".</description>
+	<operation>
+dst[15:0] := b[15:0]
+dst[31:16] := a[15:0]
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="k, k, k" name="KUNPCKWD" xed="KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+FOR i := 0 to 3
+	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ENDFOR
+FOR j := 0 to 7
+	i := j*64
+	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+FOR i := 0 to 3
+	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ENDFOR
+FOR j := 0 to 7
+	i := j*64
+	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_dbsad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
+	<operation>
+FOR i := 0 to 3
+	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
+	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
+	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
+	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
+ENDFOR
+FOR j := 0 to 7
+	i := j*64
+	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
+	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
+	
+	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
+	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
+	
+	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
+	
+	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
+	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
+ENDFOR
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_alignr_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*128
+	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+	dst[i+127:i] := tmp[127:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPALIGNR" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_alignr_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*128
+	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+	tmp_dst[i+127:i] := tmp[127:0]
+ENDFOR
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPALIGNR" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_alignr_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*128
+	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
+	tmp_dst[i+127:i] := tmp[127:0]
+ENDFOR
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPALIGNR" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_blend_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := b[i+7:i]
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMB" xed="VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_blend_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := b[i+15:i]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMW" xed="VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcastb_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := a[7:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcastb_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcastb_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcastw_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := a[15:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcastw_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcastw_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask2_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+4:i]
+		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := idx[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2W" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+4:i]
+		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2W" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		off := 16*idx[i+4:i]
+		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2W" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2W" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex2var_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	off := 16*idx[i+4:i]
+	dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMI2W" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VPERMT2W" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	id := idx[i+4:i]*16
+	IF k[j]
+		dst[i+15:i] := a[id+15:id]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMW" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	id := idx[i+4:i]*16
+	IF k[j]
+		dst[i+15:i] := a[id+15:id]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMW" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutexvar_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	id := idx[i+4:i]*16
+	dst[i+15:i] := a[id+15:id]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMW" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movepi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF a[i+7]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm" name="VPMOVB2M" xed="VPMOVB2M_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movm_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := 0xFF
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm" name="VPMOVM2B" xed="VPMOVM2B_ZMMu8_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movm_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := 0xFFFF
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm" name="VPMOVM2W" xed="VPMOVM2W_ZMMu16_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movepi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF a[i+15]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm" name="VPMOVW2M" xed="VPMOVW2M_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sad_epu8" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce eight unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
+ENDFOR
+FOR j := 0 to 7
+	i := j*64
+	dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
+	               tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
+	dst[i+63:i+16] := 0
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSADBW" xed="VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shuffle_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" within 128-bit lanes using the control in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		IF b[i+7] == 1
+			dst[i+7:i] := 0
+		ELSE
+			index[5:0] := b[i+3:i] + (j &amp; 0x30)
+			dst[i+7:i] := a[index*8+7:index*8]
+		FI
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSHUFB" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shuffle_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		IF b[i+7] == 1
+			dst[i+7:i] := 0
+		ELSE
+			index[5:0] := b[i+3:i] + (j &amp; 0x30)
+			dst[i+7:i] := a[index*8+7:index*8]
+		FI
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSHUFB" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shuffle_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF b[i+7] == 1
+		dst[i+7:i] := 0
+	ELSE
+		index[5:0] := b[i+3:i] + (j &amp; 0x30)
+		dst[i+7:i] := a[index*8+7:index*8]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSHUFB" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shufflehi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := a[63:0]
+tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+tmp_dst[191:128] := a[191:128]
+tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+tmp_dst[319:256] := a[319:256]
+tmp_dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
+tmp_dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
+tmp_dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
+tmp_dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
+tmp_dst[447:384] := a[447:384]
+tmp_dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
+tmp_dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
+tmp_dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
+tmp_dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shufflehi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := a[63:0]
+tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+tmp_dst[191:128] := a[191:128]
+tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+tmp_dst[319:256] := a[319:256]
+tmp_dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
+tmp_dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
+tmp_dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
+tmp_dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
+tmp_dst[447:384] := a[447:384]
+tmp_dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
+tmp_dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
+tmp_dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
+tmp_dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shufflehi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+dst[191:128] := a[191:128]
+dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
+dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
+dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
+dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
+dst[319:256] := a[319:256]
+dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
+dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
+dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
+dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
+dst[447:384] := a[447:384]
+dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
+dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
+dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
+dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shufflelo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+tmp_dst[127:64] := a[127:64]
+tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+tmp_dst[255:192] := a[255:192]
+tmp_dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
+tmp_dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
+tmp_dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
+tmp_dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
+tmp_dst[383:320] := a[383:320]
+tmp_dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
+tmp_dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
+tmp_dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
+tmp_dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
+tmp_dst[511:448] := a[511:448]
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shufflelo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+tmp_dst[127:64] := a[127:64]
+tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+tmp_dst[255:192] := a[255:192]
+tmp_dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
+tmp_dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
+tmp_dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
+tmp_dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
+tmp_dst[383:320] := a[383:320]
+tmp_dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
+tmp_dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
+tmp_dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
+tmp_dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
+tmp_dst[511:448] := a[511:448]
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shufflelo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
+	<operation>
+dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+dst[127:64] := a[127:64]
+dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
+dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
+dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
+dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
+dst[255:192] := a[255:192]
+dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
+dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
+dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
+dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
+dst[383:320] := a[383:320]
+dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
+dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
+dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
+dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
+dst[511:448] := a[511:448]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpackhi_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpackhi_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpackhi_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpackhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpackhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpackhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpacklo_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpacklo_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpacklo_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpacklo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpacklo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpacklo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_loadu_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 32 packed 16-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_loadu_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 64 packed 8-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_load_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" memwidth="32" type="__mmask32*" varname="mem_addr" />
+	<description>Load 32-bit mask from memory into "k".</description>
+	<operation>
+k[31:0] := MEM[mem_addr+31:mem_addr]
+	</operation>
+	<instruction form="k, m32" name="KMOVD" xed="KMOVD_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_load_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" memwidth="64" type="__mmask64*" varname="mem_addr" />
+	<description>Load 64-bit mask from memory into "k".</description>
+	<operation>
+k[63:0] := MEM[mem_addr+63:mem_addr]
+	</operation>
+	<instruction form="k, m64" name="KMOVQ" xed="KMOVQ_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mov_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mov_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mov_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mov_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_storeu_epi16" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI16" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_storeu_epi8" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI8" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_storeu_epi16" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI16" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Store 512-bits (composed of 32 packed 16-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_storeu_epi8" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI8" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Store 512-bits (composed of 64 packed 8-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_store_mask32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="MASK" memwidth="32" type="__mmask32*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<description>Store 32-bit mask from "a" into memory.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[31:0]
+	</operation>
+	<instruction form="m32, k" name="KMOVD" xed="KMOVD_MEMu32_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_store_mask64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="MASK" memwidth="64" type="__mmask64*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<description>Store 64-bit mask from "a" into memory.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+	</operation>
+	<instruction form="m64, k" name="KMOVQ" xed="KMOVQ_MEMu64_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_abs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := ABS(a[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPABSB" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_abs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := ABS(a[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPABSB" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_abs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := ABS(a[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPABSB" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_abs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ABS(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPABSW" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_abs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ABS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPABSW" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_abs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ABS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPABSW" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPADDB" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPADDB" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] + b[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPADDB" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_adds_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPADDSB" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_adds_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPADDSB" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_adds_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPADDSB" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_adds_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPADDSW" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_adds_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPADDSW" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_adds_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPADDSW" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_adds_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPADDUSB" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_adds_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPADDUSB" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_adds_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPADDUSB" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_adds_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPADDUSW" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_adds_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPADDUSW" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_adds_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPADDUSW" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPADDW" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPADDW" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] + b[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPADDW" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_avg_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPAVGB" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_avg_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPAVGB" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_avg_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPAVGB" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_avg_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPAVGW" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_avg_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPAVGW" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_avg_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPAVGW" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maddubs_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMADDUBSW" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_maddubs_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMADDUBSW" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_maddubs_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMADDUBSW" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_madd_epi16" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMADDWD" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_madd_epi16" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMADDWD" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_madd_epi16" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMADDWD" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMAXSB" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMAXSB" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMAXSB" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMAXSW" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMAXSW" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMAXSW" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMAXUB" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMAXUB" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMAXUB" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMAXUW" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMAXUW" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMAXUW" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMINSB" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMINSB" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMINSB" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMINSW" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMINSW" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMINSW" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMINUB" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMINUB" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMINUB" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMINUW" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMINUW" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMINUW" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mulhrs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+		dst[i+15:i] := tmp[16:1]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULHRSW" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mulhrs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+		dst[i+15:i] := tmp[16:1]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULHRSW" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mulhrs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+	dst[i+15:i] := tmp[16:1]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULHRSW" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mulhi_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := a[i+15:i] * b[i+15:i]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULHUW" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mulhi_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := a[i+15:i] * b[i+15:i]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULHUW" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mulhi_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	tmp[31:0] := a[i+15:i] * b[i+15:i]
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULHUW" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mulhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULHW" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mulhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULHW" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mulhi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULHW" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mullo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULLW" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mullo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+		dst[i+15:i] := tmp[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULLW" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mullo_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+	dst[i+15:i] := tmp[15:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULLW" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSUBB" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[i+7:i] - b[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSUBB" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSUBB" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_subs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSUBSB" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_subs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSUBSB" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_subs_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSUBSB" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_subs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSUBSW" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_subs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSUBSW" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_subs_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSUBSW" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_subs_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSUBUSB" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_subs_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSUBUSB" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_subs_epu8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSUBUSB" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_subs_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSUBUSW" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_subs_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSUBUSW" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_subs_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSUBUSW" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSUBW" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[i+15:i] - b[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSUBW" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSUBW" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_packs_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := Saturate16(a[31:0])
+tmp_dst[31:16] := Saturate16(a[63:32])
+tmp_dst[47:32] := Saturate16(a[95:64])
+tmp_dst[63:48] := Saturate16(a[127:96])
+tmp_dst[79:64] := Saturate16(b[31:0])
+tmp_dst[95:80] := Saturate16(b[63:32])
+tmp_dst[111:96] := Saturate16(b[95:64])
+tmp_dst[127:112] := Saturate16(b[127:96])
+tmp_dst[143:128] := Saturate16(a[159:128])
+tmp_dst[159:144] := Saturate16(a[191:160])
+tmp_dst[175:160] := Saturate16(a[223:192])
+tmp_dst[191:176] := Saturate16(a[255:224])
+tmp_dst[207:192] := Saturate16(b[159:128])
+tmp_dst[223:208] := Saturate16(b[191:160])
+tmp_dst[239:224] := Saturate16(b[223:192])
+tmp_dst[255:240] := Saturate16(b[255:224])
+tmp_dst[271:256] := Saturate16(a[287:256])
+tmp_dst[287:272] := Saturate16(a[319:288])
+tmp_dst[303:288] := Saturate16(a[351:320])
+tmp_dst[319:304] := Saturate16(a[383:352])
+tmp_dst[335:320] := Saturate16(b[287:256])
+tmp_dst[351:336] := Saturate16(b[319:288])
+tmp_dst[367:352] := Saturate16(b[351:320])
+tmp_dst[383:368] := Saturate16(b[383:352])
+tmp_dst[399:384] := Saturate16(a[415:384])
+tmp_dst[415:400] := Saturate16(a[447:416])
+tmp_dst[431:416] := Saturate16(a[479:448])
+tmp_dst[447:432] := Saturate16(a[511:480])
+tmp_dst[463:448] := Saturate16(b[415:384])
+tmp_dst[479:464] := Saturate16(b[447:416])
+tmp_dst[495:480] := Saturate16(b[479:448])
+tmp_dst[511:496] := Saturate16(b[511:480])
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPACKSSDW" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_packs_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := Saturate16(a[31:0])
+tmp_dst[31:16] := Saturate16(a[63:32])
+tmp_dst[47:32] := Saturate16(a[95:64])
+tmp_dst[63:48] := Saturate16(a[127:96])
+tmp_dst[79:64] := Saturate16(b[31:0])
+tmp_dst[95:80] := Saturate16(b[63:32])
+tmp_dst[111:96] := Saturate16(b[95:64])
+tmp_dst[127:112] := Saturate16(b[127:96])
+tmp_dst[143:128] := Saturate16(a[159:128])
+tmp_dst[159:144] := Saturate16(a[191:160])
+tmp_dst[175:160] := Saturate16(a[223:192])
+tmp_dst[191:176] := Saturate16(a[255:224])
+tmp_dst[207:192] := Saturate16(b[159:128])
+tmp_dst[223:208] := Saturate16(b[191:160])
+tmp_dst[239:224] := Saturate16(b[223:192])
+tmp_dst[255:240] := Saturate16(b[255:224])
+tmp_dst[271:256] := Saturate16(a[287:256])
+tmp_dst[287:272] := Saturate16(a[319:288])
+tmp_dst[303:288] := Saturate16(a[351:320])
+tmp_dst[319:304] := Saturate16(a[383:352])
+tmp_dst[335:320] := Saturate16(b[287:256])
+tmp_dst[351:336] := Saturate16(b[319:288])
+tmp_dst[367:352] := Saturate16(b[351:320])
+tmp_dst[383:368] := Saturate16(b[383:352])
+tmp_dst[399:384] := Saturate16(a[415:384])
+tmp_dst[415:400] := Saturate16(a[447:416])
+tmp_dst[431:416] := Saturate16(a[479:448])
+tmp_dst[447:432] := Saturate16(a[511:480])
+tmp_dst[463:448] := Saturate16(b[415:384])
+tmp_dst[479:464] := Saturate16(b[447:416])
+tmp_dst[495:480] := Saturate16(b[479:448])
+tmp_dst[511:496] := Saturate16(b[511:480])
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPACKSSDW" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_packs_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[31:0])
+dst[31:16] := Saturate16(a[63:32])
+dst[47:32] := Saturate16(a[95:64])
+dst[63:48] := Saturate16(a[127:96])
+dst[79:64] := Saturate16(b[31:0])
+dst[95:80] := Saturate16(b[63:32])
+dst[111:96] := Saturate16(b[95:64])
+dst[127:112] := Saturate16(b[127:96])
+dst[143:128] := Saturate16(a[159:128])
+dst[159:144] := Saturate16(a[191:160])
+dst[175:160] := Saturate16(a[223:192])
+dst[191:176] := Saturate16(a[255:224])
+dst[207:192] := Saturate16(b[159:128])
+dst[223:208] := Saturate16(b[191:160])
+dst[239:224] := Saturate16(b[223:192])
+dst[255:240] := Saturate16(b[255:224])
+dst[271:256] := Saturate16(a[287:256])
+dst[287:272] := Saturate16(a[319:288])
+dst[303:288] := Saturate16(a[351:320])
+dst[319:304] := Saturate16(a[383:352])
+dst[335:320] := Saturate16(b[287:256])
+dst[351:336] := Saturate16(b[319:288])
+dst[367:352] := Saturate16(b[351:320])
+dst[383:368] := Saturate16(b[383:352])
+dst[399:384] := Saturate16(a[415:384])
+dst[415:400] := Saturate16(a[447:416])
+dst[431:416] := Saturate16(a[479:448])
+dst[447:432] := Saturate16(a[511:480])
+dst[463:448] := Saturate16(b[415:384])
+dst[479:464] := Saturate16(b[447:416])
+dst[495:480] := Saturate16(b[479:448])
+dst[511:496] := Saturate16(b[511:480])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPACKSSDW" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_packs_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI8" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := Saturate8(a[15:0])
+tmp_dst[15:8] := Saturate8(a[31:16])
+tmp_dst[23:16] := Saturate8(a[47:32])
+tmp_dst[31:24] := Saturate8(a[63:48])
+tmp_dst[39:32] := Saturate8(a[79:64])
+tmp_dst[47:40] := Saturate8(a[95:80])
+tmp_dst[55:48] := Saturate8(a[111:96])
+tmp_dst[63:56] := Saturate8(a[127:112])
+tmp_dst[71:64] := Saturate8(b[15:0])
+tmp_dst[79:72] := Saturate8(b[31:16])
+tmp_dst[87:80] := Saturate8(b[47:32])
+tmp_dst[95:88] := Saturate8(b[63:48])
+tmp_dst[103:96] := Saturate8(b[79:64])
+tmp_dst[111:104] := Saturate8(b[95:80])
+tmp_dst[119:112] := Saturate8(b[111:96])
+tmp_dst[127:120] := Saturate8(b[127:112])
+tmp_dst[135:128] := Saturate8(a[143:128])
+tmp_dst[143:136] := Saturate8(a[159:144])
+tmp_dst[151:144] := Saturate8(a[175:160])
+tmp_dst[159:152] := Saturate8(a[191:176])
+tmp_dst[167:160] := Saturate8(a[207:192])
+tmp_dst[175:168] := Saturate8(a[223:208])
+tmp_dst[183:176] := Saturate8(a[239:224])
+tmp_dst[191:184] := Saturate8(a[255:240])
+tmp_dst[199:192] := Saturate8(b[143:128])
+tmp_dst[207:200] := Saturate8(b[159:144])
+tmp_dst[215:208] := Saturate8(b[175:160])
+tmp_dst[223:216] := Saturate8(b[191:176])
+tmp_dst[231:224] := Saturate8(b[207:192])
+tmp_dst[239:232] := Saturate8(b[223:208])
+tmp_dst[247:240] := Saturate8(b[239:224])
+tmp_dst[255:248] := Saturate8(b[255:240])
+tmp_dst[263:256] := Saturate8(a[271:256])
+tmp_dst[271:264] := Saturate8(a[287:272])
+tmp_dst[279:272] := Saturate8(a[303:288])
+tmp_dst[287:280] := Saturate8(a[319:304])
+tmp_dst[295:288] := Saturate8(a[335:320])
+tmp_dst[303:296] := Saturate8(a[351:336])
+tmp_dst[311:304] := Saturate8(a[367:352])
+tmp_dst[319:312] := Saturate8(a[383:368])
+tmp_dst[327:320] := Saturate8(b[271:256])
+tmp_dst[335:328] := Saturate8(b[287:272])
+tmp_dst[343:336] := Saturate8(b[303:288])
+tmp_dst[351:344] := Saturate8(b[319:304])
+tmp_dst[359:352] := Saturate8(b[335:320])
+tmp_dst[367:360] := Saturate8(b[351:336])
+tmp_dst[375:368] := Saturate8(b[367:352])
+tmp_dst[383:376] := Saturate8(b[383:368])
+tmp_dst[391:384] := Saturate8(a[399:384])
+tmp_dst[399:392] := Saturate8(a[415:400])
+tmp_dst[407:400] := Saturate8(a[431:416])
+tmp_dst[415:408] := Saturate8(a[447:432])
+tmp_dst[423:416] := Saturate8(a[463:448])
+tmp_dst[431:424] := Saturate8(a[479:464])
+tmp_dst[439:432] := Saturate8(a[495:480])
+tmp_dst[447:440] := Saturate8(a[511:496])
+tmp_dst[455:448] := Saturate8(b[399:384])
+tmp_dst[463:456] := Saturate8(b[415:400])
+tmp_dst[471:464] := Saturate8(b[431:416])
+tmp_dst[479:472] := Saturate8(b[447:432])
+tmp_dst[487:480] := Saturate8(b[463:448])
+tmp_dst[495:488] := Saturate8(b[479:464])
+tmp_dst[503:496] := Saturate8(b[495:480])
+tmp_dst[511:504] := Saturate8(b[511:496])
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPACKSSWB" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_packs_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := Saturate8(a[15:0])
+tmp_dst[15:8] := Saturate8(a[31:16])
+tmp_dst[23:16] := Saturate8(a[47:32])
+tmp_dst[31:24] := Saturate8(a[63:48])
+tmp_dst[39:32] := Saturate8(a[79:64])
+tmp_dst[47:40] := Saturate8(a[95:80])
+tmp_dst[55:48] := Saturate8(a[111:96])
+tmp_dst[63:56] := Saturate8(a[127:112])
+tmp_dst[71:64] := Saturate8(b[15:0])
+tmp_dst[79:72] := Saturate8(b[31:16])
+tmp_dst[87:80] := Saturate8(b[47:32])
+tmp_dst[95:88] := Saturate8(b[63:48])
+tmp_dst[103:96] := Saturate8(b[79:64])
+tmp_dst[111:104] := Saturate8(b[95:80])
+tmp_dst[119:112] := Saturate8(b[111:96])
+tmp_dst[127:120] := Saturate8(b[127:112])
+tmp_dst[135:128] := Saturate8(a[143:128])
+tmp_dst[143:136] := Saturate8(a[159:144])
+tmp_dst[151:144] := Saturate8(a[175:160])
+tmp_dst[159:152] := Saturate8(a[191:176])
+tmp_dst[167:160] := Saturate8(a[207:192])
+tmp_dst[175:168] := Saturate8(a[223:208])
+tmp_dst[183:176] := Saturate8(a[239:224])
+tmp_dst[191:184] := Saturate8(a[255:240])
+tmp_dst[199:192] := Saturate8(b[143:128])
+tmp_dst[207:200] := Saturate8(b[159:144])
+tmp_dst[215:208] := Saturate8(b[175:160])
+tmp_dst[223:216] := Saturate8(b[191:176])
+tmp_dst[231:224] := Saturate8(b[207:192])
+tmp_dst[239:232] := Saturate8(b[223:208])
+tmp_dst[247:240] := Saturate8(b[239:224])
+tmp_dst[255:248] := Saturate8(b[255:240])
+tmp_dst[263:256] := Saturate8(a[271:256])
+tmp_dst[271:264] := Saturate8(a[287:272])
+tmp_dst[279:272] := Saturate8(a[303:288])
+tmp_dst[287:280] := Saturate8(a[319:304])
+tmp_dst[295:288] := Saturate8(a[335:320])
+tmp_dst[303:296] := Saturate8(a[351:336])
+tmp_dst[311:304] := Saturate8(a[367:352])
+tmp_dst[319:312] := Saturate8(a[383:368])
+tmp_dst[327:320] := Saturate8(b[271:256])
+tmp_dst[335:328] := Saturate8(b[287:272])
+tmp_dst[343:336] := Saturate8(b[303:288])
+tmp_dst[351:344] := Saturate8(b[319:304])
+tmp_dst[359:352] := Saturate8(b[335:320])
+tmp_dst[367:360] := Saturate8(b[351:336])
+tmp_dst[375:368] := Saturate8(b[367:352])
+tmp_dst[383:376] := Saturate8(b[383:368])
+tmp_dst[391:384] := Saturate8(a[399:384])
+tmp_dst[399:392] := Saturate8(a[415:400])
+tmp_dst[407:400] := Saturate8(a[431:416])
+tmp_dst[415:408] := Saturate8(a[447:432])
+tmp_dst[423:416] := Saturate8(a[463:448])
+tmp_dst[431:424] := Saturate8(a[479:464])
+tmp_dst[439:432] := Saturate8(a[495:480])
+tmp_dst[447:440] := Saturate8(a[511:496])
+tmp_dst[455:448] := Saturate8(b[399:384])
+tmp_dst[463:456] := Saturate8(b[415:400])
+tmp_dst[471:464] := Saturate8(b[431:416])
+tmp_dst[479:472] := Saturate8(b[447:432])
+tmp_dst[487:480] := Saturate8(b[463:448])
+tmp_dst[495:488] := Saturate8(b[479:464])
+tmp_dst[503:496] := Saturate8(b[495:480])
+tmp_dst[511:504] := Saturate8(b[511:496])
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPACKSSWB" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_packs_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="SI8" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := Saturate8(a[15:0])
+dst[15:8] := Saturate8(a[31:16])
+dst[23:16] := Saturate8(a[47:32])
+dst[31:24] := Saturate8(a[63:48])
+dst[39:32] := Saturate8(a[79:64])
+dst[47:40] := Saturate8(a[95:80])
+dst[55:48] := Saturate8(a[111:96])
+dst[63:56] := Saturate8(a[127:112])
+dst[71:64] := Saturate8(b[15:0])
+dst[79:72] := Saturate8(b[31:16])
+dst[87:80] := Saturate8(b[47:32])
+dst[95:88] := Saturate8(b[63:48])
+dst[103:96] := Saturate8(b[79:64])
+dst[111:104] := Saturate8(b[95:80])
+dst[119:112] := Saturate8(b[111:96])
+dst[127:120] := Saturate8(b[127:112])
+dst[135:128] := Saturate8(a[143:128])
+dst[143:136] := Saturate8(a[159:144])
+dst[151:144] := Saturate8(a[175:160])
+dst[159:152] := Saturate8(a[191:176])
+dst[167:160] := Saturate8(a[207:192])
+dst[175:168] := Saturate8(a[223:208])
+dst[183:176] := Saturate8(a[239:224])
+dst[191:184] := Saturate8(a[255:240])
+dst[199:192] := Saturate8(b[143:128])
+dst[207:200] := Saturate8(b[159:144])
+dst[215:208] := Saturate8(b[175:160])
+dst[223:216] := Saturate8(b[191:176])
+dst[231:224] := Saturate8(b[207:192])
+dst[239:232] := Saturate8(b[223:208])
+dst[247:240] := Saturate8(b[239:224])
+dst[255:248] := Saturate8(b[255:240])
+dst[263:256] := Saturate8(a[271:256])
+dst[271:264] := Saturate8(a[287:272])
+dst[279:272] := Saturate8(a[303:288])
+dst[287:280] := Saturate8(a[319:304])
+dst[295:288] := Saturate8(a[335:320])
+dst[303:296] := Saturate8(a[351:336])
+dst[311:304] := Saturate8(a[367:352])
+dst[319:312] := Saturate8(a[383:368])
+dst[327:320] := Saturate8(b[271:256])
+dst[335:328] := Saturate8(b[287:272])
+dst[343:336] := Saturate8(b[303:288])
+dst[351:344] := Saturate8(b[319:304])
+dst[359:352] := Saturate8(b[335:320])
+dst[367:360] := Saturate8(b[351:336])
+dst[375:368] := Saturate8(b[367:352])
+dst[383:376] := Saturate8(b[383:368])
+dst[391:384] := Saturate8(a[399:384])
+dst[399:392] := Saturate8(a[415:400])
+dst[407:400] := Saturate8(a[431:416])
+dst[415:408] := Saturate8(a[447:432])
+dst[423:416] := Saturate8(a[463:448])
+dst[431:424] := Saturate8(a[479:464])
+dst[439:432] := Saturate8(a[495:480])
+dst[447:440] := Saturate8(a[511:496])
+dst[455:448] := Saturate8(b[399:384])
+dst[463:456] := Saturate8(b[415:400])
+dst[471:464] := Saturate8(b[431:416])
+dst[479:472] := Saturate8(b[447:432])
+dst[487:480] := Saturate8(b[463:448])
+dst[495:488] := Saturate8(b[479:464])
+dst[503:496] := Saturate8(b[495:480])
+dst[511:504] := Saturate8(b[511:496])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPACKSSWB" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_packus_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := SaturateU16(a[31:0])
+tmp_dst[31:16] := SaturateU16(a[63:32])
+tmp_dst[47:32] := SaturateU16(a[95:64])
+tmp_dst[63:48] := SaturateU16(a[127:96])
+tmp_dst[79:64] := SaturateU16(b[31:0])
+tmp_dst[95:80] := SaturateU16(b[63:32])
+tmp_dst[111:96] := SaturateU16(b[95:64])
+tmp_dst[127:112] := SaturateU16(b[127:96])
+tmp_dst[143:128] := SaturateU16(a[159:128])
+tmp_dst[159:144] := SaturateU16(a[191:160])
+tmp_dst[175:160] := SaturateU16(a[223:192])
+tmp_dst[191:176] := SaturateU16(a[255:224])
+tmp_dst[207:192] := SaturateU16(b[159:128])
+tmp_dst[223:208] := SaturateU16(b[191:160])
+tmp_dst[239:224] := SaturateU16(b[223:192])
+tmp_dst[255:240] := SaturateU16(b[255:224])
+tmp_dst[271:256] := SaturateU16(a[287:256])
+tmp_dst[287:272] := SaturateU16(a[319:288])
+tmp_dst[303:288] := SaturateU16(a[351:320])
+tmp_dst[319:304] := SaturateU16(a[383:352])
+tmp_dst[335:320] := SaturateU16(b[287:256])
+tmp_dst[351:336] := SaturateU16(b[319:288])
+tmp_dst[367:352] := SaturateU16(b[351:320])
+tmp_dst[383:368] := SaturateU16(b[383:352])
+tmp_dst[399:384] := SaturateU16(a[415:384])
+tmp_dst[415:400] := SaturateU16(a[447:416])
+tmp_dst[431:416] := SaturateU16(a[479:448])
+tmp_dst[447:432] := SaturateU16(a[511:480])
+tmp_dst[463:448] := SaturateU16(b[415:384])
+tmp_dst[479:464] := SaturateU16(b[447:416])
+tmp_dst[495:480] := SaturateU16(b[479:448])
+tmp_dst[511:496] := SaturateU16(b[511:480])
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPACKUSDW" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_packus_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[15:0] := SaturateU16(a[31:0])
+tmp_dst[31:16] := SaturateU16(a[63:32])
+tmp_dst[47:32] := SaturateU16(a[95:64])
+tmp_dst[63:48] := SaturateU16(a[127:96])
+tmp_dst[79:64] := SaturateU16(b[31:0])
+tmp_dst[95:80] := SaturateU16(b[63:32])
+tmp_dst[111:96] := SaturateU16(b[95:64])
+tmp_dst[127:112] := SaturateU16(b[127:96])
+tmp_dst[143:128] := SaturateU16(a[159:128])
+tmp_dst[159:144] := SaturateU16(a[191:160])
+tmp_dst[175:160] := SaturateU16(a[223:192])
+tmp_dst[191:176] := SaturateU16(a[255:224])
+tmp_dst[207:192] := SaturateU16(b[159:128])
+tmp_dst[223:208] := SaturateU16(b[191:160])
+tmp_dst[239:224] := SaturateU16(b[223:192])
+tmp_dst[255:240] := SaturateU16(b[255:224])
+tmp_dst[271:256] := SaturateU16(a[287:256])
+tmp_dst[287:272] := SaturateU16(a[319:288])
+tmp_dst[303:288] := SaturateU16(a[351:320])
+tmp_dst[319:304] := SaturateU16(a[383:352])
+tmp_dst[335:320] := SaturateU16(b[287:256])
+tmp_dst[351:336] := SaturateU16(b[319:288])
+tmp_dst[367:352] := SaturateU16(b[351:320])
+tmp_dst[383:368] := SaturateU16(b[383:352])
+tmp_dst[399:384] := SaturateU16(a[415:384])
+tmp_dst[415:400] := SaturateU16(a[447:416])
+tmp_dst[431:416] := SaturateU16(a[479:448])
+tmp_dst[447:432] := SaturateU16(a[511:480])
+tmp_dst[463:448] := SaturateU16(b[415:384])
+tmp_dst[479:464] := SaturateU16(b[447:416])
+tmp_dst[495:480] := SaturateU16(b[479:448])
+tmp_dst[511:496] := SaturateU16(b[511:480])
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := tmp_dst[i+15:i]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPACKUSDW" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_packus_epi32" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".</description>
+	<operation>
+dst[15:0] := SaturateU16(a[31:0])
+dst[31:16] := SaturateU16(a[63:32])
+dst[47:32] := SaturateU16(a[95:64])
+dst[63:48] := SaturateU16(a[127:96])
+dst[79:64] := SaturateU16(b[31:0])
+dst[95:80] := SaturateU16(b[63:32])
+dst[111:96] := SaturateU16(b[95:64])
+dst[127:112] := SaturateU16(b[127:96])
+dst[143:128] := SaturateU16(a[159:128])
+dst[159:144] := SaturateU16(a[191:160])
+dst[175:160] := SaturateU16(a[223:192])
+dst[191:176] := SaturateU16(a[255:224])
+dst[207:192] := SaturateU16(b[159:128])
+dst[223:208] := SaturateU16(b[191:160])
+dst[239:224] := SaturateU16(b[223:192])
+dst[255:240] := SaturateU16(b[255:224])
+dst[271:256] := SaturateU16(a[287:256])
+dst[287:272] := SaturateU16(a[319:288])
+dst[303:288] := SaturateU16(a[351:320])
+dst[319:304] := SaturateU16(a[383:352])
+dst[335:320] := SaturateU16(b[287:256])
+dst[351:336] := SaturateU16(b[319:288])
+dst[367:352] := SaturateU16(b[351:320])
+dst[383:368] := SaturateU16(b[383:352])
+dst[399:384] := SaturateU16(a[415:384])
+dst[415:400] := SaturateU16(a[447:416])
+dst[431:416] := SaturateU16(a[479:448])
+dst[447:432] := SaturateU16(a[511:480])
+dst[463:448] := SaturateU16(b[415:384])
+dst[479:464] := SaturateU16(b[447:416])
+dst[495:480] := SaturateU16(b[479:448])
+dst[511:496] := SaturateU16(b[511:480])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPACKUSDW" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_packus_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := SaturateU8(a[15:0])
+tmp_dst[15:8] := SaturateU8(a[31:16])
+tmp_dst[23:16] := SaturateU8(a[47:32])
+tmp_dst[31:24] := SaturateU8(a[63:48])
+tmp_dst[39:32] := SaturateU8(a[79:64])
+tmp_dst[47:40] := SaturateU8(a[95:80])
+tmp_dst[55:48] := SaturateU8(a[111:96])
+tmp_dst[63:56] := SaturateU8(a[127:112])
+tmp_dst[71:64] := SaturateU8(b[15:0])
+tmp_dst[79:72] := SaturateU8(b[31:16])
+tmp_dst[87:80] := SaturateU8(b[47:32])
+tmp_dst[95:88] := SaturateU8(b[63:48])
+tmp_dst[103:96] := SaturateU8(b[79:64])
+tmp_dst[111:104] := SaturateU8(b[95:80])
+tmp_dst[119:112] := SaturateU8(b[111:96])
+tmp_dst[127:120] := SaturateU8(b[127:112])
+tmp_dst[135:128] := SaturateU8(a[143:128])
+tmp_dst[143:136] := SaturateU8(a[159:144])
+tmp_dst[151:144] := SaturateU8(a[175:160])
+tmp_dst[159:152] := SaturateU8(a[191:176])
+tmp_dst[167:160] := SaturateU8(a[207:192])
+tmp_dst[175:168] := SaturateU8(a[223:208])
+tmp_dst[183:176] := SaturateU8(a[239:224])
+tmp_dst[191:184] := SaturateU8(a[255:240])
+tmp_dst[199:192] := SaturateU8(b[143:128])
+tmp_dst[207:200] := SaturateU8(b[159:144])
+tmp_dst[215:208] := SaturateU8(b[175:160])
+tmp_dst[223:216] := SaturateU8(b[191:176])
+tmp_dst[231:224] := SaturateU8(b[207:192])
+tmp_dst[239:232] := SaturateU8(b[223:208])
+tmp_dst[247:240] := SaturateU8(b[239:224])
+tmp_dst[255:248] := SaturateU8(b[255:240])
+tmp_dst[263:256] := SaturateU8(a[271:256])
+tmp_dst[271:264] := SaturateU8(a[287:272])
+tmp_dst[279:272] := SaturateU8(a[303:288])
+tmp_dst[287:280] := SaturateU8(a[319:304])
+tmp_dst[295:288] := SaturateU8(a[335:320])
+tmp_dst[303:296] := SaturateU8(a[351:336])
+tmp_dst[311:304] := SaturateU8(a[367:352])
+tmp_dst[319:312] := SaturateU8(a[383:368])
+tmp_dst[327:320] := SaturateU8(b[271:256])
+tmp_dst[335:328] := SaturateU8(b[287:272])
+tmp_dst[343:336] := SaturateU8(b[303:288])
+tmp_dst[351:344] := SaturateU8(b[319:304])
+tmp_dst[359:352] := SaturateU8(b[335:320])
+tmp_dst[367:360] := SaturateU8(b[351:336])
+tmp_dst[375:368] := SaturateU8(b[367:352])
+tmp_dst[383:376] := SaturateU8(b[383:368])
+tmp_dst[391:384] := SaturateU8(a[399:384])
+tmp_dst[399:392] := SaturateU8(a[415:400])
+tmp_dst[407:400] := SaturateU8(a[431:416])
+tmp_dst[415:408] := SaturateU8(a[447:432])
+tmp_dst[423:416] := SaturateU8(a[463:448])
+tmp_dst[431:424] := SaturateU8(a[479:464])
+tmp_dst[439:432] := SaturateU8(a[495:480])
+tmp_dst[447:440] := SaturateU8(a[511:496])
+tmp_dst[455:448] := SaturateU8(b[399:384])
+tmp_dst[463:456] := SaturateU8(b[415:400])
+tmp_dst[471:464] := SaturateU8(b[431:416])
+tmp_dst[479:472] := SaturateU8(b[447:432])
+tmp_dst[487:480] := SaturateU8(b[463:448])
+tmp_dst[495:488] := SaturateU8(b[479:464])
+tmp_dst[503:496] := SaturateU8(b[495:480])
+tmp_dst[511:504] := SaturateU8(b[511:496])
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPACKUSWB" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_packus_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[7:0] := SaturateU8(a[15:0])
+tmp_dst[15:8] := SaturateU8(a[31:16])
+tmp_dst[23:16] := SaturateU8(a[47:32])
+tmp_dst[31:24] := SaturateU8(a[63:48])
+tmp_dst[39:32] := SaturateU8(a[79:64])
+tmp_dst[47:40] := SaturateU8(a[95:80])
+tmp_dst[55:48] := SaturateU8(a[111:96])
+tmp_dst[63:56] := SaturateU8(a[127:112])
+tmp_dst[71:64] := SaturateU8(b[15:0])
+tmp_dst[79:72] := SaturateU8(b[31:16])
+tmp_dst[87:80] := SaturateU8(b[47:32])
+tmp_dst[95:88] := SaturateU8(b[63:48])
+tmp_dst[103:96] := SaturateU8(b[79:64])
+tmp_dst[111:104] := SaturateU8(b[95:80])
+tmp_dst[119:112] := SaturateU8(b[111:96])
+tmp_dst[127:120] := SaturateU8(b[127:112])
+tmp_dst[135:128] := SaturateU8(a[143:128])
+tmp_dst[143:136] := SaturateU8(a[159:144])
+tmp_dst[151:144] := SaturateU8(a[175:160])
+tmp_dst[159:152] := SaturateU8(a[191:176])
+tmp_dst[167:160] := SaturateU8(a[207:192])
+tmp_dst[175:168] := SaturateU8(a[223:208])
+tmp_dst[183:176] := SaturateU8(a[239:224])
+tmp_dst[191:184] := SaturateU8(a[255:240])
+tmp_dst[199:192] := SaturateU8(b[143:128])
+tmp_dst[207:200] := SaturateU8(b[159:144])
+tmp_dst[215:208] := SaturateU8(b[175:160])
+tmp_dst[223:216] := SaturateU8(b[191:176])
+tmp_dst[231:224] := SaturateU8(b[207:192])
+tmp_dst[239:232] := SaturateU8(b[223:208])
+tmp_dst[247:240] := SaturateU8(b[239:224])
+tmp_dst[255:248] := SaturateU8(b[255:240])
+tmp_dst[263:256] := SaturateU8(a[271:256])
+tmp_dst[271:264] := SaturateU8(a[287:272])
+tmp_dst[279:272] := SaturateU8(a[303:288])
+tmp_dst[287:280] := SaturateU8(a[319:304])
+tmp_dst[295:288] := SaturateU8(a[335:320])
+tmp_dst[303:296] := SaturateU8(a[351:336])
+tmp_dst[311:304] := SaturateU8(a[367:352])
+tmp_dst[319:312] := SaturateU8(a[383:368])
+tmp_dst[327:320] := SaturateU8(b[271:256])
+tmp_dst[335:328] := SaturateU8(b[287:272])
+tmp_dst[343:336] := SaturateU8(b[303:288])
+tmp_dst[351:344] := SaturateU8(b[319:304])
+tmp_dst[359:352] := SaturateU8(b[335:320])
+tmp_dst[367:360] := SaturateU8(b[351:336])
+tmp_dst[375:368] := SaturateU8(b[367:352])
+tmp_dst[383:376] := SaturateU8(b[383:368])
+tmp_dst[391:384] := SaturateU8(a[399:384])
+tmp_dst[399:392] := SaturateU8(a[415:400])
+tmp_dst[407:400] := SaturateU8(a[431:416])
+tmp_dst[415:408] := SaturateU8(a[447:432])
+tmp_dst[423:416] := SaturateU8(a[463:448])
+tmp_dst[431:424] := SaturateU8(a[479:464])
+tmp_dst[439:432] := SaturateU8(a[495:480])
+tmp_dst[447:440] := SaturateU8(a[511:496])
+tmp_dst[455:448] := SaturateU8(b[399:384])
+tmp_dst[463:456] := SaturateU8(b[415:400])
+tmp_dst[471:464] := SaturateU8(b[431:416])
+tmp_dst[479:472] := SaturateU8(b[447:432])
+tmp_dst[487:480] := SaturateU8(b[463:448])
+tmp_dst[495:488] := SaturateU8(b[479:464])
+tmp_dst[503:496] := SaturateU8(b[495:480])
+tmp_dst[511:504] := SaturateU8(b[511:496])
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := tmp_dst[i+7:i]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPACKUSWB" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_packus_epi16" tech="AVX-512">
+	<category>Miscellaneous</category>
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := SaturateU8(a[15:0])
+dst[15:8] := SaturateU8(a[31:16])
+dst[23:16] := SaturateU8(a[47:32])
+dst[31:24] := SaturateU8(a[63:48])
+dst[39:32] := SaturateU8(a[79:64])
+dst[47:40] := SaturateU8(a[95:80])
+dst[55:48] := SaturateU8(a[111:96])
+dst[63:56] := SaturateU8(a[127:112])
+dst[71:64] := SaturateU8(b[15:0])
+dst[79:72] := SaturateU8(b[31:16])
+dst[87:80] := SaturateU8(b[47:32])
+dst[95:88] := SaturateU8(b[63:48])
+dst[103:96] := SaturateU8(b[79:64])
+dst[111:104] := SaturateU8(b[95:80])
+dst[119:112] := SaturateU8(b[111:96])
+dst[127:120] := SaturateU8(b[127:112])
+dst[135:128] := SaturateU8(a[143:128])
+dst[143:136] := SaturateU8(a[159:144])
+dst[151:144] := SaturateU8(a[175:160])
+dst[159:152] := SaturateU8(a[191:176])
+dst[167:160] := SaturateU8(a[207:192])
+dst[175:168] := SaturateU8(a[223:208])
+dst[183:176] := SaturateU8(a[239:224])
+dst[191:184] := SaturateU8(a[255:240])
+dst[199:192] := SaturateU8(b[143:128])
+dst[207:200] := SaturateU8(b[159:144])
+dst[215:208] := SaturateU8(b[175:160])
+dst[223:216] := SaturateU8(b[191:176])
+dst[231:224] := SaturateU8(b[207:192])
+dst[239:232] := SaturateU8(b[223:208])
+dst[247:240] := SaturateU8(b[239:224])
+dst[255:248] := SaturateU8(b[255:240])
+dst[263:256] := SaturateU8(a[271:256])
+dst[271:264] := SaturateU8(a[287:272])
+dst[279:272] := SaturateU8(a[303:288])
+dst[287:280] := SaturateU8(a[319:304])
+dst[295:288] := SaturateU8(a[335:320])
+dst[303:296] := SaturateU8(a[351:336])
+dst[311:304] := SaturateU8(a[367:352])
+dst[319:312] := SaturateU8(a[383:368])
+dst[327:320] := SaturateU8(b[271:256])
+dst[335:328] := SaturateU8(b[287:272])
+dst[343:336] := SaturateU8(b[303:288])
+dst[351:344] := SaturateU8(b[319:304])
+dst[359:352] := SaturateU8(b[335:320])
+dst[367:360] := SaturateU8(b[351:336])
+dst[375:368] := SaturateU8(b[367:352])
+dst[383:376] := SaturateU8(b[383:368])
+dst[391:384] := SaturateU8(a[399:384])
+dst[399:392] := SaturateU8(a[415:400])
+dst[407:400] := SaturateU8(a[431:416])
+dst[415:408] := SaturateU8(a[447:432])
+dst[423:416] := SaturateU8(a[463:448])
+dst[431:424] := SaturateU8(a[479:464])
+dst[439:432] := SaturateU8(a[495:480])
+dst[447:440] := SaturateU8(a[511:496])
+dst[455:448] := SaturateU8(b[399:384])
+dst[463:456] := SaturateU8(b[415:400])
+dst[471:464] := SaturateU8(b[431:416])
+dst[479:472] := SaturateU8(b[447:432])
+dst[487:480] := SaturateU8(b[463:448])
+dst[495:488] := SaturateU8(b[479:464])
+dst[503:496] := SaturateU8(b[495:480])
+dst[511:504] := SaturateU8(b[511:496])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPACKUSWB" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := Saturate8(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVSWB" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m256i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVSWB" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVSWB" xed="VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtsepi16_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVSWB" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi8_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	l := j*16
+	dst[l+15:l] := SignExtend16(a[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VPMOVSXBW" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi8_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := SignExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VPMOVSXBW" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi8_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI8" type="__m256i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := SignExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VPMOVSXBW" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := SaturateU8(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVUSWB" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVUSWB" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVUSWB" xed="VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtusepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVUSWB" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	dst[l+7:l] := Truncate8(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVWB" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVWB" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi16_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVWB" xed="VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi16_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+15:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVWB" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu8_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	l := j*16
+	dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VPMOVZXBW" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu8_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VPMOVZXBW" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu8_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	l := j*16
+	IF k[j]
+		dst[l+15:l] := ZeroExtend16(a[i+7:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VPMOVZXBW" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_set1_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_set1_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[7:0]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_set1_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast 16-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_set1_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[15:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpge_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpgt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpge_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpgt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpge_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpgt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpge_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpgt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_epu8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpge_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpgt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpge_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpgt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_epu16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpge_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpgt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpge_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpgt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_test_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_test_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_test_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_test_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_testn_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="k1" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k1[j]
+		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_testn_epi8_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_testn_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k1[j]
+		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_testn_epi16_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_bslli_epi128" tech="AVX-512">
+	<return etype="M128" type="__m512i" varname="dst" />
+	<parameter etype="M128" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
+dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
+dst[383:256] := a[383:256] &lt;&lt; (tmp*8)
+dst[511:384] := a[511:384] &lt;&lt; (tmp*8)
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSLLDQ" xed="VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSLLVW" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSLLVW" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sllv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSLLVW" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sll_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_slli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sll_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_slli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sll_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_slli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSRAVW" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSRAVW" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srav_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSRAVW" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sra_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srai_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sra_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srai_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+		ELSE
+			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sra_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srai_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_bsrli_epi128" tech="AVX-512">
+	<return etype="M128" type="__m512i" varname="dst" />
+	<parameter etype="M128" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
+dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
+dst[383:256] := a[383:256] &gt;&gt; (tmp*8)
+dst[511:384] := a[511:384] &gt;&gt; (tmp*8)
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSRLDQ" xed="VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSRLVW" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[i+15:i] &lt; 16
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+		ELSE
+			dst[i+15:i] := 0
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSRLVW" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srlv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF count[i+15:i] &lt; 16
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSRLVW" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srl_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srl_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF count[63:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		IF imm8[7:0] &gt; 15
+			dst[i+15:i] := 0
+		ELSE
+			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srl_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srli_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_kadd_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Add 32-bit masks in "a" and "b", and store the result in "k".</description>
+	<operation>
+k[31:0] := a[31:0] + b[31:0]
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, k, k" name="KADDD" xed="KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kadd_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Add 64-bit masks in "a" and "b", and store the result in "k".</description>
+	<operation>
+k[63:0] := a[63:0] + b[63:0]
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, k, k" name="KADDQ" xed="KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kand_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[31:0] := a[31:0] AND b[31:0]
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDD" xed="KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kand_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[63:0] := a[63:0] AND b[63:0]
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDQ" xed="KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kandn_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise NOT of 32-bit masks "a" and then AND with "b", and store the result in "k".</description>
+	<operation>
+k[31:0] := (NOT a[31:0]) AND b[31:0]
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDND" xed="KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kandn_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise NOT of 64-bit masks "a" and then AND with "b", and store the result in "k".</description>
+	<operation>
+k[63:0] := (NOT a[63:0]) AND b[63:0]
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDNQ" xed="KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_knot_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<description>Compute the bitwise NOT of 32-bit mask "a", and store the result in "k".</description>
+	<operation>
+k[31:0] := NOT a[31:0]
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, k" name="KNOTD" xed="KNOTD_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_knot_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<description>Compute the bitwise NOT of 64-bit mask "a", and store the result in "k".</description>
+	<operation>
+k[63:0] := NOT a[63:0]
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, k" name="KNOTQ" xed="KNOTQ_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kor_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise OR of 32-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[31:0] := a[31:0] OR b[31:0]
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, k, k" name="KORD" xed="KORD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kor_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise OR of 64-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[63:0] := a[63:0] OR b[63:0]
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, k, k" name="KORQ" xed="KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kxnor_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise XNOR of 32-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[31:0] := NOT (a[31:0] XOR b[31:0])
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXNORD" xed="KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kxnor_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise XNOR of 64-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[63:0] := NOT (a[63:0] XOR b[63:0])
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXNORQ" xed="KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kxor_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise XOR of 32-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[31:0] := a[31:0] XOR b[31:0]
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXORD" xed="KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kxor_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise XOR of 64-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[63:0] := a[63:0] XOR b[63:0]
+k[MAX:64] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXORQ" xed="KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kshiftli_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
+	<description>Shift the bits of 32-bit mask "a" left by "count" while shifting in zeros, and store the least significant 32 bits of the result in "k".</description>
+	<operation>
+k[MAX:0] := 0
+IF count[7:0] &lt;= 31
+	k[31:0] := a[31:0] &lt;&lt; count[7:0]
+FI
+	</operation>
+	<instruction form="k, k, imm8" name="KSHIFTLD" xed="KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kshiftli_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
+	<description>Shift the bits of 64-bit mask "a" left by "count" while shifting in zeros, and store the least significant 64 bits of the result in "k".</description>
+	<operation>
+k[MAX:0] := 0
+IF count[7:0] &lt;= 63
+	k[63:0] := a[63:0] &lt;&lt; count[7:0]
+FI
+	</operation>
+	<instruction form="k, k, imm8" name="KSHIFTLQ" xed="KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kshiftri_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
+	<description>Shift the bits of 32-bit mask "a" right by "count" while shifting in zeros, and store the least significant 32 bits of the result in "k".</description>
+	<operation>
+k[MAX:0] := 0
+IF count[7:0] &lt;= 31
+	k[31:0] := a[31:0] &gt;&gt; count[7:0]
+FI
+	</operation>
+	<instruction form="k, k, imm8" name="KSHIFTRD" xed="KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kshiftri_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
+	<description>Shift the bits of 64-bit mask "a" right by "count" while shifting in zeros, and store the least significant 64 bits of the result in "k".</description>
+	<operation>
+k[MAX:0] := 0
+IF count[7:0] &lt;= 63
+	k[63:0] := a[63:0] &gt;&gt; count[7:0]
+FI
+	</operation>
+	<instruction form="k, k, imm8" name="KSHIFTRQ" xed="KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortest_mask32_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="all_ones" />
+	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
+	<operation>
+tmp[31:0] := a[31:0] OR b[31:0]
+IF tmp[31:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+IF tmp[31:0] == 0xFFFFFFFF
+	MEM[all_ones+7:all_ones] := 1
+ELSE
+	MEM[all_ones+7:all_ones] := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTD" xed="KORTESTD_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortestz_mask32_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[31:0] := a[31:0] OR b[31:0]
+IF tmp[31:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTD" xed="KORTESTD_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortestc_mask32_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[31:0] := a[31:0] OR b[31:0]
+IF tmp[31:0] == 0xFFFFFFFF
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTD" xed="KORTESTD_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortest_mask64_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="all_ones" />
+	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
+	<operation>
+tmp[63:0] := a[63:0] OR b[63:0]
+IF tmp[63:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+IF tmp[7:0] == 0xFFFFFFFFFFFFFFFF
+	MEM[all_ones+7:all_ones] := 1
+ELSE
+	MEM[all_ones+7:all_ones] := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTQ" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortestz_mask64_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[63:0] := a[63:0] OR b[63:0]
+IF tmp[63:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTQ" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortestc_mask64_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[63:0] := a[63:0] OR b[63:0]
+IF tmp[63:0] == 0xFFFFFFFFFFFFFFFF
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTQ" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktest_mask32_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="and_not" />
+	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
+	<operation>
+tmp1[31:0] := a[31:0] AND b[31:0]
+IF tmp1[31:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+tmp2[31:0] := (NOT a[31:0]) AND b[31:0]
+IF tmp2[31:0] == 0x0
+	MEM[and_not+7:and_not] := 1
+ELSE
+	MEM[and_not+7:and_not] := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTD" xed="KTESTD_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktestz_mask32_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[31:0] := a[31:0] AND b[31:0]
+IF tmp[31:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTD" xed="KTESTD_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktestc_mask32_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="b" />
+	<description>Compute the bitwise NOT of 32-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[31:0] := (NOT a[31:0]) AND b[31:0]
+IF tmp[31:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTD" xed="KTESTD_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktest_mask64_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="and_not" />
+	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
+	<operation>
+tmp1[63:0] := a[63:0] AND b[63:0]
+IF tmp1[63:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+tmp2[63:0] := (NOT a[63:0]) AND b[63:0]
+IF tmp2[63:0] == 0x0
+	MEM[and_not+7:and_not] := 1
+ELSE
+	MEM[and_not+7:and_not] := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTQ" xed="KTESTQ_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktestz_mask64_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[63:0] := a[63:0] AND b[63:0]
+IF tmp[63:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTQ" xed="KTESTQ_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktestc_mask64_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="b" />
+	<description>Compute the bitwise NOT of 64-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[63:0] := (NOT a[63:0]) AND b[63:0]
+IF tmp[63:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTQ" xed="KTESTQ_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_cvtmask32_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="a" />
+	<description>Convert 32-bit mask "a" into an integer value, and store the result in "dst".</description>
+	<operation>
+dst := ZeroExtend32(a[31:0])
+	</operation>
+	<instruction form="r32, k" name="KMOVD" xed="KMOVD_GPR32u32_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_cvtmask64_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="a" />
+	<description>Convert 64-bit mask "a" into an integer value, and store the result in "dst".</description>
+	<operation>
+dst := ZeroExtend64(a[63:0])
+	</operation>
+	<instruction form="r64, k" name="KMOVQ" xed="KMOVQ_GPR64u64_MASKmskw_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_cvtu32_mask32" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Convert integer value "a" into an 32-bit mask, and store the result in "k".</description>
+	<operation>
+k := ZeroExtend32(a[31:0])
+	</operation>
+	<instruction form="k, r32" name="KMOVD" xed="KMOVD_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_cvtu64_mask64" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Convert integer value "a" into an 64-bit mask, and store the result in "k".</description>
+	<operation>
+k := ZeroExtend64(a[63:0])
+	</operation>
+	<instruction form="k, r64" name="KMOVQ" xed="KMOVQ_MASKmskw_GPR64u64_AVX512" />
+	<CPUID>AVX512BW</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_broadcastmb_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ZeroExtend64(k[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm" name="VPBROADCASTMB2Q" xed="VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastmb_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ZeroExtend64(k[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm" name="VPBROADCASTMB2Q" xed="VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcastmw_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ZeroExtend32(k[15:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm" name="VPBROADCASTMW2D" xed="VPBROADCASTMW2D_YMMu32_MASKu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcastmw_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ZeroExtend32(k[15:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm" name="VPBROADCASTMW2D" xed="VPBROADCASTMW2D_XMMu32_MASKu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	FOR k := 0 to j-1
+		m := k*32
+		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+	ENDFOR
+	dst[i+31:i+j] := 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPCONFLICTD" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*32
+			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+		ENDFOR
+		dst[i+31:i+j] := 0
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPCONFLICTD" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*32
+			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+		ENDFOR
+		dst[i+31:i+j] := 0
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPCONFLICTD" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	FOR k := 0 to j-1
+		m := k*32
+		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+	ENDFOR
+	dst[i+31:i+j] := 0
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPCONFLICTD" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*32
+			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+		ENDFOR
+		dst[i+31:i+j] := 0
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPCONFLICTD" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*32
+			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+		ENDFOR
+		dst[i+31:i+j] := 0
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPCONFLICTD" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	FOR k := 0 to j-1
+		m := k*64
+		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+	ENDFOR
+	dst[i+63:i+j] := 0
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPCONFLICTQ" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*64
+			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+		ENDFOR
+		dst[i+63:i+j] := 0
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPCONFLICTQ" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*64
+			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+		ENDFOR
+		dst[i+63:i+j] := 0
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPCONFLICTQ" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	FOR k := 0 to j-1
+		m := k*64
+		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+	ENDFOR
+	dst[i+63:i+j] := 0
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*64
+			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+		ENDFOR
+		dst[i+63:i+j] := 0
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*64
+			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+		ENDFOR
+		dst[i+63:i+j] := 0
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	tmp := 31
+	dst[i+31:i] := 0
+	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+		tmp := tmp - 1
+		dst[i+31:i] := dst[i+31:i] + 1
+	OD
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPLZCNTD" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		tmp := 31
+		dst[i+31:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+31:i] := dst[i+31:i] + 1
+		OD
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPLZCNTD" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		tmp := 31
+		dst[i+31:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+31:i] := dst[i+31:i] + 1
+		OD
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPLZCNTD" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	tmp := 31
+	dst[i+31:i] := 0
+	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+		tmp := tmp - 1
+		dst[i+31:i] := dst[i+31:i] + 1
+	OD
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPLZCNTD" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		tmp := 31
+		dst[i+31:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+31:i] := dst[i+31:i] + 1
+		OD
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPLZCNTD" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		tmp := 31
+		dst[i+31:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+31:i] := dst[i+31:i] + 1
+		OD
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPLZCNTD" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp := 63
+	dst[i+63:i] := 0
+	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+		tmp := tmp - 1
+		dst[i+63:i] := dst[i+63:i] + 1
+	OD
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPLZCNTQ" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp := 63
+		dst[i+63:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+63:i] := dst[i+63:i] + 1
+		OD
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPLZCNTQ" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp := 63
+		dst[i+63:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+63:i] := dst[i+63:i] + 1
+		OD
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPLZCNTQ" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp := 63
+	dst[i+63:i] := 0
+	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+		tmp := tmp - 1
+		dst[i+63:i] := dst[i+63:i] + 1
+	OD
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPLZCNTQ" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp := 63
+		dst[i+63:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+63:i] := dst[i+63:i] + 1
+		OD
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPLZCNTQ" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp := 63
+		dst[i+63:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+63:i] := dst[i+63:i] + 1
+		OD
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPLZCNTQ" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512CD</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_broadcastmb_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ZeroExtend64(k[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm" name="VPBROADCASTMB2Q" xed="VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcastmw_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ZeroExtend32(k[15:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm" name="VPBROADCASTMW2D" xed="VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	FOR k := 0 to j-1
+		m := k*32
+		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+	ENDFOR
+	dst[i+31:i+j] := 0
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPCONFLICTD" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*32
+			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+		ENDFOR
+		dst[i+31:i+j] := 0
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPCONFLICTD" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_conflict_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*32
+			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
+		ENDFOR
+		dst[i+31:i+j] := 0
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPCONFLICTD" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	FOR k := 0 to j-1
+		m := k*64
+		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+	ENDFOR
+	dst[i+63:i+j] := 0
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*64
+			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+		ENDFOR
+		dst[i+63:i+j] := 0
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_conflict_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		FOR l := 0 to j-1
+			m := l*64
+			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
+		ENDFOR
+		dst[i+63:i+j] := 0
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	tmp := 31
+	dst[i+31:i] := 0
+	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+		tmp := tmp - 1
+		dst[i+31:i] := dst[i+31:i] + 1
+	OD
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPLZCNTD" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp := 31
+		dst[i+31:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+31:i] := dst[i+31:i] + 1
+		OD
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPLZCNTD" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_lzcnt_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp := 31
+		dst[i+31:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+31:i] := dst[i+31:i] + 1
+		OD
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPLZCNTD" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	tmp := 63
+	dst[i+63:i] := 0
+	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+		tmp := tmp - 1
+		dst[i+63:i] := dst[i+63:i] + 1
+	OD
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPLZCNTQ" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp := 63
+		dst[i+63:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+63:i] := dst[i+63:i] + 1
+		OD
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPLZCNTQ" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_lzcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp := 63
+		dst[i+63:i] := 0
+		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
+			tmp := tmp - 1
+			dst[i+63:i] := dst[i+63:i] + 1
+		OD
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPLZCNTQ" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
+	<CPUID>AVX512CD</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_mask_andnot_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VANDNPD" xed="VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_andnot_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VANDNPD" xed="VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_andnot_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VANDNPD" xed="VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_andnot_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VANDNPD" xed="VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_andnot_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VANDNPS" xed="VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_andnot_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VANDNPS" xed="VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_andnot_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VANDNPS" xed="VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_andnot_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VANDNPS" xed="VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_and_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VANDPD" xed="VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_and_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0 
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VANDPD" xed="VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_and_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VANDPD" xed="VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_and_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VANDPD" xed="VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_and_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VANDPS" xed="VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_and_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VANDPS" xed="VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_and_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VANDPS" xed="VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_and_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VANDPS" xed="VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_or_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VORPD" xed="VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_or_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VORPD" xed="VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_or_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VORPD" xed="VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_or_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VORPD" xed="VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_or_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VORPS" xed="VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_or_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VORPS" xed="VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_or_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VORPS" xed="VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_or_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VORPS" xed="VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_xor_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VXORPD" xed="VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_xor_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VXORPD" xed="VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_xor_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VXORPD" xed="VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_xor_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VXORPD" xed="VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_xor_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VXORPS" xed="VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_xor_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VXORPS" xed="VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_xor_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VXORPS" xed="VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_xor_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VXORPS" xed="VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_f32x2" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 2)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcast_f32x2" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcast_f32x2" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	n := (j % 2)*64
+	dst[i+63:i] := a[n+63:n]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	n := (j % 2)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	n := (j % 2)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 2)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	n := (j % 2)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	n := (j % 2)*64
+	dst[i+63:i] := a[n+63:n]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	n := (j % 2)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	n := (j % 2)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extractf64x2_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_extractf64x2_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_extractf64x2_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extracti64x2_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_extracti64x2_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_extracti64x2_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fpclass_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fpclass_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fpclass_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fpclass_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fpclass_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fpclass_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fpclass_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fpclass_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insertf64x2" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[255:0] := a[255:0]
+CASE imm8[0] OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_insertf64x2" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_insertf64x2" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_inserti64x2" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[255:0] := a[255:0]
+CASE imm8[0] OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_inserti64x2" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_inserti64x2" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movepi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF a[i+31]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm" name="VPMOVD2M" xed="VPMOVD2M_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movepi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF a[i+31]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm" name="VPMOVD2M" xed="VPMOVD2M_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movm_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := 0xFFFFFFFF
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm" name="VPMOVM2D" xed="VPMOVM2D_YMMu32_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movm_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := 0xFFFFFFFF
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm" name="VPMOVM2D" xed="VPMOVM2D_XMMu32_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movm_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm" name="VPMOVM2Q" xed="VPMOVM2Q_YMMu64_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movm_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm" name="VPMOVM2Q" xed="VPMOVM2Q_XMMu64_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_movepi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF a[i+63]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm" name="VPMOVQ2M" xed="VPMOVQ2M_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movepi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF a[i+63]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm" name="VPMOVQ2M" xed="VPMOVQ2M_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VRANGEPD" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VRANGEPD" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VRANGEPD" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRANGEPD" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRANGEPD" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VRANGEPD" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VRANGEPS" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VRANGEPS" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VRANGEPS" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRANGEPS" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRANGEPS" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VRANGEPS" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VREDUCEPD" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VREDUCEPD" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VREDUCEPD" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VREDUCEPS" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VREDUCEPS" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	RETURN tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VREDUCEPS" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTPD2QQ" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTPD2QQ" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTPD2QQ" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTQQ2PD" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTQQ2PD" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTQQ2PD" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := a[i+63:i] * b[i+63:i]
+		dst[i+63:i] := tmp[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULLQ" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := a[i+63:i] * b[i+63:i]
+		dst[i+63:i] := tmp[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULLQ" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := a[i+63:i] * b[i+63:i]
+	dst[i+63:i] := tmp[63:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULLQ" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := a[i+63:i] * b[i+63:i]
+		dst[i+63:i] := tmp[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULLQ" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := a[i+63:i] * b[i+63:i]
+		dst[i+63:i] := tmp[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULLQ" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := a[i+63:i] * b[i+63:i]
+	dst[i+63:i] := tmp[63:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPMULLQ" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_andnot_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VANDNPD" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_andnot_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VANDNPD" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_andnot_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VANDNPD" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_andnot_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VANDNPS" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_andnot_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VANDNPS" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_andnot_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VANDNPS" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_and_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VANDPD" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_and_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VANDPD" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_and_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VANDPD" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_and_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VANDPS" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_and_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VANDPS" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_and_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VANDPS" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_or_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VORPD" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_or_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VORPD" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_or_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VORPD" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_or_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VORPS" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_or_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VORPS" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_or_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VORPS" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_xor_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VXORPD" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_xor_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VXORPD" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_xor_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VXORPD" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_xor_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VXORPS" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_xor_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VXORPS" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_xor_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VXORPS" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_f32x2" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 2)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_f32x2" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_f32x2" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_f32x8" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 8)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m256" name="VBROADCASTF32X8" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_f32x8" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 8)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m256" name="VBROADCASTF32X8" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_f32x8" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 8)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m256" name="VBROADCASTF32X8" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 2)*64
+	dst[i+63:i] := a[n+63:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 2)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 2)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 2)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_i32x2" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 2)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_i32x8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 8)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m256" name="VBROADCASTI32X8" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_i32x8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 8)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m256" name="VBROADCASTI32X8" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_i32x8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 8)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m256" name="VBROADCASTI32X8" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 2)*64
+	dst[i+63:i] := a[n+63:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 2)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 2)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_extractf32x8_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[255:0] := a[255:0]
+1: dst[255:0] := a[511:256]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm, imm8" name="VEXTRACTF32X8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_extractf32x8_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[255:0] := a[255:0]
+1: tmp[255:0] := a[511:256]
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm, imm8" name="VEXTRACTF32X8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_extractf32x8_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[255:0] := a[255:0]
+1: tmp[255:0] := a[511:256]
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm, imm8" name="VEXTRACTF32X8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_extractf64x2_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[1:0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+2: dst[127:0] := a[383:256]
+3: dst[127:0] := a[511:384]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_extractf64x2_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[1:0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+2: tmp[127:0] := a[383:256]
+3: tmp[127:0] := a[511:384]
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_extractf64x2_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[1:0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+2: tmp[127:0] := a[383:256]
+3: tmp[127:0] := a[511:384]
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_extracti32x8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[255:0] := a[255:0]
+1: dst[255:0] := a[511:256]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm, imm8" name="VEXTRACTI32X8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_extracti32x8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[255:0] := a[255:0]
+1: tmp[255:0] := a[511:256]
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm, imm8" name="VEXTRACTI32X8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_extracti32x8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[255:0] := a[255:0]
+1: tmp[255:0] := a[511:256]
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm, imm8" name="VEXTRACTI32X8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_extracti64x2_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[1:0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+2: dst[127:0] := a[383:256]
+3: dst[127:0] := a[511:384]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_extracti64x2_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[1:0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+2: tmp[127:0] := a[383:256]
+3: tmp[127:0] := a[511:384]
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_extracti64x2_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[1:0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+2: tmp[127:0] := a[383:256]
+3: tmp[127:0] := a[511:384]
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fpclass_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fpclass_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fpclass_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fpclass_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+	[fpclass_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fpclass_sd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test the lower double-precision (64-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k".
+	[fpclass_note]</description>
+	<operation>k[0] := CheckFPClass_FP64(a[63:0], imm8[7:0])
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, imm8" name="VFPCLASSSD" xed="VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fpclass_sd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test the lower double-precision (64-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).
+	[fpclass_note]</description>
+	<operation>IF k1[0]
+	k[0] := CheckFPClass_FP64(a[63:0], imm8[7:0])
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, imm8" name="VFPCLASSSD" xed="VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fpclass_ss_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test the lower single-precision (32-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k.
+	[fpclass_note]</description>
+	<operation>k[0] := CheckFPClass_FP32(a[31:0], imm8[7:0])
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, imm8" name="VFPCLASSSS" xed="VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fpclass_ss_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test the lower single-precision (32-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).
+	[fpclass_note]</description>
+	<operation>IF k1[0]
+	k[0] := CheckFPClass_FP32(a[31:0], imm8[7:0])
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, imm8" name="VFPCLASSSS" xed="VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_insertf32x8" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: dst[255:0] := b[255:0]
+1: dst[511:256] := b[255:0]
+ESAC
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, ymm, imm8" name="VINSERTF32X8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_insertf32x8" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: tmp[255:0] := b[255:0]
+1: tmp[511:256] := b[255:0]
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, ymm, imm8" name="VINSERTF32X8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_insertf32x8" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: tmp[255:0] := b[255:0]
+1: tmp[511:256] := b[255:0]
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, ymm, imm8" name="VINSERTF32X8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_insertf64x2" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[511:0] := a[511:0]
+CASE imm8[1:0] OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+2: dst[383:256] := b[127:0]
+3: dst[511:384] := b[127:0]
+ESAC
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_insertf64x2" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+2: tmp[383:256] := b[127:0]
+3: tmp[511:384] := b[127:0]
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_insertf64x2" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+2: tmp[383:256] := b[127:0]
+3: tmp[511:384] := b[127:0]
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_inserti32x8" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[511:0] := a[511:0]
+CASE imm8[0] OF
+0: dst[255:0] := b[255:0]
+1: dst[511:256] := b[255:0]
+ESAC
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, ymm, imm8" name="VINSERTI32X8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_inserti32x8" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: tmp[255:0] := b[255:0]
+1: tmp[511:256] := b[255:0]
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, ymm, imm8" name="VINSERTI32X8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_inserti32x8" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: tmp[255:0] := b[255:0]
+1: tmp[511:256] := b[255:0]
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, ymm, imm8" name="VINSERTI32X8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_inserti64x2" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[511:0] := a[511:0]
+CASE imm8[1:0] OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+2: dst[383:256] := b[127:0]
+3: dst[511:384] := b[127:0]
+ESAC
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_inserti64x2" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+2: tmp[383:256] := b[127:0]
+3: tmp[511:384] := b[127:0]
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_inserti64x2" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+2: tmp[383:256] := b[127:0]
+3: tmp[511:384] := b[127:0]
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movepi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF a[i+31]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm" name="VPMOVD2M" xed="VPMOVD2M_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movm_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := 0xFFFFFFFF
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm" name="VPMOVM2D" xed="VPMOVM2D_ZMMu32_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movm_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm" name="VPMOVM2Q" xed="VPMOVM2Q_ZMMu64_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movepi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF a[i+63]
+		k[j] := 1
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm" name="VPMOVQ2M" xed="VPMOVQ2M_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_range_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {sae}, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_range_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {sae}, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_range_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_range_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {sae}, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_range_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {sae}, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_range_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {sae}, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_range_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_range_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[63:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {sae}, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_range_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+IF k[0]
+	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_range_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+IF k[0]
+	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_range_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+IF k[0]
+	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_range_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+IF k[0]
+	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_range_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
+	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
+	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
+	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
+	1: dst[63:0] := tmp[63:0]
+	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
+	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
+	ESAC
+	
+	RETURN dst
+}
+dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_range_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[31:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+IF k[0]
+	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_range_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[31:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+IF k[0]
+	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_range_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[31:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+IF k[0]
+	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_range_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[31:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+IF k[0]
+	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_range_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
+	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
+	<operation>
+DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
+	CASE opCtl[1:0] OF
+	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
+	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
+	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
+	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
+	ESAC
+	
+	CASE signSelCtl[1:0] OF
+	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
+	1: dst[31:0] := tmp[31:0]
+	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
+	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
+	ESAC
+	
+	RETURN dst
+}
+dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_reduce_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_reduce_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+IF k[0]
+	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+IF k[0]
+	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+IF k[0]
+	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+IF k[0]
+	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	tmp[63:0] := src1[63:0] - tmp[63:0]
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := FP64(0.0)
+	FI
+	RETURN tmp[63:0]
+}
+dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+IF k[0]
+	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+IF k[0]
+	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+IF k[0]
+	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+IF k[0]
+	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	tmp[31:0] := src1[31:0] - tmp[31:0]
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := FP32(0.0)
+	FI
+	RETURN tmp[31:0]
+}
+dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {er}" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	 [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {er}" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {er}" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {er}" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {er}" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {er}" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {er}" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {er}" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {er}" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttpd_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttpd_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {sae}" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {sae}" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {sae}" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttps_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {sae}" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {sae}" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {sae}" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttps_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu64_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {er}" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {er}" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {er}" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu64_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := a[i+63:i] * b[i+63:i]
+		dst[i+63:i] := tmp[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULLQ" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := a[i+63:i] * b[i+63:i]
+		dst[i+63:i] := tmp[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULLQ" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mullo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	tmp[127:0] := a[i+63:i] * b[i+63:i]
+	dst[i+63:i] := tmp[63:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULLQ" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_kadd_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Add 8-bit masks in "a" and "b", and store the result in "k".</description>
+	<operation>
+k[7:0] := a[7:0] + b[7:0]
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, k, k" name="KADDB" xed="KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kadd_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Add 16-bit masks in "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := a[15:0] + b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KADDW" xed="KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kand_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[7:0] := a[7:0] AND b[7:0]
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDB" xed="KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kandn_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise NOT of 8-bit masks "a" and then AND with "b", and store the result in "k".</description>
+	<operation>
+k[7:0] := (NOT a[7:0]) AND b[7:0]
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDNB" xed="KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_knot_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<description>Compute the bitwise NOT of 8-bit mask "a", and store the result in "k".</description>
+	<operation>
+k[7:0] := NOT a[7:0]
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, k" name="KNOTB" xed="KNOTB_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kor_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise OR of 8-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[7:0] := a[7:0] OR b[7:0]
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, k, k" name="KORB" xed="KORB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kxnor_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise XNOR of 8-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[7:0] := NOT (a[7:0] XOR b[7:0])
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXNORB" xed="KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kxor_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise XOR of 8-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[7:0] := a[7:0] XOR b[7:0]
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXORB" xed="KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kshiftli_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
+	<description>Shift the bits of 8-bit mask "a" left by "count" while shifting in zeros, and store the least significant 8 bits of the result in "k".</description>
+	<operation>
+k[MAX:0] := 0
+IF count[7:0] &lt;= 7
+	k[7:0] := a[7:0] &lt;&lt; count[7:0]
+FI
+	</operation>
+	<instruction form="k, k, imm8" name="KSHIFTLB" xed="KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kshiftri_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
+	<description>Shift the bits of 8-bit mask "a" right by "count" while shifting in zeros, and store the least significant 8 bits of the result in "k".</description>
+	<operation>
+k[MAX:0] := 0
+IF count[7:0] &lt;= 7
+	k[7:0] := a[7:0] &gt;&gt; count[7:0]
+FI
+	</operation>
+	<instruction form="k, k, imm8" name="KSHIFTRB" xed="KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortest_mask8_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="all_ones" />
+	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
+	<operation>
+tmp[7:0] := a[7:0] OR b[7:0]
+IF tmp[7:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+IF tmp[7:0] == 0xFF
+	MEM[all_ones+7:all_ones] := 1
+ELSE
+	MEM[all_ones+7:all_ones] := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTB" xed="KORTESTB_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortestz_mask8_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[7:0] := a[7:0] OR b[7:0]
+IF tmp[7:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTB" xed="KORTESTB_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortestc_mask8_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[7:0] := a[7:0] OR b[7:0]
+IF tmp[7:0] == 0xFF
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTB" xed="KORTESTB_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktest_mask8_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="and_not" />
+	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
+	<operation>
+tmp1[7:0] := a[7:0] AND b[7:0]
+IF tmp1[7:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+tmp2[7:0] := (NOT a[7:0]) AND b[7:0]
+IF tmp2[7:0] == 0x0
+	MEM[and_not+7:and_not] := 1
+ELSE
+	MEM[and_not+7:and_not] := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTB" xed="KTESTB_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktestz_mask8_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[7:0] := a[7:0] AND b[7:0]
+IF tmp[7:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTB" xed="KTESTB_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktestc_mask8_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="b" />
+	<description>Compute the bitwise NOT of 8-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[7:0] := (NOT a[7:0]) AND b[7:0]
+IF tmp[7:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTB" xed="KTESTB_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktest_mask16_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="and_not" />
+	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
+	<operation>
+tmp1[15:0] := a[15:0] AND b[15:0]
+IF tmp1[15:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+tmp2[15:0] := (NOT a[15:0]) AND b[15:0]
+IF tmp2[15:0] == 0x0
+	MEM[and_not+7:and_not] := 1
+ELSE
+	MEM[and_not+7:and_not] := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTW" xed="KTESTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktestz_mask16_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[15:0] := a[15:0] AND b[15:0]
+IF tmp[15:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTW" xed="KTESTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_ktestc_mask16_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise NOT of 16-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[15:0] := (NOT a[15:0]) AND b[15:0]
+IF tmp[15:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KTESTW" xed="KTESTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_cvtmask8_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<description>Convert 8-bit mask "a" into an integer value, and store the result in "dst".</description>
+	<operation>
+dst := ZeroExtend32(a[7:0])
+	</operation>
+	<instruction form="r32, k" name="KMOVB" xed="KMOVB_GPR32u32_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_cvtu32_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="unsigned int" varname="a" />
+	<description>Convert integer value "a" into an 8-bit mask, and store the result in "k".</description>
+	<operation>
+k := a[7:0]
+	</operation>
+	<instruction form="k, r32" name="KMOVB" xed="KMOVB_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_load_mask8" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="mem_addr" />
+	<description>Load 8-bit mask from memory into "k".</description>
+	<operation>
+k[7:0] := MEM[mem_addr+7:mem_addr]
+	</operation>
+	<instruction form="k, m8" name="KMOVB" xed="KMOVB_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_store_mask8" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="a" />
+	<description>Store 8-bit mask from "a" into memory.</description>
+	<operation>
+MEM[mem_addr+7:mem_addr] := a[7:0]
+	</operation>
+	<instruction form="m8, k" name="KMOVB" xed="KMOVB_MEMu8_MASKmskw_AVX512" />
+	<CPUID>AVX512DQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_acos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ACOS(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_acos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ACOS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_acos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ACOS(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_acos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ACOS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_acosh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ACOSH(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_acosh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ACOSH(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_acosh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ACOSH(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_acosh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ACOSH(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_asin_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ASIN(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_asin_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ASIN(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_asin_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ASIN(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_asin_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ASIN(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_asinh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ASINH(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_asinh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ASINH(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_asinh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ASINH(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_asinh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ASINH(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_atan2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_atan2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_atan2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_atan2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_atan_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ATAN(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_atan_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ATAN(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_atan_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ATAN(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_atan_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ATAN(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_atanh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ATANH(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_atanh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ATANH(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_atanh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse hyperblic tangent of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ATANH(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_atanh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ATANH(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := COS(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := COS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := COS(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := COS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cosd_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := COSD(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cosd_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := COSD(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cosd_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := COSD(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cosd_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := COSD(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cosh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := COSH(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cosh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := COSH(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cosh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := COSH(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cosh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := COSH(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sin_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SIN(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sin_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SIN(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sin_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SIN(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sin_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SIN(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sinh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SINH(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sinh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SINH(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sinh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SINH(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sinh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SINH(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sind_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SIND(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sind_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SIND(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sind_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SIND(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sind_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SIND(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_tan_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := TAN(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_tan_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := TAN(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_tan_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := TAN(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_tan_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := TAN(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_tand_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := TAND(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_tand_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := TAND(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_tand_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := TAND(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_tand_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := TAND(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_tanh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := TANH(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_tanh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := TANH(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_tanh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := TANH(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_tanh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := TANH(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sincos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" memwidth="512" type="__m512d *" varname="mem_addr" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SIN(a[i+63:i])
+	MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+cos_res[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sincos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" memwidth="512" type="__m512d *" varname="mem_addr" />
+	<parameter etype="FP64" type="__m512d" varname="sin_src" />
+	<parameter etype="FP64" type="__m512d" varname="cos_src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", store the cosine into memory at "mem_addr". Elements are written to their respective locations using writemask "k" (elements are copied from "sin_src" or "cos_src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SIN(a[i+63:i])
+		MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := sin_src[i+63:i]
+		MEM[mem_addr+i+63:mem_addr+i] := cos_src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+cos_res[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sincos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" memwidth="512" type="__m512 *" varname="mem_addr" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SIN(a[i+31:i])
+	MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+cos_res[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sincos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" memwidth="512" type="__m512 *" varname="mem_addr" />
+	<parameter etype="FP32" type="__m512" varname="sin_src" />
+	<parameter etype="FP32" type="__m512" varname="cos_src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", store the cosine into memory at "mem_addr". Elements are written to their respective locations using writemask "k" (elements are copied from "sin_src" or "cos_src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SIN(a[i+31:i])
+		MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := sin_src[i+31:i]
+		MEM[mem_addr+i+31:mem_addr+i] := cos_src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+cos_res[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cbrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := CubeRoot(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cbrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := CubeRoot(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cbrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := CubeRoot(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cbrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := CubeRoot(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_exp10_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := POW(10.0, a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_exp10_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POW(10.0, a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_exp10_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_exp10_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_exp2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := POW(2.0, a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_exp2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POW(2.0, a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_exp2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_exp2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_exp_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := POW(e, a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_exp_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POW(e, a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_exp_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := POW(FP32(e), a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_exp_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POW(FP32(e), a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_expm1_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expm1_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_expm1_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expm1_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_hypot_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_hypot_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_hypot_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_hypot_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_invsqrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := InvSQRT(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_invsqrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := InvSQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_invsqrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := InvSQRT(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_invsqrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := InvSQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_log10_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_log10_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_log10_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_log10_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_log1p_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := LOG(1.0 + a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_log1p_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LOG(1.0 + a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_log1p_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := LOG(1.0 + a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_log1p_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LOG(1.0 + a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_log2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_log2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_log_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_log_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LOG(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_log_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_log_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LOG(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_logb_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_logb_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_logb_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_logb_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_pow_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_pow_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_pow_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_pow_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_recip_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Computes the reciprocal of packed double-precision (64-bit) floating-point elements in "a", storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := (1.0 / a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_recip_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Computes the reciprocal of packed double-precision (64-bit) floating-point elements in "a", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_recip_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Computes the reciprocal of packed single-precision (32-bit) floating-point elements in "a", storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (1.0 / a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_recip_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Computes the reciprocal of packed single-precision (32-bit) floating-point elements in "a", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cdfnorm_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := CDFNormal(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cdfnorm_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := CDFNormal(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cdfnorm_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := CDFNormal(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cdfnorm_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := CDFNormal(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cdfnorminv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := InverseCDFNormal(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cdfnorminv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := InverseCDFNormal(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cdfnorminv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := InverseCDFNormal(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cdfnorminv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := InverseCDFNormal(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_erf_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ERF(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_erf_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ERF(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_erfc_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := 1.0 - ERF(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_erfc_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := 1.0 - ERF(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_erf_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ERF(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_erf_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ERF(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_erfc_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+63:i] := 1.0 - ERF(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_erfc_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+63:i] := 1.0 - ERF(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_erfinv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := 1.0 / ERF(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_erfinv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := 1.0 / ERF(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_erfinv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+63:i] := 1.0 / ERF(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_erfinv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+63:i] := 1.0 / ERF(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_erfcinv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_erfcinv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_erfcinv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_erfcinv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm512_ceil_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := CEIL(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_ceil_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := CEIL(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_ceil_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := CEIL(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_ceil_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := CEIL(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_floor_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := FLOOR(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_floor_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FLOOR(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_floor_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := FLOOR(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_floor_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FLOOR(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_nearbyint_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Rounds each packed double-precision (64-bit) floating-point element in "a" to the nearest integer value and stores the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := NearbyInt(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_nearbyint_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Rounds each packed double-precision (64-bit) floating-point element in "a" to the nearest integer value and stores the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := NearbyInt(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_nearbyint_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Rounds each packed single-precision (32-bit) floating-point element in "a" to the nearest integer value and stores the results as packed single-precision floating-point elements in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := NearbyInt(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_nearbyint_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Rounds each packed single-precision (32-bit) floating-point element in "a" to the nearest integer value and stores the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := NearbyInt(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rint_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Rounds the packed double-precision (64-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := RoundToNearestEven(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rint_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Rounds the packed double-precision (64-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundToNearestEven(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rint_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Rounds the packed single-precision (32-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := RoundToNearestEven(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rint_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Rounds the packed single-precision (32-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundToNearestEven(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_svml_round_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ROUND(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_svml_round_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ROUND(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i] 
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_trunc_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := TRUNCATE(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_trunc_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := TRUNCATE(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_trunc_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := TRUNCATE(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_trunc_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := TRUNCATE(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF b[i+31:i] == 0
+		#DE
+	FI
+	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_div_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		IF b[i+31:i] == 0
+			#DE
+		FI
+		dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_epi8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := 8*j
+	IF b[i+7:i] == 0
+		#DE
+	FI
+	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_epi16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	IF b[i+15:i] == 0
+		#DE
+	FI
+	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_epi64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	IF b[i+63:i] == 0
+		#DE
+	FI
+	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rem_epi8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 63
+	i := 8*j
+	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rem_epi16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 31
+	i := 16*j
+	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rem_epi64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 64*j
+	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_epu32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF b[i+31:i] == 0
+		#DE
+	FI
+	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_div_epu32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		IF b[i+31:i] == 0
+			#DE
+		FI
+		dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_epu8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := 8*j
+	IF b[i+7:i] == 0
+		#DE
+	FI
+	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_epu16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := 16*j
+	IF b[i+15:i] == 0
+		#DE
+	FI
+	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_epu64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	IF b[i+63:i] == 0
+		#DE
+	FI
+	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rem_epu32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rem_epu32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rem_epu8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 63
+	i := 8*j
+	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rem_epu16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 31
+	i := 16*j
+	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rem_epu64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 64*j
+	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_log2_ps" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VLOG2PS" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_log2_ps" tech="SVML">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VLOG2PS" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_mask_add_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VADDPD" xed="VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_add_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VADDPD" xed="VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VADDPD" xed="VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VADDPD" xed="VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_add_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VADDPS" xed="VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_add_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VADDPS" xed="VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VADDPS" xed="VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VADDPS" xed="VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_div_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VDIVPD" xed="VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_div_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VDIVPD" xed="VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VDIVPD" xed="VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VDIVPD" xed="VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_div_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VDIVPS" xed="VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_div_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VDIVPS" xed="VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VDIVPS" xed="VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VDIVPS" xed="VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PD" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PD" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PD" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PD" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PD" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PD" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD132PD" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD213PD" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD231PD" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PD" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PD" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PD" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PD" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PD" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PD" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132PD" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213PD" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231PD" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PS" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PS" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PS" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PS" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PS" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PS" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD132PS" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD213PS" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD231PS" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PS" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PS" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PS" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PS" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PS" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PS" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132PS" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213PS" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231PS" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PD" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PD" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PD" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PD" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PD" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PD" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB132PD" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB213PD" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB231PD" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PD" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PD" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PD" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PD" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PD" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PD" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132PD" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213PD" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231PD" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PS" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PS" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PS" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PS" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PS" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PS" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB132PS" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB213PS" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB231PS" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PS" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PS" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PS" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PS" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PS" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PS" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132PS" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213PS" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231PS" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1 
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0) 
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PD" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PD" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PD" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PD" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PD" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PD" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD132PD" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD213PD" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD231PD" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PD" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PD" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PD" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PD" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PD" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PD" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132PD" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213PD" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231PD" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PS" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PS" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PS" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PS" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PS" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PS" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD132PS" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD213PS" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD231PS" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PS" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PS" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PS" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PS" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PS" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PS" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132PS" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213PS" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231PS" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PD" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PD" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PD" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PD" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PD" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PD" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB132PD" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB213PD" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB231PD" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PS" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PS" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PS" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PS" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PS" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PS" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB132PS" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB213PS" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB231PS" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMAXPD" xed="VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMAXPD" xed="VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMAXPD" xed="VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMAXPD" xed="VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMAXPS" xed="VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMAXPS" xed="VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMAXPS" xed="VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMAXPS" xed="VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMINPD" xed="VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMINPD" xed="VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMINPD" xed="VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMINPD" xed="VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMINPS" xed="VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMINPS" xed="VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMINPS" xed="VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMINPS" xed="VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mul_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMULPD" xed="VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mul_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMULPD" xed="VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMULPD" xed="VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMULPD" xed="VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mul_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  RM.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMULPS" xed="VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mul_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMULPS" xed="VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMULPS" xed="VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMULPS" xed="VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_abs_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ABS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPABSD" xed="VPABSD_YMMi32_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_abs_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ABS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPABSD" xed="VPABSD_YMMi32_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_abs_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ABS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPABSD" xed="VPABSD_XMMi32_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_abs_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ABS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPABSD" xed="VPABSD_XMMi32_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ABS(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPABSQ" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ABS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPABSQ" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ABS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPABSQ" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ABS(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPABSQ" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ABS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPABSQ" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ABS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPABSQ" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_add_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPADDD" xed="VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_add_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPADDD" xed="VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPADDD" xed="VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPADDD" xed="VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_add_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPADDQ" xed="VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_add_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] :=0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPADDQ" xed="VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPADDQ" xed="VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPADDQ" xed="VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMAXSD" xed="VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMAXSD" xed="VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMAXSD" xed="VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMAXSD" xed="VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMAXSQ" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMAXSQ" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMAXSQ" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMAXSQ" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMAXSQ" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPMAXSQ" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMAXUD" xed="VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMAXUD" xed="VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMAXUD" xed="VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMAXUD" xed="VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMAXUQ" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMAXUQ" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMAXUQ" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMAXUQ" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMAXUQ" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPMAXUQ" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMINSD" xed="VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMINSD" xed="VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMINSD" xed="VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMINSD" xed="VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMINSQ" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMINSQ" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMINSQ" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMINSQ" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMINSQ" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPMINSQ" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMINUD" xed="VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMINUD" xed="VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMINUD" xed="VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMINUD" xed="VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMINUQ" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMINUQ" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMINUQ" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMINUQ" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMINUQ" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPMINUQ" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mul_epi32" tech="AVX-512">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULDQ" xed="VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mul_epi32" tech="AVX-512">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULDQ" xed="VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_epi32" tech="AVX-512">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULDQ" xed="VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_epi32" tech="AVX-512">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULDQ" xed="VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mullo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		tmp[63:0] := a[i+31:i] * b[i+31:i]
+		dst[i+31:i] := tmp[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULLD" xed="VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mullo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		tmp[63:0] := a[i+31:i] * b[i+31:i]
+		dst[i+31:i] := tmp[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULLD" xed="VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mullo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		tmp[63:0] := a[i+31:i] * b[i+31:i]
+		dst[i+31:i] := tmp[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULLD" xed="VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mullo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		tmp[63:0] := a[i+31:i] * b[i+31:i]
+		dst[i+31:i] := tmp[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULLD" xed="VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mul_epu32" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULUDQ" xed="VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mul_epu32" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULUDQ" xed="VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_epu32" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULUDQ" xed="VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_epu32" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULUDQ" xed="VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sub_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSUBD" xed="VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sub_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSUBD" xed="VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSUBD" xed="VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSUBD" xed="VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sub_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSUBQ" xed="VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sub_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSUBQ" xed="VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSUBQ" xed="VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSUBQ" xed="VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VRCP14PD" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VRCP14PD" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := (1.0 / a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VRCP14PD" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VRCP14PD" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VRCP14PD" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (1.0 / a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VRCP14PD" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VRCP14PS" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VRCP14PS" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := (1.0 / a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VRCP14PS" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VRCP14PS" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VRCP14PS" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (1.0 / a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VRCP14PS" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VRSQRT14PD" xed="VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VRSQRT14PD" xed="VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VRSQRT14PD" xed="VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VRSQRT14PD" xed="VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VRSQRT14PD" xed="VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VRSQRT14PD" xed="VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VRSQRT14PS" xed="VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VRSQRT14PS" xed="VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VRSQRT14PS" xed="VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VRSQRT14PS" xed="VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VRSQRT14PS" xed="VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VRSQRT14PS" xed="VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VSUBPD" xed="VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VSUBPD" xed="VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSUBPD" xed="VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSUBPD" xed="VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VSUBPS" xed="VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VSUBPS" xed="VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSUBPS" xed="VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSUBPS" xed="VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst".</description>
+	<operation>
+temp[511:256] := a[255:0]
+temp[255:0] := b[255:0]
+temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
+dst[255:0] := temp[255:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VALIGND" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+temp[511:256] := a[255:0]
+temp[255:0] := b[255:0]
+temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := temp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VALIGND" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+temp[511:256] := a[255:0]
+temp[255:0] := b[255:0]
+temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := temp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VALIGND" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst".</description>
+	<operation>
+temp[255:128] := a[127:0]
+temp[127:0] := b[127:0]
+temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
+dst[127:0] := temp[127:0]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VALIGND" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+temp[255:128] := a[127:0]
+temp[127:0] := b[127:0]
+temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := temp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VALIGND" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+temp[255:128] := a[127:0]
+temp[127:0] := b[127:0]
+temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := temp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VALIGND" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst".</description>
+	<operation>
+temp[511:256] := a[255:0]
+temp[255:0] := b[255:0]
+temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
+dst[255:0] := temp[255:0]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VALIGNQ" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+temp[511:256] := a[255:0]
+temp[255:0] := b[255:0]
+temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := temp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VALIGNQ" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+temp[511:256] := a[255:0]
+temp[255:0] := b[255:0]
+temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := temp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VALIGNQ" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst".</description>
+	<operation>
+temp[255:128] := a[127:0]
+temp[127:0] := b[127:0]
+temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
+dst[127:0] := temp[127:0]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VALIGNQ" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+temp[255:128] := a[127:0]
+temp[127:0] := b[127:0]
+temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := temp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VALIGNQ" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+temp[255:128] := a[127:0]
+temp[127:0] := b[127:0]
+temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := temp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VALIGNQ" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_blend_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VBLENDMPD" xed="VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_blend_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VBLENDMPD" xed="VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_blend_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VBLENDMPS" xed="VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_blend_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VBLENDMPS" xed="VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_f32x4" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 4)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcast_f32x4" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 4)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcast_f32x4" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 4)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_broadcast_i32x4" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 4)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcast_i32x4" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 4)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcast_i32x4" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := (j % 4)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcastsd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcastsd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcastss_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcastss_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_broadcastss_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_broadcastss_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compress_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := src[255:m]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCOMPRESSPD" xed="VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_compress_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCOMPRESSPD" xed="VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compress_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := src[127:m]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_compress_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compress_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := src[255:m]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCOMPRESSPS" xed="VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_compress_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCOMPRESSPS" xed="VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compress_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := src[127:m]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_compress_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expand_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VEXPANDPD" xed="VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expand_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VEXPANDPD" xed="VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expand_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VEXPANDPD" xed="VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expand_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm " name="VEXPANDPD" xed="VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expand_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VEXPANDPS" xed="VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expand_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VEXPANDPS" xed="VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expand_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VEXPANDPS" xed="VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expand_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VEXPANDPS" xed="VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extractf32x4_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_extractf32x4_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_extractf32x4_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_extracti32x4_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_extracti32x4_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_extracti32x4_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN: j := 0
+	SNAN_TOKEN: j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VGETEXPPD" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VGETEXPPD" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VGETEXPPD" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VGETEXPPD" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VGETEXPPD" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VGETEXPPD" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VGETEXPPS" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VGETEXPPS" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VGETEXPPS" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VGETEXPPS" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VGETEXPPS" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VGETEXPPS" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VGETMANTPD" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VGETMANTPD" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VGETMANTPD" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VGETMANTPS" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VGETMANTPS" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VGETMANTPS" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_insertf32x4" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_insertf32x4" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_insertf32x4" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_inserti32x4" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_inserti32x4" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_inserti32x4" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[255:0] := a[255:0]
+CASE (imm8[0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_blend_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMD" xed="VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_blend_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMD" xed="VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_blend_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMQ" xed="VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_blend_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMQ" xed="VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcastd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcastd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_broadcastd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_broadcastd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_broadcastq_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_broadcastq_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_broadcastq_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_broadcastq_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compress_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := src[255:m]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPCOMPRESSD" xed="VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_compress_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPCOMPRESSD" xed="VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compress_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := src[127:m]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_compress_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compress_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := src[255:m]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_compress_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compress_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := src[127:m]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_compress_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutexvar_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	id := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMD" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutexvar_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	id := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMD" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutexvar_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	id := idx[i+2:i]*32
+	dst[i+31:i] := a[id+31:id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMD" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask2_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	off := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := idx[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2D" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	off := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2D" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	off := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := (idx[i+3]) ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2D" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2D" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	off := idx[i+2:i]*32
+	dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMI2D" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VPERMT2D" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask2_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	off := idx[i+1:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := idx[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2D" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="idx" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	off := idx[i+1:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2D" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="idx" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	off := idx[i+1:i]*32
+	IF k[j]
+		dst[i+31:i] := (idx[i+2]) ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2D" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2D" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="idx" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	off := idx[i+1:i]*32
+	dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMI2D" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VPERMT2D" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask2_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	off := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := idx[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2PD" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	off := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2PD" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	off := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := (idx[i+2]) ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2PD" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2PD" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	off := idx[i+1:i]*64
+	dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMI2PD" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VPERMT2PD" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask2_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set)</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	off := idx[i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := idx[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2PD" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="idx" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	off := idx[i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2PD" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="idx" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	off := idx[i]*64
+	IF k[j]
+		dst[i+63:i] := (idx[i+1]) ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2PD" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2PD" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="idx" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	off := idx[i]*64
+	dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMI2PD" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VPERMT2PD" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask2_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	off := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := idx[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2PS" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	off := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2PS" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	off := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := (idx[i+3]) ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2PS" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2PS" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	off := idx[i+2:i]*32
+	dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMI2PS" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VPERMT2PS" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask2_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	off := idx[i+1:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := idx[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2PS" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="idx" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	off := idx[i+1:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2PS" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="idx" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	off := idx[i+1:i]*32
+	IF k[j]
+		dst[i+31:i] := (idx[i+2]) ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2PS" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2PS" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="idx" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	off := idx[i+1:i]*32
+	dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMI2PS" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VPERMT2PS" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask2_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	off := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := idx[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2Q" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	off := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2Q" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	off := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := (idx[i+2]) ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2Q" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2Q" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	off := idx[i+1:i]*64
+	dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMI2Q" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VPERMT2Q" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask2_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	off := idx[i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := idx[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2Q" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="idx" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	off := idx[i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2Q" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="idx" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	off := idx[i]*64
+	IF k[j]
+		dst[i+63:i] := (idx[i+1]) ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2Q" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2Q" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="idx" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	off := idx[i]*64
+	dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMI2Q" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VPERMT2Q" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permute_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
+IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
+IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
+IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPERMILPD" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutevar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
+IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
+IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
+IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMILPD" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permute_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
+IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
+IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
+IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPERMILPD" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutevar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
+IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
+IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
+IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMILPD" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permute_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPERMILPD" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutevar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMILPD" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permute_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPERMILPD" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutevar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMILPD" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permute_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPERMILPS" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutevar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
+tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
+tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
+tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMILPS" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permute_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPERMILPS" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutevar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
+tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
+tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
+tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMILPS" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permute_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPERMILPS" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutevar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMILPS" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permute_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPERMILPS" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutevar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMILPS" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutex_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutexvar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	id := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := a[id+63:id]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutex_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutexvar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	id := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := a[id+63:id]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutexvar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	id := idx[i+1:i]*64
+	dst[i+63:i] := a[id+63:id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutexvar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	id := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMPS" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutexvar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	id := idx[i+2:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMPS" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutexvar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="idx" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	id := idx[i+2:i]*32
+	dst[i+31:i] := a[id+31:id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMPS" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutex_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 64-bit integers in "a" across lanes lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutexvar_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	id := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := a[id+63:id]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutex_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutexvar_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	id := idx[i+1:i]*64
+	IF k[j]
+		dst[i+63:i] := a[id+63:id]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutexvar_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="idx" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	id := idx[i+1:i]*64
+	dst[i+63:i] := a[id+63:id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expand_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPEXPANDD" xed="VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expand_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPEXPANDD" xed="VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expand_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPEXPANDD" xed="VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expand_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPEXPANDD" xed="VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expand_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPEXPANDQ" xed="VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expand_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPEXPANDQ" xed="VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expand_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPEXPANDQ" xed="VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expand_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPEXPANDQ" xed="VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shuffle_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSHUFD" xed="VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shuffle_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSHUFD" xed="VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shuffle_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSHUFD" xed="VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shuffle_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSHUFD" xed="VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpackhi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpackhi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpackhi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpackhi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpackhi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpackhi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpackhi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpackhi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpacklo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpacklo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpacklo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpacklo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpacklo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpacklo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpacklo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpacklo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VSCALEFPD" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VSCALEFPD" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VSCALEFPD" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFPD" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFPD" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSCALEFPD" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VSCALEFPS" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VSCALEFPS" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VSCALEFPS" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFPS" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFPS" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSCALEFPS" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shuffle_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst.m128[0] := a.m128[imm8[0]]
+tmp_dst.m128[1] := b.m128[imm8[1]]
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shuffle_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst.m128[0] := a.m128[imm8[0]]
+tmp_dst.m128[1] := b.m128[imm8[1]]
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shuffle_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst.m128[0] := a.m128[imm8[0]]
+dst.m128[1] := b.m128[imm8[1]]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shuffle_f64x2" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst.m128[0] := a.m128[imm8[0]]
+tmp_dst.m128[1] := b.m128[imm8[1]]
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shuffle_f64x2" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst.m128[0] := a.m128[imm8[0]]
+tmp_dst.m128[1] := b.m128[imm8[1]]
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shuffle_f64x2" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst.m128[0] := a.m128[imm8[0]]
+dst.m128[1] := b.m128[imm8[1]]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shuffle_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst.m128[0] := a.m128[imm8[0]]
+tmp_dst.m128[1] := b.m128[imm8[1]]
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shuffle_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst.m128[0] := a.m128[imm8[0]]
+tmp_dst.m128[1] := b.m128[imm8[1]]
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shuffle_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst.m128[0] := a.m128[imm8[0]]
+dst.m128[1] := b.m128[imm8[1]]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shuffle_i64x2" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst.m128[0] := a.m128[imm8[0]]
+tmp_dst.m128[1] := b.m128[imm8[1]]
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shuffle_i64x2" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst.m128[0] := a.m128[imm8[0]]
+tmp_dst.m128[1] := b.m128[imm8[1]]
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shuffle_i64x2" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst.m128[0] := a.m128[imm8[0]]
+dst.m128[1] := b.m128[imm8[1]]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shuffle_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFPD" xed="VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shuffle_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFPD" xed="VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shuffle_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VSHUFPD" xed="VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shuffle_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VSHUFPD" xed="VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shuffle_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFPS" xed="VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shuffle_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFPS" xed="VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shuffle_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VSHUFPS" xed="VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shuffle_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VSHUFPS" xed="VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpackhi_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VUNPCKHPD" xed="VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpackhi_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VUNPCKHPD" xed="VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpackhi_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VUNPCKHPD" xed="VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpackhi_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VUNPCKHPD" xed="VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpackhi_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VUNPCKHPS" xed="VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpackhi_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VUNPCKHPS" xed="VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpackhi_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VUNPCKHPS" xed="VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpackhi_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VUNPCKHPS" xed="VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpacklo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VUNPCKLPD" xed="VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpacklo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VUNPCKLPD" xed="VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpacklo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VUNPCKLPD" xed="VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpacklo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VUNPCKLPD" xed="VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_unpacklo_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VUNPCKLPS" xed="VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_unpacklo_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VUNPCKLPS" xed="VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_unpacklo_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VUNPCKLPS" xed="VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_unpacklo_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VUNPCKLPS" xed="VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpge_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmple_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmplt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpneq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpeq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpge_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpgt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmple_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmplt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpneq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="SI32" type="__m256i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpeq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpge_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpgt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmple_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmplt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpneq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpge_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmple_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmplt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpneq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpeq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpge_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpgt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmple_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmplt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpneq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="SI64" type="__m256i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpeq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpge_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpgt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmple_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmplt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpneq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpge_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmple_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmplt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpneq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpeq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpge_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpgt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmple_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmplt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpneq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpeq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpge_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpgt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmple_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmplt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpneq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpeq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpge_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpgt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmple_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmplt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmpneq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpeq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpge_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpgt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmple_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmplt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmpneq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpeq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpge_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpgt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmple_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmplt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmpneq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_test_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_test_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_test_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_test_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_test_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_test_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_test_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_test_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_testn_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k1[j]
+		k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testn_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_testn_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k1[j]
+		k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_testn_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_testn_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k1[j]
+		k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_testn_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:4] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_testn_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k1[j]
+		k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_testn_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:2] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compressstoreu_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 64
+m := base_addr
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		MEM[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VCOMPRESSPD" xed="VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compressstoreu_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 64
+m := base_addr
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		MEM[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compressstoreu_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 32
+m := base_addr
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		MEM[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VCOMPRESSPS" xed="VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compressstoreu_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 32
+m := base_addr
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		MEM[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_store_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVAPD" xed="VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_store_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVAPD" xed="VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_store_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_store_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_store_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_store_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_store_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_store_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_storeu_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_storeu_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_storeu_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_storeu_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_storeu_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVUPD" xed="VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_storeu_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVUPD" xed="VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_storeu_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_storeu_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compressstoreu_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 32
+m := base_addr
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		MEM[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VPCOMPRESSD" xed="VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compressstoreu_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 32
+m := base_addr
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		MEM[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compressstoreu_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 64
+m := base_addr
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		MEM[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compressstoreu_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 64
+m := base_addr
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		MEM[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i32scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32y, ymm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i32scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32y {k}, ymm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_i32scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32x, xmm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i32scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32x {k}, xmm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i32scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32x, ymm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i32scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32x {k}, ymm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_i32scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32x, xmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i32scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32x {k}, xmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i64scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64y, xmm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i64scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64y {k}, xmm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_i64scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64x, xmm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i64scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64x {k}, xmm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i64scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64y, ymm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i64scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64y {k}, ymm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_i64scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64x, xmm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i64scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64x {k}, xmm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i32scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32x, ymm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i32scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32x {k}, ymm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_i32scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32x, xmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i32scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32x {k}, xmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i32scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32y, ymm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i32scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32y {k}, ymm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_i32scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32x, xmm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i32scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32x {k}, xmm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i64scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64y, ymm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i64scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64y {k}, ymm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_i64scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64x, xmm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i64scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64x {k}, xmm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_i64scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64y, xmm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_i64scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64y {k}, xmm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_i64scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64x, xmm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_i64scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64x {k}, xmm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Store 256-bits (composed of 4 packed 64-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Store 256-bits (composed of 8 packed 32-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Store 128-bits (composed of 2 packed 64-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Store 128-bits (composed of 4 packed 32-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_store_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Store 256-bits (composed of 4 packed 64-bit integers) from "a" into memory.
+		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_store_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="256" type="void*" varname="mem_addr" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Store 256-bits (composed of 8 packed 32-bit integers) from "a" into memory.
+		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Store 128-bits (composed of 2 packed 64-bit integers) from "a" into memory.
+		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Store 128-bits (composed of 4 packed 32-bit integers) from "a" into memory.
+		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	IF k[j]
+		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+	ELSE
+		dst[m+63:m] := src[m+63:m]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	IF k[j]
+		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+	ELSE
+		dst[m+63:m] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	IF k[j]
+		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+	ELSE
+		dst[m+63:m] := src[m+63:m]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	IF k[j]
+		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+	ELSE
+		dst[m+63:m] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTDQ2PS" xed="VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTDQ2PS" xed="VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTPS2DQ" xed="VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTPS2DQ" xed="VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvt_roundps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvt_roundps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvt_roundps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvt_roundps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_Int32_To_FP64(a[l+31:l])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_Int32_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := Truncate8(a[i+31:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, ymm" name="VPMOVDB" xed="VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := Truncate8(a[i+31:i])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVDB" xed="VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := Truncate16(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVDW" xed="VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := Truncate16(a[i+31:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVDW" xed="VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := Truncate8(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, ymm" name="VPMOVQB" xed="VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := Truncate8(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="16" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m16 {k}, xmm" name="VPMOVQB" xed="VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := Truncate32(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Truncate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI32" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVQD" xed="VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Truncate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := Truncate32(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Truncate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI32" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVQD" xed="VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Truncate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := Truncate16(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, ymm" name="VPMOVQW" xed="VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := Truncate16(a[i+63:i])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, xmm" name="VPMOVQW" xed="VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := Saturate8(a[i+31:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, ymm" name="VPMOVSDB" xed="VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := Saturate8(a[i+31:i])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, xmm" name="VPMOVSDB" xed="VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := Saturate16(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI16" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVSDW" xed="VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := Saturate16(a[i+31:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI16" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVSDW" xed="VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := Saturate8(a[i+63:i])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, ymm" name="VPMOVSQB" xed="VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := Saturate8(a[i+63:i])
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="16" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m16 {k}, xmm" name="VPMOVSQB" xed="VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := Saturate32(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Saturate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI32" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVSQD" xed="VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Saturate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := Saturate32(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Saturate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI32" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVSQD" xed="VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Saturate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := Saturate16(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtsepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI16" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, ymm" name="VPMOVSQW" xed="VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := Saturate16(a[i+63:i])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI16" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, xmm" name="VPMOVSQW" xed="VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi8_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi8_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi8_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi8_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi8_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi8_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi8_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi8_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi32_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi32_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi32_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi32_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi16_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*16
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi16_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi16_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	l := j*16
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi16_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi16_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi16_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi16_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi16_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := SaturateU8(a[i+31:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, ymm" name="VPMOVUSDB" xed="VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := SaturateU8(a[i+31:i])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, xmm" name="VPMOVUSDB" xed="VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := SaturateU16(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVUSDW" xed="VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := SaturateU16(a[i+31:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVUSDW" xed="VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := SaturateU8(a[i+63:i])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, ymm" name="VPMOVUSQB" xed="VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := SaturateU8(a[i+63:i])
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="16" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m16 {k}, xmm" name="VPMOVUSQB" xed="VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := SaturateU32(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := SaturateU32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI32" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, ymm" name="VPMOVUSQD" xed="VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := SaturateU32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := SaturateU32(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := SaturateU32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI32" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VPMOVUSQD" xed="VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := SaturateU32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := SaturateU16(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtusepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, ymm" name="VPMOVUSQW" xed="VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := SaturateU16(a[i+63:i])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtusepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, xmm" name="VPMOVUSQW" xed="VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in th elow 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu8_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu8_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu8_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu8_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu32_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu32_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+	ELSE 
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu32_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu32_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+	ELSE 
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu16_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu16_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu16_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu16_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu16_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu16_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu16_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu16_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expandloadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m256" name="VEXPANDPD" xed="VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expandloadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m256" name="VEXPANDPD" xed="VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expandloadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m128" name="VEXPANDPD" xed="VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expandloadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m128" name="VEXPANDPD" xed="VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expandloadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m256" name="VEXPANDPS" xed="VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expandloadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m256" name="VEXPANDPS" xed="VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expandloadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m128" name="VEXPANDPS" xed="VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expandloadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m128" name="VEXPANDPS" xed="VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mmask_i32gather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, vm32x" name="VGATHERDPD" xed="VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mmask_i32gather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, vm32x" name="VGATHERDPD" xed="VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mmask_i32gather_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="FP32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, vm32y" name="VGATHERDPS" xed="VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mmask_i32gather_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="FP32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, vm32x" name="VGATHERDPS" xed="VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mmask_i64gather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, vm64y" name="VGATHERQPD" xed="VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mmask_i64gather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, vm64x" name="VGATHERQPD" xed="VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mmask_i64gather_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="FP32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="ymm {k}, vm64y" name="VGATHERQPS" xed="VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mmask_i64gather_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="FP32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, vm64x" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_load_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VMOVAPD" xed="VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_load_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m256" name="VMOVAPD" xed="VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_load_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m128" name="VMOVAPD" xed="VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_load_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m128" name="VMOVAPD" xed="VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_load_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m256" name="VMOVAPS" xed="VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_load_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m256" name="VMOVAPS" xed="VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_load_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m128" name="VMOVAPS" xed="VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_load_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m128" name="VMOVAPS" xed="VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m64" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m64" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VMOVDQU32" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m64" name="VMOVDQU32" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VMOVDQU32" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VMOVDQU32" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VMOVDQU64" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m64" name="VMOVDQU64" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VMOVDQU64" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VMOVDQU64" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_loadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VMOVUPD" xed="VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_loadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m64" name="VMOVUPD" xed="VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_loadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VMOVUPD" xed="VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_loadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VMOVUPD" xed="VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_loadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VMOVUPS" xed="VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_loadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m64" name="VMOVUPS" xed="VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_loadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VMOVUPS" xed="VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_loadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VMOVUPS" xed="VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expandloadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VPEXPANDD" xed="VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expandloadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m64" name="VPEXPANDD" xed="VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expandloadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VPEXPANDD" xed="VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expandloadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VPEXPANDD" xed="VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expandloadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expandloadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expandloadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expandloadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mmask_i32gather_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, vm32y" name="VPGATHERDD" xed="VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mmask_i32gather_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, vm32x" name="VPGATHERDD" xed="VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mmask_i32gather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, vm32x" name="VPGATHERDQ" xed="VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mmask_i32gather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, vm32x" name="VPGATHERDQ" xed="VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mmask_i64gather_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, vm64y" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mmask_i64gather_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, vm64x" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mmask_i64gather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, vm64y" name="VPGATHERQQ" xed="VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mmask_i64gather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, vm64x" name="VPGATHERQQ" xed="VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits (composed of 4 packed 64-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVDQU64" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits (composed of 8 packed 32-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVDQU32" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 2 packed 64-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m128" name="VMOVDQU64" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 4 packed 32-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m128" name="VMOVDQU32" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits (composed of 4 packed 64-bit integers) from memory into "dst".
+		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits (composed of 8 packed 32-bit integers) from memory into "dst".
+		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 2 packed 64-bit integers) from memory into "dst".
+		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m128" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 4 packed 32-bit integers) from memory into "dst".
+		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m128" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mov_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVAPD" xed="VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mov_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVAPD" xed="VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mov_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVAPD" xed="VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mov_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVAPD" xed="VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mov_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVAPS" xed="VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mov_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVAPS" xed="VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mov_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVAPS" xed="VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mov_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVAPS" xed="VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_movedup_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[63:0] := a[63:0]
+tmp[127:64] := a[63:0]
+tmp[191:128] := a[191:128]
+tmp[255:192] := a[191:128]
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVDDUP" xed="VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_movedup_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[63:0] := a[63:0]
+tmp[127:64] := a[63:0]
+tmp[191:128] := a[191:128]
+tmp[255:192] := a[191:128]
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVDDUP" xed="VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_movedup_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[63:0] := a[63:0]
+tmp[127:64] := a[63:0]
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVDDUP" xed="VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_movedup_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[63:0] := a[63:0]
+tmp[127:64] := a[63:0]
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVDDUP" xed="VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mov_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mov_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mov_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mov_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mov_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mov_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mov_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mov_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_movehdup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[63:32] 
+tmp[63:32] := a[63:32] 
+tmp[95:64] := a[127:96] 
+tmp[127:96] := a[127:96]
+tmp[159:128] := a[191:160] 
+tmp[191:160] := a[191:160] 
+tmp[223:192] := a[255:224] 
+tmp[255:224] := a[255:224]
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVSHDUP" xed="VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_movehdup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[63:32] 
+tmp[63:32] := a[63:32] 
+tmp[95:64] := a[127:96] 
+tmp[127:96] := a[127:96]
+tmp[159:128] := a[191:160] 
+tmp[191:160] := a[191:160] 
+tmp[223:192] := a[255:224] 
+tmp[255:224] := a[255:224]
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVSHDUP" xed="VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_movehdup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[63:32] 
+tmp[63:32] := a[63:32] 
+tmp[95:64] := a[127:96] 
+tmp[127:96] := a[127:96]
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVSHDUP" xed="VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_movehdup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[63:32] 
+tmp[63:32] := a[63:32] 
+tmp[95:64] := a[127:96] 
+tmp[127:96] := a[127:96]
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVSHDUP" xed="VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_moveldup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[31:0] 
+tmp[63:32] := a[31:0] 
+tmp[95:64] := a[95:64] 
+tmp[127:96] := a[95:64]
+tmp[159:128] := a[159:128] 
+tmp[191:160] := a[159:128] 
+tmp[223:192] := a[223:192] 
+tmp[255:224] := a[223:192]
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VMOVSLDUP" xed="VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_moveldup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[31:0] 
+tmp[63:32] := a[31:0] 
+tmp[95:64] := a[95:64] 
+tmp[127:96] := a[95:64]
+tmp[159:128] := a[159:128] 
+tmp[191:160] := a[159:128] 
+tmp[223:192] := a[223:192] 
+tmp[255:224] := a[223:192]
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VMOVSLDUP" xed="VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_moveldup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[31:0] 
+tmp[63:32] := a[31:0] 
+tmp[95:64] := a[95:64] 
+tmp[127:96] := a[95:64]
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VMOVSLDUP" xed="VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_moveldup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[31:0] 
+tmp[63:32] := a[31:0] 
+tmp[95:64] := a[95:64] 
+tmp[127:96] := a[95:64]
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VMOVSLDUP" xed="VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_and_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPANDD" xed="VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_and_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPANDD" xed="VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_and_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPANDD" xed="VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_and_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPANDD" xed="VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_andnot_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPANDND" xed="VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_andnot_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPANDND" xed="VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_andnot_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPANDND" xed="VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_andnot_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPANDND" xed="VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_andnot_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPANDNQ" xed="VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_andnot_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPANDNQ" xed="VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_andnot_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPANDNQ" xed="VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_andnot_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPANDNQ" xed="VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_and_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPANDQ" xed="VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_and_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPANDQ" xed="VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_and_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPANDQ" xed="VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_and_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPANDQ" xed="VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPORD" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPORD" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPORD" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPORD" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPORQ" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPORQ" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPORQ" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPORQ" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		FOR h := 0 to 31
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		FOR h := 0 to 31
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 7
+	i := j*32
+	FOR h := 0 to 31
+		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		FOR h := 0 to 31
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		FOR h := 0 to 31
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 3
+	i := j*32
+	FOR h := 0 to 31
+		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		FOR h := 0 to 63
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		FOR h := 0 to 63
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 3
+	i := j*64
+	FOR h := 0 to 63
+		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		FOR h := 0 to 63
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		FOR h := 0 to 63
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 1
+	i := j*64
+	FOR h := 0 to 63
+		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPXORD" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPXORD" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPXORD" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPXORD" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPXORQ" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPXORQ" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPXORQ" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPXORQ" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPXORQ" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPXORD" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPXORQ" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPXORD" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPORQ" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPORD" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPORQ" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPORD" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_set1_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_set1_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_set1_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_set1_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_set1_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_set1_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_set1_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_set1_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPROLD" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPROLD" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPROLD" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPROLD" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPROLD" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VPROLD" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPROLQ" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPROLQ" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPROLQ" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPROLQ" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPROLQ" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VPROLQ" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPROLVD" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPROLVD" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPROLVD" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPROLVD" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPROLVD" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPROLVD" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPROLVQ" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPROLVQ" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPROLVQ" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPROLVQ" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPROLVQ" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPROLVQ" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPRORD" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPRORD" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPRORD" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPRORD" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPRORD" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VPRORD" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPRORQ" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPRORQ" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPRORQ" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPRORQ" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPRORQ" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VPRORQ" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPRORVD" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPRORVD" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPRORVD" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPRORVD" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPRORVD" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPRORVD" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPRORVQ" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPRORVQ" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPRORVQ" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPRORVQ" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPRORVQ" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPRORVQ" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sll_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSLLD" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_slli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSLLD" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sll_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSLLD" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_slli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSLLD" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sll_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSLLD" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_slli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSLLD" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sll_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSLLD" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_slli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSLLD" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sll_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSLLQ" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_slli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSLLQ" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sll_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSLLQ" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_slli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSLLQ" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sll_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSLLQ" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_slli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSLLQ" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sll_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSLLQ" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_slli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSLLQ" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sllv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSLLVD" xed="VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sllv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSLLVD" xed="VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sllv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSLLVD" xed="VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sllv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSLLVD" xed="VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sllv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSLLVQ" xed="VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sllv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSLLVQ" xed="VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sllv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSLLVQ" xed="VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sllv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSLLVQ" xed="VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sra_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSRAD" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srai_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSRAD" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sra_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSRAD" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srai_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSRAD" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sra_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRAD" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srai_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSRAD" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sra_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRAD" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srai_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="6" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSRAD" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+	ELSE
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, xmm" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+	ELSE
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="7" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+	ELSE
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="7" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+	ELSE
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srav_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSRAVD" xed="VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srav_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSRAVD" xed="VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srav_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRAVD" xed="VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srav_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRAVD" xed="VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSRAVQ" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSRAVQ" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSRAVQ" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRAVQ" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRAVQ" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSRAVQ" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srl_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSRLD" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSRLD" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srl_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSRLD" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSRLD" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srl_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRLD" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSRLD" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srl_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRLD" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSRLD" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srl_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, xmm" name="VPSRLQ" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VPSRLQ" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srl_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, xmm" name="VPSRLQ" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VPSRLQ" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srl_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRLQ" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VPSRLQ" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srl_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRLQ" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VPSRLQ" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srlv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSRLVD" xed="VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srlv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSRLVD" xed="VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srlv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRLVD" xed="VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srlv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRLVD" xed="VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_srlv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSRLVQ" xed="VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_srlv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSRLVQ" xed="VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_srlv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSRLVQ" xed="VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_srlv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSRLVQ" xed="VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sqrt_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VSQRTPD" xed="VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sqrt_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VSQRTPD" xed="VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VSQRTPD" xed="VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VSQRTPD" xed="VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sqrt_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VSQRTPS" xed="VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sqrt_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VSQRTPS" xed="VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VSQRTPS" xed="VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VSQRTPS" xed="VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_aesenclast_epi128" tech="Other">
+	<return etype="M128" type="__m512i" varname="dst" />
+	<parameter etype="M128" type="__m512i" varname="a" />
+	<parameter etype="M128" type="__m512i" varname="RoundKey" />
+	<description>Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
+	<operation>FOR j := 0 to 3
+	i := j*128
+	a[i+127:i] := ShiftRows(a[i+127:i])
+	a[i+127:i] := SubBytes(a[i+127:i])
+	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VAESENCLAST" xed="VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>VAES</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm512_aesenc_epi128" tech="Other">
+	<return etype="M128" type="__m512i" varname="dst" />
+	<parameter etype="M128" type="__m512i" varname="a" />
+	<parameter etype="M128" type="__m512i" varname="RoundKey" />
+	<description>Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
+	<operation>FOR j := 0 to 3
+	i := j*128
+	a[i+127:i] := ShiftRows(a[i+127:i])
+	a[i+127:i] := SubBytes(a[i+127:i])
+	a[i+127:i] := MixColumns(a[i+127:i])
+	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VAESENC" xed="VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>VAES</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm512_aesdeclast_epi128" tech="Other">
+	<return etype="M128" type="__m512i" varname="dst" />
+	<parameter etype="M128" type="__m512i" varname="a" />
+	<parameter etype="M128" type="__m512i" varname="RoundKey" />
+	<description>Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*128
+	a[i+127:i] := InvShiftRows(a[i+127:i])
+	a[i+127:i] := InvSubBytes(a[i+127:i])
+	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VAESDECLAST" xed="VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>VAES</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm512_aesdec_epi128" tech="Other">
+	<return etype="M128" type="__m512i" varname="dst" />
+	<parameter etype="M128" type="__m512i" varname="a" />
+	<parameter etype="M128" type="__m512i" varname="RoundKey" />
+	<description>Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*128
+	a[i+127:i] := InvShiftRows(a[i+127:i])
+	a[i+127:i] := InvSubBytes(a[i+127:i])
+	a[i+127:i] := InvMixColumns(a[i+127:i])
+	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VAESDEC" xed="VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<CPUID>VAES</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_maskz_mullo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp[63:0] := a[i+31:i] * b[i+31:i]
+		dst[i+31:i] := tmp[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULLD" xed="VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := a[63:0] + b[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] + b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] + b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] + b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] + b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+dst[31:0] := a[31:0] + b[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] + b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] + b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] + b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] + b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", =and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_div_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_div_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_div_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_div_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] / b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_div_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_div_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_div_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_div_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] / b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+		[round_note]</description>
+	<operation>
+dst[63:0] := a[63:0] / b[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". 
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] / b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] / b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] / b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] / b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+dst[31:0] := a[31:0] / b[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] / b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] / b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] / b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] / b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "a" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := c[63:0]
+FI
+dst[127:64] := c[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := c[63:0]
+FI
+dst[127:64] := c[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := c[31:0]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := c[31:0]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF ((j &amp; 1) == 0)
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmaddsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF ((j &amp; 1) == 0)
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmaddsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE 
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmaddsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmaddsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmaddsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF ((j &amp; 1) == 0)
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmaddsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF ((j &amp; 1) == 0)
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmaddsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmaddsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmaddsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmaddsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := c[63:0]
+FI
+dst[127:64] := c[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := c[63:0]
+FI
+dst[127:64] := c[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". 
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := c[31:0]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := c[31:0]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF ((j &amp; 1) == 0)
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsubadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF ((j &amp; 1) == 0)
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsubadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsubadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsubadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsubadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+		ELSE
+			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF ((j &amp; 1) == 0)
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsubadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF ((j &amp; 1) == 0)
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsubadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsubadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsubadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsubadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+		ELSE
+			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := c[63:0]
+FI
+dst[127:64] := c[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := c[63:0]
+FI
+dst[127:64] := c[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := c[31:0]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := c[31:0]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := c[63:0]
+FI
+dst[127:64] := c[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := c[63:0]
+FI
+dst[127:64] := c[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", subtract the lower element in "c" from the negated intermediate result, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := c[31:0]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := c[31:0]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] * b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] * b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] * b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] * b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+		[round_note]</description>
+	<operation>
+dst[63:0] := a[63:0] * b[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] * b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] * b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] * b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] * b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+dst[31:0] := a[31:0] * b[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPADDD" xed="VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPADDQ" xed="VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPADDQ" xed="VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPADDQ" xed="VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_epi32" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULDQ" xed="VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_epi32" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULDQ" xed="VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_epi32" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULDQ" xed="VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_epu32" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULUDQ" xed="VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_epu32" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULUDQ" xed="VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_epu32" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+31:i] * b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULUDQ" xed="VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSUBD" xed="VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSUBQ" xed="VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSUBQ" xed="VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSUBQ" xed="VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] - b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] - b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] - b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := a[63:0] - b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := a[63:0] - b[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] - b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] - b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] - b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := a[31:0] - b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := a[31:0] - b[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_storeu_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Store 512-bits (composed of 8 packed 64-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_storeu_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Store 512-bits (composed of 16 packed 32-bit integers) from "a" into memory.
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_store_mask16" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="MASK" memwidth="16" type="__mmask16*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<description>Store 16-bit mask from "a" into memory.</description>
+	<operation>
+MEM[mem_addr+15:mem_addr] := a[15:0]
+	</operation>
+	<instruction form="m16, k" name="KMOVW" xed="KMOVW_MEMu16_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compressstoreu_pd" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="FP64" memwidth="512" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 64
+m := base_addr
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		MEM[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compressstoreu_ps" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="FP32" memwidth="512" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 32
+m := base_addr
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		MEM[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_storeu_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_storeu_si512" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="M512" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="M512" type="__m512i" varname="a" />
+	<description>Store 512-bits of integer data from "a" into memory.
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_storeu_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_stream_si512" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="M512" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="M512" type="__m512i" varname="a" />
+	<description>Store 512-bits of integer data from "a" into memory using a non-temporal memory hint. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVNTDQ" xed="VMOVNTDQ_MEMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_stream_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVNTPD" xed="VMOVNTPD_MEMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_stream_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVNTPS" xed="VMOVNTPS_MEMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_store_sd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store the lower double-precision (64-bit) floating-point element from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+IF k[0]
+	MEM[mem_addr+63:mem_addr] := a[63:0]
+FI
+	</operation>
+	<instruction form="m64 {k}, xmm" name="VMOVSD" xed="VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_store_ss" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="32" type="float*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store the lower single-precision (32-bit) floating-point element from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+IF k[0]
+	MEM[mem_addr+31:mem_addr] := a[31:0]
+FI
+	</operation>
+	<instruction form="m32 {k}, xmm" name="VMOVSS" xed="VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_storeu_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVUPD" xed="VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_storeu_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVUPD" xed="VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_storeu_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_storeu_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compressstoreu_epi32" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="UI32" memwidth="512" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 32
+m := base_addr
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		MEM[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m32 {k}, zmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compressstoreu_epi64" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="UI64" memwidth="512" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 64
+m := base_addr
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		MEM[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, zmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32y, zmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32y {k}, zmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i64scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64z, ymm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i64scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64z {k}, ymm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i64scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm64z, zmm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i64scatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm64z {k}, zmm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32y, zmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32y {k}, zmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i64scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32z, zmm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i64scatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32z {k}, zmm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i64scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32z, ymm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i64scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32z {k}, ymm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mullox_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Multiplies elements in packed 64-bit integer vectors "a" and "b" together, storing the lower 64 bits of the result in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mullox_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Multiplies elements in packed 64-bit integer vectors "a" and "b" together, storing the lower 64 bits of the result in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 8 packed 64-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVDQU64" xed="VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 16 packed 32-bit integers) from memory into "dst".
+		"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVDQU32" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_load_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" memwidth="16" type="__mmask16*" varname="mem_addr" />
+	<description>Load 16-bit mask from memory into "k".</description>
+	<operation>
+k[15:0] := MEM[mem_addr+15:mem_addr]
+	</operation>
+	<instruction form="k, m16" name="KMOVW" xed="KMOVW_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expandloadu_pd" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VEXPANDPD" xed="VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expandloadu_pd" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VEXPANDPD" xed="VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expandloadu_ps" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VEXPANDPS" xed="VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expandloadu_ps" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VEXPANDPS" xed="VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32gather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, vm32y" name="VGATHERDPD" xed="VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32gather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, vm32y" name="VGATHERDPD" xed="VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i64gather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, vm32z" name="VGATHERQPD" xed="VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i64gather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, vm32z" name="VGATHERQPD" xed="VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i64gather_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm64z" name="VGATHERQPS" xed="VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i64gather_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, vm64z" name="VGATHERQPS" xed="VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_load_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_load_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_loadu_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits of integer data from memory into "dst".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVDQU32" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVDQU32" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_loadu_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVDQU32" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVDQU64" xed="VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_loadu_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVDQU64" xed="VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_stream_load_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits of integer data from memory into "dst" using a non-temporal memory hint. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVNTDQA" xed="VMOVNTDQA_ZMMu32_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_load_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="64" type="const double*" varname="mem_addr" />
+	<description>Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and set the upper element of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MEM[mem_addr+63:mem_addr]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VMOVSD" xed="VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_load_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="64" type="const double*" varname="mem_addr" />
+	<description>Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and set the upper element of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MEM[mem_addr+63:mem_addr]
+ELSE
+	dst[63:0] := 0
+FI
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VMOVSD" xed="VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_load_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="32" type="const float*" varname="mem_addr" />
+	<description>Load a single-precision (32-bit) floating-point element from memory into the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and set the upper elements of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MEM[mem_addr+31:mem_addr]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, m32" name="VMOVSS" xed="VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_load_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" memwidth="32" type="const float*" varname="mem_addr" />
+	<description>Load a single-precision (32-bit) floating-point element from memory into the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and set the upper elements of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MEM[mem_addr+31:mem_addr]
+ELSE
+	dst[31:0] := 0
+FI
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, m32" name="VMOVSS" xed="VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_loadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVUPD" xed="VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_loadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVUPD" xed="VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_loadu_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVUPD" xed="VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_loadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVUPS" xed="VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_loadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVUPS" xed="VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_loadu_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VMOVUPS" xed="VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expandloadu_epi32" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m32" name="VPEXPANDD" xed="VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expandloadu_epi32" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m32" name="VPEXPANDD" xed="VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expandloadu_epi64" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expandloadu_epi64" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32gather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, vm32y" name="VPGATHERDQ" xed="VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32gather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, vm32y" name="VPGATHERDQ" xed="VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i64gather_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, vm64z" name="VPGATHERQD" xed="VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i64gather_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, vm64z" name="VPGATHERQD" xed="VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i64gather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*64
+	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, vm64z" name="VPGATHERQQ" xed="VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i64gather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*64
+	IF k[j]
+		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, vm64z" name="VPGATHERQQ" xed="VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_kand_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := a[15:0] AND b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDW" xed="KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kandn_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise NOT of 16-bit masks "a" and then AND with "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := (NOT a[15:0]) AND b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDNW" xed="KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_knot_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<description>Compute the bitwise NOT of 16-bit mask "a", and store the result in "k".</description>
+	<operation>
+k[15:0] := NOT a[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k" name="KNOTW" xed="KNOTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kor_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise OR of 16-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := a[15:0] OR b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KORW" xed="KORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kxnor_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise XNOR of 16-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := NOT (a[15:0] XOR b[15:0])
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXNORW" xed="KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kxor_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise XOR of 16-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := a[15:0] XOR b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXORW" xed="KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kshiftli_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
+	<description>Shift the bits of 16-bit mask "a" left by "count" while shifting in zeros, and store the least significant 16 bits of the result in "k".</description>
+	<operation>
+k[MAX:0] := 0
+IF count[7:0] &lt;= 15
+	k[15:0] := a[15:0] &lt;&lt; count[7:0]
+FI
+	</operation>
+	<instruction form="k, k, imm8" name="KSHIFTLW" xed="KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kshiftri_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
+	<description>Shift the bits of 16-bit mask "a" right by "count" while shifting in zeros, and store the least significant 16 bits of the result in "k".</description>
+	<operation>
+k[MAX:0] := 0
+IF count[7:0] &lt;= 15
+	k[15:0] := a[15:0] &gt;&gt; count[7:0]
+FI
+	</operation>
+	<instruction form="k, k, imm8" name="KSHIFTRW" xed="KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortest_mask16_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="all_ones" />
+	<description>Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
+	<operation>
+tmp[15:0] := a[15:0] OR b[15:0]
+IF tmp[15:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+IF tmp[15:0] == 0xFFFF
+	MEM[all_ones+7:all_ones] := 1
+ELSE
+	MEM[all_ones+7:all_ones] := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortestz_mask16_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[15:0] := a[15:0] OR b[15:0]
+IF tmp[15:0] == 0x0
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_kortestc_mask16_u8" tech="AVX-512">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
+	<operation>
+tmp[15:0] := a[15:0] OR b[15:0]
+IF tmp[15:0] == 0xFFFF
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_cvtmask16_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<description>Convert 16-bit mask "a" into an integer value, and store the result in "dst".</description>
+	<operation>
+dst := ZeroExtend32(a[15:0])
+	</operation>
+	<instruction form="r32, k" name="KMOVW" xed="KMOVW_GPR32u32_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_cvtu32_mask16" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="unsigned int" varname="a" />
+	<description>Convert integer value "a" into an 16-bit mask, and store the result in "k".</description>
+	<operation>
+k := ZeroExtend16(a[15:0])
+	</operation>
+	<instruction form="k, r32" name="KMOVW" xed="KMOVW_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kandn" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise NOT of 16-bit masks "a" and then AND with "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := (NOT a[15:0]) AND b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDNW" xed="KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kand" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := a[15:0] AND b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KANDW" xed="KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kmov" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<description>Copy 16-bit mask "a" to "k".</description>
+	<operation>
+k[15:0] := a[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k" name="KMOVW" xed="KMOVW_MASKmskw_MASKu16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_knot" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<description>Compute the bitwise NOT of 16-bit mask "a", and store the result in "k".</description>
+	<operation>
+k[15:0] := NOT a[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k" name="KNOTW" xed="KNOTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kor" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise OR of 16-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := a[15:0] OR b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KORW" xed="KORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kunpackb" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Unpack and interleave 8 bits from masks "a" and "b", and store the 16-bit result in "k".</description>
+	<operation>
+k[7:0] := b[7:0]
+k[15:8] := a[7:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KUNPCKBW" xed="KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kxnor" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise XNOR of 16-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := NOT (a[15:0] XOR b[15:0])
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXNORW" xed="KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kxor" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="b" />
+	<description>Compute the bitwise XOR of 16-bit masks "a" and "b", and store the result in "k".</description>
+	<operation>
+k[15:0] := a[15:0] XOR b[15:0]
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, k, k" name="KXORW" xed="KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kortestz" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="MASK" type="__mmask16" varname="k2" />
+	<description>Performs bitwise OR between "k1" and "k2", storing the result in "dst". ZF flag is set if "dst" is 0.</description>
+	<operation>dst[15:0] := k1[15:0] | k2[15:0]
+IF dst == 0
+	SetZF()
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_kortestc" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="MASK" type="__mmask16" varname="k2" />
+	<description>Performs bitwise OR between "k1" and "k2", storing the result in "dst". CF flag is set if "dst" consists of all 1's.</description>
+	<operation>dst[15:0] := k1[15:0] | k2[15:0]
+IF PopCount(dst[15:0]) == 16
+	SetCF()
+FI
+	</operation>
+	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask2int" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<description>Converts bit mask "k1" into an integer value, storing the results in "dst".</description>
+	<operation>
+dst := ZeroExtend32(k1)
+	</operation>
+	<instruction form="r32, k" name="KMOVW" xed="KMOVW_GPR32u32_MASKmskw_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_int2mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="dst" />
+	<parameter etype="UI16" type="int" varname="mask" />
+	<description>Converts integer "mask" into bitmask, storing the result in "dst".</description>
+	<operation>
+dst := mask[15:0]
+	</operation>
+	<instruction form="k, r32" name="KMOVW" xed="KMOVW_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and stores the low 64 bytes (16 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+temp[1023:512] := a[511:0]
+temp[511:0] := b[511:0]
+temp[1023:0] := temp[1023:0] &gt;&gt; (32*imm8[3:0])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := temp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VALIGND" xed="VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 64 bytes (8 elements) in "dst".</description>
+	<operation>
+temp[1023:512] := a[511:0]
+temp[511:0] := b[511:0]
+temp[1023:0] := temp[1023:0] &gt;&gt; (64*imm8[2:0])
+dst[511:0] := temp[511:0]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VALIGNQ" xed="VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 64 bytes (8 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+temp[1023:512] := a[511:0]
+temp[511:0] := b[511:0]
+temp[1023:0] := temp[1023:0] &gt;&gt; (64*imm8[2:0])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := temp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VALIGNQ" xed="VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_alignr_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and stores the low 64 bytes (8 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+temp[1023:512] := a[511:0]
+temp[511:0] := b[511:0]
+temp[1023:0] := temp[1023:0] &gt;&gt; (64*imm8[2:0])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := temp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VALIGNQ" xed="VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fixupimm_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fixupimm_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fixupimm_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fixupimm_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fixupimm_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fixupimm_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fixupimm_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fixupimm_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fixupimm_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst", and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
+dst[127:64] := b[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fixupimm_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst", and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
+dst[127:64] := b[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fixupimm_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+IF k[0]
+	dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := b[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fixupimm_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+IF k[0]
+	dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := a[63:0]
+FI
+dst[127:64] := b[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fixupimm_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+IF k[0]
+	dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := b[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fixupimm_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
+	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
+	CASE(tsrc[63:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[63:0] := src1[63:0]
+	1 : dest[63:0] := tsrc[63:0]
+	2 : dest[63:0] := QNaN(tsrc[63:0])
+	3 : dest[63:0] := QNAN_Indefinite
+	4 : dest[63:0] := -INF
+	5 : dest[63:0] := +INF
+	6 : dest[63:0] := tsrc.sign? -INF : +INF
+	7 : dest[63:0] := -0
+	8 : dest[63:0] := +0
+	9 : dest[63:0] := -1
+	10: dest[63:0] := +1
+	11: dest[63:0] := 1/2
+	12: dest[63:0] := 90.0
+	13: dest[63:0] := PI/2
+	14: dest[63:0] := MAX_FLOAT
+	15: dest[63:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[63:0]
+}
+IF k[0]
+	dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := b[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fixupimm_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst", and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
+dst[127:32] := b[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fixupimm_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst", and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
+dst[127:32] := b[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fixupimm_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+IF k[0]
+	dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := b[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fixupimm_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+IF k[0]
+	dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := a[31:0]
+FI
+dst[127:32] := b[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fixupimm_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.
+	[sae_note]</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+IF k[0]
+	dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := b[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fixupimm_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.</description>
+	<operation>enum TOKEN_TYPE {
+	QNAN_TOKEN := 0, \
+	SNAN_TOKEN := 1, \
+	ZERO_VALUE_TOKEN := 2, \
+	ONE_VALUE_TOKEN := 3, \
+	NEG_INF_TOKEN := 4, \
+	POS_INF_TOKEN := 5, \
+	NEG_VALUE_TOKEN := 6, \
+	POS_VALUE_TOKEN := 7
+}
+DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
+	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
+	CASE(tsrc[31:0]) OF
+	QNAN_TOKEN:j := 0
+	SNAN_TOKEN:j := 1
+	ZERO_VALUE_TOKEN: j := 2
+	ONE_VALUE_TOKEN: j := 3
+	NEG_INF_TOKEN: j := 4
+	POS_INF_TOKEN: j := 5
+	NEG_VALUE_TOKEN: j := 6
+	POS_VALUE_TOKEN: j := 7
+	ESAC
+	
+	token_response[3:0] := src3[3+4*j:4*j]
+	
+	CASE(token_response[3:0]) OF
+	0 : dest[31:0] := src1[31:0]
+	1 : dest[31:0] := tsrc[31:0]
+	2 : dest[31:0] := QNaN(tsrc[31:0])
+	3 : dest[31:0] := QNAN_Indefinite
+	4 : dest[31:0] := -INF
+	5 : dest[31:0] := +INF
+	6 : dest[31:0] := tsrc.sign? -INF : +INF
+	7 : dest[31:0] := -0
+	8 : dest[31:0] := +0
+	9 : dest[31:0] := -1
+	10: dest[31:0] := +1
+	11: dest[31:0] := 1/2
+	12: dest[31:0] := 90.0
+	13: dest[31:0] := PI/2
+	14: dest[31:0] := MAX_FLOAT
+	15: dest[31:0] := -MAX_FLOAT
+	ESAC
+	
+	CASE(tsrc[31:0]) OF
+	ZERO_VALUE_TOKEN:
+		IF (imm8[0]) #ZE; FI
+	ZERO_VALUE_TOKEN:
+		IF (imm8[1]) #IE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[2]) #ZE; FI
+	ONE_VALUE_TOKEN:
+		IF (imm8[3]) #IE; FI
+	SNAN_TOKEN:
+		IF (imm8[4]) #IE; FI
+	NEG_INF_TOKEN:
+		IF (imm8[5]) #IE; FI
+	NEG_VALUE_TOKEN:
+		IF (imm8[6]) #IE; FI
+	POS_INF_TOKEN:
+		IF (imm8[7]) #IE; FI
+	ESAC
+	RETURN dest[31:0]
+}
+IF k[0]
+	dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := b[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getexp_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.
+	[sae_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getexp_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.
+	[sae_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
+	[sae_note]</description>
+	<operation>dst[63:0] := ConvertExpFP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>dst[63:0] := ConvertExpFP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
+	[sae_note]</description>
+	<operation>IF k[0]
+	dst[63:0] := ConvertExpFP64(b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>IF k[0]
+	dst[63:0] := ConvertExpFP64(b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
+	[sae_note]</description>
+	<operation>IF k[0]
+	dst[63:0] := ConvertExpFP64(b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>IF k[0]
+	dst[63:0] := ConvertExpFP64(b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
+	[sae_note]</description>
+	<operation>dst[31:0] := ConvertExpFP32(b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>dst[31:0] := ConvertExpFP32(b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
+	[sae_note]</description>
+	<operation>IF k[0]
+	dst[31:0] := ConvertExpFP32(b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>IF k[0]
+	dst[31:0] := ConvertExpFP32(b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
+	[sae_note]</description>
+	<operation>IF k[0]
+	dst[31:0] := ConvertExpFP32(b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>IF k[0]
+	dst[31:0] := ConvertExpFP32(b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getmant_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8 {sae}" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getmant_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8 {sae}" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>IF k[0]
+	dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>IF k[0]
+	dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>IF k[0]
+	dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>IF k[0]
+	dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>IF k[0]
+	dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>IF k[0]
+	dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>IF k[0]
+	dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>IF k[0]
+	dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPRORVD" xed="VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_roundscale_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8 {sae}" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_roundscale_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8 {sae}" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_roundscale_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_roundscale_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8 {sae}" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_roundscale_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8 {sae}" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_roundscale_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8 {sae}" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_roundscale_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_roundscale_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8 {sae}" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+IF k[0]
+	dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+IF k[0]
+	dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+IF k[0]
+	dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+IF k[0]
+	dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
+	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
+	IF IsInf(tmp[63:0])
+		tmp[63:0] := src1[63:0]
+	FI
+	RETURN tmp[63:0]
+}
+dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+IF k[0]
+	dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+IF k[0]
+	dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+IF k[0]
+	dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+IF k[0]
+	dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
+	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
+	IF IsInf(tmp[31:0])
+		tmp[31:0] := src1[31:0]
+	FI
+	RETURN tmp[31:0]
+}
+dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_scalef_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_scalef_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_scalef_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_scalef_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_scalef_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_scalef_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_scalef_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_scalef_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[31:0]
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+IF k[0]
+	dst[63:0] := SCALE(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+IF k[0]
+	dst[63:0] := SCALE(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+IF k[0]
+	dst[63:0] := SCALE(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+IF k[0]
+	dst[63:0] := SCALE(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+dst[63:0] := SCALE(a[63:0], b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
+	RETURN dst[63:0]
+}
+dst[63:0] := SCALE(a[63:0], b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[63:0]
+}
+IF k[0]
+	dst[31:0] := SCALE(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[63:0]
+}
+IF k[0]
+	dst[31:0] := SCALE(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[63:0]
+}
+IF k[0]
+	dst[31:0] := SCALE(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[63:0]
+}
+IF k[0]
+	dst[31:0] := SCALE(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[63:0]
+}
+dst[31:0] := SCALE(a[31:0], b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>DEFINE SCALE(src1, src2) {
+	IF (src2 == NaN)
+		IF (src2 == SNaN)
+			RETURN QNAN(src2)
+		FI
+	ELSE IF (src1 == NaN)
+		IF (src1 == SNaN)
+			RETURN QNAN(src1)
+		FI
+		IF (src2 != INF)
+			RETURN QNAN(src1)
+		FI
+	ELSE
+		tmp_src2 := src2
+		tmp_src1 := src1
+		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
+			tmp_src2 := 0
+		FI
+		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
+			tmp_src1 := 0
+		FI
+	FI
+	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
+	RETURN dst[63:0]
+}
+dst[31:0] := SCALE(a[31:0], b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 4)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 4)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 4)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_f64x4" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 4)*64
+	dst[i+63:i] := a[n+63:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m256" name="VBROADCASTF64X4" xed="VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_f64x4" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 4)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m256" name="VBROADCASTF64X4" xed="VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_f64x4" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 4)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m256" name="VBROADCASTF64X4" xed="VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 4)*32
+	dst[i+31:i] := a[n+31:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 4)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	n := (j % 4)*32
+	IF k[j]
+		dst[i+31:i] := a[n+31:n]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcast_i64x4" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 4)*64
+	dst[i+63:i] := a[n+63:n]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m256" name="VBROADCASTI64X4" xed="VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcast_i64x4" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 4)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m256" name="VBROADCASTI64X4" xed="VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcast_i64x4" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	n := (j % 4)*64
+	IF k[j]
+		dst[i+63:i] := a[n+63:n]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m256" name="VBROADCASTI64X4" xed="VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcastsd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcastsd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcastsd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcastss_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcastss_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcastss_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compress_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := src[511:m]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_compress_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := 0
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compress_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := src[511:m]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_compress_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := 0
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expand_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VEXPANDPD" xed="VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expand_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VEXPANDPD" xed="VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expand_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VEXPANDPS" xed="VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expand_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VEXPANDPS" xed="VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_extractf32x4_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[1:0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+2: dst[127:0] := a[383:256]
+3: dst[127:0] := a[511:384]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_extractf32x4_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[1:0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+2: tmp[127:0] := a[383:256]
+3: tmp[127:0] := a[511:384]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_extractf32x4_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[1:0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+2: tmp[127:0] := a[383:256]
+3: tmp[127:0] := a[511:384]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_extractf64x4_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[255:0] := a[255:0]
+1: dst[255:0] := a[511:256]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm, imm8" name="VEXTRACTF64X4" xed="VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_extractf64x4_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[255:0] := a[255:0]
+1: tmp[255:0] := a[511:256]
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm, imm8" name="VEXTRACTF64X4" xed="VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_extractf64x4_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[255:0] := a[255:0]
+1: tmp[255:0] := a[511:256]
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm, imm8" name="VEXTRACTF64X4" xed="VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_extracti32x4_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[1:0] OF
+0: dst[127:0] := a[127:0]
+1: dst[127:0] := a[255:128]
+2: dst[127:0] := a[383:256]
+3: dst[127:0] := a[511:384]
+ESAC
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_extracti32x4_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[1:0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+2: tmp[127:0] := a[383:256]
+3: tmp[127:0] := a[511:384]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_extracti32x4_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[1:0] OF
+0: tmp[127:0] := a[127:0]
+1: tmp[127:0] := a[255:128]
+2: tmp[127:0] := a[383:256]
+3: tmp[127:0] := a[511:384]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_extracti64x4_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+CASE imm8[0] OF
+0: dst[255:0] := a[255:0]
+1: dst[255:0] := a[511:256]
+ESAC
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm, imm8" name="VEXTRACTI64X4" xed="VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_extracti64x4_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[255:0] := a[255:0]
+1: tmp[255:0] := a[511:256]
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm, imm8" name="VEXTRACTI64X4" xed="VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_extracti64x4_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+CASE imm8[0] OF
+0: tmp[255:0] := a[255:0]
+1: tmp[255:0] := a[511:256]
+ESAC
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm, imm8" name="VEXTRACTI64X4" xed="VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_insertf32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+2: dst[383:256] := b[127:0]
+3: dst[511:384] := b[127:0]
+ESAC
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_insertf32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+2: tmp[383:256] := b[127:0]
+3: tmp[511:384] := b[127:0]
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_insertf32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+2: tmp[383:256] := b[127:0]
+3: tmp[511:384] := b[127:0]
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_insertf64x4" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: dst[255:0] := b[255:0]
+1: dst[511:256] := b[255:0]
+ESAC
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, ymm, imm8" name="VINSERTF64X4" xed="VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_insertf64x4" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: tmp[255:0] := b[255:0]
+1: tmp[511:256] := b[255:0]
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, ymm, imm8" name="VINSERTF64X4" xed="VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_insertf64x4" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: tmp[255:0] := b[255:0]
+1: tmp[511:256] := b[255:0]
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, ymm, imm8" name="VINSERTF64X4" xed="VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_inserti32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: dst[127:0] := b[127:0]
+1: dst[255:128] := b[127:0]
+2: dst[383:256] := b[127:0]
+3: dst[511:384] := b[127:0]
+ESAC
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_inserti32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+2: tmp[383:256] := b[127:0]
+3: tmp[511:384] := b[127:0]
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_inserti32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[1:0]) OF
+0: tmp[127:0] := b[127:0]
+1: tmp[255:128] := b[127:0]
+2: tmp[383:256] := b[127:0]
+3: tmp[511:384] := b[127:0]
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_inserti64x4" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: dst[255:0] := b[255:0]
+1: dst[511:256] := b[255:0]
+ESAC
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, ymm, imm8" name="VINSERTI64X4" xed="VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_inserti64x4" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: tmp[255:0] := b[255:0]
+1: tmp[511:256] := b[255:0]
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, ymm, imm8" name="VINSERTI64X4" xed="VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_inserti64x4" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[511:0] := a[511:0]
+CASE (imm8[0]) OF
+0: tmp[255:0] := b[255:0]
+1: tmp[511:256] := b[255:0]
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, ymm, imm8" name="VINSERTI64X4" xed="VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcastd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcastd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcastd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_broadcastq_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_broadcastq_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_broadcastq_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compress_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := src[511:m]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_compress_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 32
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[m+size-1:m] := a[i+31:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := 0
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compress_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := src[511:m]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_compress_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 64
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[m+size-1:m] := a[i+63:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := 0
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutexvar_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	id := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutexvar_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	id := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutexvar_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	id := idx[i+3:i]*32
+	dst[i+31:i] := a[id+31:id]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask2_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	off := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := idx[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2D" xed="VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	off := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2D" xed="VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	off := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := (idx[i+4]) ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2D" xed="VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2D" xed="VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex2var_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	off := idx[i+3:i]*32
+	dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMI2D" xed="VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VPERMT2D" xed="VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask2_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set)</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	off := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := idx[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2PD" xed="VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	off := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2PD" xed="VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	off := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := (idx[i+3]) ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2PD" xed="VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2PD" xed="VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex2var_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	off := idx[i+2:i]*64
+	dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMI2PD" xed="VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VPERMT2PD" xed="VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask2_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	off := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := idx[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2PS" xed="VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	off := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2PS" xed="VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	off := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := (idx[i+4]) ? b[off+31:off] : a[off+31:off]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2PS" xed="VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2PS" xed="VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex2var_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	off := idx[i+3:i]*32
+	dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMI2PS" xed="VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VPERMT2PS" xed="VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask2_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	off := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := idx[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2Q" xed="VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	off := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2Q" xed="VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	off := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := (idx[i+3]) ? b[off+63:off] : a[off+63:off]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2Q" xed="VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2Q" xed="VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex2var_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	off := idx[i+2:i]*64
+	dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMI2Q" xed="VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VPERMT2Q" xed="VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permute_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
+IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
+IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
+IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
+IF (imm8[4] == 0) tmp_dst[319:256] := a[319:256]; FI
+IF (imm8[4] == 1) tmp_dst[319:256] := a[383:320]; FI
+IF (imm8[5] == 0) tmp_dst[383:320] := a[319:256]; FI
+IF (imm8[5] == 1) tmp_dst[383:320] := a[383:320]; FI
+IF (imm8[6] == 0) tmp_dst[447:384] := a[447:384]; FI
+IF (imm8[6] == 1) tmp_dst[447:384] := a[511:448]; FI
+IF (imm8[7] == 0) tmp_dst[511:448] := a[447:384]; FI
+IF (imm8[7] == 1) tmp_dst[511:448] := a[511:448]; FI
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutevar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
+IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
+IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
+IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
+IF (b[257] == 0) tmp_dst[319:256] := a[319:256]; FI
+IF (b[257] == 1) tmp_dst[319:256] := a[383:320]; FI
+IF (b[321] == 0) tmp_dst[383:320] := a[319:256]; FI
+IF (b[321] == 1) tmp_dst[383:320] := a[383:320]; FI
+IF (b[385] == 0) tmp_dst[447:384] := a[447:384]; FI
+IF (b[385] == 1) tmp_dst[447:384] := a[511:448]; FI
+IF (b[449] == 0) tmp_dst[511:448] := a[447:384]; FI
+IF (b[449] == 1) tmp_dst[511:448] := a[511:448]; FI
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permute_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
+IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
+IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
+IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
+IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
+IF (imm8[4] == 0) tmp_dst[319:256] := a[319:256]; FI
+IF (imm8[4] == 1) tmp_dst[319:256] := a[383:320]; FI
+IF (imm8[5] == 0) tmp_dst[383:320] := a[319:256]; FI
+IF (imm8[5] == 1) tmp_dst[383:320] := a[383:320]; FI
+IF (imm8[6] == 0) tmp_dst[447:384] := a[447:384]; FI
+IF (imm8[6] == 1) tmp_dst[447:384] := a[511:448]; FI
+IF (imm8[7] == 0) tmp_dst[511:448] := a[447:384]; FI
+IF (imm8[7] == 1) tmp_dst[511:448] := a[511:448]; FI
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutevar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
+IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
+IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
+IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
+IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
+IF (b[257] == 0) tmp_dst[319:256] := a[319:256]; FI
+IF (b[257] == 1) tmp_dst[319:256] := a[383:320]; FI
+IF (b[321] == 0) tmp_dst[383:320] := a[319:256]; FI
+IF (b[321] == 1) tmp_dst[383:320] := a[383:320]; FI
+IF (b[385] == 0) tmp_dst[447:384] := a[447:384]; FI
+IF (b[385] == 1) tmp_dst[447:384] := a[511:448]; FI
+IF (b[449] == 0) tmp_dst[511:448] := a[447:384]; FI
+IF (b[449] == 1) tmp_dst[511:448] := a[511:448]; FI
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permute_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
+IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
+IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
+IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
+IF (imm8[2] == 0) dst[191:128] := a[191:128]; FI
+IF (imm8[2] == 1) dst[191:128] := a[255:192]; FI
+IF (imm8[3] == 0) dst[255:192] := a[191:128]; FI
+IF (imm8[3] == 1) dst[255:192] := a[255:192]; FI
+IF (imm8[4] == 0) dst[319:256] := a[319:256]; FI
+IF (imm8[4] == 1) dst[319:256] := a[383:320]; FI
+IF (imm8[5] == 0) dst[383:320] := a[319:256]; FI
+IF (imm8[5] == 1) dst[383:320] := a[383:320]; FI
+IF (imm8[6] == 0) dst[447:384] := a[447:384]; FI
+IF (imm8[6] == 1) dst[447:384] := a[511:448]; FI
+IF (imm8[7] == 0) dst[511:448] := a[447:384]; FI
+IF (imm8[7] == 1) dst[511:448] := a[511:448]; FI
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutevar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
+	<operation>
+IF (b[1] == 0) dst[63:0] := a[63:0]; FI
+IF (b[1] == 1) dst[63:0] := a[127:64]; FI
+IF (b[65] == 0) dst[127:64] := a[63:0]; FI
+IF (b[65] == 1) dst[127:64] := a[127:64]; FI
+IF (b[129] == 0) dst[191:128] := a[191:128]; FI
+IF (b[129] == 1) dst[191:128] := a[255:192]; FI
+IF (b[193] == 0) dst[255:192] := a[191:128]; FI
+IF (b[193] == 1) dst[255:192] := a[255:192]; FI
+IF (b[257] == 0) dst[319:256] := a[319:256]; FI
+IF (b[257] == 1) dst[319:256] := a[383:320]; FI
+IF (b[321] == 0) dst[383:320] := a[319:256]; FI
+IF (b[321] == 1) dst[383:320] := a[383:320]; FI
+IF (b[385] == 0) dst[447:384] := a[447:384]; FI
+IF (b[385] == 1) dst[447:384] := a[511:448]; FI
+IF (b[449] == 0) dst[511:448] := a[447:384]; FI
+IF (b[449] == 1) dst[511:448] := a[511:448]; FI
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permute_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4])
+tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6])
+tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4])
+tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutevar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
+tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
+tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
+tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
+tmp_dst[287:256] := SELECT4(a[383:256], b[257:256])
+tmp_dst[319:288] := SELECT4(a[383:256], b[289:288])
+tmp_dst[351:320] := SELECT4(a[383:256], b[321:320])
+tmp_dst[383:352] := SELECT4(a[383:256], b[353:352])
+tmp_dst[415:384] := SELECT4(a[511:384], b[385:384])
+tmp_dst[447:416] := SELECT4(a[511:384], b[417:416])
+tmp_dst[479:448] := SELECT4(a[511:384], b[449:448])
+tmp_dst[511:480] := SELECT4(a[511:384], b[481:480])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permute_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4])
+tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6])
+tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4])
+tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutevar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
+tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
+tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
+tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
+tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
+tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
+tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
+tmp_dst[287:256] := SELECT4(a[383:256], b[257:256])
+tmp_dst[319:288] := SELECT4(a[383:256], b[289:288])
+tmp_dst[351:320] := SELECT4(a[383:256], b[321:320])
+tmp_dst[383:352] := SELECT4(a[383:256], b[353:352])
+tmp_dst[415:384] := SELECT4(a[511:384], b[385:384])
+tmp_dst[447:416] := SELECT4(a[511:384], b[417:416])
+tmp_dst[479:448] := SELECT4(a[511:384], b[449:448])
+tmp_dst[511:480] := SELECT4(a[511:384], b[481:480])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permute_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+dst[351:320] := SELECT4(a[383:256], imm8[5:4])
+dst[383:352] := SELECT4(a[383:256], imm8[7:6])
+dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+dst[479:448] := SELECT4(a[511:384], imm8[5:4])
+dst[511:480] := SELECT4(a[511:384], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutevar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], b[1:0])
+dst[63:32] := SELECT4(a[127:0], b[33:32])
+dst[95:64] := SELECT4(a[127:0], b[65:64])
+dst[127:96] := SELECT4(a[127:0], b[97:96])
+dst[159:128] := SELECT4(a[255:128], b[129:128])
+dst[191:160] := SELECT4(a[255:128], b[161:160])
+dst[223:192] := SELECT4(a[255:128], b[193:192])
+dst[255:224] := SELECT4(a[255:128], b[225:224])
+dst[287:256] := SELECT4(a[383:256], b[257:256])
+dst[319:288] := SELECT4(a[383:256], b[289:288])
+dst[351:320] := SELECT4(a[383:256], b[321:320])
+dst[383:352] := SELECT4(a[383:256], b[353:352])
+dst[415:384] := SELECT4(a[511:384], b[385:384])
+dst[447:416] := SELECT4(a[511:384], b[417:416])
+dst[479:448] := SELECT4(a[511:384], b[449:448])
+dst[511:480] := SELECT4(a[511:384], b[481:480])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutex_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0])
+tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2])
+tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4])
+tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutexvar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	id := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := a[id+63:id]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutex_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0])
+tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2])
+tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4])
+tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutexvar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	id := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := a[id+63:id]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+dst[319:256] := SELECT4(a[511:256], imm8[1:0])
+dst[383:320] := SELECT4(a[511:256], imm8[3:2])
+dst[447:384] := SELECT4(a[511:256], imm8[5:4])
+dst[511:448] := SELECT4(a[511:256], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutexvar_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	id := idx[i+2:i]*64
+	dst[i+63:i] := a[id+63:id]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutexvar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	id := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMPS" xed="VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutexvar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	id := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMPS" xed="VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutexvar_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	id := idx[i+3:i]*32
+	dst[i+31:i] := a[id+31:id]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMPS" xed="VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutex_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0])
+tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2])
+tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4])
+tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutexvar_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	id := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := a[id+63:id]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutex_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0])
+tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2])
+tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4])
+tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutexvar_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	id := idx[i+2:i]*64
+	IF k[j]
+		dst[i+63:i] := a[id+63:id]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[63:0] := src[63:0]
+	1:	tmp[63:0] := src[127:64]
+	2:	tmp[63:0] := src[191:128]
+	3:	tmp[63:0] := src[255:192]
+	ESAC
+	RETURN tmp[63:0]
+}
+dst[63:0] := SELECT4(a[255:0], imm8[1:0])
+dst[127:64] := SELECT4(a[255:0], imm8[3:2])
+dst[191:128] := SELECT4(a[255:0], imm8[5:4])
+dst[255:192] := SELECT4(a[255:0], imm8[7:6])
+dst[319:256] := SELECT4(a[511:256], imm8[1:0])
+dst[383:320] := SELECT4(a[511:256], imm8[3:2])
+dst[447:384] := SELECT4(a[511:256], imm8[5:4])
+dst[511:448] := SELECT4(a[511:256], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutexvar_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="idx" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	id := idx[i+2:i]*64
+	dst[i+63:i] := a[id+63:id]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expand_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPEXPANDD" xed="VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expand_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[m+31:m]
+		m := m + 32
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPEXPANDD" xed="VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expand_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPEXPANDQ" xed="VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expand_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[m+63:m]
+		m := m + 64
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPEXPANDQ" xed="VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shuffle_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4])
+tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6])
+tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4])
+tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSHUFD" xed="VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpackhi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpackhi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpackhi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpackhi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpackhi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpackhi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpacklo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpacklo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpacklo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpacklo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpacklo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpacklo_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shuffle_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shuffle_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shuffle_f32x4" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shuffle_f64x2" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shuffle_f64x2" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shuffle_f64x2" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shuffle_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shuffle_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shuffle_i32x4" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shuffle_i64x2" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shuffle_i64x2" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shuffle_i64x2" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[127:0] := src[127:0]
+	1:	tmp[127:0] := src[255:128]
+	2:	tmp[127:0] := src[383:256]
+	3:	tmp[127:0] := src[511:384]
+	ESAC
+	RETURN tmp[127:0]
+}
+dst[127:0] := SELECT4(a[511:0], imm8[1:0])
+dst[255:128] := SELECT4(a[511:0], imm8[3:2])
+dst[383:256] := SELECT4(b[511:0], imm8[5:4])
+dst[511:384] := SELECT4(b[511:0], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shuffle_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+tmp_dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320]
+tmp_dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320]
+tmp_dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448]
+tmp_dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448]
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFPD" xed="VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shuffle_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+tmp_dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320]
+tmp_dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320]
+tmp_dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448]
+tmp_dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448]
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFPD" xed="VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shuffle_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
+dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
+dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320]
+dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320]
+dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448]
+dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFPD" xed="VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shuffle_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+tmp_dst[351:320] := SELECT4(b[383:256], imm8[5:4])
+tmp_dst[383:352] := SELECT4(b[383:256], imm8[7:6])
+tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+tmp_dst[479:448] := SELECT4(b[511:384], imm8[5:4])
+tmp_dst[511:480] := SELECT4(b[511:384], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFPS" xed="VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shuffle_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+tmp_dst[351:320] := SELECT4(b[383:256], imm8[5:4])
+tmp_dst[383:352] := SELECT4(b[383:256], imm8[7:6])
+tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+tmp_dst[479:448] := SELECT4(b[511:384], imm8[5:4])
+tmp_dst[511:480] := SELECT4(b[511:384], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFPS" xed="VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shuffle_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+dst[223:192] := SELECT4(b[255:128], imm8[5:4])
+dst[255:224] := SELECT4(b[255:128], imm8[7:6])
+dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+dst[351:320] := SELECT4(b[383:256], imm8[5:4])
+dst[383:352] := SELECT4(b[383:256], imm8[7:6])
+dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+dst[479:448] := SELECT4(b[511:384], imm8[5:4])
+dst[511:480] := SELECT4(b[511:384], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFPS" xed="VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpackhi_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VUNPCKHPD" xed="VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpackhi_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VUNPCKHPD" xed="VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpackhi_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VUNPCKHPD" xed="VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpackhi_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VUNPCKHPS" xed="VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpackhi_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VUNPCKHPS" xed="VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpackhi_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VUNPCKHPS" xed="VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpacklo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VUNPCKLPD" xed="VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpacklo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp_dst[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VUNPCKLPD" xed="VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpacklo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VUNPCKLPD" xed="VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_unpacklo_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VUNPCKLPS" xed="VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_unpacklo_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
+tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VUNPCKLPS" xed="VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_unpacklo_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
+dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
+dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VUNPCKLPS" xed="VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_round_sd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k". [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, xmm {sae}, imm8" name="VCMPSD" xed="VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_sd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VCMPSD" xed="VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_round_sd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+IF k1[0]
+	k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm {sae}, imm8" name="VCMPSD" xed="VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_sd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+IF k1[0]
+	k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPSD" xed="VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_round_ss_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k". [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, xmm {sae}, imm8" name="VCMPSS" xed="VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_ss_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VCMPSS" xed="VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_round_ss_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+IF k1[0]
+	k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm {sae}, imm8" name="VCMPSS" xed="VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_ss_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+IF k1[0]
+	k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPSS" xed="VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comi_round_sd" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1). [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+RETURN ( a[63:0] OP b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm {sae}" name="VCOMISD" xed="VCOMISD_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comi_round_ss" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1). [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+RETURN ( a[31:0] OP b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm {sae}" name="VCOMISS" xed="VCOMISS_XMMf32_XMMf32_AVX512" />
+	<instruction form="xmm, xmm {sae}" name="VUCOMISS" xed="VUCOMISS_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPEQQ" xed="VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpge_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpgt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPGTQ" xed="VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPEQQ" xed="VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpge_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpgt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPGTQ" xed="VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpge_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpgt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpge_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpgt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_epu64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTDQ2PD" xed="VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	IF k[j]
+		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+	ELSE
+		dst[m+63:m] := src[m+63:m]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTDQ2PD" xed="VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*64
+	IF k[j]
+		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+	ELSE
+		dst[m+63:m] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTDQ2PD" xed="VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {er}" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {er}" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {er}" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {er}" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {er}" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {er}" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {er}" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {er}" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {er}" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP16" type="__m256i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {sae}" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP16" type="__m256i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {sae}" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {sae}" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundps_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {sae}" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtps_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundps_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {sae}" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtps_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundps_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {sae}" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtps_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". [round2_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 32*j
+	dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". [round2_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 32*j
+	dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round2_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round2_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round2_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtps_ph" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round2_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 16*j
+	l := 32*j
+	IF k[j]
+		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsd_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_Int32(a[63:0])
+	</operation>
+	<instruction form="r32, xmm {er}" name="VCVTSD2SI" xed="VCVTSD2SI_GPR32i32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsd_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64(a[63:0])
+	</operation>
+	<instruction form="r64, xmm {er}" name="VCVTSD2SI" xed="VCVTSD2SI_GPR64i64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsd_si32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_Int32(a[63:0])
+	</operation>
+	<instruction form="r32, xmm {er}" name="VCVTSD2SI" xed="VCVTSD2SI_GPR32i32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsd_si64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64(a[63:0])
+	</operation>
+	<instruction form="r64, xmm {er}" name="VCVTSD2SI" xed="VCVTSD2SI_GPR64i64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_Int32(a[63:0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTSD2SI" xed="VCVTSD2SI_GPR32i32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64(a[63:0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTSD2SI" xed="VCVTSD2SI_GPR64i64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_FP32(b[63:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvt_roundsd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := Convert_FP64_To_FP32(b[63:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := Convert_FP64_To_FP32(b[63:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvt_roundsd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := Convert_FP64_To_FP32(b[63:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsd_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := Convert_FP64_To_FP32(b[63:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsd_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_UInt32(a[63:0])
+	</operation>
+	<instruction form="r32, xmm {er}" name="VCVTSD2USI" xed="VCVTSD2USI_GPR32u32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsd_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_UInt64(a[63:0])
+	</operation>
+	<instruction form="r64, xmm {er}" name="VCVTSD2USI" xed="VCVTSD2USI_GPR64u64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_UInt32(a[63:0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTSD2USI" xed="VCVTSD2USI_GPR32u32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_UInt64(a[63:0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTSD2USI" xed="VCVTSD2USI_GPR64u64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundi64_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_Int64_To_FP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SD" xed="VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsi64_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". 
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_Int64_To_FP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SD" xed="VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvti32_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<description>Convert the signed 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := Convert_Int32_To_FP64(b[31:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32" name="VCVTSI2SD" xed="VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvti64_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := Convert_Int64_To_FP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64" name="VCVTSI2SD" xed="VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundi32_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32 {er}" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundi64_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_Int64_To_FP32(b[63:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsi32_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32 {er}" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsi64_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_Int64_To_FP32(b[63:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvti32_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvti64_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<description>Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int64_To_FP32(b[63:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundss_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". 
+	[sae_note]</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_FP64(b[31:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvt_roundss_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[sae_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := Convert_FP32_To_FP64(b[31:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtss_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := Convert_FP32_To_FP64(b[31:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvt_roundss_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". 
+	[sae_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := Convert_FP32_To_FP64(b[31:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtss_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := Convert_FP32_To_FP64(b[31:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundss_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32(a[31:0])
+	</operation>
+	<instruction form="r32, xmm {er}" name="VCVTSS2SI" xed="VCVTSS2SI_GPR32i32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundss_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_Int64(a[31:0])
+	</operation>
+	<instruction form="r64, xmm {er}" name="VCVTSS2SI" xed="VCVTSS2SI_GPR64i64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundss_si32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32(a[31:0])
+	</operation>
+	<instruction form="r32, xmm {er}" name="VCVTSS2SI" xed="VCVTSS2SI_GPR32i32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundss_si64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_Int64(a[31:0])
+	</operation>
+	<instruction form="r64, xmm {er}" name="VCVTSS2SI" xed="VCVTSS2SI_GPR64i64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32(a[31:0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTSS2SI" xed="VCVTSS2SI_GPR32i32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_Int64(a[31:0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTSS2SI" xed="VCVTSS2SI_GPR64i64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundss_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_UInt32(a[31:0])
+	</operation>
+	<instruction form="r32, xmm {er}" name="VCVTSS2USI" xed="VCVTSS2USI_GPR32u32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundss_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_UInt64(a[31:0])
+	</operation>
+	<instruction form="r64, xmm {er}" name="VCVTSS2USI" xed="VCVTSS2USI_GPR64u64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_UInt32(a[31:0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTSS2USI" xed="VCVTSS2USI_GPR32u32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_UInt64(a[31:0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTSS2USI" xed="VCVTSS2USI_GPR64u64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".  [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {sae}" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {sae}" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {sae}" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttpd_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".  [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {sae}" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {sae}" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {sae}" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttpd_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 32*j
+	l := 64*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".  [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttps_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".  [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttps_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsd_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR32i32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsd_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
+	</operation>
+	<instruction form="r64, xmm {sae}" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR64i64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsd_si32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR32i32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsd_si64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
+	</operation>
+	<instruction form="r64, xmm {sae}" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR64i64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsd_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR32i32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsd_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR64i64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsd_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_UInt32_Truncate(a[63:0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTTSD2USI" xed="VCVTTSD2USI_GPR32u32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsd_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_UInt64_Truncate(a[63:0])
+	</operation>
+	<instruction form="r64, xmm {sae}" name="VCVTTSD2USI" xed="VCVTTSD2USI_GPR64u64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsd_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_UInt32_Truncate(a[63:0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTTSD2USI" xed="VCVTTSD2USI_GPR32u32_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsd_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_UInt64_Truncate(a[63:0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTTSD2USI" xed="VCVTTSD2USI_GPR64u64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundss_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR32i32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundss_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0])
+	</operation>
+	<instruction form="r64, xmm {sae}" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR64i64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundss_si32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR32i32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundss_si64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0])
+	</operation>
+	<instruction form="r64, xmm {sae}" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR64i64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttss_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR32i32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttss_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR64i64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundss_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_UInt32_Truncate(a[31:0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTTSS2USI" xed="VCVTTSS2USI_GPR32u32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundss_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".
+	[sae_note]</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_UInt64_Truncate(a[31:0])
+	</operation>
+	<instruction form="r64, xmm {sae}" name="VCVTTSS2USI" xed="VCVTTSS2USI_GPR64u64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttss_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_UInt32_Truncate(a[31:0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTTSS2USI" xed="VCVTTSS2USI_GPR32u32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttss_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_UInt64_Truncate(a[31:0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTTSS2USI" xed="VCVTTSS2USI_GPR64u64_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu32_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepu32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepu32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepu32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu32_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	IF k[j]
+		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundu64_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the unsigned 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". 
+	[round_note]</description>
+	<operation>
+dst[63:0] := Convert_Int64_To_FP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64 {er}" name="VCVTUSI2SD" xed="VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtu32_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<description>Convert the unsigned 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := Convert_Int32_To_FP64(b[31:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32" name="VCVTUSI2SD" xed="VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtu64_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<description>Convert the unsigned 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := Convert_Int64_To_FP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64" name="VCVTUSI2SD" xed="VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundu32_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the unsigned 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32 {er}" name="VCVTUSI2SS" xed="VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundu64_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the unsigned 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
+	[round_note]</description>
+	<operation>
+dst[31:0] := Convert_Int64_To_FP32(b[63:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64 {er}" name="VCVTUSI2SS" xed="VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtu32_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<description>Convert the unsigned 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32" name="VCVTUSI2SS" xed="VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtu64_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<description>Convert the unsigned 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int64_To_FP32(b[63:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64" name="VCVTUSI2SS" xed="VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := Truncate8(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, zmm" name="VPMOVDB" xed="VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := Truncate16(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVDW" xed="VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVDW" xed="VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVDW" xed="VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVDW" xed="VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := Truncate8(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, zmm" name="VPMOVQB" xed="VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Truncate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := Truncate32(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVQD" xed="VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Truncate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVQD" xed="VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI32" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVQD" xed="VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Truncate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVQD" xed="VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := Truncate16(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, zmm" name="VPMOVQW" xed="VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Truncate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := Saturate8(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, zmm" name="VPMOVSDB" xed="VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtsepi32_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := Saturate16(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVSDW" xed="VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVSDW" xed="VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI16" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVSDW" xed="VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtsepi32_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVSDW" xed="VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := Saturate8(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, zmm" name="VPMOVSQB" xed="VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtsepi64_epi8" tech="AVX-512">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := Saturate8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := Saturate32(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVSQD" xed="VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Saturate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVSQD" xed="VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI32" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVSQD" xed="VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtsepi64_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := Saturate32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVSQD" xed="VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := Saturate16(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtsepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="SI16" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, zmm" name="VPMOVSQW" xed="VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtsepi64_epi16" tech="AVX-512">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := Saturate16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi8_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 8*j
+	dst[i+31:i] := SignExtend32(a[k+7:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi8_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi8_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi8_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 8*j
+	dst[i+63:i] := SignExtend64(a[k+7:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi8_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi8_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi32_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := SignExtend64(a[k+31:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VPMOVSXDQ" xed="VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VPMOVSXDQ" xed="VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi32_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VPMOVSXDQ" xed="VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi16_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 16*j
+	dst[i+31:i] := SignExtend32(a[k+15:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VPMOVSXWD" xed="VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi16_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	l := j*16
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VPMOVSXWD" xed="VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi16_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := SignExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VPMOVSXWD" xed="VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi16_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 16*j
+	dst[i+63:i] := SignExtend64(a[k+15:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi16_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi16_epi64" tech="AVX-512">
+	<return etype="SI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := SignExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 8*j
+	dst[k+7:k] := SaturateU8(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi32_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, zmm" name="VPMOVUSDB" xed="VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtusepi32_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+31:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 16*j
+	dst[k+15:k] := SaturateU16(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVUSDW" xed="VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVUSDW" xed="VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi32_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVUSDW" xed="VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtusepi32_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+31:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVUSDW" xed="VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 8*j
+	dst[k+7:k] := SaturateU8(a[i+63:i])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := src[l+7:l]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi64_storeu_epi8" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m64 {k}, zmm" name="VPMOVUSQB" xed="VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtusepi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[l+7:l] := SaturateU8(a[i+63:i])
+	ELSE
+		dst[l+7:l] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 32*j
+	dst[k+31:k] := SaturateU32(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VPMOVUSQD" xed="VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := SaturateU32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VPMOVUSQD" xed="VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi64_storeu_epi32" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI32" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, zmm" name="VPMOVUSQD" xed="VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtusepi64_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[l+31:l] := SaturateU32(a[i+63:i])
+	ELSE
+		dst[l+31:l] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VPMOVUSQD" xed="VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 16*j
+	dst[k+15:k] := SaturateU16(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := src[l+15:l]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtusepi64_storeu_epi16" tech="AVX-512">
+	<category>Store</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, zmm" name="VPMOVUSQW" xed="VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtusepi64_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[l+15:l] := SaturateU16(a[i+63:i])
+	ELSE
+		dst[l+15:l] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 8*j
+	dst[i+31:i] := ZeroExtend32(a[k+7:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu8_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 8*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+7:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu8_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 8*j
+	dst[i+63:i] := ZeroExtend64(a[k+7:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu8_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu8_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 8*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+7:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu32_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := ZeroExtend64(a[k+31:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VPMOVZXDQ" xed="VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu32_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VPMOVZXDQ" xed="VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu32_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 32*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+31:l])
+	ELSE 
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VPMOVZXDQ" xed="VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu16_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	k := 16*j
+	dst[i+31:i] := ZeroExtend32(a[k+15:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VPMOVZXWD" xed="VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu16_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VPMOVZXWD" xed="VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu16_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := 32*j
+	l := 16*j
+	IF k[j]
+		dst[i+31:i] := ZeroExtend32(a[l+15:l])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VPMOVZXWD" xed="VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu16_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	k := 16*j
+	dst[i+63:i] := ZeroExtend64(a[k+15:k])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu16_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu16_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := 64*j
+	l := 16*j
+	IF k[j]
+		dst[i+63:i] := ZeroExtend64(a[l+15:l])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtss_f32" tech="AVX-512" vexEq="TRUE">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+	</operation>
+	<instruction form="m32, xmm" name="VMOVSS" xed="VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsd_f64" tech="AVX-512" vexEq="TRUE">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="m64, xmm" name="VMOVSD" xed="VMOVSD_MEMq_XMMq" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsi512_si32" tech="AVX-512" vexEq="TRUE">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+	</operation>
+	<instruction form="r32, xmm" name="VMOVD" xed="VMOVD_GPR32u32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".  [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {sae}" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".  [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {sae}" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note][max_float_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MAX(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MAX(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note][max_float_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MAX(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MAX(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [sae_note][max_float_note]</description>
+	<operation>
+dst[63:0] := MAX(a[63:0], b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MAX(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MAX(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MAX(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MAX(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
+	<operation>
+dst[31:0] := MAX(a[31:0], b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note][min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note][min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".  [sae_note][min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {sae}" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note][min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note][min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".  [sae_note][min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {sae}" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note][min_float_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MIN(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MIN(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note][min_float_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MIN(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := MIN(a[63:0], b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" , and copy the upper element from "a" to the upper element of "dst". [sae_note][min_float_note]</description>
+	<operation>
+dst[63:0] := MIN(a[63:0], b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MIN(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MIN(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MIN(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := MIN(a[31:0], b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
+	<operation>
+dst[31:0] := MIN(a[31:0], b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_abs_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ABS(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPABSD" xed="VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_abs_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ABS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPABSD" xed="VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_abs_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ABS(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPABSD" xed="VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ABS(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPABSQ" xed="VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ABS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPABSQ" xed="VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_abs_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ABS(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPABSQ" xed="VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0 
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMAXSD" xed="VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMAXSQ" xed="VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMAXSQ" xed="VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMAXSQ" xed="VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMAXUD" xed="VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMAXUQ" xed="VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMAXUQ" xed="VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMAXUQ" xed="VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMINSD" xed="VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMINSQ" xed="VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMINSQ" xed="VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="SI64" type="__m512i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMINSQ" xed="VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMINUD" xed="VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMINUQ" xed="VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMINUQ" xed="VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMINUQ" xed="VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mov_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mov_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_movedup_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[63:0] := a[63:0]
+tmp[127:64] := a[63:0]
+tmp[191:128] := a[191:128]
+tmp[255:192] := a[191:128]
+tmp[319:256] := a[319:256] 
+tmp[383:320] := a[319:256] 
+tmp[447:384] := a[447:384]
+tmp[511:448] := a[447:384]
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVDDUP" xed="VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_movedup_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[63:0] := a[63:0]
+tmp[127:64] := a[63:0]
+tmp[191:128] := a[191:128]
+tmp[255:192] := a[191:128]
+tmp[319:256] := a[319:256] 
+tmp[383:320] := a[319:256] 
+tmp[447:384] := a[447:384]
+tmp[511:448] := a[447:384]
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := tmp[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVDDUP" xed="VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movedup_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := a[63:0]
+dst[191:128] := a[191:128]
+dst[255:192] := a[191:128]
+dst[319:256] := a[319:256]
+dst[383:320] := a[319:256]
+dst[447:384] := a[447:384]
+dst[511:448] := a[447:384]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VMOVDDUP" xed="VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mov_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mov_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_move_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := b[63:0]
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMOVSD" xed="VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_move_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := b[63:0]
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMOVSD" xed="VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_movehdup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[63:32] 
+tmp[63:32] := a[63:32] 
+tmp[95:64] := a[127:96] 
+tmp[127:96] := a[127:96]
+tmp[159:128] := a[191:160] 
+tmp[191:160] := a[191:160] 
+tmp[223:192] := a[255:224] 
+tmp[255:224] := a[255:224]
+tmp[287:256] := a[319:288] 
+tmp[319:288] := a[319:288] 
+tmp[351:320] := a[383:352] 
+tmp[383:352] := a[383:352] 
+tmp[415:384] := a[447:416] 
+tmp[447:416] := a[447:416] 
+tmp[479:448] := a[511:480]
+tmp[511:480] := a[511:480]
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVSHDUP" xed="VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_movehdup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[63:32] 
+tmp[63:32] := a[63:32] 
+tmp[95:64] := a[127:96] 
+tmp[127:96] := a[127:96]
+tmp[159:128] := a[191:160] 
+tmp[191:160] := a[191:160] 
+tmp[223:192] := a[255:224] 
+tmp[255:224] := a[255:224]
+tmp[287:256] := a[319:288] 
+tmp[319:288] := a[319:288] 
+tmp[351:320] := a[383:352] 
+tmp[383:352] := a[383:352] 
+tmp[415:384] := a[447:416] 
+tmp[447:416] := a[447:416] 
+tmp[479:448] := a[511:480]
+tmp[511:480] := a[511:480]
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVSHDUP" xed="VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_movehdup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32] 
+dst[63:32] := a[63:32] 
+dst[95:64] := a[127:96] 
+dst[127:96] := a[127:96]
+dst[159:128] := a[191:160] 
+dst[191:160] := a[191:160] 
+dst[223:192] := a[255:224] 
+dst[255:224] := a[255:224]
+dst[287:256] := a[319:288] 
+dst[319:288] := a[319:288] 
+dst[351:320] := a[383:352] 
+dst[383:352] := a[383:352] 
+dst[415:384] := a[447:416] 
+dst[447:416] := a[447:416] 
+dst[479:448] := a[511:480]
+dst[511:480] := a[511:480]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VMOVSHDUP" xed="VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_moveldup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[31:0] 
+tmp[63:32] := a[31:0] 
+tmp[95:64] := a[95:64] 
+tmp[127:96] := a[95:64]
+tmp[159:128] := a[159:128] 
+tmp[191:160] := a[159:128] 
+tmp[223:192] := a[223:192] 
+tmp[255:224] := a[223:192]
+tmp[287:256] := a[287:256] 
+tmp[319:288] := a[287:256] 
+tmp[351:320] := a[351:320] 
+tmp[383:352] := a[351:320] 
+tmp[415:384] := a[415:384] 
+tmp[447:416] := a[415:384] 
+tmp[479:448] := a[479:448]
+tmp[511:480] := a[479:448]
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVSLDUP" xed="VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_moveldup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+tmp[31:0] := a[31:0] 
+tmp[63:32] := a[31:0] 
+tmp[95:64] := a[95:64] 
+tmp[127:96] := a[95:64]
+tmp[159:128] := a[159:128] 
+tmp[191:160] := a[159:128] 
+tmp[223:192] := a[223:192] 
+tmp[255:224] := a[223:192]
+tmp[287:256] := a[287:256] 
+tmp[319:288] := a[287:256] 
+tmp[351:320] := a[351:320] 
+tmp[383:352] := a[351:320] 
+tmp[415:384] := a[415:384] 
+tmp[447:416] := a[415:384] 
+tmp[479:448] := a[479:448]
+tmp[511:480] := a[479:448]
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VMOVSLDUP" xed="VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_moveldup_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] 
+dst[63:32] := a[31:0] 
+dst[95:64] := a[95:64] 
+dst[127:96] := a[95:64]
+dst[159:128] := a[159:128] 
+dst[191:160] := a[159:128] 
+dst[223:192] := a[223:192] 
+dst[255:224] := a[223:192]
+dst[287:256] := a[287:256] 
+dst[319:288] := a[287:256] 
+dst[351:320] := a[351:320] 
+dst[383:352] := a[351:320] 
+dst[415:384] := a[415:384] 
+dst[447:416] := a[415:384] 
+dst[479:448] := a[479:448]
+dst[511:480] := a[479:448]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VMOVSLDUP" xed="VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_move_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := b[31:0]
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMOVSS" xed="VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_move_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := b[31:0]
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMOVSS" xed="VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_and_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_andnot_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPANDND" xed="VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_andnot_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPANDNQ" xed="VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_and_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPORD" xed="VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPORQ" xed="VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		FOR h := 0 to 31
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		FOR h := 0 to 31
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_ternarylogic_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 15
+	i := j*32
+	FOR h := 0 to 31
+		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		FOR h := 0 to 63
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		FOR h := 0 to 63
+			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+		ENDFOR
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_ternarylogic_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
+	<operation>
+DEFINE TernaryOP(imm8, a, b, c) {
+	CASE imm8[7:0] OF
+	0: dst[0] := 0                   // imm8[7:0] := 0
+	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
+	// ...
+	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
+	255: dst[0] := 1                 // imm8[7:0] := 1
+	ESAC
+}
+imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
+FOR j := 0 to 7
+	i := j*64
+	FOR h := 0 to 63
+		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_test_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_test_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_testn_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_testn_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_testn_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_testn_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPXORD" xed="VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set1_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := a[7:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, r8" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_set1_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_set1_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[31:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set1_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, r32" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_set1_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_set1_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[63:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set1_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set1_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast the low packed 16-bit integer from "a" to all all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := a[15:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, r16" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set1_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="a" />
+	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set1_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set4_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="d" />
+	<parameter etype="UI32" type="int" varname="c" />
+	<parameter etype="UI32" type="int" varname="b" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Set packed 32-bit integers in "dst" with the repeated 4 element sequence.</description>
+	<operation>
+dst[31:0] := a
+dst[63:32] := b
+dst[95:64] := c
+dst[127:96] := d
+dst[159:128] := a
+dst[191:160] := b
+dst[223:192] := c
+dst[255:224] := d
+dst[287:256] := a
+dst[319:288] := b
+dst[351:320] := c
+dst[383:352] := d
+dst[415:384] := a
+dst[447:416] := b
+dst[479:448] := c
+dst[511:480] := d
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set4_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="d" />
+	<parameter etype="UI64" type="__int64" varname="c" />
+	<parameter etype="UI64" type="__int64" varname="b" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Set packed 64-bit integers in "dst" with the repeated 4 element sequence.</description>
+	<operation>
+dst[63:0] := a
+dst[127:64] := b
+dst[191:128] := c
+dst[255:192] := d
+dst[319:256] := a
+dst[383:320] := b
+dst[447:384] := c
+dst[511:448] := d
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set4_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="d" />
+	<parameter etype="FP64" type="double" varname="c" />
+	<parameter etype="FP64" type="double" varname="b" />
+	<parameter etype="FP64" type="double" varname="a" />
+	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the repeated 4 element sequence.</description>
+	<operation>
+dst[63:0] := a
+dst[127:64] := b
+dst[191:128] := c
+dst[255:192] := d
+dst[319:256] := a
+dst[383:320] := b
+dst[447:384] := c
+dst[511:448] := d
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set4_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="float" varname="d" />
+	<parameter etype="FP32" type="float" varname="c" />
+	<parameter etype="FP32" type="float" varname="b" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the repeated 4 element sequence.</description>
+	<operation>
+dst[31:0] := a
+dst[63:32] := b
+dst[95:64] := c
+dst[127:96] := d
+dst[159:128] := a
+dst[191:160] := b
+dst[223:192] := c
+dst[255:224] := d
+dst[287:256] := a
+dst[319:288] := b
+dst[351:320] := c
+dst[383:352] := d
+dst[415:384] := a
+dst[447:416] := b
+dst[479:448] := c
+dst[511:480] := d
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set_epi8" sequence="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="char" varname="e63" />
+	<parameter etype="UI8" type="char" varname="e62" />
+	<parameter etype="UI8" type="char" varname="e61" />
+	<parameter etype="UI8" type="char" varname="e60" />
+	<parameter etype="UI8" type="char" varname="e59" />
+	<parameter etype="UI8" type="char" varname="e58" />
+	<parameter etype="UI8" type="char" varname="e57" />
+	<parameter etype="UI8" type="char" varname="e56" />
+	<parameter etype="UI8" type="char" varname="e55" />
+	<parameter etype="UI8" type="char" varname="e54" />
+	<parameter etype="UI8" type="char" varname="e53" />
+	<parameter etype="UI8" type="char" varname="e52" />
+	<parameter etype="UI8" type="char" varname="e51" />
+	<parameter etype="UI8" type="char" varname="e50" />
+	<parameter etype="UI8" type="char" varname="e49" />
+	<parameter etype="UI8" type="char" varname="e48" />
+	<parameter etype="UI8" type="char" varname="e47" />
+	<parameter etype="UI8" type="char" varname="e46" />
+	<parameter etype="UI8" type="char" varname="e45" />
+	<parameter etype="UI8" type="char" varname="e44" />
+	<parameter etype="UI8" type="char" varname="e43" />
+	<parameter etype="UI8" type="char" varname="e42" />
+	<parameter etype="UI8" type="char" varname="e41" />
+	<parameter etype="UI8" type="char" varname="e40" />
+	<parameter etype="UI8" type="char" varname="e39" />
+	<parameter etype="UI8" type="char" varname="e38" />
+	<parameter etype="UI8" type="char" varname="e37" />
+	<parameter etype="UI8" type="char" varname="e36" />
+	<parameter etype="UI8" type="char" varname="e35" />
+	<parameter etype="UI8" type="char" varname="e34" />
+	<parameter etype="UI8" type="char" varname="e33" />
+	<parameter etype="UI8" type="char" varname="e32" />
+	<parameter etype="UI8" type="char" varname="e31" />
+	<parameter etype="UI8" type="char" varname="e30" />
+	<parameter etype="UI8" type="char" varname="e29" />
+	<parameter etype="UI8" type="char" varname="e28" />
+	<parameter etype="UI8" type="char" varname="e27" />
+	<parameter etype="UI8" type="char" varname="e26" />
+	<parameter etype="UI8" type="char" varname="e25" />
+	<parameter etype="UI8" type="char" varname="e24" />
+	<parameter etype="UI8" type="char" varname="e23" />
+	<parameter etype="UI8" type="char" varname="e22" />
+	<parameter etype="UI8" type="char" varname="e21" />
+	<parameter etype="UI8" type="char" varname="e20" />
+	<parameter etype="UI8" type="char" varname="e19" />
+	<parameter etype="UI8" type="char" varname="e18" />
+	<parameter etype="UI8" type="char" varname="e17" />
+	<parameter etype="UI8" type="char" varname="e16" />
+	<parameter etype="UI8" type="char" varname="e15" />
+	<parameter etype="UI8" type="char" varname="e14" />
+	<parameter etype="UI8" type="char" varname="e13" />
+	<parameter etype="UI8" type="char" varname="e12" />
+	<parameter etype="UI8" type="char" varname="e11" />
+	<parameter etype="UI8" type="char" varname="e10" />
+	<parameter etype="UI8" type="char" varname="e9" />
+	<parameter etype="UI8" type="char" varname="e8" />
+	<parameter etype="UI8" type="char" varname="e7" />
+	<parameter etype="UI8" type="char" varname="e6" />
+	<parameter etype="UI8" type="char" varname="e5" />
+	<parameter etype="UI8" type="char" varname="e4" />
+	<parameter etype="UI8" type="char" varname="e3" />
+	<parameter etype="UI8" type="char" varname="e2" />
+	<parameter etype="UI8" type="char" varname="e1" />
+	<parameter etype="UI8" type="char" varname="e0" />
+	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[7:0] := e0
+dst[15:8] := e1
+dst[23:16] := e2
+dst[31:24] := e3
+dst[39:32] := e4
+dst[47:40] := e5
+dst[55:48] := e6
+dst[63:56] := e7
+dst[71:64] := e8
+dst[79:72] := e9
+dst[87:80] := e10
+dst[95:88] := e11
+dst[103:96] := e12
+dst[111:104] := e13
+dst[119:112] := e14
+dst[127:120] := e15
+dst[135:128] := e16
+dst[143:136] := e17
+dst[151:144] := e18
+dst[159:152] := e19
+dst[167:160] := e20
+dst[175:168] := e21
+dst[183:176] := e22
+dst[191:184] := e23
+dst[199:192] := e24
+dst[207:200] := e25
+dst[215:208] := e26
+dst[223:216] := e27
+dst[231:224] := e28
+dst[239:232] := e29
+dst[247:240] := e30
+dst[255:248] := e31
+dst[263:256] := e32
+dst[271:264] := e33
+dst[279:272] := e34
+dst[287:280] := e35
+dst[295:288] := e36
+dst[303:296] := e37
+dst[311:304] := e38
+dst[319:312] := e39
+dst[327:320] := e40
+dst[335:328] := e41
+dst[343:336] := e42
+dst[351:344] := e43
+dst[359:352] := e44
+dst[367:360] := e45
+dst[375:368] := e46
+dst[383:376] := e47
+dst[391:384] := e48
+dst[399:392] := e49
+dst[407:400] := e50
+dst[415:408] := e51
+dst[423:416] := e52
+dst[431:424] := e53
+dst[439:432] := e54
+dst[447:440] := e55
+dst[455:448] := e56
+dst[463:456] := e57
+dst[471:464] := e58
+dst[479:472] := e59
+dst[487:480] := e60
+dst[495:488] := e61
+dst[503:496] := e62
+dst[511:504] := e63
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set_epi16" sequence="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="e31" />
+	<parameter etype="UI16" type="short" varname="e30" />
+	<parameter etype="UI16" type="short" varname="e29" />
+	<parameter etype="UI16" type="short" varname="e28" />
+	<parameter etype="UI16" type="short" varname="e27" />
+	<parameter etype="UI16" type="short" varname="e26" />
+	<parameter etype="UI16" type="short" varname="e25" />
+	<parameter etype="UI16" type="short" varname="e24" />
+	<parameter etype="UI16" type="short" varname="e23" />
+	<parameter etype="UI16" type="short" varname="e22" />
+	<parameter etype="UI16" type="short" varname="e21" />
+	<parameter etype="UI16" type="short" varname="e20" />
+	<parameter etype="UI16" type="short" varname="e19" />
+	<parameter etype="UI16" type="short" varname="e18" />
+	<parameter etype="UI16" type="short" varname="e17" />
+	<parameter etype="UI16" type="short" varname="e16" />
+	<parameter etype="UI16" type="short" varname="e15" />
+	<parameter etype="UI16" type="short" varname="e14" />
+	<parameter etype="UI16" type="short" varname="e13" />
+	<parameter etype="UI16" type="short" varname="e12" />
+	<parameter etype="UI16" type="short" varname="e11" />
+	<parameter etype="UI16" type="short" varname="e10" />
+	<parameter etype="UI16" type="short" varname="e9" />
+	<parameter etype="UI16" type="short" varname="e8" />
+	<parameter etype="UI16" type="short" varname="e7" />
+	<parameter etype="UI16" type="short" varname="e6" />
+	<parameter etype="UI16" type="short" varname="e5" />
+	<parameter etype="UI16" type="short" varname="e4" />
+	<parameter etype="UI16" type="short" varname="e3" />
+	<parameter etype="UI16" type="short" varname="e2" />
+	<parameter etype="UI16" type="short" varname="e1" />
+	<parameter etype="UI16" type="short" varname="e0" />
+	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[15:0] := e0
+dst[31:16] := e1
+dst[47:32] := e2
+dst[63:48] := e3
+dst[79:64] := e4
+dst[95:80] := e5
+dst[111:96] := e6
+dst[127:112] := e7
+dst[143:128] := e8
+dst[159:144] := e9
+dst[175:160] := e10
+dst[191:176] := e11
+dst[207:192] := e12
+dst[223:208] := e13
+dst[239:224] := e14
+dst[255:240] := e15
+dst[271:256] := e16
+dst[287:272] := e17
+dst[303:288] := e18
+dst[319:304] := e19
+dst[335:320] := e20
+dst[351:336] := e21
+dst[367:352] := e22
+dst[383:368] := e23
+dst[399:384] := e24
+dst[415:400] := e25
+dst[431:416] := e26
+dst[447:432] := e27
+dst[463:448] := e28
+dst[479:464] := e29
+dst[495:480] := e30
+dst[511:496] := e31
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="e15" />
+	<parameter etype="UI32" type="int" varname="e14" />
+	<parameter etype="UI32" type="int" varname="e13" />
+	<parameter etype="UI32" type="int" varname="e12" />
+	<parameter etype="UI32" type="int" varname="e11" />
+	<parameter etype="UI32" type="int" varname="e10" />
+	<parameter etype="UI32" type="int" varname="e9" />
+	<parameter etype="UI32" type="int" varname="e8" />
+	<parameter etype="UI32" type="int" varname="e7" />
+	<parameter etype="UI32" type="int" varname="e6" />
+	<parameter etype="UI32" type="int" varname="e5" />
+	<parameter etype="UI32" type="int" varname="e4" />
+	<parameter etype="UI32" type="int" varname="e3" />
+	<parameter etype="UI32" type="int" varname="e2" />
+	<parameter etype="UI32" type="int" varname="e1" />
+	<parameter etype="UI32" type="int" varname="e0" />
+	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[31:0] := e0
+dst[63:32] := e1
+dst[95:64] := e2
+dst[127:96] := e3
+dst[159:128] := e4
+dst[191:160] := e5
+dst[223:192] := e6
+dst[255:224] := e7
+dst[287:256] := e8
+dst[319:288] := e9
+dst[351:320] := e10
+dst[383:352] := e11
+dst[415:384] := e12
+dst[447:416] := e13
+dst[479:448] := e14
+dst[511:480] := e15
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="e7" />
+	<parameter etype="UI64" type="__int64" varname="e6" />
+	<parameter etype="UI64" type="__int64" varname="e5" />
+	<parameter etype="UI64" type="__int64" varname="e4" />
+	<parameter etype="UI64" type="__int64" varname="e3" />
+	<parameter etype="UI64" type="__int64" varname="e2" />
+	<parameter etype="UI64" type="__int64" varname="e1" />
+	<parameter etype="UI64" type="__int64" varname="e0" />
+	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[63:0] := e0
+dst[127:64] := e1
+dst[191:128] := e2
+dst[255:192] := e3
+dst[319:256] := e4
+dst[383:320] := e5
+dst[447:384] := e6
+dst[511:448] := e7
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="e7" />
+	<parameter etype="FP64" type="double" varname="e6" />
+	<parameter etype="FP64" type="double" varname="e5" />
+	<parameter etype="FP64" type="double" varname="e4" />
+	<parameter etype="FP64" type="double" varname="e3" />
+	<parameter etype="FP64" type="double" varname="e2" />
+	<parameter etype="FP64" type="double" varname="e1" />
+	<parameter etype="FP64" type="double" varname="e0" />
+	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst[63:0] := e0
+dst[127:64] := e1
+dst[191:128] := e2
+dst[255:192] := e3
+dst[319:256] := e4
+dst[383:320] := e5
+dst[447:384] := e6
+dst[511:448] := e7
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="float" varname="e15" />
+	<parameter etype="FP32" type="float" varname="e14" />
+	<parameter etype="FP32" type="float" varname="e13" />
+	<parameter etype="FP32" type="float" varname="e12" />
+	<parameter etype="FP32" type="float" varname="e11" />
+	<parameter etype="FP32" type="float" varname="e10" />
+	<parameter etype="FP32" type="float" varname="e9" />
+	<parameter etype="FP32" type="float" varname="e8" />
+	<parameter etype="FP32" type="float" varname="e7" />
+	<parameter etype="FP32" type="float" varname="e6" />
+	<parameter etype="FP32" type="float" varname="e5" />
+	<parameter etype="FP32" type="float" varname="e4" />
+	<parameter etype="FP32" type="float" varname="e3" />
+	<parameter etype="FP32" type="float" varname="e2" />
+	<parameter etype="FP32" type="float" varname="e1" />
+	<parameter etype="FP32" type="float" varname="e0" />
+	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst[31:0] := e0
+dst[63:32] := e1
+dst[95:64] := e2
+dst[127:96] := e3
+dst[159:128] := e4
+dst[191:160] := e5
+dst[223:192] := e6
+dst[255:224] := e7
+dst[287:256] := e8
+dst[319:288] := e9
+dst[351:320] := e10
+dst[383:352] := e11
+dst[415:384] := e12
+dst[447:416] := e13
+dst[479:448] := e14
+dst[511:480] := e15
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr4_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="d" />
+	<parameter etype="UI32" type="int" varname="c" />
+	<parameter etype="UI32" type="int" varname="b" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Set packed 32-bit integers in "dst" with the repeated 4 element sequence in reverse order.</description>
+	<operation>
+dst[31:0] := d
+dst[63:32] := c
+dst[95:64] := b
+dst[127:96] := a
+dst[159:128] := d
+dst[191:160] := c
+dst[223:192] := b
+dst[255:224] := a
+dst[287:256] := d
+dst[319:288] := c
+dst[351:320] := b
+dst[383:352] := a
+dst[415:384] := d
+dst[447:416] := c
+dst[479:448] := b
+dst[511:480] := a
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr4_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="d" />
+	<parameter etype="UI64" type="__int64" varname="c" />
+	<parameter etype="UI64" type="__int64" varname="b" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Set packed 64-bit integers in "dst" with the repeated 4 element sequence in reverse order.</description>
+	<operation>
+dst[63:0] := d
+dst[127:64] := c
+dst[191:128] := b
+dst[255:192] := a
+dst[319:256] := d
+dst[383:320] := c
+dst[447:384] := b
+dst[511:448] := a
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr4_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="d" />
+	<parameter etype="FP64" type="double" varname="c" />
+	<parameter etype="FP64" type="double" varname="b" />
+	<parameter etype="FP64" type="double" varname="a" />
+	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the repeated 4 element sequence in reverse order.</description>
+	<operation>
+dst[63:0] := d
+dst[127:64] := c
+dst[191:128] := b
+dst[255:192] := a
+dst[319:256] := d
+dst[383:320] := c
+dst[447:384] := b
+dst[511:448] := a
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr4_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="float" varname="d" />
+	<parameter etype="FP32" type="float" varname="c" />
+	<parameter etype="FP32" type="float" varname="b" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the repeated 4 element sequence in reverse order.</description>
+	<operation>
+dst[31:0] := d
+dst[63:32] := c
+dst[95:64] := b
+dst[127:96] := a
+dst[159:128] := d
+dst[191:160] := c
+dst[223:192] := b
+dst[255:224] := a
+dst[287:256] := d
+dst[319:288] := c
+dst[351:320] := b
+dst[383:352] := a
+dst[415:384] := d
+dst[447:416] := c
+dst[479:448] := b
+dst[511:480] := a
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="e15" />
+	<parameter etype="UI32" type="int" varname="e14" />
+	<parameter etype="UI32" type="int" varname="e13" />
+	<parameter etype="UI32" type="int" varname="e12" />
+	<parameter etype="UI32" type="int" varname="e11" />
+	<parameter etype="UI32" type="int" varname="e10" />
+	<parameter etype="UI32" type="int" varname="e9" />
+	<parameter etype="UI32" type="int" varname="e8" />
+	<parameter etype="UI32" type="int" varname="e7" />
+	<parameter etype="UI32" type="int" varname="e6" />
+	<parameter etype="UI32" type="int" varname="e5" />
+	<parameter etype="UI32" type="int" varname="e4" />
+	<parameter etype="UI32" type="int" varname="e3" />
+	<parameter etype="UI32" type="int" varname="e2" />
+	<parameter etype="UI32" type="int" varname="e1" />
+	<parameter etype="UI32" type="int" varname="e0" />
+	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[31:0] := e15
+dst[63:32] := e14
+dst[95:64] := e13
+dst[127:96] := e12
+dst[159:128] := e11
+dst[191:160] := e10
+dst[223:192] := e9
+dst[255:224] := e8
+dst[287:256] := e7
+dst[319:288] := e6
+dst[351:320] := e5
+dst[383:352] := e4
+dst[415:384] := e3
+dst[447:416] := e2
+dst[479:448] := e1
+dst[511:480] := e0
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="e7" />
+	<parameter etype="UI64" type="__int64" varname="e6" />
+	<parameter etype="UI64" type="__int64" varname="e5" />
+	<parameter etype="UI64" type="__int64" varname="e4" />
+	<parameter etype="UI64" type="__int64" varname="e3" />
+	<parameter etype="UI64" type="__int64" varname="e2" />
+	<parameter etype="UI64" type="__int64" varname="e1" />
+	<parameter etype="UI64" type="__int64" varname="e0" />
+	<description>Set packed 64-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[63:0] := e7
+dst[127:64] := e6
+dst[191:128] := e5
+dst[255:192] := e4
+dst[319:256] := e3
+dst[383:320] := e2
+dst[447:384] := e1
+dst[511:448] := e0
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="e7" />
+	<parameter etype="FP64" type="double" varname="e6" />
+	<parameter etype="FP64" type="double" varname="e5" />
+	<parameter etype="FP64" type="double" varname="e4" />
+	<parameter etype="FP64" type="double" varname="e3" />
+	<parameter etype="FP64" type="double" varname="e2" />
+	<parameter etype="FP64" type="double" varname="e1" />
+	<parameter etype="FP64" type="double" varname="e0" />
+	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[63:0] := e7
+dst[127:64] := e6
+dst[191:128] := e5
+dst[255:192] := e4
+dst[319:256] := e3
+dst[383:320] := e2
+dst[447:384] := e1
+dst[511:448] := e0
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="float" varname="e15" />
+	<parameter etype="FP32" type="float" varname="e14" />
+	<parameter etype="FP32" type="float" varname="e13" />
+	<parameter etype="FP32" type="float" varname="e12" />
+	<parameter etype="FP32" type="float" varname="e11" />
+	<parameter etype="FP32" type="float" varname="e10" />
+	<parameter etype="FP32" type="float" varname="e9" />
+	<parameter etype="FP32" type="float" varname="e8" />
+	<parameter etype="FP32" type="float" varname="e7" />
+	<parameter etype="FP32" type="float" varname="e6" />
+	<parameter etype="FP32" type="float" varname="e5" />
+	<parameter etype="FP32" type="float" varname="e4" />
+	<parameter etype="FP32" type="float" varname="e3" />
+	<parameter etype="FP32" type="float" varname="e2" />
+	<parameter etype="FP32" type="float" varname="e1" />
+	<parameter etype="FP32" type="float" varname="e0" />
+	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[31:0] := e15
+dst[63:32] := e14
+dst[95:64] := e13
+dst[127:96] := e12
+dst[159:128] := e11
+dst[191:160] := e10
+dst[223:192] := e9
+dst[255:224] := e8
+dst[287:256] := e7
+dst[319:288] := e6
+dst[351:320] := e5
+dst[383:352] := e4
+dst[415:384] := e3
+dst[447:416] := e2
+dst[479:448] := e1
+dst[511:480] := e0
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setzero" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m512 with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setzero_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<description>Return vector of type __m512i with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setzero_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<description>Return vector of type __m512d with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setzero_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<description>Return vector of type __m512 with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setzero_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<description>Return vector of type __m512i with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPROLD" xed="VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPROLD" xed="VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rol_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPROLD" xed="VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPROLQ" xed="VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPROLQ" xed="VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rol_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPROLQ" xed="VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPROLVD" xed="VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPROLVD" xed="VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rolv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPROLVD" xed="VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPROLVQ" xed="VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPROLVQ" xed="VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rolv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPROLVQ" xed="VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPRORD" xed="VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPRORD" xed="VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_ror_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPRORD" xed="VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPRORQ" xed="VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPRORQ" xed="VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_ror_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPRORQ" xed="VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPRORVD" xed="VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rorv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
+	count := count_src % 32
+	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPRORVD" xed="VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPRORVQ" xed="VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPRORVQ" xed="VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rorv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
+	<operation>
+DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
+	count := count_src % 64
+	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPRORVQ" xed="VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sll_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sll_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_slli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sll_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sll_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_slli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sll_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_slli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sll_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_slli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sllv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSLLVD" xed="VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sllv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSLLVQ" xed="VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sllv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSLLVQ" xed="VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sllv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSLLVQ" xed="VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sra_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sra_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srai_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sra_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+		ELSE
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sra_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+	ELSE
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srai_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
+	ELSE
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srav_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSRAVD" xed="VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSRAVQ" xed="VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSRAVQ" xed="VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srav_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSRAVQ" xed="VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srl_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srl_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[63:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srl_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srl_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, xmm" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srl_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[63:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, xmm" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF imm8[7:0] &gt; 63
+			dst[i+63:i] := 0
+		ELSE
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srl_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, xmm" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srli_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srlv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSRLVD" xed="VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srlv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSRLVQ" xed="VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_srlv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		IF count[i+63:i] &lt; 64
+			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+		ELSE
+			dst[i+63:i] := 0
+		FI
+	ELSE
+		dst[i+63:i] := 0
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSRLVQ" xed="VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srlv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF count[i+63:i] &lt; 64
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSRLVQ" xed="VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VRCP14PD" xed="VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VRCP14PD" xed="VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rcp14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := (1.0 / a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VRCP14PD" xed="VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VRCP14PS" xed="VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VRCP14PS" xed="VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rcp14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (1.0 / a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VRCP14PS" xed="VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rcp14_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (1.0 / b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VRCP14SD" xed="VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rcp14_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (1.0 / b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VRCP14SD" xed="VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rcp14_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+dst[63:0] := (1.0 / b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VRCP14SD" xed="VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rcp14_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (1.0 / b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VRCP14SS" xed="VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rcp14_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (1.0 / b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VRCP14SS" xed="VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rcp14_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+dst[31:0] := (1.0 / b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VRCP14SS" xed="VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VRSQRT14PD" xed="VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VRSQRT14PD" xed="VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rsqrt14_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VRSQRT14PD" xed="VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VRSQRT14PS" xed="VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VRSQRT14PS" xed="VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rsqrt14_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VRSQRT14PS" xed="VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rsqrt14_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (1.0 / SQRT(b[63:0]))
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VRSQRT14SD" xed="VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rsqrt14_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+IF k[0]
+	dst[63:0] := (1.0 / SQRT(b[63:0]))
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VRSQRT14SD" xed="VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rsqrt14_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+dst[63:0] := (1.0 / SQRT(b[63:0]))
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VRSQRT14SD" xed="VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rsqrt14_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (1.0 / SQRT(b[31:0]))
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VRSQRT14SS" xed="VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rsqrt14_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+IF k[0]
+	dst[31:0] := (1.0 / SQRT(b[31:0]))
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VRSQRT14SS" xed="VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rsqrt14_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
+	<operation>
+dst[31:0] := (1.0 / SQRT(b[31:0]))
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VRSQRT14SS" xed="VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sqrt_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sqrt_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sqrt_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sqrt_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note].</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := SQRT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sqrt_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SQRT(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sqrt_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".
+	[round_note].</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := SQRT(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sqrt_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sqrt_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sqrt_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sqrt_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := SQRT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sqrt_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SQRT(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sqrt_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".
+	[round_note].</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := SQRT(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := SQRT(b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := SQRT(b[63:0])
+ELSE
+	dst[63:0] := src[63:0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[63:0] := SQRT(b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst[63:0] := SQRT(b[63:0])
+ELSE
+	dst[63:0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_round_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := SQRT(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := SQRT(b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := SQRT(b[31:0])
+ELSE
+	dst[31:0] := src[31:0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst[31:0] := SQRT(b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst[31:0] := SQRT(b[31:0])
+ELSE
+	dst[31:0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_round_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := SQRT(b[31:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castpd128_pd512" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are undefined. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castpd256_pd512" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are undefined. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castpd512_pd128" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Cast vector of type __m512d to type __m128d. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castps512_ps128" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Cast vector of type __m512 to type __m128. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castpd512_pd256" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Cast vector of type __m512d to type __m256d. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castps128_ps512" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Cast vector of type __m128 to type __m512; the upper 384 bits of the result are undefined. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castps256_ps512" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Cast vector of type __m256 to type __m512; the upper 256 bits of the result are undefined. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castps512_ps256" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Cast vector of type __m512 to type __m256. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castsi128_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" type="__m128i" varname="a" />
+	<description>Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are undefined. 
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castsi256_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" type="__m256i" varname="a" />
+	<description>Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are undefined.
+	 This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castsi512_si128" tech="AVX-512">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m512i" varname="a" />
+	<description>Cast vector of type __m512i to type __m128i.
+	 This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castsi512_si256" tech="AVX-512">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="M256" type="__m512i" varname="a" />
+	<description>Cast vector of type __m512i to type __m256i.
+	 This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_zextpd128_pd512" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_zextps128_ps512" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Cast vector of type __m128 to type __m512; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_zextsi128_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" type="__m128i" varname="a" />
+	<description>Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_zextpd256_pd512" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_zextps256_ps512" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Cast vector of type __m256 to type __m512; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_zextsi256_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" type="__m256i" varname="a" />
+	<description>Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_undefined" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m512 with undefined elements.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm512_undefined_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<description>Return vector of type __m512i with undefined elements.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm512_undefined_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<description>Return vector of type __m512d with undefined elements.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm512_undefined_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<description>Return vector of type __m512 with undefined elements.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE 
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".
+	 [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmadd_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmadd_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".  
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmadd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmadd_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".  
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := c[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmsub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmsub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="FP64" type="__m512d" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := c[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmsub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmsub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="FP32" type="__m512" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR	
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  RM.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] * b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  RM.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	 [round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] * b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". 
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPADDD" xed="VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPADDD" xed="VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mullo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp[63:0] := a[i+31:i] * b[i+31:i]
+		dst[i+31:i] := tmp[31:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULLD" xed="VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mullo_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	tmp[63:0] := a[i+31:i] * b[i+31:i]
+	dst[i+31:i] := tmp[31:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULLD" xed="VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSUBD" xed="VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSUBD" xed="VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_add_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed 32-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[31:0] + src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] + src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := 0
+	FI
+ENDFOR
+dst[31:0] := REDUCE_ADD(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_add_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed 64-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[63:0] + src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] + src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := 0
+	FI
+ENDFOR
+dst[63:0] := REDUCE_ADD(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_add_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[63:0] + src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] + src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := 0
+	FI
+ENDFOR
+dst[63:0] := REDUCE_ADD(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_add_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[31:0] + src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] + src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := 0
+	FI
+ENDFOR
+dst[31:0] := REDUCE_ADD(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_mul_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed 32-bit integers in "a" by multiplication using mask "k". Returns the product of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[31:0] * src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] * src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := 1
+	FI
+ENDFOR
+dst[31:0] := REDUCE_MUL(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_mul_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed 64-bit integers in "a" by multiplication using mask "k". Returns the product of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[63:0] * src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] * src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := 1
+	FI
+ENDFOR
+dst[63:0] := REDUCE_MUL(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_mul_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by multiplication using mask "k". Returns the product of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[63:0] * src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] * src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := 1.0
+	FI
+ENDFOR
+dst[63:0] := REDUCE_MUL(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_mul_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by multiplication using mask "k". Returns the product of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[31:0] * src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] * src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := FP32(1.0)
+	FI
+ENDFOR
+dst[31:0] := REDUCE_MUL(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_add_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed 32-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[31:0] + src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] + src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_ADD(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_add_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed 64-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[63:0] + src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] + src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_ADD(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_add_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[63:0] + src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] + src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_ADD(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_add_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_ADD(src, len) {
+	IF len == 2
+		RETURN src[31:0] + src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] + src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_ADD(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_ADD(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_mul_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed 32-bit integers in "a" by multiplication. Returns the product of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[31:0] * src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] * src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_MUL(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_mul_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed 64-bit integers in "a" by multiplication. Returns the product of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[63:0] * src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] * src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_MUL(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_mul_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[63:0] * src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] * src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_MUL(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_mul_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MUL(src, len) {
+	IF len == 2
+		RETURN src[31:0] * src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] * src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_MUL(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_MUL(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_abs_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="v2" />
+	<description>Finds the absolute value of each packed single-precision (32-bit) floating-point element in "v2", storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ABS(v2[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, m512" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_abs_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="v2" />
+	<description>Finds the absolute value of each packed single-precision (32-bit) floating-point element in "v2", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ABS(v2[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, m512" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_abs_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="v2" />
+	<description>Finds the absolute value of each packed double-precision (64-bit) floating-point element in "v2", storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ABS(v2[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, m512" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_abs_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="v2" />
+	<description>Finds the absolute value of each packed double-precision (64-bit) floating-point element in "v2", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ABS(v2[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, m512" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 64 bytes (16 elements) in "dst".</description>
+	<operation>
+temp[1023:512] := a[511:0]
+temp[511:0] := b[511:0]
+temp[1023:0] := temp[1023:0] &gt;&gt; (32*imm8[3:0])
+dst[511:0] := temp[511:0]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VALIGND" xed="VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_alignr_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 64 bytes (16 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+temp[1023:512] := a[511:0]
+temp[511:0] := b[511:0]
+temp[1023:0] := temp[1023:0] &gt;&gt; (32*imm8[3:0])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := temp[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VALIGND" xed="VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getexp_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.
+	[sae_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getexp_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getexp_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.
+	[sae_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getexp_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.
+	[sae_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getexp_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getexp_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.
+	[sae_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getmant_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8 {sae}" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getmant_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getmant_round_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8 {sae}" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getmant_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8 {sae}" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getmant_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getmant_round_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8 {sae}" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_blend_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VBLENDMPD" xed="VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_blend_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VBLENDMPS" xed="VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_blend_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMD" xed="VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_blend_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMQ" xed="VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutevar_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Note that this intrinsic shuffles across 128-bit lanes, unlike past intrinsics that use the "permutevar" name. This intrinsic is identical to "_mm512_mask_permutexvar_epi32", and it is recommended that you use that intrinsic name.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	id := idx[i+3:i]*32
+	IF k[j]
+		dst[i+31:i] := a[id+31:id]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutevar_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="idx" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". Note that this intrinsic shuffles across 128-bit lanes, unlike past intrinsics that use the "permutevar" name. This intrinsic is identical to "_mm512_permutexvar_epi32", and it is recommended that you use that intrinsic name.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	id := idx[i+3:i]*32
+	dst[i+31:i] := a[id+31:id]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shuffle_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4])
+tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6])
+tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4])
+tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6])
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := tmp_dst[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSHUFD" xed="VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shuffle_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+dst[159:128] := SELECT4(a[255:128], imm8[1:0])
+dst[191:160] := SELECT4(a[255:128], imm8[3:2])
+dst[223:192] := SELECT4(a[255:128], imm8[5:4])
+dst[255:224] := SELECT4(a[255:128], imm8[7:6])
+dst[287:256] := SELECT4(a[383:256], imm8[1:0])
+dst[319:288] := SELECT4(a[383:256], imm8[3:2])
+dst[351:320] := SELECT4(a[383:256], imm8[5:4])
+dst[383:352] := SELECT4(a[383:256], imm8[7:6])
+dst[415:384] := SELECT4(a[511:384], imm8[1:0])
+dst[447:416] := SELECT4(a[511:384], imm8[3:2])
+dst[479:448] := SELECT4(a[511:384], imm8[5:4])
+dst[511:480] := SELECT4(a[511:384], imm8[7:6])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSHUFD" xed="VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_round_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm {sae}, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := (a[i+63:i] == b[i+63:i]) ? 1 : 0
+ENDFOR	
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := (a[i+63:i] &lt;= b[i+63:i]) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := (a[i+63:i] &lt; b[i+63:i]) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := (a[i+63:i] != b[i+63:i]) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpnle_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := (!(a[i+63:i] &lt;= b[i+63:i])) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpnlt_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k[j] := (!(a[i+63:i] &lt; b[i+63:i])) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpord_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	k[j] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 1 : 0 
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpunord_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k".</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	k[j] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 1 : 0 
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_round_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm {sae}, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := (a[i+63:i] == b[i+63:i]) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR	
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := (a[i+63:i] &lt;= b[i+63:i]) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := (a[i+63:i] &lt; b[i+63:i]) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := (a[i+63:i] != b[i+63:i]) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpnle_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := (!(a[i+63:i] &lt;= b[i+63:i])) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpnlt_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := (!(a[i+63:i] &lt; b[i+63:i])) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpord_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpunord_pd_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="FP64" type="__m512d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 7
+	i := j*64
+	IF k1[j]
+		k[j] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_round_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm {sae}, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := (a[i+31:i] == b[i+31:i]) ? 1 : 0
+ENDFOR	
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := (a[i+31:i] &lt;= b[i+31:i]) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := (a[i+31:i] &lt; b[i+31:i]) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := (a[i+31:i] != b[i+31:i]) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpnle_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := (!(a[i+31:i] &lt;= b[i+31:i])) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpnlt_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := (!(a[i+31:i] &lt; b[i+31:i])) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpord_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	k[j] := ((a[i+31:i] != NaN) AND (b[i+31:i] != NaN)) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpunord_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k".</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	k[j] := ((a[i+31:i] == NaN) OR (b[i+31:i] == NaN)) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_round_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q 
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ 
+26: OP := _CMP_NGT_UQ 
+27: OP := _CMP_FALSE_OS 
+28: OP := _CMP_NEQ_OS 
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm {sae}, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := (a[i+31:i] == b[i+31:i]) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR		
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := (a[i+31:i] &lt;= b[i+31:i]) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := (a[i+31:i] &lt; b[i+31:i]) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := (a[i+31:i] != b[i+31:i]) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpnle_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := (!(a[i+31:i] &lt;= b[i+31:i])) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpnlt_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := (!(a[i+31:i] &lt; b[i+31:i])) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpord_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ((a[i+31:i] != NaN) AND (b[i+31:i] != NaN)) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpunord_ps_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ((a[i+31:i] == NaN) OR (b[i+31:i] == NaN)) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPEQD" xed="VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpge_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpgt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPCMPGTD" xed="VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPEQD" xed="VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpge_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpgt_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPCMPGTD" xed="VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpeq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpge_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpgt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmple_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmplt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmpneq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[2:0]) OF
+0: OP := _MM_CMPINT_EQ
+1: OP := _MM_CMPINT_LT
+2: OP := _MM_CMPINT_LE
+3: OP := _MM_CMPINT_FALSE
+4: OP := _MM_CMPINT_NE
+5: OP := _MM_CMPINT_NLT
+6: OP := _MM_CMPINT_NLE
+7: OP := _MM_CMPINT_TRUE
+ESAC
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpeq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpge_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpgt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmple_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmplt_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmpneq_epu32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
+	ELSE 
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32gather_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="FP32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, vm32z" name="VGATHERDPS" xed="VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32gather_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="FP32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, vm32z" name="VGATHERDPS" xed="VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_load_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_load_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_load_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_load_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 16 packed 32-bit integers) from memory into "dst". 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_load_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits of integer data from memory into "dst". 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_load_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 8 packed 64-bit integers) from memory into "dst". 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_load_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32gather_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+31:i] := MEM[addr+31:addr]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, vm32z" name="VPGATHERDD" xed="VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32gather_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="UI32" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+31:i] := MEM[addr+31:addr]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, vm32z" name="VPGATHERDD" xed="VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32logather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Loads 8 64-bit integer elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" and stores them in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VPGATHERDQ" xed="VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32logather_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="UI64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Loads 8 64-bit integer elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VPGATHERDQ" xed="VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32logather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Loads 8 double-precision (64-bit) floating-point elements stored at memory locations starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" them in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	dst[i+63:i] := MEM[addr+63:addr]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VGATHERDPD" xed="VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32logather_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="vindex" />
+	<parameter etype="FP64" type="void const*" varname="base_addr" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Loads 8 double-precision (64-bit) floating-point elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		dst[i+63:i] := MEM[addr+63:addr]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VGATHERDPD" xed="VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mov_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mov_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mov_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mov_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_store_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVAPD" xed="VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_store_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory.
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVAPD" xed="VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_store_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_store_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_store_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_store_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Store 512-bits (composed of 16 packed 32-bit integers) from "a" into memory. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_store_si512" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="M512" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="M512" type="__m512i" varname="a" />
+	<description>Store 512-bits of integer data from "a" into memory. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_store_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_store_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="512" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Store 512-bits (composed of 8 packed 64-bit integers) from "a" into memory. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32z, zmm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32scatter_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32z {k}, zmm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+31:addr] := a[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="vm32z, zmm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32scatter_ps" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP32" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+31:addr] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="vm32z {k}, zmm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32loscatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Stores 8 packed double-precision (64-bit) floating-point elements in "a" and to memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="m512, zmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32loscatter_pd" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Stores 8 packed double-precision (64-bit) floating-point elements in "a" to memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". Only those elements whose corresponding mask bit is set in writemask "k" are written to memory.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_and_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] AND b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_and_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" type="__m512i" varname="a" />
+	<parameter etype="M512" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of 512 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[511:0] := (a[511:0] AND b[511:0])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_andnot_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPANDND" xed="VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_andnot_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" type="__m512i" varname="a" />
+	<parameter etype="M512" type="__m512i" varname="b" />
+	<description>Compute the bitwise NOT of 512 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
+	<operation>
+dst[511:0] := ((NOT a[511:0]) AND b[511:0])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPANDND" xed="VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_andnot_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPANDND" xed="VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_andnot_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise NOT of 512 bits (composed of packed 64-bit integers) in "a" and then AND with "b", and store the results in "dst".</description>
+	<operation>
+dst[511:0] := ((NOT a[511:0]) AND b[511:0])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPANDNQ" xed="VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_andnot_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPANDNQ" xed="VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_and_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of 512 bits (composed of packed 64-bit integers) in "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst[511:0] := (a[511:0] AND b[511:0])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_and_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPORD" xed="VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_or_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPORD" xed="VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_or_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" type="__m512i" varname="a" />
+	<parameter etype="M512" type="__m512i" varname="b" />
+	<description>Compute the bitwise OR of 512 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[511:0] := (a[511:0] OR b[511:0])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPORD" xed="VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPORQ" xed="VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_or_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the resut in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPORQ" xed="VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_test_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k1[j]
+		k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_test_epi32_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPXORD" xed="VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_xor_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORD" xed="VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_xor_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="M512" type="__m512i" varname="a" />
+	<parameter etype="M512" type="__m512i" varname="b" />
+	<description>Compute the bitwise XOR of 512 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[511:0] := (a[511:0] XOR b[511:0])
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORD" xed="VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_xor_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_and_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed 32-bit integers in "a" by bitwise AND using mask "k". Returns the bitwise AND of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[31:0] AND src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] AND src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := 0xFFFFFFFF
+	FI
+ENDFOR
+dst[31:0] := REDUCE_AND(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_and_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed 64-bit integers in "a" by bitwise AND using mask "k". Returns the bitwise AND of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[63:0] AND src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] AND src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := 0xFFFFFFFFFFFFFFFF
+	FI
+ENDFOR
+dst[63:0] := REDUCE_AND(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_or_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed 32-bit integers in "a" by bitwise OR using mask "k". Returns the bitwise OR of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[31:0] OR src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] OR src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := 0
+	FI
+ENDFOR
+dst[31:0] := REDUCE_OR(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_or_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed 64-bit integers in "a" by bitwise OR using mask "k". Returns the bitwise OR of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[63:0] OR src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] OR src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := 0
+	FI
+ENDFOR
+dst[63:0] := REDUCE_OR(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_and_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed 32-bit integers in "a" by bitwise AND. Returns the bitwise AND of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[31:0] AND src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] AND src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_AND(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_and_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed 64-bit integers in "a" by bitwise AND. Returns the bitwise AND of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_AND(src, len) {
+	IF len == 2
+		RETURN src[63:0] AND src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] AND src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_AND(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_AND(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_or_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed 32-bit integers in "a" by bitwise OR. Returns the bitwise OR of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[31:0] OR src[63:32]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := src[i+31:i] OR src[i+32*len+31:i+32*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_OR(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_or_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed 64-bit integers in "a" by bitwise OR. Returns the bitwise OR of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_OR(src, len) {
+	IF len == 2
+		RETURN src[63:0] OR src[127:64]
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := src[i+63:i] OR src[i+64*len+63:i+64*len]
+	ENDFOR
+	RETURN REDUCE_OR(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_OR(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_and_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="v2" />
+	<parameter etype="UI32" type="__m512i" varname="v3" />
+	<description>Performs element-by-element bitwise AND between packed 32-bit integer elements of "v2" and "v3", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := v2[i+31:i] &amp; v3[i+31:i]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMAXSD" xed="VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMAXSD" xed="VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMAXUD" xed="VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMAXUD" xed="VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMINSD" xed="VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="SI32" type="__m512i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMINSD" xed="VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMINUD" xed="VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMINUD" xed="VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_max_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="SI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Reduce the packed signed 32-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := Int32(-0x80000000)
+	FI
+ENDFOR
+dst[31:0] := REDUCE_MAX(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_max_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="SI64" type="__int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Reduce the packed signed 64-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := Int64(-0x8000000000000000)
+	FI
+ENDFOR
+dst[63:0] := REDUCE_MAX(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_max_epu32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed unsigned 32-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := 0
+	FI
+ENDFOR
+dst[31:0] := REDUCE_MAX(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_max_epu64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed unsigned 64-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := 0
+	FI
+ENDFOR
+dst[63:0] := REDUCE_MAX(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_max_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := Cast_FP64(0xFFEFFFFFFFFFFFFF)
+	FI
+ENDFOR
+dst[63:0] := REDUCE_MAX(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_max_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := Cast_FP32(0xFF7FFFFF)
+	FI
+ENDFOR
+dst[31:0] := REDUCE_MAX(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_min_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="SI32" type="int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Reduce the packed signed 32-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := Int32(0x7FFFFFFF)
+	FI
+ENDFOR
+dst[31:0] := REDUCE_MIN(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_min_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="SI64" type="__int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Reduce the packed signed 64-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := Int64(0x7FFFFFFFFFFFFFFF)
+	FI
+ENDFOR
+dst[63:0] := REDUCE_MIN(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_min_epu32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed unsigned 32-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := 0xFFFFFFFF
+	FI
+ENDFOR
+dst[31:0] := REDUCE_MIN(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_min_epu64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed unsigned 64-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := 0xFFFFFFFFFFFFFFFF
+	FI
+ENDFOR
+dst[63:0] := REDUCE_MIN(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_min_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". [min_float_note]</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[64*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 8
+	i := j*64
+	IF k[j]
+		tmp[i+63:i] := a[i+63:i]
+	ELSE
+		tmp[i+63:i] := Cast_FP64(0x7FEFFFFFFFFFFFFF)
+	FI
+ENDFOR
+dst[63:0] := REDUCE_MIN(tmp, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_min_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". [min_float_note]</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[32*len-1:0], len)
+}
+tmp := a
+FOR j := 0 to 16
+	i := j*32
+	IF k[j]
+		tmp[i+31:i] := a[i+31:i]
+	ELSE
+		tmp[i+31:i] := Cast_FP32(0x7F7FFFFF)
+	FI
+ENDFOR
+dst[31:0] := REDUCE_MIN(tmp, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_max_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="SI32" type="int" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Reduce the packed signed 32-bit integers in "a" by maximum. Returns the maximum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_MAX(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_max_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="SI64" type="__int64" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Reduce the packed signed 64-bit integers in "a" by maximum. Returns the maximum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_MAX(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_max_epu32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed unsigned 32-bit integers in "a" by maximum. Returns the maximum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_MAX(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_max_epu64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed unsigned 64-bit integers in "a" by maximum. Returns the maximum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_MAX(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_max_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_MAX(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_max_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MAX(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MAX(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_MAX(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_min_epi32" sequence="TRUE" tech="AVX-512">
+	<return etype="SI32" type="int" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Reduce the packed signed 32-bit integers in "a" by minimum. Returns the minimum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_MIN(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_min_epi64" sequence="TRUE" tech="AVX-512">
+	<return etype="SI64" type="__int64" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Reduce the packed signed 64-bit integers in "a" by minimum. Returns the minimum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_MIN(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_min_epu32" sequence="TRUE" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Reduce the packed unsigned 32-bit integers in "a" by minimum. Returns the minimum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_MIN(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_min_epu64" sequence="TRUE" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Reduce the packed unsigned 64-bit integers in "a" by minimum. Returns the minimum of all elements in "a".</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_MIN(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_min_pd" sequence="TRUE" tech="AVX-512">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a". [min_float_note]</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*64
+		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[64*len-1:0], len)
+}
+dst[63:0] := REDUCE_MIN(a, 8)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_min_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a". [min_float_note]</description>
+	<operation>
+DEFINE REDUCE_MIN(src, len) {
+	IF len == 2
+		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
+	FI
+	len := len / 2
+	FOR j:= 0 to (len-1)
+		i := j*32
+		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
+	ENDFOR
+	RETURN REDUCE_MIN(src[32*len-1:0], len)
+}
+dst[31:0] := REDUCE_MIN(a, 16)
+	</operation>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_slli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_slli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sllv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSLLVD" xed="VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sllv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSLLVD" xed="VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srai_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+		ELSE
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srai_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="6" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srav_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSRAVD" xed="VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srav_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSRAVD" xed="VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF imm8[7:0] &gt; 31
+			dst[i+31:i] := 0
+		ELSE
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srli_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_srlv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		IF count[i+31:i] &lt; 32
+			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+		ELSE
+			dst[i+31:i] := 0
+		FI
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI	
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSRLVD" xed="VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_srlv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF count[i+31:i] &lt; 32
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSRLVD" xed="VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castpd_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Cast vector of type __m512d to type __m512.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castpd_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Cast vector of type __m512d to type __m512i.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castps_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Cast vector of type __m512 to type __m512d.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castps_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Cast vector of type __m512 to type __m512i.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castsi512_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Cast vector of type __m512i to type __m512d.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castsi512_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Cast vector of type __m512i to type __m512.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtpslo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="v2" />
+	<description>Performs element-by-element conversion of the lower half of packed single-precision (32-bit) floating-point elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := j*64
+	dst[n+63:n] := Convert_FP32_To_FP64(v2[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTPS2PD" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpslo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="v2" />
+	<description>Performs element-by-element conversion of the lower half of packed single-precision (32-bit) floating-point elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[l+63:l] := Convert_FP32_To_FP64(v2[i+31:i])
+	ELSE
+		dst[l+63:l] := src[l+63:l]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTPS2PD" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi32lo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="v2" />
+	<description>Performs element-by-element conversion of the lower half of packed 32-bit integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	dst[l+63:l] := Convert_Int32_To_FP64(v2[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTDQ2PD" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32lo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="v2" />
+	<description>Performs element-by-element conversion of the lower half of packed 32-bit integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := j*64
+	IF k[j]
+		dst[n+63:n] := Convert_Int32_To_FP64(v2[i+31:i])
+	ELSE
+		dst[n+63:n] := src[n+63:n]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTDQ2PD" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu32lo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="v2" />
+	<description>Performs element-by-element conversion of the lower half of packed 32-bit unsigned integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	n := j*64
+	dst[n+63:n] := Convert_Int32_To_FP64(v2[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTUDQ2PD" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu32lo_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="v2" />
+	<description>Performs element-by-element conversion of the lower half of 32-bit unsigned integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	l := j*64
+	IF k[j]
+		dst[l+63:l] := Convert_Int32_To_FP64(v2[i+31:i])
+	ELSE
+		dst[l+63:l] := src[l+63:l]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTUDQ2PD" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtpd_pslo" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="v2" />
+	<description>Performs an element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to single-precision (32-bit) floating-point elements and stores them in "dst". The elements are stored in the lower half of the results vector, while the remaining upper half locations are set to 0.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	k := j*32
+	dst[k+31:k] := Convert_FP64_To_FP32(v2[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTPD2PS" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpd_pslo" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="v2" />
+	<description>Performs an element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to single-precision (32-bit) floating-point elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The elements are stored in the lower half of the results vector, while the remaining upper half locations are set to 0.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	l := j*32
+	IF k[j]
+		dst[l+31:l] := Convert_FP64_To_FP32(v2[i+63:i])
+	ELSE
+		dst[l+31:l] := src[l+31:l]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTPD2PS" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_i32loscatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Stores 8 packed 64-bit integer elements located in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+	MEM[addr+63:addr] := a[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="m512, zmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_i32loscatter_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="vindex" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
+	<description>Stores 8 packed 64-bit integer elements located in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using writemask "k" (elements whose corresponding mask bit is not set are not written to memory).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	m := j*32
+	IF k[j]
+		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
+		MEM[addr+63:addr] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	
+<intrinsic name="_mm256_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMADD52LUQ" xed="VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMADD52LUQ" xed="VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMADD52LUQ" xed="VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMADD52HUQ" xed="VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMADD52HUQ" xed="VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMADD52HUQ" xed="VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_madd52lo_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_madd52hi_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
+		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512IFMA52</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_maskz_popcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POPCNT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPOPCNTQ" xed="VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_popcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POPCNT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPOPCNTQ" xed="VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_popcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := POPCNT(a[i+63:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPOPCNTQ" xed="VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_popcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POPCNT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPOPCNTQ" xed="VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_popcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POPCNT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPOPCNTQ" xed="VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_popcnt_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := POPCNT(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPOPCNTQ" xed="VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := POPCNT(a[i+31:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPOPCNTD" xed="VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POPCNT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPOPCNTD" xed="VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POPCNT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPOPCNTD" xed="VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := POPCNT(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPOPCNTD" xed="VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POPCNT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPOPCNTD" xed="VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POPCNT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPOPCNTD" xed="VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := POPCNT(a[i+31:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPOPCNTD" xed="VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POPCNT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPOPCNTD" xed="VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := POPCNT(a[i+31:i])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPOPCNTD" xed="VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_popcnt_epi64" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := POPCNT(a[i+63:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPOPCNTQ" xed="VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_popcnt_epi64" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POPCNT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPOPCNTQ" xed="VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_popcnt_epi64" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := POPCNT(a[i+63:i])
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPOPCNTQ" xed="VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512VPOPCNTDQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+	<intrinsic name="_mm512_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="BF16" type="__m256bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="BF16" type="__m256bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="BF16" type="__m256bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsbh_ss" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="BF16" type="__bfloat16" varname="a" />
+	<description>Convert the BF16 (16-bit) floating-point element in "a" to a floating-point element, and store the result in "dst". This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+dst[31:0] := Convert_BF16_To_FP32(a[15:0])
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m512bh" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	IF j &lt; 16
+		t := b.fp32[j]
+	ELSE
+		t := a.fp32[j-16]
+	FI
+	dst.word[j] := Convert_FP32_To_BF16(t)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m512bh" varname="dst" />
+	<parameter etype="BF16" type="__m512bh" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF j &lt; 16
+			t := b.fp32[j]
+		ELSE
+			t := a.fp32[j-16]
+		FI
+		dst.word[j] := Convert_FP32_To_BF16(t)
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m512bh" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="FP32" type="__m512" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF j &lt; 16
+			t := b.fp32[j]
+		ELSE
+			t := a.fp32[j-16]
+		FI
+		dst.word[j] := Convert_FP32_To_BF16(t)
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m256bh" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m256bh" varname="dst" />
+	<parameter etype="BF16" type="__m256bh" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m256bh" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="BF16" type="__m512bh" varname="a" />
+	<parameter etype="BF16" type="__m512bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst".</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 15
+	dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+	dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VDPBF16PS" xed="VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="BF16" type="__m512bh" varname="a" />
+	<parameter etype="BF16" type="__m512bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VDPBF16PS" xed="VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="BF16" type="__m512bh" varname="a" />
+	<parameter etype="BF16" type="__m512bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VDPBF16PS" xed="VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+	<intrinsic name="_mm_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*16
+	dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*16
+	dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*16
+	IF k[j]
+		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtness_sbh" sequence="TRUE" tech="AVX-512">
+	<return etype="BF16" type="__bfloat16" varname="dst" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Convert the single-precision (32-bit) floating-point element in "a" to a BF16 (16-bit) floating-point element, and store the result in "dst".</description>
+	<operation>
+dst[15:0] := Convert_FP32_To_BF16(a[31:0])
+	</operation>
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	IF j &lt; 4
+		t := b.fp32[j]
+	ELSE
+		t := a.fp32[j-4]
+	FI
+	dst.word[j] := Convert_FP32_To_BF16(t)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="BF16" type="__m128bh" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		IF j &lt; 4
+			t := b.fp32[j]
+		ELSE
+			t := a.fp32[j-4]
+		FI
+		dst.word[j] := Convert_FP32_To_BF16(t)
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		IF j &lt; 4
+			t := b.fp32[j]
+		ELSE
+			t := a.fp32[j-4]
+		FI
+		dst.word[j] := Convert_FP32_To_BF16(t)
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m256bh" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	IF j &lt; 8
+		t := b.fp32[j]
+	ELSE
+		t := a.fp32[j-8]
+	FI
+	dst.word[j] := Convert_FP32_To_BF16(t)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m256bh" varname="dst" />
+	<parameter etype="BF16" type="__m256bh" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		IF j &lt; 8
+			t := b.fp32[j]
+		ELSE
+			t := a.fp32[j-8]
+		FI
+		dst.word[j] := Convert_FP32_To_BF16(t)
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtne2ps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m256bh" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		IF j &lt; 8
+			t := b.fp32[j]
+		ELSE
+			t := a.fp32[j-8]
+		FI
+		dst.word[j] := Convert_FP32_To_BF16(t)
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="BF16" type="__m128bh" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="BF16" type="__m128bh" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtneps_pbh" tech="AVX-512">
+	<return etype="BF16" type="__m128bh" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<parameter etype="BF16" type="__m128bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst".</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 3
+	dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+	dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VDPBF16PS" xed="VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<parameter etype="BF16" type="__m128bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 3
+	IF k[j]
+		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VDPBF16PS" xed="VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="BF16" type="__m128bh" varname="a" />
+	<parameter etype="BF16" type="__m128bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 3
+	IF k[j]
+		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VDPBF16PS" xed="VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="BF16" type="__m256bh" varname="a" />
+	<parameter etype="BF16" type="__m256bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst".</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 7
+	dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+	dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VDPBF16PS" xed="VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="BF16" type="__m256bh" varname="a" />
+	<parameter etype="BF16" type="__m256bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VDPBF16PS" xed="VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_dpbf16_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="BF16" type="__m256bh" varname="a" />
+	<parameter etype="BF16" type="__m256bh" varname="b" />
+	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE make_fp32(x[15:0]) {
+	y.fp32  := 0.0
+	y[31:16] := x[15:0]
+	RETURN y
+}
+dst := src
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
+		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VDPBF16PS" xed="VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_BF16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_mask_bitshuffle_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 3 //Qword
+	FOR j := 0 to 7 // Byte
+		IF k[i*8+j]
+			m := c.qword[i].byte[j] &amp; 0x3F
+			dst[i*8+j] := b.qword[i].bit[m]
+		ELSE
+			dst[i*8+j] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_bitshuffle_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst".</description>
+	<operation>
+FOR i := 0 to 3 //Qword
+	FOR j := 0 to 7 // Byte
+		m := c.qword[i].byte[j] &amp; 0x3F
+		dst[i*8+j] := b.qword[i].bit[m]
+	ENDFOR
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="k, ymm, ymm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_bitshuffle_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 1 //Qword
+	FOR j := 0 to 7 // Byte
+		IF k[i*8+j]
+			m := c.qword[i].byte[j] &amp; 0x3F
+			dst[i*8+j] := b.qword[i].bit[m]
+		ELSE
+			dst[i*8+j] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_bitshuffle_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst".</description>
+	<operation>
+FOR i := 0 to 1 //Qword
+	FOR j := 0 to 7 // Byte
+		m := c.qword[i].byte[j] &amp; 0x3F
+		dst[i*8+j] := b.qword[i].bit[m]
+	ENDFOR
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="k, xmm, xmm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := POPCNT(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPOPCNTW" xed="VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POPCNT(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPOPCNTW" xed="VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POPCNT(a[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPOPCNTW" xed="VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := POPCNT(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPOPCNTW" xed="VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POPCNT(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPOPCNTW" xed="VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POPCNT(a[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPOPCNTW" xed="VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 31
+	i := j*8
+	dst[i+7:i] := POPCNT(a[i+7:i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VPOPCNTB" xed="VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := POPCNT(a[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPOPCNTB" xed="VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := POPCNT(a[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPOPCNTB" xed="VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := POPCNT(a[i+7:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VPOPCNTB" xed="VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := POPCNT(a[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPOPCNTB" xed="VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := POPCNT(a[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPOPCNTB" xed="VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_mask_bitshuffle_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 7 //Qword
+	FOR j := 0 to 7 // Byte
+		IF k[i*8+j]
+			m := c.qword[i].byte[j] &amp; 0x3F
+			dst[i*8+j] := b.qword[i].bit[m]
+		ELSE
+			dst[i*8+j] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_bitshuffle_epi64_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask64" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst".</description>
+	<operation>
+FOR i := 0 to 7 //Qword
+	FOR j := 0 to 7 // Byte
+		m := c.qword[i].byte[j] &amp; 0x3F
+		dst[i*8+j] := b.qword[i].bit[m]
+	ENDFOR
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="k, zmm, zmm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := POPCNT(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPOPCNTW" xed="VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POPCNT(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPOPCNTW" xed="VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POPCNT(a[i+15:i])
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPOPCNTW" xed="VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 63
+	i := j*8
+	dst[i+7:i] := POPCNT(a[i+7:i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VPOPCNTB" xed="VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := POPCNT(a[i+7:i])
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPOPCNTB" xed="VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE POPCNT(a) {
+	count := 0
+	DO WHILE a &gt; 0
+		count += a[0]
+		a &gt;&gt;= 1
+	OD
+	RETURN count
+}
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := POPCNT(a[i+7:i])
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPOPCNTB" xed="VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512_BITALG</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+	<intrinsic name="_mm256_acos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ACOS(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_acosh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ACOSH(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_asin_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ASIN(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_asinh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ASINH(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_atan2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+		<parameter etype="FP16" type="__m256h" varname="b" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ATAN2(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_atan_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ATAN(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_atanh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ATANH(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_cbrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := CubeRoot(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_cdfnorm_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := CDFNormal(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_cdfnorminv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := InverseCDFNormal(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_cos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := COS(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_cosd_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := COSD(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_cosh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := COSH(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_erf_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ERF(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_erfc_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := 1.0 - ERF(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_erfcinv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := 1.0 / (1.0 - ERF(a[i+15:i]))
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_erfinv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := 1.0 / ERF(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_exp10_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the exponential value of 10 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := POW(FP16(10.0), a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_exp2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the exponential value of 2 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := POW(FP16(2.0), a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_exp_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := POW(FP16(e), a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_expm1_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := POW(FP16(e), a[i+15:i]) - 1.0
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_hypot_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+		<parameter etype="FP16" type="__m256h" varname="b" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := SQRT(POW(a[i+15:i], 2.0) + POW(b[i+15:i], 2.0))
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_invcbrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := InvCubeRoot(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_invsqrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the inverse square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := InvSQRT(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_log10_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the base-10 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_log1p_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the natural logarithm of one plus packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := LOG(1.0 + a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_log2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the base-2 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_log_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the natural logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_logb_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ConvertExpFP16(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_pow_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the exponential value of packed half-precision (16-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+		<parameter etype="FP16" type="__m256h" varname="b" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := POW(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_sin_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := SIN(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_sincos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the sine and cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+		<parameter etype="FP16" memwidth="256" type="__m256h*" varname="mem_addr" />
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := SIN(a[i+15:i])
+	MEM[mem_addr+i+15:mem_addr+i] := COS(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+cos_res[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_sind_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := SIND(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_sinh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := SINH(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_svml_ceil_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" up to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := CEIL(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_svml_floor_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" down to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := FLOOR(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_svml_round_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ROUND(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_svml_sqrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := SQRT(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_tan_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := TAN(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_tand_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := TAND(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_tanh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Compute the hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := TANH(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm256_trunc_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m256h" varname="dst" />
+		<description>Truncate the packed half-precision (16-bit) floating-point elements in "a", and store the results as packed half-precision floating-point elements in "dst"</description>
+		<parameter etype="FP16" type="__m256h" varname="a" />
+	<category>Special Math Functions</category><operation>FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := TRUNCATE(a[i+15:i])
+ENDFOR
+dst[MAX:256] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_acos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ACOS(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_acosh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ACOSH(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_asin_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ASIN(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_asinh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ASINH(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_atan2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+		<parameter etype="FP16" type="__m512h" varname="b" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ATAN2(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_atan_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" expressed in radians.</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ATAN(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_atanh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse hyperblic tangent of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" expressed in radians.</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ATANH(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_cbrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := CubeRoot(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_cdfnorm_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := CDFNormal(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_cdfnorminv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := InverseCDFNormal(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_ceil_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" up to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := CEIL(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_cos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := COS(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_cosd_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := COSD(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_cosh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := COSH(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_erf_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ERF(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_erfc_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := 1.0 - ERF(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_erfcinv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := 1.0 / (1.0 - ERF(a[i+15:i]))
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_erfinv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := 1.0 / ERF(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_exp10_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of 10 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := POW(FP16(10.0), a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_exp2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of 2 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := POW(FP16(2.0), a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_exp_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := POW(FP16(e), a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_expm1_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := POW(FP16(e), a[i+15:i]) - 1.0
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_floor_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" down to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := FLOOR(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_hypot_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+		<parameter etype="FP16" type="__m512h" varname="b" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := SQRT(POW(a[i+15:i], 2.0) + POW(b[i+15:i], 2.0))
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_invsqrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := InvSQRT(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_log10_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the base-10 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_log1p_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the natural logarithm of one plus packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := LOG(1.0 + a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_log2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the base-2 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_log_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the natural logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_logb_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ConvertExpFP16(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_acos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ACOS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_acosh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ACOSH(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_asin_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ASIN(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_asinh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ASINH(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_atan_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ATAN(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_atanh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ATANH(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_cbrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := CubeRoot(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_cdfnorm_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := CDFNormal(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_cdfnorminv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := InverseCDFNormal(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_ceil_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" up to an integer value, and store the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := CEIL(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_cos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := COS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_cosd_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := COSD(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_cosh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := COSH(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_erf_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ERF(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_erfc_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := 1.0 - ERF(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_erfcinv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := 1.0 / (1.0 - ERF(a[i+15:i]))
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_erfinv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := 1.0 / ERF(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_exp10_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of 10 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POW(FP16(10.0), a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_exp2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of 2 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POW(FP16(2.0), a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_exp_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POW(FP16(e), a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_expm1_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := POW(FP16(e), a[i+15:i]) - 1.0
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_floor_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" down to an integer value, and store the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := FLOOR(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_invsqrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the inverse square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := InvSQRT(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_log10_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the base-10 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := LOG(a[i+15:i]) / LOG(10.0)
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_log1p_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the natural logarithm of one plus packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := LOG(1.0 + a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_log2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the base-2 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := LOG(a[i+15:i]) / LOG(2.0)
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_log_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the natural logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := LOG(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_logb_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ConvertExpFP16(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_nearbyint_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Rounds each packed half-precision (16-bit) floating-point element in "a" to the nearest integer value and stores the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := NearbyInt(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_recip_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Computes the reciprocal of packed half-precision (16-bit) floating-point elements in "a", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := (1.0 / a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_rint_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Rounds the packed half-precision (16-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := RoundToNearestEven(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_sin_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SIN(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_sincos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the sine and cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", store the cosine into memory at "mem_addr". Elements are written to their respective locations using writemask "k" (elements are copied from "sin_src" or "cos_src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" memwidth="512" type="__m512h*" varname="mem_addr" />
+		<parameter etype="FP16" type="__m512h" varname="sin_src" />
+		<parameter etype="FP16" type="__m512h" varname="cos_src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SIN(a[i+15:i])
+		MEM[mem_addr+i+15:mem_addr+i] := COS(a[i+15:i])
+	ELSE
+		dst[i+15:i] := sin_src[i+15:i]
+		MEM[mem_addr+i+15:mem_addr+i] := cos_src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+cos_res[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_sind_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SIND(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_sinh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := SINH(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_svml_round_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ROUND(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_tan_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := TAN(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_tand_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := TAND(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_tanh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := TANH(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_mask_trunc_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Truncate the packed half-precision (16-bit) floating-point elements in "a", and store the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+		<parameter etype="FP16" type="__m512h" varname="src" />
+		<parameter etype="MASK" type="__mmask32" varname="k" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := TRUNCATE(a[i+15:i])
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_nearbyint_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Rounds each packed half-precision (16-bit) floating-point element in "a" to the nearest integer value and stores the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := NearbyInt(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_pow_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the exponential value of packed half-precision (16-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+		<parameter etype="FP16" type="__m512h" varname="b" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := POW(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_recip_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Computes the reciprocal of packed half-precision (16-bit) floating-point elements in "a", storing the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := (1.0 / a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_rint_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Rounds the packed half-precision (16-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := RoundToNearestEven(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_sin_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := SIN(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_sincos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the sine and cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+		<parameter etype="FP16" memwidth="512" type="__m512h*" varname="mem_addr" />
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := SIN(a[i+15:i])
+	MEM[mem_addr+i+15:mem_addr+i] := COS(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+cos_res[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_sind_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := SIND(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_sinh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := SINH(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_svml_round_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ROUND(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_tan_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := TAN(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_tand_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := TAND(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_tanh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Compute the hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := TANH(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm512_trunc_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m512h" varname="dst" />
+		<description>Truncate the packed half-precision (16-bit) floating-point elements in "a", and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m512h" varname="a" />
+	<category>Special Math Functions</category><operation>FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := TRUNCATE(a[i+15:i])
+ENDFOR
+dst[MAX:512] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_acos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ACOS(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_acosh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ACOSH(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_asin_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ASIN(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_asinh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ASINH(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_atan2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+		<parameter etype="FP16" type="__m128h" varname="b" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ATAN2(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_atan_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ATAN(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_atanh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ATANH(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_cbrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := CubeRoot(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_cdfnorm_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := CDFNormal(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_cdfnorminv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := InverseCDFNormal(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_cos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := COS(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_cosd_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := COSD(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_cosh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := COSH(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_erf_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ERF(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_erfc_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := 1.0 - ERF(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_erfcinv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := 1.0 / (1.0 - ERF(a[i+15:i]))
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_erfinv_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := 1.0 / ERF(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_exp10_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the exponential value of 10 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := POW(FP16(10.0), a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_exp2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the exponential value of 2 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := POW(FP16(2.0), a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_exp_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := POW(FP16(e), a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_expm1_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := POW(FP16(e), a[i+15:i]) - 1.0
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_hypot_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+		<parameter etype="FP16" type="__m128h" varname="b" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := SQRT(POW(a[i+15:i], 2.0) + POW(b[i+15:i], 2.0))
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_invcbrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := InvCubeRoot(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_invsqrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the inverse square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := InvSQRT(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_log10_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the base-10 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_log1p_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the natural logarithm of one plus packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := LOG(1.0 + a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_log2_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the base-2 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_log_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the natural logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := LOG(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_logb_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ConvertExpFP16(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_pow_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the exponential value of packed half-precision (16-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+		<parameter etype="FP16" type="__m128h" varname="b" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := POW(a[i+15:i], b[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_sin_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := SIN(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_sincos_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the sine and cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+		<parameter etype="FP16" memwidth="128" type="__m128h*" varname="mem_addr" />
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := SIN(a[i+15:i])
+	MEM[mem_addr+i+15:mem_addr+i] := COS(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+cos_res[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_sind_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := SIND(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_sinh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := SINH(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_svml_ceil_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" up to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := CEIL(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_svml_floor_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" down to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := FLOOR(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_svml_round_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Round the packed half-precision (16-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Special Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ROUND(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_svml_sqrt_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Elementary Math Functions</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := SQRT(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_tan_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := TAN(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_tand_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := TAND(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_tanh_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Compute the hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Trigonometry</category><operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := TANH(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+	<intrinsic name="_mm_trunc_ph" sequence="TRUE" tech="SVML">
+		<return etype="FP16" type="__m128h" varname="dst" />
+		<description>Truncate the packed half-precision (16-bit) floating-point elements in "a", and store the results as packed half-precision floating-point elements in "dst".</description>
+		<parameter etype="FP16" type="__m128h" varname="a" />
+	<category>Special Math Functions</category><operation>FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := TRUNCATE(a[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
+<intrinsic name="_mm_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := a.fp16[j] + b.fp16[j]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VADDPH" xed="VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] + b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VADDPH" xed="VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] + b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VADDPH" xed="VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.fp16[j] := a.fp16[j] + b.fp16[j]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VADDPH" xed="VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] + b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VADDPH" xed="VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] + b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VADDPH" xed="VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := a.fp16[j] / b.fp16[j]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VDIVPH" xed="VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] / b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VDIVPH" xed="VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] / b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VDIVPH" xed="VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := a.fp16[j] / b.fp16[j]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VDIVPH" xed="VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] / b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VDIVPH" xed="VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] / b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VDIVPH" xed="VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADD132PH" xed="VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD213PH" xed="VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD231PH" xed="VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PH" xed="VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PH" xed="VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PH" xed="VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PH" xed="VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PH" xed="VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PH" xed="VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132PH" xed="VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213PH" xed="VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231PH" xed="VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMADD132PH" xed="VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFMADD213PH" xed="VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFMADD231PH" xed="VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PH" xed="VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PH" xed="VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PH" xed="VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PH" xed="VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PH" xed="VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PH" xed="VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD132PH" xed="VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD213PH" xed="VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADD231PH" xed="VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMADD132PH" xed="VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD213PH" xed="VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD231PH" xed="VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PH" xed="VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PH" xed="VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PH" xed="VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PH" xed="VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PH" xed="VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PH" xed="VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132PH" xed="VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213PH" xed="VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231PH" xed="VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFNMADD132PH" xed="VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFNMADD213PH" xed="VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFNMADD231PH" xed="VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PH" xed="VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PH" xed="VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PH" xed="VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PH" xed="VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PH" xed="VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PH" xed="VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD132PH" xed="VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD213PH" xed="VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD231PH" xed="VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUB132PH" xed="VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB213PH" xed="VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB231PH" xed="VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PH" xed="VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PH" xed="VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PH" xed="VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PH" xed="VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PH" xed="VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PH" xed="VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132PH" xed="VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213PH" xed="VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231PH" xed="VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMSUB132PH" xed="VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUB213PH" xed="VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUB231PH" xed="VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PH" xed="VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PH" xed="VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PH" xed="VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PH" xed="VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PH" xed="VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PH" xed="VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB132PH" xed="VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB213PH" xed="VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB231PH" xed="VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB132PH" xed="VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB213PH" xed="VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB231PH" xed="VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PH" xed="VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PH" xed="VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PH" xed="VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PH" xed="VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PH" xed="VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PH" xed="VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB132PH" xed="VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB213PH" xed="VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB231PH" xed="VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	IF ((j &amp; 1) == 0)
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	IF ((j &amp; 1) == 0)
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	IF ((j &amp; 1) == 0)
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	IF ((j &amp; 1) == 0)
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := a.fp16[j] - b.fp16[j]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSUBPH" xed="VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] - b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSUBPH" xed="VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] - b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSUBPH" xed="VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.fp16[j] := a.fp16[j] - b.fp16[j]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VSUBPH" xed="VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] - b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VSUBPH" xed="VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] - b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VSUBPH" xed="VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR i := 0 TO 7
+	dst.fp16[i] := a.fp16[i] * b.fp16[i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VMULPH" xed="VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 TO 7
+	IF k[i]
+		dst.fp16[i] := a.fp16[i] * b.fp16[i]
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMULPH" xed="VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 TO 7
+	IF k[i]
+		dst.fp16[i] := a.fp16[i] * b.fp16[i]
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMULPH" xed="VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR i := 0 TO 15
+	dst.fp16[i] := a.fp16[i] * b.fp16[i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMULPH" xed="VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 TO 15
+	IF k[i]
+		dst.fp16[i] := a.fp16[i] * b.fp16[i]
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMULPH" xed="VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 TO 15
+	IF k[i]
+		dst.fp16[i] := a.fp16[i] * b.fp16[i]
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMULPH" xed="VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADDCPH" xed="VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := a.fp16[2*i+0]
+		dst.fp16[2*i+1] := a.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDCPH" xed="VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := c.fp16[2*i+0]
+		dst.fp16[2*i+1] := c.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDCPH" xed="VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDCPH" xed="VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMADDCPH" xed="VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := a.fp16[2*i+0]
+		dst.fp16[2*i+1] := a.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDCPH" xed="VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := c.fp16[2*i+0]
+		dst.fp16[2*i+1] := c.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFMADDCPH" xed="VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFMADDCPH" xed="VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFCMADDCPH" xed="VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := a.fp16[2*i+0]
+		dst.fp16[2*i+1] := a.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFCMADDCPH" xed="VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := c.fp16[2*i+0]
+		dst.fp16[2*i+1] := c.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFCMADDCPH" xed="VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 3
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFCMADDCPH" xed="VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFCMADDCPH" xed="VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := a.fp16[2*i+0]
+		dst.fp16[2*i+1] := a.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFCMADDCPH" xed="VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask3_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := c.fp16[2*i+0]
+		dst.fp16[2*i+1] := c.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VFCMADDCPH" xed="VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="FP16" type="__m256h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VFCMADDCPH" xed="VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_add_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 7
+	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+8]
+ENDFOR
+FOR i := 0 to 3
+	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+4]
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+2]
+ENDFOR
+dst.fp16[0] := tmp.fp16[0] + tmp.fp16[1]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_mul_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Reduce the packed half-precision (316-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 7
+	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+8]
+ENDFOR
+FOR i := 0 to 3
+	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+4]
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+2]
+ENDFOR
+dst.fp16[0] := tmp.fp16[0] * tmp.fp16[1]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_max_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 7
+	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+8] ? tmp.fp16[i] : tmp.fp16[i+8])
+ENDFOR
+FOR i := 0 to 3
+	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
+ENDFOR
+dst.fp16[0] := (tmp.fp16[0] &gt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_min_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 7
+	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+8] ? tmp.fp16[i] : tmp.fp16[i+8])
+ENDFOR
+FOR i := 0 to 3
+	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
+ENDFOR
+dst.fp16[0] := (tmp.fp16[0] &lt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_add_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 3
+	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+4]
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+2]
+ENDFOR
+dst.fp16[0] := tmp.fp16[0] + tmp.fp16[1]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_mul_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 3
+	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+4]
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+2]
+ENDFOR
+dst.fp16[0] := tmp.fp16[0] * tmp.fp16[1]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_max_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 3
+	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
+ENDFOR
+dst.fp16[0] := (tmp.fp16[0] &gt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_min_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 3
+	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
+ENDFOR
+dst.fp16[0] := (tmp.fp16[0] &lt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_abs_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="v2" />
+	<description>Finds the absolute value of each packed half-precision (16-bit) floating-point element in "v2", storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := ABS(v2.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_abs_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="v2" />
+	<description>Finds the absolute value of each packed half-precision (16-bit) floating-point element in "v2", storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := ABS(v2.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	k[j] := (a.fp16[j] OP b.fp16[j]) ? 1 : 0
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 7
+	IF k1[j]
+		k[j] := ( a.fp16[j] OP b.fp16[j] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cmp_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 15
+	k[j] := (a.fp16[j] OP b.fp16[j]) ? 1 : 0
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, ymm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cmp_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 15
+	IF k1[j]
+		k[j] := ( a.fp16[j] OP b.fp16[j] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, ymm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTW2PH" xed="VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTW2PH" xed="VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTW2PH" xed="VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTW2PH" xed="VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTW2PH" xed="VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTW2PH" xed="VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTUW2PH" xed="VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTUW2PH" xed="VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTUW2PH" xed="VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTUW2PH" xed="VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTUW2PH" xed="VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTUW2PH" xed="VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m256i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".  The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 to 3
+	dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  The upper 64 bits of "dst" are zeroed out.</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, ymm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, ymm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 1
+	dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 1
+	dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 1
+	dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 1
+	dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 1
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 3
+	dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 3
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2W" xed="VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2W" xed="VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2W" xed="VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTPH2W" xed="VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTPH2W" xed="VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTPH2W" xed="VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPH2W" xed="VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPH2W" xed="VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPH2W" xed="VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTTPH2W" xed="VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTTPH2W" xed="VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTTPH2W" xed="VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2UW" xed="VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2UW" xed="VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2UW" xed="VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTPH2UW" xed="VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTPH2UW" xed="VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTPH2UW" xed="VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VCVTTPH2UW" xed="VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VCVTTPH2UW" xed="VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VCVTTPH2UW" xed="VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	IF k[j]
+		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+	ELSE
+		dst.fp64[j] := src.fp64[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	IF k[j]
+		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+	ELSE
+		dst.fp64[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+	ELSE
+		dst.fp64[j] := src.fp64[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+	ELSE
+		dst.fp64[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+	ELSE
+		dst.fp32[j] := src.fp32[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+	ELSE
+		dst.fp32[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+	ELSE
+		dst.fp32[j] := src.fp32[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+	ELSE
+		dst.fp32[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VMAXPH" xed="VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMAXPH" xed="VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMAXPH" xed="VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMAXPH" xed="VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMAXPH" xed="VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMAXPH" xed="VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [max_float_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_max_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_max_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VMINPH" xed="VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMINPH" xed="VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMINPH" xed="VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VMINPH" xed="VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VMINPH" xed="VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VMINPH" xed="VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [min_float_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_min_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_min_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 7
+	dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+ENDFOR
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 15
+	dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+ENDFOR
+dest[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dest[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dest[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 7
+	dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VGETEXPPH" xed="VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VGETEXPPH" xed="VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VGETEXPPH" xed="VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 15
+	dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VGETEXPPH" xed="VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VGETEXPPH" xed="VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VGETEXPPH" xed="VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR i := 0 TO 7
+	dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR i := 0 TO 7
+	IF k[i]
+		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note]</description>
+	<operation>FOR i := 0 TO 7
+	IF k[i]
+		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+		[getmant_note]</description>
+	<operation>FOR i := 0 TO 15
+	dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VGETMANTPH" xed="VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+		[getmant_note]</description>
+	<operation>FOR i := 0 TO 15
+	IF k[i]
+		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VGETMANTPH" xed="VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+		[getmant_note]</description>
+	<operation>FOR i := 0 TO 15
+	IF k[i]
+		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VGETMANTPH" xed="VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 7
+	dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 15
+	dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, imm8" name="VREDUCEPH" xed="VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, imm8" name="VREDUCEPH" xed="VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, imm8" name="VREDUCEPH" xed="VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 7
+	dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSCALEFPH" xed="VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFPH" xed="VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFPH" xed="VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VSCALEFPH" xed="VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VSCALEFPH" xed="VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VSCALEFPH" xed="VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fpclass_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+		[fpclass_note]</description>
+	<operation>FOR i := 0 to 7
+	k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k, xmm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fpclass_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+		[fpclass_note]</description>
+	<operation>FOR i := 0 to 7
+	IF k1[i]
+		k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
+	ELSE
+		k[i] := 0
+	FI
+ENDFOR
+k[MAX:8] := 0
+	</operation>
+	<instruction form="k {k}, xmm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fpclass_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+			[fpclass_note]</description>
+	<operation>FOR i := 0 to 15
+	k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k, ymm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_fpclass_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="MASK" type="__mmask16" varname="k1" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+		[fpclass_note]</description>
+	<operation>FOR i := 0 to 15
+	IF k1[i]
+		k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
+	ELSE
+		k[i] := 0
+	FI
+ENDFOR
+k[MAX:16] := 0
+	</operation>
+	<instruction form="k {k}, ymm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutex2var_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Shuffle half-precision (16-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	off := idx[i+2:i]
+	dst.fp16[j] := idx[i+3] ? b.fp16[off] : a.fp16[off]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex2var_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Shuffle half-precision (16-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	off := idx[i+3:i]
+	dst.fp16[j] := idx[i+4] ? b.fp16[off] : a.fp16[off]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMI2W" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<instruction form="ymm, ymm, ymm" name="VPERMT2W" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_blend_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="FP16" type="__m256h" varname="b" />
+	<description>Blend packed half-precision (16-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := b.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMW" xed="VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_blend_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Blend packed half-precision (16-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp16[j] := b.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMW" xed="VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutexvar_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="idx" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Shuffle half-precision (16-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	id := idx[i+3:i]
+	dst.fp16[j] := a.fp16[id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMW" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutexvar_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="idx" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Shuffle half-precision (16-bit) floating-point elements in "a" using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	id := idx[i+2:i]
+	dst.fp16[j] := a.fp16[id]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMW" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VRSQRTPH" xed="VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VRSQRTPH" xed="VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VRSQRTPH" xed="VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VRSQRTPH" xed="VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VRSQRTPH" xed="VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VRSQRTPH" xed="VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[i] := SQRT(a.fp16[i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VSQRTPH" xed="VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := SQRT(a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VSQRTPH" xed="VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := SQRT(a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VSQRTPH" xed="VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[i] := SQRT(a.fp16[i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VSQRTPH" xed="VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := SQRT(a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VSQRTPH" xed="VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := SQRT(a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VSQRTPH" xed="VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[i] := (1.0 / a.fp16[i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VRCPPH" xed="VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := (1.0 / a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VRCPPH" xed="VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 7
+	IF k[i]
+		dst.fp16[i] := (1.0 / a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VRCPPH" xed="VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[i] := (1.0 / a.fp16[i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VRCPPH" xed="VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := (1.0 / a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VRCPPH" xed="VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := (1.0 / a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VRCPPH" xed="VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm256_load_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVAPS" xed="VMOVAPS_YMMqq_MEMqq" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m128" name="MOVAPS" xed="MOVAPS_XMMps_MEMps" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_loadu_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" memwidth="256" type="void const*" varname="mem_addr" />
+	<description>Load 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[255:0] := MEM[mem_addr+255:mem_addr]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, m256" name="VMOVUPS" xed="VMOVUPS_YMMqq_MEMqq" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" memwidth="128" type="void const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, m128" name="MOVUPS" xed="MOVUPS_XMMps_MEMps" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_store_ph" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP16" memwidth="256" type="void *" varname="mem_addr" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Store 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVAPS" xed="VMOVAPS_MEMqq_YMMqq" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_ph" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP16" memwidth="128" type="void *" varname="mem_addr" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Store 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVAPS" xed="MOVAPS_MEMps_XMMps" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_storeu_ph" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP16" memwidth="256" type="void *" varname="mem_addr" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Store 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+255:mem_addr] := a[255:0]
+	</operation>
+	<instruction form="m256, ymm" name="VMOVUPS" xed="VMOVUPS_MEMqq_YMMqq" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_ph" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP16" memwidth="128" type="void *" varname="mem_addr" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Store 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVUPS" xed="MOVUPS_MEMps_XMMps" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_undefined_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m256h with undefined elements.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_undefined_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m128h with undefined elements.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setzero_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m256h with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VXORPS" xed="VXORPS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setzero_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m128h with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="XORPS" xed="XORPS_XMMxud_XMMxud" />
+	<CPUID>AVX512_FP16</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.fp16[j] := a.fp16[j] + b.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] + b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] + b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_add_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.fp16[j] := a.fp16[j] + b.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_add_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] + b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_add_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] + b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := a.fp16[0] + b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+dst.fp16[0] := a.fp16[0] + b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] + b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_add_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] + b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] + b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_add_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] + b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := a.fp16[j] / b.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] / b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_div_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] / b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_div_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := a.fp16[j] / b.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_div_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] / b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_div_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] / b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := a.fp16[0] / b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] / b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] / b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+dst.fp16[0] := a.fp16[0] / b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_div_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] / b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_div_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] / b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+FI
+dst[127:16] := c[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+FI
+dst[127:16] := c[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+FI
+dst[127:16] := c[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmadd_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmadd_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+FI
+dst[127:16] := c[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmadd_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+FI
+dst[127:16] := c[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmsub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmsub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+FI
+dst[127:16] := c[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmsub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fnmsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fnmsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fnmsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fnmsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+FI
+dst[127:16] := c[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fnmsub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fnmsub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+FI
+dst[127:16] := c[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fnmsub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	IF ((j &amp; 1) == 0)
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmaddsub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmaddsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".
+		[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF ((j &amp; 1) == 0)
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	ELSE
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmaddsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+		[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmaddsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
+		[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmaddsub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+		[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	IF ((j &amp; 1) == 0)
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsubadd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmsubadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst".
+		[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF ((j &amp; 1) == 0)
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+	ELSE
+		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmsubadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
+		[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmsubadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
+		[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := c.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmsubadd_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+		[round_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		IF ((j &amp; 1) == 0)
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
+		ELSE
+			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
+		FI
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.fp16[j] := a.fp16[j] - b.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.fp16[j] := a.fp16[j] - b.fp16[j]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] - b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] - b.fp16[j]
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] - b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sub_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := a.fp16[j] - b.fp16[j]
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := a.fp16[0] - b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := a.fp16[0] - b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] - b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] - b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] - b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sub_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] - b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR i := 0 TO 31
+	dst.fp16[i] := a.fp16[i] * b.fp16[i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".
+	 [round_note]</description>
+	<operation>
+FOR i := 0 TO 31
+	dst.fp16[i] := a.fp16[i] * b.fp16[i]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 TO 31
+	IF k[i]
+		dst.fp16[i] := a.fp16[i] * b.fp16[i]
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	 [round_note]</description>
+	<operation>
+FOR i := 0 TO 31
+	IF k[i]
+		dst.fp16[i] := a.fp16[i] * b.fp16[i]
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 TO 31
+	IF k[i]
+		dst.fp16[i] := a.fp16[i] * b.fp16[i]
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	 [round_note]</description>
+	<operation>
+FOR i := 0 TO 31
+	IF k[i]
+		dst.fp16[i] := a.fp16[i] * b.fp16[i]
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := a.fp16[0] * b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := a.fp16[0] * b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] * b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] * b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] * b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := a.fp16[0] * b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+			[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+			[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_mul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+			[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_mul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+			[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+	dst.fp16[1] := src.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+	dst.fp16[1] := src.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+			[round_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+			[round_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+	dst.fp16[1] := src.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_mul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+	dst.fp16[1] := src.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+			[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_mul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+			[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fcmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cmul_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fcmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fcmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := src.fp16[2*i+0]
+		dst.fp16[2*i+1] := src.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fcmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cmul_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fcmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fcmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+	dst.fp16[1] := src.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+	dst.fp16[1] := src.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fcmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cmul_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fcmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fcmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+	dst.fp16[1] := src.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+	dst.fp16[1] := src.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fcmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cmul_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "src", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := a.fp16[2*i+0]
+		dst.fp16[2*i+1] := a.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "src", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := c.fp16[2*i+0]
+		dst.fp16[2*i+1] := c.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fmadd_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fmadd_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := a.fp16[2*i+0]
+		dst.fp16[2*i+1] := a.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fmadd_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := c.fp16[2*i+0]
+		dst.fp16[2*i+1] := c.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fmadd_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "a" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+	dst.fp16[1] := a.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower complex number in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "c" when mask bit 0 is not set), and copy the upper 6 packed elements from "c" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+	dst.fp16[1] := c.fp16[1]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fmadd_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "a" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+	dst.fp16[1] := a.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fmadd_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "c" when mask bit 0 is not set), and copy the upper 6 packed elements from "c" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+	dst.fp16[1] := c.fp16[1]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fmadd_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := a.fp16[2*i+0]
+		dst.fp16[2*i+1] := a.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := c.fp16[2*i+0]
+		dst.fp16[2*i+1] := c.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fcmadd_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fcmadd_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fcmadd_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := a.fp16[2*i+0]
+		dst.fp16[2*i+1] := a.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask3_fcmadd_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := c.fp16[2*i+0]
+		dst.fp16[2*i+1] := c.fp16[2*i+1]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_fcmadd_round_pch" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="FP16" type="__m512h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
+		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
+	ELSE
+		dst.fp16[2*i+0] := 0
+		dst.fp16[2*i+1] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fcmadd_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />	
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fcmadd_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "a" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+	dst.fp16[1] := a.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fcmadd_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "c" when mask bit 0 is not set), and copy the upper 6 packed elements from "c" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+	dst.fp16[1] := c.fp16[1]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fcmadd_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fcmadd_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fcmadd_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "a" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := a.fp16[0]
+	dst.fp16[1] := a.fp16[1]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask3_fcmadd_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "c" when mask bit 0 is not set), and copy the upper 6 packed elements from "c" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := c.fp16[0]
+	dst.fp16[1] := c.fp16[1]
+FI
+dst[127:32] := c[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_fcmadd_round_sch" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="FP16" type="__m128h" varname="c" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
+	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
+ELSE
+	dst.fp16[0] := 0
+	dst.fp16[1] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_add_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP32" type="__m512h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 15
+	tmp.fp16[i] := tmp.fp16[i] + a.fp16[i+16]
+ENDFOR
+FOR i := 0 to 7
+	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+8]
+ENDFOR
+FOR i := 0 to 3
+	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+4]
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+2]
+ENDFOR
+dst.fp16[0] := tmp.fp16[0] + tmp.fp16[1]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_mul_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP32" type="__m512h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
+	<operation>
+tmp := a
+FOR i := 0 to 15
+	tmp.fp16[i] := tmp.fp16[i] * a.fp16[i+16]
+ENDFOR
+FOR i := 0 to 7
+	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+8]
+ENDFOR
+FOR i := 0 to 3
+	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+4]
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+2]
+ENDFOR
+dst.fp16[0] := tmp.fp16[0] * tmp.fp16[1]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_max_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP32" type="__m512h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a". [max_float_note]</description>
+	<operation>
+tmp := a
+FOR i := 0 to 15
+	tmp.fp16[i] := (a.fp16[i] &gt; a.fp16[i+16] ? a.fp16[i] : a.fp16[i+16])
+ENDFOR
+FOR i := 0 to 7
+	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+8] ? tmp.fp16[i] : tmp.fp16[i+8])
+ENDFOR
+FOR i := 0 to 3
+	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
+ENDFOR
+dst.fp16[0] := (tmp.fp16[0] &gt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_min_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP32" type="__m512h" varname="a" />
+	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a". [min_float_note]</description>
+	<operation>
+tmp := a
+FOR i := 0 to 15
+	tmp.fp16[i] := (a.fp16[i] &lt; a.fp16[i+16] ? tmp.fp16[i] : a.fp16[i+16])
+ENDFOR
+FOR i := 0 to 7
+	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+8] ? tmp.fp16[i] : tmp.fp16[i+8])
+ENDFOR
+FOR i := 0 to 3
+	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
+ENDFOR
+FOR i := 0 to 1
+	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
+ENDFOR
+dst.fp16[0] := (tmp.fp16[0] &lt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_abs_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="v2" />
+	<description>Finds the absolute value of each packed half-precision (16-bit) floating-point element in "v2", storing the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := ABS(v2.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP32" type="__m512h" varname="dst" />
+	<parameter etype="FP32" type="__m512h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_conj_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 31
+	k[j] := (a.fp16[j] OP b.fp16[j]) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 31
+	IF k1[j]
+		k[j] := ( a.fp16[j] OP b.fp16[j] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cmp_round_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 31
+	k[j] := (a.fp16[j] OP b.fp16[j]) ? 1 : 0
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, zmm {sae}, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cmp_round_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>CASE (imm8[3:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+FOR j := 0 to 31
+	IF k1[j]
+		k[j] := ( a.fp16[j] OP b.fp16[j] ) ? 1 : 0
+	ELSE
+		k[j] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, zmm {sae}, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_sh_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+k[0] := (a.fp16[0] OP b.fp16[0]) ? 1 : 0
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, xmm, imm8" name="VCMPSH" xed="VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmp_round_sh_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+k[0] := (a.fp16[0] OP b.fp16[0]) ? 1 : 0
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, xmm {sae}, imm8" name="VCMPSH" xed="VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_sh_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+IF k1[0]
+	k[0] := ( a.fp16[0] OP b.fp16[0] ) ? 1 : 0
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPSH" xed="VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cmp_round_sh_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+IF k1[0]
+	k[0] := ( a.fp16[0] OP b.fp16[0] ) ? 1 : 0
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, xmm {sae}, imm8" name="VCMPSH" xed="VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comi_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1).</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+RETURN ( a.fp16[0] OP b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comi_round_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1). [sae_note]</description>
+	<operation>CASE (imm8[4:0]) OF
+0: OP := _CMP_EQ_OQ
+1: OP := _CMP_LT_OS
+2: OP := _CMP_LE_OS
+3: OP := _CMP_UNORD_Q
+4: OP := _CMP_NEQ_UQ
+5: OP := _CMP_NLT_US
+6: OP := _CMP_NLE_US
+7: OP := _CMP_ORD_Q
+8: OP := _CMP_EQ_UQ
+9: OP := _CMP_NGE_US
+10: OP := _CMP_NGT_US
+11: OP := _CMP_FALSE_OQ
+12: OP := _CMP_NEQ_OQ
+13: OP := _CMP_GE_OS
+14: OP := _CMP_GT_OS
+15: OP := _CMP_TRUE_UQ
+16: OP := _CMP_EQ_OS
+17: OP := _CMP_LT_OQ
+18: OP := _CMP_LE_OQ
+19: OP := _CMP_UNORD_S
+20: OP := _CMP_NEQ_US
+21: OP := _CMP_NLT_UQ
+22: OP := _CMP_NLE_UQ
+23: OP := _CMP_ORD_S
+24: OP := _CMP_EQ_US
+25: OP := _CMP_NGE_UQ
+26: OP := _CMP_NGT_UQ
+27: OP := _CMP_FALSE_OS
+28: OP := _CMP_NEQ_OS
+29: OP := _CMP_GE_OQ
+30: OP := _CMP_GT_OQ
+31: OP := _CMP_TRUE_US
+ESAC
+RETURN ( a.fp16[0] OP b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm {sae}" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comieq_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for equality, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] == b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comilt_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for less-than, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &lt; b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comile_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &lt;= b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comigt_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for greater-than, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &gt; b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comige_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &gt;= b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comineq_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for not-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a.fp16[0] ==NaN OR b.fp16[0] ==NaN OR a.fp16[0] != b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomieq_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] == b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomilt_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &lt; b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomile_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &lt;= b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomigt_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &gt; b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomige_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &gt;= b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomineq_sh" tech="AVX-512">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a.fp16[0] ==NaN OR b.fp16[0] ==NaN OR a.fp16[0] != b.fp16[0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepi16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepu16_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {er}" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {er}" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepi32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {er}" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {er}" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {er}" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepu32_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {er}" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm {er}" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm {er}" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepi64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm {er}" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm {er}" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm {er}" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundepu64_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm {er}" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, zmm {er}" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, zmm {er}" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, zmm {er}" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper element of "dst".</description>
+	<operation>
+dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvt_roundsd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvt_roundsd_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtx_roundps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, zmm {er}" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtx_roundps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, zmm {er}" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtxps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtx_roundps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, zmm {er}" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundss_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtss_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvt_roundss_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtss_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvt_roundss_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {er}" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {er}" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {er}" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {sae}" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {sae}" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundph_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {sae}" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {er}" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {er}" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {er}" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {sae}" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {sae}" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundph_epu32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 15
+	IF k[j]
+		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {sae}" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm {er}" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm {er}" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm {er}" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm {sae}" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm {sae}" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundph_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm {sae}" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm {er}" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm {er}" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm  {er}" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm {sae}" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := src.qword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm {sae}" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundph_epu64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 7
+	IF k[j]
+		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
+	ELSE
+		dst.qword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm {sae}" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundph_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtt_roundph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtt_roundph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := src.word[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvttph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtt_roundph_epu16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 TO 31
+	IF k[j]
+		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
+	ELSE
+		dst.word[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvt_roundph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, xmm {sae}" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+	ELSE
+		dst.fp64[j] := src.fp64[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvt_roundph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+	ELSE
+		dst.fp64[j] := src.fp64[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, xmm {sae}" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+	ELSE
+		dst.fp64[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvt_roundph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
+	ELSE
+		dst.fp64[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, xmm {sae}" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtx_roundph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, ymm {sae}" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+	ELSE
+		dst.fp32[j] := src.fp32[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_cvtx_roundph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+	ELSE
+		dst.fp32[j] := src.fp32[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, ymm {sae}" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtxph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+	ELSE
+		dst.fp32[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_cvtx_roundph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
+	ELSE
+		dst.fp32[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, ymm {sae}" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsh_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsh_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [sae_note]</description>
+	<operation>
+dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsh_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
+ELSE
+	dst.fp64[0] := src.fp64[0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvt_roundsh_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note]</description>
+	<operation>
+IF k[0]
+	dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
+ELSE
+	dst.fp64[0] := src.fp64[0]
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsh_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
+ELSE
+	dst.fp64[0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvt_roundsh_sd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note]</description>
+	<operation>
+IF k[0]
+	dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
+ELSE
+	dst.fp64[0] := 0
+FI
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsh_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsh_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note]</description>
+	<operation>
+dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvtsh_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
+ELSE
+	dst.fp32[0] := src.fp32[0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_cvt_roundsh_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note]</description>
+	<operation>
+IF k[0]
+	dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
+ELSE
+	dst.fp32[0] := src.fp32[0]
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvtsh_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
+ELSE
+	dst.fp32[0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_cvt_roundsh_ss" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note]</description>
+	<operation>
+IF k[0]
+	dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
+ELSE
+	dst.fp32[0] := 0
+FI
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsh_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst.dword := Convert_FP16_To_Int32(a.fp16[0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTSH2SI" xed="VCVTSH2SI_GPR32i32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsh_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst.dword := Convert_FP16_To_Int32(a.fp16[0])
+	</operation>
+	<instruction form="r32, xmm {er}" name="VCVTSH2SI" xed="VCVTSH2SI_GPR32i32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsh_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst.qword := Convert_FP16_To_Int64(a.fp16[0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTSH2SI" xed="VCVTSH2SI_GPR64i64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsh_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst.qword := Convert_FP16_To_Int64(a.fp16[0])
+	</operation>
+	<instruction form="r64, xmm {er}" name="VCVTSH2SI" xed="VCVTSH2SI_GPR64i64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsh_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst.dword := Convert_FP16_To_Int32_Truncate(a.fp16[0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTTSH2SI" xed="VCVTTSH2SI_GPR32i32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsh_i32" tech="AVX-512">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". [sae_note]</description>
+	<operation>
+dst.dword := Convert_FP16_To_Int32_Truncate(a.fp16[0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTTSH2SI" xed="VCVTTSH2SI_GPR32i32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsh_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst.qword := Convert_FP16_To_Int64_Truncate(a.fp16[0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTTSH2SI" xed="VCVTTSH2SI_GPR64i64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsh_i64" tech="AVX-512">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". [sae_note]</description>
+	<operation>
+dst.qword := Convert_FP16_To_Int64_Truncate(a.fp16[0])
+	</operation>
+	<instruction form="r64, xmm {sae}" name="VCVTTSH2SI" xed="VCVTTSH2SI_GPR64i64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsh_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst.dword := Convert_FP16_To_UInt32(a.fp16[0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTSH2USI" xed="VCVTSH2USI_GPR32u32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsh_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst". [sae_note]</description>
+	<operation>
+dst.dword := Convert_FP16_To_UInt32(a.fp16[0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTSH2USI" xed="VCVTSH2USI_GPR32u32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsh_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst.qword := Convert_FP16_To_UInt64(a.fp16[0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTSH2USI" xed="VCVTSH2USI_GPR64u64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundsh_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst". [round_note]</description>
+	<operation>
+dst.qword := Convert_FP16_To_UInt64(a.fp16[0])
+	</operation>
+	<instruction form="r64, xmm {er}" name="VCVTSH2USI" xed="VCVTSH2USI_GPR64u64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsh_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst.dword := Convert_FP16_To_UInt32_Truncate(a.fp16[0])
+	</operation>
+	<instruction form="r32, xmm" name="VCVTTSH2USI" xed="VCVTTSH2USI_GPR32u32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsh_u32" tech="AVX-512">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst". [sae_note]</description>
+	<operation>
+dst.dword := Convert_FP16_To_UInt32_Truncate(a.fp16[0])
+	</operation>
+	<instruction form="r32, xmm {sae}" name="VCVTTSH2USI" xed="VCVTTSH2USI_GPR32u32_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsh_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst.qword := Convert_FP16_To_UInt64_Truncate(a.fp16[0])
+	</operation>
+	<instruction form="r64, xmm" name="VCVTTSH2USI" xed="VCVTTSH2USI_GPR64u64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_roundsh_u64" tech="AVX-512">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst". [sae_note]</description>
+	<operation>
+dst.qword := Convert_FP16_To_UInt64_Truncate(a.fp16[0])
+	</operation>
+	<instruction form="r64, xmm {sae}" name="VCVTTSH2USI" xed="VCVTTSH2USI_GPR64u64_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvti32_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<description>Convert the signed 32-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := Convert_Int32_To_FP16(b.fp32[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32" name="VCVTSI2SH" xed="VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundi32_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the signed 32-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := Convert_Int32_To_FP16(b.fp32[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32 {er}" name="VCVTSI2SH" xed="VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtu32_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<description>Convert the unsigned 32-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := Convert_Int32_To_FP16(b.fp32[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32" name="VCVTUSI2SH" xed="VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundu32_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the unsigned 32-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := Convert_Int32_To_FP16(b.fp32[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r32 {er}" name="VCVTUSI2SH" xed="VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvti64_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<description>Convert the signed 64-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := Convert_Int64_To_FP16(b.fp64[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64" name="VCVTSI2SH" xed="VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundi64_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the signed 64-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := Convert_Int64_To_FP16(b.fp64[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SH" xed="VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtu64_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<description>Convert the unsigned 64-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := Convert_Int64_To_FP16(b.fp64[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64" name="VCVTUSI2SH" xed="VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_roundu64_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the unsigned 64-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst.fp16[0] := Convert_Int64_To_FP16(b.fp64[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, r64 {er}" name="VCVTUSI2SH" xed="VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi16_si128" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Copy 16-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := a.fp16[0]
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm, r16" name="VMOVW" xed="VMOVW_XMMf16_GPR32f16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi128_si16" tech="AVX-512">
+	<return etype="UI16" type="short" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Copy the lower 16-bit integer in "a" to "dst".</description>
+	<operation>
+dst.fp16[0] := a.fp16[0]
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="r16, xmm" name="VMOVW" xed="VMOVW_GPR32f16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsh_h" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Copy the lower half-precision (16-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[15:0] := a.fp16[0]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtsh_h" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Copy the lower half-precision (16-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[15:0] := a.fp16[0]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_cvtsh_h" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="_Float16" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Copy the lower half-precision (16-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[15:0] := a.fp16[0]
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_max_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {sae}" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_max_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_max_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note][max_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_min_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [sae_note] [min_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {sae}" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_min_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note][min_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := src.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_min_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
+	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note][min_float_note]</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
+	ELSE
+		dst.fp16[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_reduce_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+IF k[0]
+	dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_reduce_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+IF k[0]
+	dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+IF k[0]
+	dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_reduce_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+IF k[0]
+	dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" memwidth="16" type="void const*" varname="mem_addr" />
+	<description>Load a half-precision (16-bit) floating-point element from memory into the lower element of "dst", and zero the upper elements.</description>
+	<operation>
+dst.fp16[0] := MEM[mem_addr].fp16[0]
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm, m64" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_load_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" memwidth="16" type="void const*" varname="mem_addr" />
+	<description>Load a half-precision (16-bit) floating-point element from memory into the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and set the upper elements of "dst" to zero.</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := MEM[mem_addr].fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm {k}, m64" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_load_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" memwidth="16" type="void const*" varname="mem_addr" />
+	<description>Load a half-precision (16-bit) floating-point element from memory into the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and set the upper elements of "dst" to zero.</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := MEM[mem_addr].fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="xmm {z}, m64" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_load_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_loadu_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" memwidth="512" type="void const*" varname="mem_addr" />
+	<description>Load 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[511:0] := MEM[mem_addr+511:mem_addr]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, m512" name="VMOVUPS" xed="VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_sh" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP16" memwidth="16" type="void *" varname="mem_addr" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Store the lower half-precision (16-bit) floating-point element from "a" into memory.</description>
+	<operation>
+MEM[mem_addr].fp16[0] := a.fp16[0]
+	</operation>
+	<instruction form="m16, xmm" name="VMOVSH" xed="VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_store_sh" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP16" memwidth="16" type="void *" varname="mem_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Store the lower half-precision (16-bit) floating-point element from "a" into memory using writemask "k".</description>
+	<operation>
+IF k[0]
+	MEM[mem_addr].fp16[0] := a.fp16[0]
+FI
+	</operation>
+	<instruction form="m16 {k}, xmm" name="VMOVSH" xed="VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_store_ph" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP16" memwidth="512" type="void *" varname="mem_addr" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Store 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_storeu_ph" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="FP16" memwidth="512" type="void *" varname="mem_addr" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Store 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+511:mem_addr] := a[511:0]
+	</operation>
+	<instruction form="m512, zmm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_move_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Move the lower half-precision (16-bit) floating-point element from "b" to the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := b.fp16[0]
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_move_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Move the lower half-precision (16-bit) floating-point element from "b" to the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := b.fp16[0]
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_move_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Move the lower half-precision (16-bit) floating-point element from "b" to the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := b.fp16[0]
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm512_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 31
+	dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+ENDFOR
+dest[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_roundscale_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 31
+	dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+ENDFOR
+dest[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dest[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_roundscale_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dest[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_roundscale_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dest[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_roundscale_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dest[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
+dst[127:16] := a[127:16]
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_roundscale_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
+dst[127:16] := a[127:16]
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+IF k[0]
+	dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_roundscale_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+IF k[0]
+	dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+IF k[0]
+	dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_roundscale_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
+	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
+	RETURN tmp.fp16
+}
+IF k[0]
+	dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dest[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 31
+	dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getexp_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. [sae_note]</description>
+	<operation>FOR i := 0 to 31
+	dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getexp_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. [sae_note]</description>
+	<operation>FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getexp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getexp_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. [sae_note]</description>
+	<operation>FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>dst.fp16[0] := ConvertExpFP16(b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getexp_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. [sae_note]</description>
+	<operation>dst.fp16[0] := ConvertExpFP16(b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>IF k[0]
+	dst.fp16[0] := ConvertExpFP16(b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getexp_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. [sae_note]</description>
+	<operation>IF k[0]
+	dst.fp16[0] := ConvertExpFP16(b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
+	<operation>IF k[0]
+	dst.fp16[0] := ConvertExpFP16(b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getexp_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. [sae_note]</description>
+	<operation>IF k[0]
+	dst.fp16[0] := ConvertExpFP16(b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+			[getmant_note]</description>
+	<operation>FOR i := 0 TO 31
+	dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_getmant_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+			[getmant_note][sae_note]</description>
+	<operation>FOR i := 0 TO 31
+	dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+			[getmant_note]</description>
+	<operation>FOR i := 0 TO 31
+	IF k[i]
+		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_getmant_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+			[getmant_note][sae_note]</description>
+	<operation>FOR i := 0 TO 31
+	IF k[i]
+		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getmant_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+			[getmant_note]</description>
+	<operation>FOR i := 0 TO 31
+	IF k[i]
+		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_getmant_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+			[getmant_note][sae_note]</description>
+	<operation>FOR i := 0 TO 31
+	IF k[i]
+		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note]</description>
+	<operation>dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_getmant_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note]</description>
+	<operation>IF k[0]
+	dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_getmant_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>IF k[0]
+	dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note]</description>
+	<operation>IF k[0]
+	dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_getmant_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
+	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
+	[getmant_note][sae_note]</description>
+	<operation>IF k[0]
+	dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 31
+	dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_reduce_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 31
+	dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {sae}, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_reduce_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {sae}, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_reduce_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_reduce_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
+	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
+	<operation>
+DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
+	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
+	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
+	tmp[15:0] := src[15:0] - tmp[15:0]
+	IF IsInf(tmp[15:0])
+		tmp[15:0] := FP16(0.0)
+	FI
+	RETURN tmp[15:0]
+}
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {sae}, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_scalef_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst".
+	[round_note]</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm {er}" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_scalef_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm {er}" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_scalef_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_scalef_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+FOR i := 0 to 15
+	IF k[i]
+		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm {er}" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_scalef_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+IF k[0]
+	dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_scalef_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+IF k[0]
+	dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+IF k[0]
+	dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_scalef_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>DEFINE ScaleFP16(src1, src2) {
+	denormal1 := (a.exp == 0) and (a.fraction != 0)
+	denormal2 := (b.exp == 0) and (b.fraction != 0)
+	tmp1 := src1
+	tmp2 := src2
+	IF MXCSR.DAZ
+		IF denormal1
+			tmp1 := 0
+		FI
+		IF denormal2
+			tmp2 := 0
+		FI
+	FI
+	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
+}
+IF k[0]
+	dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_fpclass_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
+				[fpclass_note]</description>
+	<operation>FOR i := 0 to 31
+	k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k, zmm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_fpclass_ph_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="MASK" type="__mmask32" varname="k1" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
+			[fpclass_note]</description>
+	<operation>FOR i := 0 to 31
+	IF k1[i]
+		k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
+	ELSE
+		k[i] := 0
+	FI
+ENDFOR
+k[MAX:32] := 0
+	</operation>
+	<instruction form="k {k}, zmm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_fpclass_sh_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test the lower half-precision (16-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k".
+			[fpclass_note]</description>
+	<operation>k[0] := CheckFPClass_FP16(a.fp16[0], imm8[7:0])
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k, xmm, imm8" name="VFPCLASSSH" xed="VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_fpclass_sh_mask" tech="AVX-512">
+	<return etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="MASK" type="__mmask8" varname="k1" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Test the lower half-precision (16-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).
+		[fpclass_note]</description>
+	<operation>IF k1[0]
+	k[0] := CheckFPClass_FP16(a.fp16[0], imm8[7:0])
+ELSE
+	k[0] := 0
+FI
+k[MAX:1] := 0
+	</operation>
+	<instruction form="k {k}, xmm, imm8" name="VFPCLASSSH" xed="VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex2var_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Shuffle half-precision (16-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	off := idx[i+4:i]
+	dst.fp16[j] := idx[i+5] ? b.fp16[off] : a.fp16[off]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMI2W" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<instruction form="zmm, zmm, zmm" name="VPERMT2W" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_blend_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="FP16" type="__m512h" varname="b" />
+	<description>Blend packed half-precision (16-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	IF k[j]
+		dst.fp16[j] := b.fp16[j]
+	ELSE
+		dst.fp16[j] := a.fp16[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMW" xed="VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutexvar_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="idx" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Shuffle half-precision (16-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	id := idx[i+4:i]
+	dst.fp16[j] := a.fp16[id]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMW" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 31
+	dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VRSQRTPH" xed="VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VRSQRTPH" xed="VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rsqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VRSQRTPH" xed="VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rsqrt_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+dst.fp16[0] := (1.0 / SQRT(b.fp16[0]))
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VRSQRTSH" xed="VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rsqrt_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (1.0 / SQRT(b.fp16[0]))
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VRSQRTSH" xed="VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rsqrt_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (1.0 / SQRT(b.fp16[0]))
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VRSQRTSH" xed="VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR i := 0 to 31
+	dst.fp16[i] := SQRT(a.fp16[i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_sqrt_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 31
+	dst.fp16[i] := SQRT(a.fp16[i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm {er}" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := SQRT(a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_sqrt_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := SQRT(a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm {er}" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sqrt_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := SQRT(a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_sqrt_round_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
+	[round_note]</description>
+	<operation>
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := SQRT(a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm {er}" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst.fp16[0] := SQRT(b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+dst.fp16[0] := SQRT(b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm {er}" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := SQRT(b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_sqrt_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := SQRT(b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm {er}" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := SQRT(b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_sqrt_round_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
+	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
+		[round_note]</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := SQRT(b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm {er}" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 31
+	dst.fp16[i] := (1.0 / a.fp16[i])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm" name="VRCPPH" xed="VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := (1.0 / a.fp16[i])
+	ELSE
+		dst.fp16[i] := src.fp16[i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VRCPPH" xed="VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_rcp_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR i := 0 to 31
+	IF k[i]
+		dst.fp16[i] := (1.0 / a.fp16[i])
+	ELSE
+		dst.fp16[i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VRCPPH" xed="VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rcp_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+dst.fp16[0] := (1.0 / b.fp16[0])
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VRCPSH" xed="VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_rcp_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (1.0 / b.fp16[0])
+ELSE
+	dst.fp16[0] := src.fp16[0]
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VRCPSH" xed="VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_rcp_sh" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<parameter etype="FP16" type="__m128h" varname="b" />
+	<description>Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+IF k[0]
+	dst.fp16[0] := (1.0 / b.fp16[0])
+ELSE
+	dst.fp16[0] := 0
+FI
+dst[127:16] := a[127:16]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VRCPSH" xed="VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="e7" />
+	<parameter etype="FP16" type="_Float16" varname="e6" />
+	<parameter etype="FP16" type="_Float16" varname="e5" />
+	<parameter etype="FP16" type="_Float16" varname="e4" />
+	<parameter etype="FP16" type="_Float16" varname="e3" />
+	<parameter etype="FP16" type="_Float16" varname="e2" />
+	<parameter etype="FP16" type="_Float16" varname="e1" />
+	<parameter etype="FP16" type="_Float16" varname="e0" />
+	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst.fp16[0] := e0
+dst.fp16[1] := e1
+dst.fp16[2] := e2
+dst.fp16[3] := e3
+dst.fp16[4] := e4
+dst.fp16[5] := e5
+dst.fp16[6] := e6
+dst.fp16[7] := e7
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="e15" />
+	<parameter etype="FP16" type="_Float16" varname="e14" />
+	<parameter etype="FP16" type="_Float16" varname="e13" />
+	<parameter etype="FP16" type="_Float16" varname="e12" />
+	<parameter etype="FP16" type="_Float16" varname="e11" />
+	<parameter etype="FP16" type="_Float16" varname="e10" />
+	<parameter etype="FP16" type="_Float16" varname="e9" />
+	<parameter etype="FP16" type="_Float16" varname="e8" />
+	<parameter etype="FP16" type="_Float16" varname="e7" />
+	<parameter etype="FP16" type="_Float16" varname="e6" />
+	<parameter etype="FP16" type="_Float16" varname="e5" />
+	<parameter etype="FP16" type="_Float16" varname="e4" />
+	<parameter etype="FP16" type="_Float16" varname="e3" />
+	<parameter etype="FP16" type="_Float16" varname="e2" />
+	<parameter etype="FP16" type="_Float16" varname="e1" />
+	<parameter etype="FP16" type="_Float16" varname="e0" />
+	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst.fp16[0] := e0
+dst.fp16[1] := e1
+dst.fp16[2] := e2
+dst.fp16[3] := e3
+dst.fp16[4] := e4
+dst.fp16[5] := e5
+dst.fp16[6] := e6
+dst.fp16[7] := e7
+dst.fp16[8] := e8
+dst.fp16[9] := e9
+dst.fp16[10] := e10
+dst.fp16[11] := e11
+dst.fp16[12] := e12
+dst.fp16[13] := e13
+dst.fp16[14] := e14
+dst.fp16[15] := e15
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="e31" />
+	<parameter etype="FP16" type="_Float16" varname="e30" />
+	<parameter etype="FP16" type="_Float16" varname="e29" />
+	<parameter etype="FP16" type="_Float16" varname="e28" />
+	<parameter etype="FP16" type="_Float16" varname="e27" />
+	<parameter etype="FP16" type="_Float16" varname="e26" />
+	<parameter etype="FP16" type="_Float16" varname="e25" />
+	<parameter etype="FP16" type="_Float16" varname="e24" />
+	<parameter etype="FP16" type="_Float16" varname="e23" />
+	<parameter etype="FP16" type="_Float16" varname="e22" />
+	<parameter etype="FP16" type="_Float16" varname="e21" />
+	<parameter etype="FP16" type="_Float16" varname="e20" />
+	<parameter etype="FP16" type="_Float16" varname="e19" />
+	<parameter etype="FP16" type="_Float16" varname="e18" />
+	<parameter etype="FP16" type="_Float16" varname="e17" />
+	<parameter etype="FP16" type="_Float16" varname="e16" />
+	<parameter etype="FP16" type="_Float16" varname="e15" />
+	<parameter etype="FP16" type="_Float16" varname="e14" />
+	<parameter etype="FP16" type="_Float16" varname="e13" />
+	<parameter etype="FP16" type="_Float16" varname="e12" />
+	<parameter etype="FP16" type="_Float16" varname="e11" />
+	<parameter etype="FP16" type="_Float16" varname="e10" />
+	<parameter etype="FP16" type="_Float16" varname="e9" />
+	<parameter etype="FP16" type="_Float16" varname="e8" />
+	<parameter etype="FP16" type="_Float16" varname="e7" />
+	<parameter etype="FP16" type="_Float16" varname="e6" />
+	<parameter etype="FP16" type="_Float16" varname="e5" />
+	<parameter etype="FP16" type="_Float16" varname="e4" />
+	<parameter etype="FP16" type="_Float16" varname="e3" />
+	<parameter etype="FP16" type="_Float16" varname="e2" />
+	<parameter etype="FP16" type="_Float16" varname="e1" />
+	<parameter etype="FP16" type="_Float16" varname="e0" />
+	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst.fp16[0] := e0
+dst.fp16[1] := e1
+dst.fp16[2] := e2
+dst.fp16[3] := e3
+dst.fp16[4] := e4
+dst.fp16[5] := e5
+dst.fp16[6] := e6
+dst.fp16[7] := e7
+dst.fp16[8] := e8
+dst.fp16[9] := e9
+dst.fp16[10] := e10
+dst.fp16[11] := e11
+dst.fp16[12] := e12
+dst.fp16[13] := e13
+dst.fp16[14] := e14
+dst.fp16[15] := e15
+dst.fp16[16] := e16
+dst.fp16[17] := e17
+dst.fp16[18] := e18
+dst.fp16[19] := e19
+dst.fp16[20] := e20
+dst.fp16[21] := e21
+dst.fp16[22] := e22
+dst.fp16[23] := e23
+dst.fp16[24] := e24
+dst.fp16[25] := e25
+dst.fp16[26] := e26
+dst.fp16[27] := e27
+dst.fp16[28] := e28
+dst.fp16[29] := e29
+dst.fp16[30] := e30
+dst.fp16[31] := e31
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="e7" />
+	<parameter etype="FP16" type="_Float16" varname="e6" />
+	<parameter etype="FP16" type="_Float16" varname="e5" />
+	<parameter etype="FP16" type="_Float16" varname="e4" />
+	<parameter etype="FP16" type="_Float16" varname="e3" />
+	<parameter etype="FP16" type="_Float16" varname="e2" />
+	<parameter etype="FP16" type="_Float16" varname="e1" />
+	<parameter etype="FP16" type="_Float16" varname="e0" />
+	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst.fp16[0] := e7
+dst.fp16[1] := e6
+dst.fp16[2] := e5
+dst.fp16[3] := e4
+dst.fp16[4] := e3
+dst.fp16[5] := e2
+dst.fp16[6] := e1
+dst.fp16[7] := e0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_setr_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="e15" />
+	<parameter etype="FP16" type="_Float16" varname="e14" />
+	<parameter etype="FP16" type="_Float16" varname="e13" />
+	<parameter etype="FP16" type="_Float16" varname="e12" />
+	<parameter etype="FP16" type="_Float16" varname="e11" />
+	<parameter etype="FP16" type="_Float16" varname="e10" />
+	<parameter etype="FP16" type="_Float16" varname="e9" />
+	<parameter etype="FP16" type="_Float16" varname="e8" />
+	<parameter etype="FP16" type="_Float16" varname="e7" />
+	<parameter etype="FP16" type="_Float16" varname="e6" />
+	<parameter etype="FP16" type="_Float16" varname="e5" />
+	<parameter etype="FP16" type="_Float16" varname="e4" />
+	<parameter etype="FP16" type="_Float16" varname="e3" />
+	<parameter etype="FP16" type="_Float16" varname="e2" />
+	<parameter etype="FP16" type="_Float16" varname="e1" />
+	<parameter etype="FP16" type="_Float16" varname="e0" />
+	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst.fp16[0] := e15
+dst.fp16[1] := e14
+dst.fp16[2] := e13
+dst.fp16[3] := e12
+dst.fp16[4] := e11
+dst.fp16[5] := e10
+dst.fp16[6] := e9
+dst.fp16[7] := e8
+dst.fp16[8] := e7
+dst.fp16[9] := e6
+dst.fp16[10] := e5
+dst.fp16[11] := e4
+dst.fp16[12] := e3
+dst.fp16[13] := e2
+dst.fp16[14] := e1
+dst.fp16[15] := e0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setr_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="e31" />
+	<parameter etype="FP16" type="_Float16" varname="e30" />
+	<parameter etype="FP16" type="_Float16" varname="e29" />
+	<parameter etype="FP16" type="_Float16" varname="e28" />
+	<parameter etype="FP16" type="_Float16" varname="e27" />
+	<parameter etype="FP16" type="_Float16" varname="e26" />
+	<parameter etype="FP16" type="_Float16" varname="e25" />
+	<parameter etype="FP16" type="_Float16" varname="e24" />
+	<parameter etype="FP16" type="_Float16" varname="e23" />
+	<parameter etype="FP16" type="_Float16" varname="e22" />
+	<parameter etype="FP16" type="_Float16" varname="e21" />
+	<parameter etype="FP16" type="_Float16" varname="e20" />
+	<parameter etype="FP16" type="_Float16" varname="e19" />
+	<parameter etype="FP16" type="_Float16" varname="e18" />
+	<parameter etype="FP16" type="_Float16" varname="e17" />
+	<parameter etype="FP16" type="_Float16" varname="e16" />
+	<parameter etype="FP16" type="_Float16" varname="e15" />
+	<parameter etype="FP16" type="_Float16" varname="e14" />
+	<parameter etype="FP16" type="_Float16" varname="e13" />
+	<parameter etype="FP16" type="_Float16" varname="e12" />
+	<parameter etype="FP16" type="_Float16" varname="e11" />
+	<parameter etype="FP16" type="_Float16" varname="e10" />
+	<parameter etype="FP16" type="_Float16" varname="e9" />
+	<parameter etype="FP16" type="_Float16" varname="e8" />
+	<parameter etype="FP16" type="_Float16" varname="e7" />
+	<parameter etype="FP16" type="_Float16" varname="e6" />
+	<parameter etype="FP16" type="_Float16" varname="e5" />
+	<parameter etype="FP16" type="_Float16" varname="e4" />
+	<parameter etype="FP16" type="_Float16" varname="e3" />
+	<parameter etype="FP16" type="_Float16" varname="e2" />
+	<parameter etype="FP16" type="_Float16" varname="e1" />
+	<parameter etype="FP16" type="_Float16" varname="e0" />
+	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst.fp16[0] := e31
+dst.fp16[1] := e30
+dst.fp16[2] := e29
+dst.fp16[3] := e28
+dst.fp16[4] := e27
+dst.fp16[5] := e26
+dst.fp16[6] := e25
+dst.fp16[7] := e24
+dst.fp16[8] := e23
+dst.fp16[9] := e22
+dst.fp16[10] := e21
+dst.fp16[11] := e20
+dst.fp16[12] := e19
+dst.fp16[13] := e18
+dst.fp16[14] := e17
+dst.fp16[15] := e16
+dst.fp16[16] := e15
+dst.fp16[17] := e14
+dst.fp16[18] := e13
+dst.fp16[19] := e12
+dst.fp16[20] := e11
+dst.fp16[21] := e10
+dst.fp16[22] := e9
+dst.fp16[23] := e8
+dst.fp16[24] := e7
+dst.fp16[25] := e6
+dst.fp16[26] := e5
+dst.fp16[27] := e4
+dst.fp16[28] := e3
+dst.fp16[29] := e2
+dst.fp16[30] := e1
+dst.fp16[31] := e0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="a" />
+	<description>Broadcast half-precision (16-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[i] := a[15:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set1_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="a" />
+	<description>Broadcast half-precision (16-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[i] := a[15:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set1_ph" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="a" />
+	<description>Broadcast half-precision (16-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR i := 0 to 31
+	dst.fp16[i] := a[15:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="_Float16 _Complex" varname="a" />
+	<description>Broadcast half-precision (16-bit) complex floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR i := 0 to 3
+	dst.fp16[2*i+0] := a[15:0]
+	dst.fp16[2*i+1] := a[31:16]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm256_set1_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="_Float16 _Complex" varname="a" />
+	<description>Broadcast half-precision (16-bit) complex floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR i := 0 to 7
+	dst.fp16[2*i+0] := a[15:0]
+	dst.fp16[2*i+1] := a[31:16]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_set1_pch" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="_Float16 _Complex" varname="a" />
+	<description>Broadcast half-precision (16-bit) complex floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR i := 0 to 15
+	dst.fp16[2*i+0] := a[15:0]
+	dst.fp16[2*i+1] := a[31:16]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_sh" sequence="TRUE" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="_Float16" varname="a" />
+	<description>Copy half-precision (16-bit) floating-point element "a" to the lower element of "dst", and zero the upper 7 elements.</description>
+	<operation>
+dst.fp16[0] := a[15:0]
+dst[127:16] := 0
+	</operation>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm512_setzero_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<description>Return vector of type __m512h with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_castph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Cast vector of type "__m128h" to type "__m128". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Cast vector of type "__m256h" to type "__m256". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castph_ps" tech="AVX-512">
+	<return etype="FP32" type="__m512" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Cast vector of type "__m512h" to type "__m512". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Cast vector of type "__m128h" to type "__m128d". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Cast vector of type "__m256h" to type "__m256d". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castph_pd" tech="AVX-512">
+	<return etype="FP64" type="__m512d" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Cast vector of type "__m512h" to type "__m512d". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castph_si128" tech="AVX-512">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Cast vector of type "__m128h" to type "__m128i". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castph_si256" tech="AVX-512">
+	<return etype="M256" type="__m256i" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Cast vector of type "__m256h" to type "__m256i". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castph_si512" tech="AVX-512">
+	<return etype="M512" type="__m512i" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Cast vector of type "__m512h" to type "__m512i". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Cast vector of type "__m128" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<description>Cast vector of type "__m256" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castps_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP32" type="__m512" varname="a" />
+	<description>Cast vector of type "__m512" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Cast vector of type "__m128d" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<description>Cast vector of type "__m256d" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castpd_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP64" type="__m512d" varname="a" />
+	<description>Cast vector of type "__m512d" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castsi128_ph" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Cast vector of type "__m128i" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castsi256_ph" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Cast vector of type "__m256i" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castsi512_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Cast vector of type "__m512i" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castph256_ph128" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Cast vector of type "__m256h" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castph512_ph128" tech="AVX-512">
+	<return etype="FP16" type="__m128h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Cast vector of type "__m512h" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castph512_ph256" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m512h" varname="a" />
+	<description>Cast vector of type "__m512h" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_castph128_ph256" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Cast vector of type "__m128h" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castph128_ph512" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Cast vector of type "__m128h" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_castph256_ph512" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Cast vector of type "__m256h" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm256_zextph128_ph256" tech="AVX-512">
+	<return etype="FP16" type="__m256h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Cast vector of type "__m128h" to type "__m256h"; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_zextph128_ph512" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m128h" varname="a" />
+	<description>Cast vector of type "__m128h" to type "__m512h"; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_zextph256_ph512" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<parameter etype="FP16" type="__m256h" varname="a" />
+	<description>Cast vector of type "__m256h" to type "__m512h"; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm512_undefined_ph" tech="AVX-512">
+	<return etype="FP16" type="__m512h" varname="dst" />
+	<description>Return vector of type __m512h with undefined elements.</description>
+	<CPUID>AVX512_FP16</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst".</description>
+	<operation>
+FOR i := 0 to 3
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		dst[q+j*8+7:q+j*8] := tmp8[7:0]
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 3
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		IF k[i*8+j]
+			dst[q+j*8+7:q+j*8] := tmp8[7:0]
+		ELSE
+			dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 3
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		IF k[i*8+j]
+			dst[q+j*8+7:q+j*8] := tmp8[7:0]
+		ELSE
+			dst[q+j*8+7:q+j*8] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst".</description>
+	<operation>
+FOR i := 0 to 1
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		dst[q+j*8+7:q+j*8] := tmp8[7:0]
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 1
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		IF k[i*8+j]
+			dst[q+j*8+7:q+j*8] := tmp8[7:0]
+		ELSE
+			dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 1
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		IF k[i*8+j]
+			dst[q+j*8+7:q+j*8] := tmp8[7:0]
+		ELSE
+			dst[q+j*8+7:q+j*8] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="idx" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	id := idx[i+4:i]*8
+	dst[i+7:i] := a[id+7:id]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMB" xed="VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="idx" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	id := idx[i+4:i]*8
+	IF k[j]
+		dst[i+7:i] := a[id+7:id]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMB" xed="VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="idx" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	id := idx[i+4:i]*8
+	IF k[j]
+		dst[i+7:i] := a[id+7:id]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMB" xed="VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="idx" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	id := idx[i+3:i]*8
+	dst[i+7:i] := a[id+7:id]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMB" xed="VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="idx" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	id := idx[i+3:i]*8
+	IF k[j]
+		dst[i+7:i] := a[id+7:id]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMB" xed="VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="idx" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	id := idx[i+3:i]*8
+	IF k[j]
+		dst[i+7:i] := a[id+7:id]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMB" xed="VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="idx" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	off := 8*idx[i+4:i]
+	dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPERMI2B" xed="VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="idx" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+4:i]
+		dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2B" xed="VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask2_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="idx" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+4:i]
+		dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := idx[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2B" xed="VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="idx" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+4:i]
+		dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2B" xed="VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2B" xed="VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="idx" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	off := 8*idx[i+3:i]
+	dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPERMI2B" xed="VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="idx" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+3:i]
+		dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2B" xed="VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask2_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="idx" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+3:i]
+		dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := idx[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2B" xed="VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="idx" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+3:i]
+		dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2B" xed="VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2B" xed="VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst".</description>
+	<operation>
+FOR i := 0 to 7
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		dst[q+j*8+7:q+j*8] := tmp8[7:0]
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 7
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		IF k[i*8+j]
+			dst[q+j*8+7:q+j*8] := tmp8[7:0]
+		ELSE
+			dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_multishift_epi64_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR i := 0 to 7
+	q := i * 64
+	FOR j := 0 to 7
+		tmp8 := 0
+		ctrl := a[q+j*8+7:q+j*8] &amp; 63
+		FOR l := 0 to 7
+			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
+		ENDFOR
+		IF k[i*8+j]
+			dst[q+j*8+7:q+j*8] := tmp8[7:0]
+		ELSE
+			dst[q+j*8+7:q+j*8] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="idx" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	id := idx[i+5:i]*8
+	dst[i+7:i] := a[id+7:id]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMB" xed="VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="idx" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	id := idx[i+5:i]*8
+	IF k[j]
+		dst[i+7:i] := a[id+7:id]
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMB" xed="VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutexvar_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="idx" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	id := idx[i+5:i]*8
+	IF k[j]
+		dst[i+7:i] := a[id+7:id]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMB" xed="VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="idx" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	off := 8*idx[i+5:i]
+	dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPERMI2B" xed="VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="idx" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+5:i]
+		dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2B" xed="VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask2_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="idx" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+5:i]
+		dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := idx[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2B" xed="VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_permutex2var_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="idx" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		off := 8*idx[i+5:i]
+		dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off]
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2B" xed="VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2B" xed="VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_maskz_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSHRDVQ" xed="VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSHRDVQ" xed="VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSHRDVQ" xed="VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSHRDVQ" xed="VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSHRDVQ" xed="VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSHRDVQ" xed="VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSHRDVD" xed="VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSHRDVD" xed="VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSHRDVD" xed="VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSHRDVD" xed="VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSHRDVD" xed="VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSHRDVD" xed="VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="UI16" type="__m256i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSHRDVW" xed="VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="UI16" type="__m256i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSHRDVW" xed="VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="UI16" type="__m256i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSHRDVW" xed="VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="UI16" type="__m128i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSHRDVW" xed="VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="UI16" type="__m128i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSHRDVW" xed="VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="UI16" type="__m128i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSHRDVW" xed="VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHRDQ" xed="VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHRDQ" xed="VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPSHRDQ" xed="VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHRDD" xed="VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHRDD" xed="VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPSHRDD" xed="VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHRDD" xed="VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHRDD" xed="VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPSHRDD" xed="VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHRDW" xed="VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHRDW" xed="VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPSHRDW" xed="VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHRDW" xed="VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHRDW" xed="VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPSHRDW" xed="VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSHLDVQ" xed="VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSHLDVQ" xed="VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="UI64" type="__m256i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+	dst[i+63:i] := tmp[127:64]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSHLDVQ" xed="VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSHLDVQ" xed="VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSHLDVQ" xed="VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="UI64" type="__m128i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+	dst[i+63:i] := tmp[127:64]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSHLDVQ" xed="VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSHLDVD" xed="VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSHLDVD" xed="VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="UI32" type="__m256i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+	dst[i+31:i] := tmp[63:32]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSHLDVD" xed="VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSHLDVD" xed="VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSHLDVD" xed="VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+	dst[i+31:i] := tmp[63:32]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSHLDVD" xed="VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="UI16" type="__m256i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPSHLDVW" xed="VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="UI16" type="__m256i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPSHLDVW" xed="VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="UI16" type="__m256i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPSHLDVW" xed="VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="UI16" type="__m128i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPSHLDVW" xed="VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="UI16" type="__m128i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPSHLDVW" xed="VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="UI16" type="__m128i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPSHLDVW" xed="VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHLDQ" xed="VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHLDQ" xed="VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst").</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+	dst[i+63:i] := tmp[127:64]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPSHLDQ" xed="VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst").</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+	dst[i+63:i] := tmp[127:64]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHLDD" xed="VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHLDD" xed="VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m256i" varname="dst" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+	dst[i+31:i] := tmp[63:32]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPSHLDD" xed="VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHLDD" xed="VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHLDD" xed="VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+	dst[i+31:i] := tmp[63:32]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPSHLDD" xed="VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHLDW" xed="VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHLDW" xed="VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<parameter etype="UI16" type="__m256i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst").</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*16
+	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPSHLDW" xed="VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHLDW" xed="VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHLDW" xed="VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst").</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VPSHLDW" xed="VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expandloadu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" memwidth="256" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m256" name="VPEXPANDW" xed="VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expandloadu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" memwidth="256" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m256" name="VPEXPANDW" xed="VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expandloadu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" memwidth="128" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m128" name="VPEXPANDW" xed="VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expandloadu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" memwidth="128" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m128" name="VPEXPANDW" xed="VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expandloadu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" memwidth="256" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, m256" name="VPEXPANDB" xed="VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expandloadu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" memwidth="256" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, m256" name="VPEXPANDB" xed="VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expandloadu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" memwidth="128" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, m128" name="VPEXPANDB" xed="VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expandloadu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" memwidth="128" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, m128" name="VPEXPANDB" xed="VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expand_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[m+15:m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPEXPANDW" xed="VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expand_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[m+15:m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPEXPANDW" xed="VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expand_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[m+15:m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPEXPANDW" xed="VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expand_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[m+15:m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPEXPANDW" xed="VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_expand_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[m+7:m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPEXPANDB" xed="VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_expand_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[m+7:m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPEXPANDB" xed="VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_expand_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[m+7:m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPEXPANDB" xed="VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_expand_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[m+7:m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPEXPANDB" xed="VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_compress_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 16
+m := 0
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPCOMPRESSW" xed="VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compress_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m256i" varname="dst" />
+	<parameter etype="UI16" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 16
+m := 0
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		dst[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := src[255:m]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPCOMPRESSW" xed="VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_compress_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 16
+m := 0
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compress_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 16
+m := 0
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		dst[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := src[127:m]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_compress_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 8
+m := 0
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := 0
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm" name="VPCOMPRESSB" xed="VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compress_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 8
+m := 0
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		dst[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+dst[255:m] := src[255:m]
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm" name="VPCOMPRESSB" xed="VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_compress_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 8
+m := 0
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := 0
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compress_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 8
+m := 0
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		dst[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+dst[127:m] := src[127:m]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compressstoreu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI16" type="__m256i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 16
+m := base_addr
+FOR j := 0 to 15
+	i := j*16
+	IF k[j]
+		MEM[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VPCOMPRESSW" xed="VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compressstoreu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 16
+m := base_addr
+FOR j := 0 to 7
+	i := j*16
+	IF k[j]
+		MEM[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_compressstoreu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="256" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 8
+m := base_addr
+FOR j := 0 to 31
+	i := j*8
+	IF k[j]
+		MEM[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m256 {k}, ymm" name="VPCOMPRESSB" xed="VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_compressstoreu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 8
+m := base_addr
+FOR j := 0 to 15
+	i := j*8
+	IF k[j]
+		MEM[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m128 {k}, xmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_maskz_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSHRDVQ" xed="VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSHRDVQ" xed="VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shrdv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSHRDVQ" xed="VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSHRDVD" xed="VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSHRDVD" xed="VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shrdv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSHRDVD" xed="VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="UI16" type="__m512i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSHRDVW" xed="VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="UI16" type="__m512i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSHRDVW" xed="VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shrdv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="UI16" type="__m512i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSHRDVW" xed="VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shrdi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHRDD" xed="VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHRDD" xed="VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shrdi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPSHRDD" xed="VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHRDW" xed="VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHRDW" xed="VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shrdi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPSHRDW" xed="VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSHLDVQ" xed="VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSHLDVQ" xed="VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shldv_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="UI64" type="__m512i" varname="c" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
+	dst[i+63:i] := tmp[127:64]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSHLDVQ" xed="VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSHLDVD" xed="VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSHLDVD" xed="VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shldv_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="UI32" type="__m512i" varname="c" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
+	dst[i+31:i] := tmp[63:32]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSHLDVD" xed="VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="UI16" type="__m512i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPSHLDVW" xed="VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="UI16" type="__m512i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPSHLDVW" xed="VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shldv_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="UI16" type="__m512i" varname="c" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPSHLDVW" xed="VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	IF k[j]
+		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+		dst[i+63:i] := tmp[127:64]
+	ELSE
+		dst[i+63:i] := src[i+63:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shldi_epi64" tech="AVX-512">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst").</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*64
+	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
+	dst[i+63:i] := tmp[127:64]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHLDD" xed="VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	IF k[j]
+		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+		dst[i+31:i] := tmp[63:32]
+	ELSE
+		dst[i+31:i] := src[i+31:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHLDD" xed="VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shldi_epi32" tech="AVX-512">
+	<return etype="UI32" type="__m512i" varname="dst" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*32
+	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
+	dst[i+31:i] := tmp[63:32]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPSHLDD" xed="VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHLDW" xed="VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+		dst[i+15:i] := tmp[31:16]
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHLDW" xed="VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_shldi_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<parameter etype="UI16" type="__m512i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst").</description>
+	<operation>
+FOR j := 0 to 31
+	i := j*16
+	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPSHLDW" xed="VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expandloadu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" memwidth="512" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VPEXPANDW" xed="VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expandloadu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" memwidth="512" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VPEXPANDW" xed="VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expandloadu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" memwidth="512" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, m512" name="VPEXPANDB" xed="VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expandloadu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" memwidth="512" type="const void*" varname="mem_addr" />
+	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, m512" name="VPEXPANDB" xed="VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expand_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[m+15:m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPEXPANDW" xed="VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expand_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[i+15:i] := a[m+15:m]
+		m := m + 16
+	ELSE
+		dst[i+15:i] := src[i+15:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPEXPANDW" xed="VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_expand_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[m+7:m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPEXPANDB" xed="VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_expand_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+m := 0
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[i+7:i] := a[m+7:m]
+		m := m + 8
+	ELSE
+		dst[i+7:i] := src[i+7:i]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPEXPANDB" xed="VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_compress_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 16
+m := 0
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := 0
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compress_epi16" tech="AVX-512">
+	<return etype="UI16" type="__m512i" varname="dst" />
+	<parameter etype="UI16" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 16
+m := 0
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		dst[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := src[511:m]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_compress_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
+	<operation>
+size := 8
+m := 0
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := 0
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compress_epi8" tech="AVX-512">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
+	<operation>
+size := 8
+m := 0
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		dst[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+dst[511:m] := src[511:m]
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compressstoreu_epi16" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="UI16" memwidth="512" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI16" type="__m512i" varname="a" />
+	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 16
+m := base_addr
+FOR j := 0 to 31
+	i := j*16
+	IF k[j]
+		MEM[m+size-1:m] := a[i+15:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_compressstoreu_epi8" tech="AVX-512">
+	<category>Swizzle</category>
+	<return type="void" />
+	<parameter etype="UI8" memwidth="512" type="void*" varname="base_addr" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
+	<operation>
+size := 8
+m := base_addr
+FOR j := 0 to 63
+	i := j*8
+	IF k[j]
+		MEM[m+size-1:m] := a[i+7:i]
+		m := m + size
+	FI
+ENDFOR
+	</operation>
+	<instruction form="m512 {k}, zmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512" />
+	<CPUID>AVX512_VBMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_maskz_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPDPWSSDS" xed="VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPDPWSSDS" xed="VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPDPWSSDS" xed="VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPDPWSSDS" xed="VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPDPWSSDS" xed="VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPDPWSSDS" xed="VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPDPWSSD" xed="VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPDPWSSD" xed="VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="SI16" type="__m256i" varname="a" />
+	<parameter etype="SI16" type="__m256i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPDPWSSD" xed="VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPDPWSSD" xed="VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPDPWSSD" xed="VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPDPWSSD" xed="VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPDPBUSDS" xed="VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPDPBUSDS" xed="VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPDPBUSDS" xed="VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPDPBUSDS" xed="VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPDPBUSDS" xed="VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPDPBUSDS" xed="VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VPDPBUSD" xed="VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 7
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VPDPBUSD" xed="VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m256i" varname="dst" />
+	<parameter etype="SI32" type="__m256i" varname="src" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="SI8" type="__m256i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VPDPBUSD" xed="VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VPDPBUSD" xed="VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask8" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 3
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VPDPBUSD" xed="VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="src" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VPDPBUSD" xed="VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_maskz_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPDPWSSDS" xed="VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPDPWSSDS" xed="VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_dpwssds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPDPWSSDS" xed="VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPDPWSSD" xed="VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPDPWSSD" xed="VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_dpwssd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="SI16" type="__m512i" varname="a" />
+	<parameter etype="SI16" type="__m512i" varname="b" />
+	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPDPWSSD" xed="VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPDPBUSDS" xed="VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPDPBUSDS" xed="VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_dpbusds_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPDPBUSDS" xed="VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+	ELSE
+		dst.dword[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VPDPBUSD" xed="VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+FOR j := 0 to 15
+	IF k[j]
+		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+	ELSE
+		dst.dword[j] := src.dword[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VPDPBUSD" xed="VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_dpbusd_epi32" tech="AVX-512">
+	<return etype="SI32" type="__m512i" varname="dst" />
+	<parameter etype="SI32" type="__m512i" varname="src" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="SI8" type="__m512i" varname="b" />
+	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VPDPBUSD" xed="VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
+	<CPUID>AVX512_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_2intersect_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="__m512i" varname="a" />
+	<parameter etype="UI32" type="__m512i" varname="b" />
+	<parameter etype="MASK" memwidth="16" type="__mmask16*" varname="k1" />
+	<parameter etype="MASK" memwidth="16" type="__mmask16*" varname="k2" />
+	<description>Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
+	<operation>
+MEM[k1+15:k1] := 0
+MEM[k2+15:k2] := 0
+FOR i := 0 TO 15
+	FOR j := 0 TO 15
+		match := (a.dword[i] == b.dword[j] ? 1 : 0)
+		MEM[k1+15:k1].bit[i] |= match
+		MEM[k2+15:k2].bit[j] |= match
+	ENDFOR
+ENDFOR
+	</operation>
+	<instruction form="k, zmm, zmm" name="VP2INTERSECTD" xed="VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512" />
+	<CPUID>AVX512_VP2INTERSECT</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm512_2intersect_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="__m512i" varname="a" />
+	<parameter etype="UI64" type="__m512i" varname="b" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
+	<description>Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
+	<operation>
+MEM[k1+7:k1] := 0
+MEM[k2+7:k2] := 0
+FOR i := 0 TO 7
+	FOR j := 0 TO 7
+		match := (a.qword[i] == b.qword[j] ? 1 : 0)
+		MEM[k1+7:k1].bit[i] |= match
+		MEM[k2+7:k2].bit[j] |= match
+	ENDFOR
+ENDFOR
+	</operation>
+	<instruction form="k, zmm, zmm" name="VP2INTERSECTQ" xed="VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512" />
+	<CPUID>AVX512_VP2INTERSECT</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_2intersect_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
+	<description>Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
+	<operation>
+MEM[k1+7:k1] := 0
+MEM[k2+7:k2] := 0
+FOR i := 0 TO 3
+	FOR j := 0 TO 3
+		match := (a.dword[i] == b.dword[j] ? 1 : 0)
+		MEM[k1+7:k1].bit[i] |= match
+		MEM[k2+7:k2].bit[j] |= match
+	ENDFOR
+ENDFOR
+	</operation>
+	<instruction form="k, xmm, xmm" name="VP2INTERSECTD" xed="VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512" />
+	<CPUID>AVX512_VP2INTERSECT</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm256_2intersect_epi32" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI32" type="__m256i" varname="a" />
+	<parameter etype="UI32" type="__m256i" varname="b" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
+	<description>Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
+	<operation>
+MEM[k1+7:k1] := 0
+MEM[k2+7:k2] := 0
+FOR i := 0 TO 7
+	FOR j := 0 TO 7
+		match := (a.dword[i] == b.dword[j] ? 1 : 0)
+		MEM[k1+7:k1].bit[i] |= match
+		MEM[k2+7:k2].bit[j] |= match
+	ENDFOR
+ENDFOR
+	</operation>
+	<instruction form="k, ymm, ymm" name="VP2INTERSECTD" xed="VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512" />
+	<CPUID>AVX512_VP2INTERSECT</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm_2intersect_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
+	<description>Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
+	<operation>
+MEM[k1+7:k1] := 0
+MEM[k2+7:k2] := 0
+FOR i := 0 TO 1
+	FOR j := 0 TO 1
+		match := (a.qword[i] == b.qword[j] ? 1 : 0)
+		MEM[k1+7:k1].bit[i] |= match
+		MEM[k2+7:k2].bit[j] |= match
+	ENDFOR
+ENDFOR
+	</operation>
+	<instruction form="k, xmm, xmm" name="VP2INTERSECTQ" xed="VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512" />
+	<CPUID>AVX512_VP2INTERSECT</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	<intrinsic name="_mm256_2intersect_epi64" tech="AVX-512">
+	<return type="void" />
+	<parameter etype="UI64" type="__m256i" varname="a" />
+	<parameter etype="UI64" type="__m256i" varname="b" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
+	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
+	<description>Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
+	<operation>
+MEM[k1+7:k1] := 0
+MEM[k2+7:k2] := 0
+FOR i := 0 TO 3
+	FOR j := 0 TO 3
+		match := (a.qword[i] == b.qword[j] ? 1 : 0)
+		MEM[k1+7:k1].bit[i] |= match
+		MEM[k2+7:k2].bit[j] |= match
+	ENDFOR
+ENDFOR
+	</operation>
+	<instruction form="k, ymm, ymm" name="VP2INTERSECTQ" xed="VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512" />
+	<CPUID>AVX512_VP2INTERSECT</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Mask</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_madd52hi_avx_epu64" tech="AVX_ALL">
+	<return type="__m256i" varname="dst" etype="UI64" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
+	<instruction name="VPMADD52HUQ" form="ymm, ymm, ymm" xed="VPMADD52HUQ_YMMu64_YMMu64_YMMu64" />
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
+	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+	<parameter type="__m256i" varname="__X" etype="UI64" />
+	<parameter type="__m256i" varname="__Y" etype="UI64" />
+	<parameter type="__m256i" varname="__Z" etype="UI64" />
+	<CPUID>AVX_IFMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_madd52lo_avx_epu64" tech="AVX_ALL">
+	<return type="__m256i" varname="dst" etype="UI64" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
+	<instruction name="VPMADD52LUQ" form="ymm, ymm, ymm" xed="VPMADD52LUQ_YMMu64_YMMu64_YMMu64" />
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
+	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+	<parameter type="__m256i" varname="__X" etype="UI64" />
+	<parameter type="__m256i" varname="__Y" etype="UI64" />
+	<parameter type="__m256i" varname="__Z" etype="UI64" />
+	<CPUID>AVX_IFMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_madd52hi_avx_epu64" tech="AVX_ALL">
+	<return type="__m128i" varname="dst" etype="UI64" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
+	<instruction name="VPMADD52HUQ" form="xmm, xmm, xmm" xed="VPMADD52HUQ_XMMu64_XMMu64_XMMu64" />
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
+	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+	<parameter type="__m128i" varname="__X" etype="UI64" />
+	<parameter type="__m128i" varname="__Y" etype="UI64" />
+	<parameter type="__m128i" varname="__Z" etype="UI64" />
+	<CPUID>AVX_IFMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_madd52lo_avx_epu64" tech="AVX_ALL">
+	<return type="__m128i" varname="dst" etype="UI64" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
+	<instruction name="VPMADD52LUQ" form="xmm, xmm, xmm" xed="VPMADD52LUQ_XMMu64_XMMu64_XMMu64" />
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
+	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+	<parameter type="__m128i" varname="__X" etype="UI64" />
+	<parameter type="__m128i" varname="__Y" etype="UI64" />
+	<parameter type="__m128i" varname="__Z" etype="UI64" />
+	<CPUID>AVX_IFMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+<intrinsic name="_mm256_madd52hi_epu64" tech="AVX_ALL">
+	<return type="__m256i" varname="dst" etype="UI64" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
+	<instruction name="VPMADD52HUQ" form="ymm, ymm, ymm" xed="VPMADD52HUQ_YMMu64_YMMu64_YMMu64" />
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
+	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+	<parameter type="__m256i" varname="__X" etype="UI64" />
+	<parameter type="__m256i" varname="__Y" etype="UI64" />
+	<parameter type="__m256i" varname="__Z" etype="UI64" />
+	<CPUID>AVX_IFMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_madd52lo_epu64" tech="AVX_ALL">
+	<return type="__m256i" varname="dst" etype="UI64" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
+	<instruction name="VPMADD52LUQ" form="ymm, ymm, ymm" xed="VPMADD52LUQ_YMMu64_YMMu64_YMMu64" />
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
+	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+	<parameter type="__m256i" varname="__X" etype="UI64" />
+	<parameter type="__m256i" varname="__Y" etype="UI64" />
+	<parameter type="__m256i" varname="__Z" etype="UI64" />
+	<CPUID>AVX_IFMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_madd52hi_epu64" tech="AVX_ALL">
+	<return type="__m128i" varname="dst" etype="UI64" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
+	<instruction name="VPMADD52HUQ" form="xmm, xmm, xmm" xed="VPMADD52HUQ_XMMu64_XMMu64_XMMu64" />
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
+	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+	<parameter type="__m128i" varname="__X" etype="UI64" />
+	<parameter type="__m128i" varname="__Y" etype="UI64" />
+	<parameter type="__m128i" varname="__Z" etype="UI64" />
+	<CPUID>AVX_IFMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_madd52lo_epu64" tech="AVX_ALL">
+	<return type="__m128i" varname="dst" etype="UI64" />
+	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
+	<instruction name="VPMADD52LUQ" form="xmm, xmm, xmm" xed="VPMADD52LUQ_XMMu64_XMMu64_XMMu64" />
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
+	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+	<parameter type="__m128i" varname="__X" etype="UI64" />
+	<parameter type="__m128i" varname="__Y" etype="UI64" />
+	<parameter type="__m128i" varname="__Z" etype="UI64" />
+	<CPUID>AVX_IFMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+<intrinsic name="_mm256_bcstnebf16_ps" tech="AVX_ALL">
+		<return type="__m256" varname="dst" etype="FP32" />
+		<description>Convert scalar BF16 (16-bit) floating-point element stored at memory locations starting at location "__A" to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VBCSTNEBF162PS" form="ymm, m16" xed="VBCSTNEBF162PS_YMMf32_MEMbf16" />
+		<operation>
+b := Convert_BF16_To_FP32(MEM[__A+15:__A])
+FOR j := 0 to 7
+	m := j*32
+	dst[m+31:m] := b
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="const __bf16*" memwidth="16" varname="__A" etype="BF16"/>
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_bcstnesh_ps" tech="AVX_ALL">
+		<return type="__m256" varname="dst" etype="FP32" />
+		<description>Convert scalar half-precision (16-bit) floating-point element stored at memory locations starting at location "__A" to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VBCSTNESH2PS" form="ymm, m16" xed="VBCSTNESH2PS_YMMf32_MEMf16" />
+		<operation>
+b := Convert_FP16_To_FP32(MEM[__A+15:__A])
+FOR j := 0 to 7
+	m := j*32
+	dst[m+31:m] := b
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="const _Float16*" memwidth="16" varname="__A" etype="FP16"/>
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtneebf16_ps" tech="AVX_ALL">
+		<return type="__m256" varname="dst" etype="FP32" />
+		<description>Convert packed BF16 (16-bit) floating-point even-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEEBF162PS" form="ymm, m256" xed="VCVTNEEBF162PS_YMMf32_MEMbf16" />
+		<operation>
+FOR j := 0 to 7
+	m := j*32
+	dst[m+31:m] := Convert_BF16_To_FP32(MEM[__A+m+15:__A+m])
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="const __m256bh*" memwidth="256" varname="__A" etype="BF16"/>
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtneeph_ps" tech="AVX_ALL">
+		<return type="__m256" varname="dst" etype="FP32" />
+		<description>Convert packed half-precision (16-bit) floating-point even-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEEPH2PS" form="ymm, m256" xed="VCVTNEEPH2PS_YMMf32_MEMf16" />
+		<operation>
+FOR j := 0 to 7
+	m := j*32
+	dst[m+31:m] := Convert_FP16_To_FP32(MEM[__A+m+15:__A+m])
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="const __m256h*" memwidth="256" etype="FP16" varname="__A" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtneobf16_ps" tech="AVX_ALL">
+		<return type="__m256" varname="dst" etype="FP32" />
+		<description>Convert packed BF16 (16-bit) floating-point odd-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEOBF162PS" form="ymm, m256" xed="VCVTNEOBF162PS_YMMf32_MEMbf16" />
+		<operation>
+FOR j := 0 to 7
+	m := j*32
+	dst[m+31:m] := Convert_BF16_To_FP32(MEM[__A+m+31:__A+m+16])
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="const __m256bh*" memwidth="256" etype="BF16" varname="__A" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtneoph_ps" tech="AVX_ALL">
+		<return type="__m256" varname="dst" etype="FP32" />
+		<description>Convert packed half-precision (16-bit) floating-point odd-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEOPH2PS" form="ymm, m256" xed="VCVTNEOPH2PS_YMMf32_MEMf16" />
+		<operation>
+FOR j := 0 to 7
+	m := j*32
+	dst[m+31:m] := Convert_FP16_To_FP32(MEM[__A+m+31:__A+m+16])
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="const __m256h*" memwidth="256" etype="FP16" varname="__A" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtneps_avx_pbh" tech="AVX_ALL">
+		<return type="__m128bh" varname="dst" etype="BF16" />
+		<description>Convert packed single-precision (32-bit) floating-point elements in "__A" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEPS2BF16" form="xmm, ymm" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
+		<operation>
+FOR j := 0 to 7
+	dst.word[j] := Convert_FP32_To_BF16(__A.fp32[j])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="__m256" varname="__A" etype="FP32" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_bcstnebf16_ps" tech="AVX_ALL">
+		<return type="__m128" varname="dst" etype="FP32" />
+		<description>Convert scalar BF16 (16-bit) floating-point element stored at memory locations starting at location "__A" to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VBCSTNEBF162PS" form="xmm, m16" xed="VBCSTNEBF162PS_XMMf32_MEMbf16" />
+		<operation>
+b := Convert_BF16_To_FP32(MEM[__A+15:__A])
+FOR j := 0 to 3
+	m := j*32
+	dst[m+31:m] := b
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="const __bf16*" varname="__A" memwidth="16" etype="BF16"/>
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_bcstnesh_ps" tech="AVX_ALL">
+		<return type="__m128" varname="dst" etype="FP32" />
+		<description>Convert scalar half-precision (16-bit) floating-point element stored at memory locations starting at location "__A" to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VBCSTNESH2PS" form="xmm, m16" xed="VBCSTNESH2PS_XMMf32_MEMf16" />
+		<operation>
+b := Convert_FP16_To_FP32(MEM[__A+15:__A])
+FOR j := 0 to 3
+	m := j*32
+	dst[m+31:m] := b
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="const _Float16*" varname="__A" memwidth="16" etype="FP16"/>
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtneebf16_ps" tech="AVX_ALL">
+		<return type="__m128" varname="dst" etype="FP32" />
+		<description>Convert packed BF16 (16-bit) floating-point even-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEEBF162PS" form="xmm, m128" xed="VCVTNEEBF162PS_XMMf32_MEMbf16" />
+		<operation>
+FOR j := 0 to 3
+	m := j*32
+	dst[m+31:m] := Convert_BF16_To_FP32(MEM[__A+m+15:__A+m])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="const __m128bh*" memwidth="128" etype="BF16" varname="__A" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtneeph_ps" tech="AVX_ALL">
+		<return type="__m128" varname="dst" etype="FP32" />
+		<description>Convert packed half-precision (16-bit) floating-point even-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEEPH2PS" form="xmm, m128" xed="VCVTNEEPH2PS_XMMf32_MEMf16" />
+		<operation>
+FOR j := 0 to 3
+	m := j*32
+	dst[m+31:m] := Convert_FP16_To_FP32(MEM[__A+m+15:__A+m])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="const __m128h*" memwidth="128" etype="FP16" varname="__A" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtneobf16_ps" tech="AVX_ALL">
+		<return type="__m128" varname="dst" etype="FP32" />
+		<description>Convert packed BF16 (16-bit) floating-point odd-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEOBF162PS" form="xmm, m128" xed="VCVTNEOBF162PS_XMMf32_MEMbf16" />
+		<operation>
+FOR j := 0 to 3
+	m := j*32
+	dst[m+31:m] := Convert_BF16_To_FP32(MEM[__A+m+31:__A+m+16])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="const __m128bh*" memwidth="128" etype="BF16" varname="__A" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtneoph_ps" tech="AVX_ALL">
+		<return type="__m128" varname="dst" etype="FP32" />
+		<description>Convert packed half-precision (16-bit) floating-point odd-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEOPH2PS" form="xmm, m128" xed="VCVTNEOPH2PS_XMMf32_MEMf16" />
+		<operation>
+FOR j := 0 to 3
+	m := j*32
+	dst[m+31:m] := Convert_FP16_To_FP32(MEM[__A+m+31:__A+m+16])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="const __m128h*" memwidth="128" etype="FP16" varname="__A" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtneps_avx_pbh" tech="AVX_ALL">
+		<return type="__m128bh" varname="dst" etype="BF16" />
+		<description>Convert packed single-precision (32-bit) floating-point elements in "__A" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEPS2BF16" form="xmm, xmm" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
+		<operation>
+FOR j := 0 to 3
+	dst.word[j] := Convert_FP32_To_BF16(__A.fp32[j])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="__m128" varname="__A" etype="FP32" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtneps_pbh" tech="AVX_ALL">
+		<return type="__m128bh" varname="dst" etype="BF16" />
+		<description>Convert packed single-precision (32-bit) floating-point elements in "__A" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEPS2BF16" form="xmm, ymm" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
+		<operation>
+FOR j := 0 to 7
+	dst.word[j] := Convert_FP32_To_BF16(__A.fp32[j])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="__m256" varname="__A" etype="FP32" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtneps_pbh" tech="AVX_ALL">
+		<return type="__m128bh" varname="dst" etype="BF16" />
+		<description>Convert packed single-precision (32-bit) floating-point elements in "__A" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
+		<instruction name="VCVTNEPS2BF16" form="xmm, xmm" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
+		<operation>
+FOR j := 0 to 3
+	dst.word[j] := Convert_FP32_To_BF16(__A.fp32[j])
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="__m128" varname="__A" etype="FP32" />
+	<CPUID>AVX_NE_CONVERT</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+<intrinsic name="_mm256_dpbusd_avx_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<parameter type="__m256i" varname="src" etype="SI32" />
+		<parameter type="__m256i" varname="a" etype="UI8" />
+		<parameter type="__m256i" varname="b" etype="SI8" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:256] := 0
+		</operation>
+		<instruction name="VPDPBUSD" form="ymm, ymm, ymm" xed="VPDPBUSD_YMMi32_YMMu32_YMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbusds_avx_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<parameter type="__m256i" varname="src" etype="SI32" />
+		<parameter type="__m256i" varname="a" etype="UI8" />
+		<parameter type="__m256i" varname="b" etype="SI8" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:256] := 0
+		</operation>
+		<instruction name="VPDPBUSDS" form="ymm, ymm, ymm" xed="VPDPBUSDS_YMMi32_YMMu32_YMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpwssd_avx_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<parameter type="__m256i" varname="src" etype="SI32" />
+		<parameter type="__m256i" varname="a" etype="SI16" />
+		<parameter type="__m256i" varname="b" etype="SI16" />
+		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 7
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:256] := 0
+		</operation>
+		<instruction name="VPDPWSSD" form="ymm, ymm, ymm" xed="VPDPWSSD_YMMi32_YMMu32_YMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpwssds_avx_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<parameter type="__m256i" varname="src" etype="SI32" />
+		<parameter type="__m256i" varname="a" etype="SI16" />
+		<parameter type="__m256i" varname="b" etype="SI16" />
+		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 7
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:256] := 0
+		</operation>
+		<instruction name="VPDPWSSDS" form="ymm, ymm, ymm" xed="VPDPWSSDS_YMMi32_YMMu32_YMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbusd_avx_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<parameter type="__m128i" varname="src" etype="SI32" />
+		<parameter type="__m128i" varname="a" etype="SI16" />
+		<parameter type="__m128i" varname="b" etype="SI16" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:128] := 0
+		</operation>
+		<instruction name="VPDPBUSD" form="xmm, xmm, xmm" xed="VPDPBUSD_XMMi32_XMMu32_XMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbusds_avx_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<parameter type="__m128i" varname="src" etype="SI32" />
+		<parameter type="__m128i" varname="a" etype="UI8" />
+		<parameter type="__m128i" varname="b" etype="SI8" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:128] := 0
+		</operation>
+		<instruction name="VPDPBUSDS" form="xmm, xmm, xmm" xed="VPDPBUSDS_XMMi32_XMMu32_XMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpwssd_avx_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<parameter type="__m128i" varname="src" etype="SI32" />
+		<parameter type="__m128i" varname="a" etype="SI16" />
+		<parameter type="__m128i" varname="b" etype="SI16" />
+		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 3
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:128] := 0
+		</operation>
+		<instruction name="VPDPWSSD" form="xmm, xmm, xmm" xed="VPDPWSSD_XMMi32_XMMu32_XMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpwssds_avx_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<parameter type="__m128i" varname="src" etype="SI32" />
+		<parameter type="__m128i" varname="a" etype="SI16" />
+		<parameter type="__m128i" varname="b" etype="SI16" />
+		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 3
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:128] := 0
+		</operation>
+		<instruction name="VPDPWSSDS" form="xmm, xmm, xmm" xed="VPDPWSSDS_XMMi32_XMMu32_XMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+<intrinsic name="_mm256_dpbusd_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<parameter type="__m256i" varname="src" etype="SI32" />
+		<parameter type="__m256i" varname="a" etype="UI8" />
+		<parameter type="__m256i" varname="b" etype="SI8" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:256] := 0
+		</operation>
+		<instruction name="VPDPBUSD" form="ymm, ymm, ymm" xed="VPDPBUSD_YMMi32_YMMu32_YMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbusds_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<parameter type="__m256i" varname="src" etype="SI32" />
+		<parameter type="__m256i" varname="a" etype="UI8" />
+		<parameter type="__m256i" varname="b" etype="SI8" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:256] := 0
+		</operation>
+		<instruction name="VPDPBUSDS" form="ymm, ymm, ymm" xed="VPDPBUSDS_YMMi32_YMMu32_YMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpwssd_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<parameter type="__m256i" varname="src" etype="SI32" />
+		<parameter type="__m256i" varname="a" etype="SI16" />
+		<parameter type="__m256i" varname="b" etype="SI16" />
+		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 7
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:256] := 0
+		</operation>
+		<instruction name="VPDPWSSD" form="ymm, ymm, ymm" xed="VPDPWSSD_YMMi32_YMMu32_YMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpwssds_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<parameter type="__m256i" varname="src" etype="SI32" />
+		<parameter type="__m256i" varname="a" etype="SI16" />
+		<parameter type="__m256i" varname="b" etype="SI16" />
+		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 7
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:256] := 0
+		</operation>
+		<instruction name="VPDPWSSDS" form="ymm, ymm, ymm" xed="VPDPWSSDS_YMMi32_YMMu32_YMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbusd_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<parameter type="__m128i" varname="src" etype="SI32" />
+		<parameter type="__m128i" varname="a" etype="SI16" />
+		<parameter type="__m128i" varname="b" etype="SI16" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:128] := 0
+		</operation>
+		<instruction name="VPDPBUSD" form="xmm, xmm, xmm" xed="VPDPBUSD_XMMi32_XMMu32_XMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbusds_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<parameter type="__m128i" varname="src" etype="SI32" />
+		<parameter type="__m128i" varname="a" etype="UI8" />
+		<parameter type="__m128i" varname="b" etype="SI8" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
+	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
+	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
+	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:128] := 0
+		</operation>
+		<instruction name="VPDPBUSDS" form="xmm, xmm, xmm" xed="VPDPBUSDS_XMMi32_XMMu32_XMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpwssd_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<parameter type="__m128i" varname="src" etype="SI32" />
+		<parameter type="__m128i" varname="a" etype="SI16" />
+		<parameter type="__m128i" varname="b" etype="SI16" />
+		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 3
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := src.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:128] := 0
+		</operation>
+		<instruction name="VPDPWSSD" form="xmm, xmm, xmm" xed="VPDPWSSD_XMMi32_XMMu32_XMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpwssds_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<parameter type="__m128i" varname="src" etype="SI32" />
+		<parameter type="__m128i" varname="a" etype="SI16" />
+		<parameter type="__m128i" varname="b" etype="SI16" />
+		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
+		<operation>
+FOR j := 0 to 3
+	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
+	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
+	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:128] := 0
+		</operation>
+		<instruction name="VPDPWSSDS" form="xmm, xmm, xmm" xed="VPDPWSSDS_XMMi32_XMMu32_XMMu32" />
+	<CPUID>AVX_VNNI</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+<intrinsic name="_mm256_dpwsud_epi32" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWSUD" form="ymm, ymm, ymm" xed="VPDPWSUD_YMMi32_YMMu32_YMMu32" />
+    <operation>
+FOR j := 0 to 7
+	tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
+	tmp2.dword := SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+    <parameter type="__m256i" varname="__W" etype="SI32" />
+    <parameter type="__m256i" varname="__A" etype="SI16" />
+    <parameter type="__m256i" varname="__B" etype="UI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm256_dpwsuds_epi32" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWSUDS" form="ymm, ymm, ymm" xed="VPDPWSUDS_YMMi32_YMMu32_YMMu32" />
+    <operation>
+FOR j := 0 to 7
+	tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
+	tmp2.dword := SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
+	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:256] := 0			</operation>
+    <parameter type="__m256i" varname="__W" etype="SI32" />
+    <parameter type="__m256i" varname="__A" etype="SI16" />
+    <parameter type="__m256i" varname="__B" etype="UI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm256_dpwusd_epi32" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding signed 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWUSD" form="ymm, ymm, ymm" xed="VPDPWUSD_YMMi32_YMMu32_YMMu32" />
+    <operation>
+FOR j := 0 to 7
+	tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
+	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+    <parameter type="__m256i" varname="__W" etype="SI32" />
+    <parameter type="__m256i" varname="__A" etype="UI16" />
+    <parameter type="__m256i" varname="__B" etype="SI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm256_dpwusds_epi32" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding signed 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWUSDS" form="ymm, ymm, ymm" xed="VPDPWUSDS_YMMi32_YMMu32_YMMu32" />
+    <operation>
+FOR j := 0 to 7
+	tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
+	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
+	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:256] := 0			</operation>
+    <parameter type="__m256i" varname="__W" etype="SI32" />
+    <parameter type="__m256i" varname="__A" etype="UI16" />
+    <parameter type="__m256i" varname="__B" etype="SI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm256_dpwuud_epi32" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWUUD" form="ymm, ymm, ymm" xed="VPDPWUUD_YMMi32_YMMu32_YMMu32" />
+    <operation>
+FOR j := 0 to 7
+	tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
+	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+    <parameter type="__m256i" varname="__W" etype="UI32" />
+    <parameter type="__m256i" varname="__A" etype="UI16" />
+    <parameter type="__m256i" varname="__B" etype="UI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm256_dpwuuds_epi32" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWUUDS" form="ymm, ymm, ymm" xed="VPDPWUUDS_YMMi32_YMMu32_YMMu32" />
+    <operation>
+FOR j := 0 to 7
+	tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
+	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
+	dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:256] := 0			</operation>
+    <parameter type="__m256i" varname="__W" etype="UI32" />
+    <parameter type="__m256i" varname="__A" etype="UI16" />
+    <parameter type="__m256i" varname="__B" etype="UI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm_dpwsud_epi32" tech="AVX_ALL">
+    <return type="__m128i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWSUD" form="xmm, xmm, xmm" xed="VPDPWSUD_XMMi32_XMMu32_XMMu32" />
+    <operation>
+FOR j := 0 to 3
+	tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
+	tmp2.dword := SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+    <parameter type="__m128i" varname="__W" etype="SI32" />
+    <parameter type="__m128i" varname="__A" etype="SI16" />
+    <parameter type="__m128i" varname="__B" etype="UI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm_dpwsuds_epi32" tech="AVX_ALL">
+    <return type="__m128i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWSUDS" form="xmm, xmm, xmm" xed="VPDPWSUDS_XMMi32_XMMu32_XMMu32" />
+    <operation>
+FOR j := 0 to 3
+	tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
+	tmp2.dword := SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
+	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:128] := 0			</operation>
+    <parameter type="__m128i" varname="__W" etype="SI32" />
+    <parameter type="__m128i" varname="__A" etype="SI16" />
+    <parameter type="__m128i" varname="__B" etype="UI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm_dpwusd_epi32" tech="AVX_ALL">
+    <return type="__m128i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding signed 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWUSD" form="xmm, xmm, xmm" xed="VPDPWUSD_XMMi32_XMMu32_XMMu32" />
+    <operation>
+FOR j := 0 to 3
+	tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
+	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+    <parameter type="__m128i" varname="__W" etype="SI32" />
+    <parameter type="__m128i" varname="__A" etype="UI16" />
+    <parameter type="__m128i" varname="__B" etype="SI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm_dpwusds_epi32" tech="AVX_ALL">
+    <return type="__m128i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding signed 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWUSDS" form="xmm, xmm, xmm" xed="VPDPWUSDS_XMMi32_XMMu32_XMMu32" />
+    <operation>
+FOR j := 0 to 3
+	tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
+	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
+	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:128] := 0			</operation>
+    <parameter type="__m128i" varname="__W" etype="SI32" />
+    <parameter type="__m128i" varname="__A" etype="UI16" />
+    <parameter type="__m128i" varname="__B" etype="SI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm_dpwuud_epi32" tech="AVX_ALL">
+    <return type="__m128i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWUUD" form="xmm, xmm, xmm" xed="VPDPWUUD_XMMi32_XMMu32_XMMu32" />
+    <operation>
+FOR j := 0 to 3
+	tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
+	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+    <parameter type="__m128i" varname="__W" etype="UI32" />
+    <parameter type="__m128i" varname="__A" etype="UI16" />
+    <parameter type="__m128i" varname="__B" etype="UI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+  <intrinsic name="_mm_dpwuuds_epi32" tech="AVX_ALL">
+    <return type="__m128i" varname="dst" etype="SI32" />
+    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+    <instruction name="VPDPWUUDS" form="xmm, xmm, xmm" xed="VPDPWUUDS_XMMi32_XMMu32_XMMu32" />
+    <operation>
+FOR j := 0 to 3
+	tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
+	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
+	dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
+ENDFOR
+dst[MAX:128] := 0			</operation>
+    <parameter type="__m128i" varname="__W" etype="UI32" />
+    <parameter type="__m128i" varname="__A" etype="UI16" />
+    <parameter type="__m128i" varname="__B" etype="UI16" />
+  <CPUID>AVX_VNNI_INT16</CPUID>
+	<header>immintrin.h</header>
+  <category>Arithmetic</category>
+  </intrinsic>
+<intrinsic name="_mm256_dpbssd_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding signed 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBSSD" form="ymm, ymm, ymm" xed="VPDPBSSD_YMMi32_YMMu32_YMMu32" />
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := SignExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j])
+	tmp2.word := SignExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1])
+	tmp3.word := SignExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2])
+	tmp4.word := SignExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="__m256i" varname="__W" etype="SI32" />
+		<parameter type="__m256i" varname="__A" etype="SI8" />
+		<parameter type="__m256i" varname="__B" etype="SI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbssds_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding signed 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBSSDS" form="ymm, ymm, ymm" xed="VPDPBSSDS_YMMi32_YMMu32_YMMu32" />
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := SignExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j])
+	tmp2.word := SignExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1])
+	tmp3.word := SignExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2])
+	tmp4.word := SignExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3])
+	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:256] := 0			</operation>
+		<parameter type="__m256i" varname="__W" etype="SI32" />
+		<parameter type="__m256i" varname="__A" etype="SI8" />
+		<parameter type="__m256i" varname="__B" etype="SI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbsud_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBSUD" form="ymm, ymm, ymm" xed="VPDPBSUD_YMMi32_YMMu32_YMMu32" />
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := Signed(SignExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j]))
+	tmp2.word := Signed(SignExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1]))
+	tmp3.word := Signed(SignExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2]))
+	tmp4.word := Signed(SignExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3]))
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="__m256i" varname="__W" etype="SI32" />
+		<parameter type="__m256i" varname="__A" etype="SI8" />
+		<parameter type="__m256i" varname="__B" etype="UI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbsuds_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBSUDS" form="ymm, ymm, ymm" xed="VPDPBSUDS_YMMi32_YMMu32_YMMu32" />
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := Signed(SignExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j]))
+	tmp2.word := Signed(SignExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1]))
+	tmp3.word := Signed(SignExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2]))
+	tmp4.word := Signed(SignExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3]))
+	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:256] := 0			</operation>
+		<parameter type="__m256i" varname="__W" etype="SI32" />
+		<parameter type="__m256i" varname="__A" etype="SI8" />
+		<parameter type="__m256i" varname="__B" etype="UI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbuud_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBUUD" form="ymm, ymm, ymm" xed="VPDPBUUD_YMMi32_YMMu32_YMMu32" />
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := ZeroExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j])
+	tmp2.word := ZeroExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1])
+	tmp3.word := ZeroExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2])
+	tmp4.word := ZeroExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+		<parameter type="__m256i" varname="__W" etype="SI32" />
+		<parameter type="__m256i" varname="__A" etype="UI8" />
+		<parameter type="__m256i" varname="__B" etype="UI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_dpbuuds_epi32" tech="AVX_ALL">
+		<return type="__m256i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with unsigned saturation, and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBUUDS" form="ymm, ymm, ymm" xed="VPDPBUUDS_YMMi32_YMMu32_YMMu32" />
+		<operation>
+FOR j := 0 to 7
+	tmp1.word := ZeroExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j])
+	tmp2.word := ZeroExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1])
+	tmp3.word := ZeroExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2])
+	tmp4.word := ZeroExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3])
+	dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:256] := 0			</operation>
+		<parameter type="__m256i" varname="__W" etype="SI32" />
+		<parameter type="__m256i" varname="__A" etype="UI8" />
+		<parameter type="__m256i" varname="__B" etype="UI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbssd_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding signed 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBSSD" form="xmm, xmm, xmm" xed="VPDPBSSD_XMMi32_XMMu32_XMMu32" />
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := SignExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j])
+	tmp2.word := SignExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1])
+	tmp3.word := SignExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2])
+	tmp4.word := SignExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="__m128i" varname="__W" etype="SI32" />
+		<parameter type="__m128i" varname="__A" etype="SI8" />
+		<parameter type="__m128i" varname="__B" etype="SI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbssds_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding signed 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBSSDS" form="xmm, xmm, xmm" xed="VPDPBSSDS_XMMi32_XMMu32_XMMu32" />
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := SignExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j])
+	tmp2.word := SignExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1])
+	tmp3.word := SignExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2])
+	tmp4.word := SignExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3])
+	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:128] := 0			</operation>
+		<parameter type="__m128i" varname="__W" etype="SI32" />
+		<parameter type="__m128i" varname="__A" etype="SI8" />
+		<parameter type="__m128i" varname="__B" etype="SI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbsud_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBSUD" form="xmm, xmm, xmm" xed="VPDPBSUD_XMMi32_XMMu32_XMMu32" />
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := Signed(SignExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j]))
+	tmp2.word := Signed(SignExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1]))
+	tmp3.word := Signed(SignExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2]))
+	tmp4.word := Signed(SignExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3]))
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="__m128i" varname="__W" etype="SI32" />
+		<parameter type="__m128i" varname="__A" etype="SI8" />
+		<parameter type="__m128i" varname="__B" etype="UI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbsuds_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBSUDS" form="xmm, xmm, xmm" xed="VPDPBSUDS_XMMi32_XMMu32_XMMu32" />
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := Signed(SignExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j]))
+	tmp2.word := Signed(SignExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1]))
+	tmp3.word := Signed(SignExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2]))
+	tmp4.word := Signed(SignExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3]))
+	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:128] := 0			</operation>
+		<parameter type="__m128i" varname="__W" etype="SI32" />
+		<parameter type="__m128i" varname="__A" etype="SI8" />
+		<parameter type="__m128i" varname="__B" etype="UI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbuud_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBUUD" form="xmm, xmm, xmm" xed="VPDPBUUD_XMMi32_XMMu32_XMMu32" />
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := ZeroExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j])
+	tmp2.word := ZeroExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1])
+	tmp3.word := ZeroExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2])
+	tmp4.word := ZeroExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3])
+	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
+ENDFOR
+dst[MAX:128] := 0
+</operation>
+		<parameter type="__m128i" varname="__W" etype="SI32" />
+		<parameter type="__m128i" varname="__A" etype="UI8" />
+		<parameter type="__m128i" varname="__B" etype="UI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dpbuuds_epi32" tech="AVX_ALL">
+		<return type="__m128i" varname="dst" etype="SI32" />
+		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with unsigned saturation, and store the packed 32-bit results in "dst".</description>
+		<instruction name="VPDPBUUDS" form="xmm, xmm, xmm" xed="VPDPBUUDS_XMMi32_XMMu32_XMMu32" />
+		<operation>
+FOR j := 0 to 3
+	tmp1.word := ZeroExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j])
+	tmp2.word := ZeroExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1])
+	tmp3.word := ZeroExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2])
+	tmp4.word := ZeroExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3])
+	dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
+ENDFOR
+dst[MAX:128] := 0			</operation>
+		<parameter type="__m128i" varname="__W" etype="SI32" />
+		<parameter type="__m128i" varname="__A" etype="UI8" />
+		<parameter type="__m128i" varname="__B" etype="UI8" />
+	<CPUID>AVX_VNNI_INT8</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+<intrinsic name="_bextr_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="start" />
+	<parameter etype="UI32" type="unsigned int" varname="len" />
+	<description>Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst". Extract the number of bits specified by "len", starting at the bit specified by "start".</description>
+	<operation>
+tmp[511:0] := a
+dst[31:0] := ZeroExtend32(tmp[(start[7:0] + len[7:0] - 1):start[7:0]])
+	</operation>
+	<instruction form="r32, r32, r32" name="BEXTR" xed="BEXTR_VGPR32d_VGPR32d_VGPR32d" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bextr2_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="control" />
+	<description>Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst". Extract the number of bits specified by bits 15:8 of "control", starting at the bit specified by bits 0:7 of "control".</description>
+	<operation>
+start := control[7:0]
+len := control[15:8]
+tmp[511:0] := a
+dst[31:0] := ZeroExtend32(tmp[(start[7:0] + len[7:0] - 1):start[7:0]])
+	</operation>
+	<instruction form="r32, r32, r32" name="BEXTR" xed="BEXTR_VGPR32d_VGPR32d_VGPR32d" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bextr_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="start" />
+	<parameter etype="UI32" type="unsigned int" varname="len" />
+	<description>Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst". Extract the number of bits specified by "len", starting at the bit specified by "start".</description>
+	<operation>
+tmp[511:0] := a
+dst[63:0] := ZeroExtend64(tmp[(start[7:0] + len[7:0] - 1):start[7:0]])
+	</operation>
+	<instruction form="r64, r64, r64" name="BEXTR" xed="BEXTR_VGPR64q_VGPR64q_VGPR64q" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bextr2_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="control" />
+	<description>Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst". Extract the number of bits specified by bits 15:8 of "control", starting at the bit specified by bits 0:7 of "control"..</description>
+	<operation>
+start := control[7:0]
+len := control[15:8]
+tmp[511:0] := a
+dst[63:0] := ZeroExtend64(tmp[(start[7:0] + len[7:0] - 1):start[7:0]])
+	</operation>
+	<instruction form="r64, r64, r64" name="BEXTR" xed="BEXTR_VGPR64q_VGPR64q_VGPR64q" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_blsi_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Extract the lowest set bit from unsigned 32-bit integer "a" and set the corresponding bit in "dst". All other bits in "dst" are zeroed, and all bits are zeroed if no bits are set in "a".</description>
+	<operation>
+dst := (-a) AND a
+	</operation>
+	<instruction form="r32, r32" name="BLSI" xed="BLSI_VGPR32d_VGPR32d" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_blsi_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Extract the lowest set bit from unsigned 64-bit integer "a" and set the corresponding bit in "dst". All other bits in "dst" are zeroed, and all bits are zeroed if no bits are set in "a".</description>
+	<operation>
+dst := (-a) AND a
+	</operation>
+	<instruction form="r64, r64" name="BLSI" xed="BLSI_VGPR64q_VGPR64q" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_blsmsk_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 32-bit integer "a".</description>
+	<operation>
+dst := (a - 1) XOR a
+	</operation>
+	<instruction form="r32, r32" name="BLSMSK" xed="BLSMSK_VGPR32d_VGPR32d" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_blsmsk_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 64-bit integer "a".</description>
+	<operation>
+dst := (a - 1) XOR a
+	</operation>
+	<instruction form="r64, r64" name="BLSMSK" xed="BLSMSK_VGPR64q_VGPR64q" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_blsr_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a".</description>
+	<operation>
+dst := (a - 1) AND a
+	</operation>
+	<instruction form="r32, r32" name="BLSR" xed="BLSR_VGPR32d_VGPR32d" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_blsr_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a".</description>
+	<operation>
+dst := (a - 1) AND a
+	</operation>
+	<instruction form="r64, r64" name="BLSR" xed="BLSR_VGPR64q_VGPR64q" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_andn_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<description>Compute the bitwise NOT of 32-bit integer "a" and then AND with b, and store the results in dst.</description>
+	<operation>
+dst[31:0] := ((NOT a[31:0]) AND b[31:0])
+	</operation>
+	<instruction form="r32, r32, r32" name="ANDN" xed="ANDN_VGPR32d_VGPR32d_VGPR32d" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_andn_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<description>Compute the bitwise NOT of 64-bit integer "a" and then AND with b, and store the results in dst.</description>
+	<operation>
+dst[63:0] := ((NOT a[63:0]) AND b[63:0])
+	</operation>
+	<instruction form="r64, r64, r64" name="ANDN" xed="ANDN_VGPR64q_VGPR64q_VGPR64q" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_tzcnt_u16" tech="Other">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="UI16" type="unsigned short" varname="a" />
+	<description>Count the number of trailing zero bits in unsigned 16-bit integer "a", and return that count in "dst".</description>
+	<operation>
+tmp := 0
+dst := 0
+DO WHILE ((tmp &lt; 16) AND a[tmp] == 0)
+	tmp := tmp + 1
+	dst := dst + 1
+OD
+	</operation>
+	<instruction form="r16, r16" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_tzcnt_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Count the number of trailing zero bits in unsigned 32-bit integer "a", and return that count in "dst".</description>
+	<operation>
+tmp := 0
+dst := 0
+DO WHILE ((tmp &lt; 32) AND a[tmp] == 0)
+	tmp := tmp + 1
+	dst := dst + 1
+OD
+	</operation>
+	<instruction form="r32, r32" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_tzcnt_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Count the number of trailing zero bits in unsigned 64-bit integer "a", and return that count in "dst".</description>
+	<operation>
+tmp := 0
+dst := 0
+DO WHILE ((tmp &lt; 64) AND a[tmp] == 0)
+	tmp := tmp + 1
+	dst := dst + 1
+OD
+	</operation>
+	<instruction form="r64, r64" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_tzcnt_32" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Count the number of trailing zero bits in unsigned 32-bit integer "a", and return that count in "dst".</description>
+	<operation>
+tmp := 0
+dst := 0
+DO WHILE ((tmp &lt; 32) AND a[tmp] == 0)
+	tmp := tmp + 1
+	dst := dst + 1
+OD
+	</operation>
+	<instruction form="r32, r32" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_tzcnt_64" tech="Other">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Count the number of trailing zero bits in unsigned 64-bit integer "a", and return that count in "dst".</description>
+	<operation>
+tmp := 0
+dst := 0
+DO WHILE ((tmp &lt; 64) AND a[tmp] == 0)
+	tmp := tmp + 1
+	dst := dst + 1
+OD
+	</operation>
+	<instruction form="r64, r64" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
+	<CPUID>BMI1</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_bzhi_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="index" />
+	<description>Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index".</description>
+	<operation>
+n := index[7:0]
+dst := a
+IF (n &lt; 32)
+	dst[31:n] := 0
+FI
+	</operation>
+	<instruction form="r32, r32, r32" name="BZHI" xed="BZHI_VGPR32d_VGPR32d_VGPR32d" />
+	<CPUID>BMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bzhi_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="index" />
+	<description>Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index".</description>
+	<operation>
+n := index[7:0]
+dst := a
+IF (n &lt; 64)
+	dst[63:n] := 0
+FI
+	</operation>
+	<instruction form="r64, r64, r64" name="BZHI" xed="BZHI_VGPR64q_VGPR64q_VGPR64q" />
+	<CPUID>BMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_pdep_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="mask" />
+	<description>Deposit contiguous low bits from unsigned 32-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"; all other bits in "dst" are set to zero.</description>
+	<operation>
+tmp := a
+dst := 0
+m := 0
+k := 0
+DO WHILE m &lt; 32
+	IF mask[m] == 1
+		dst[m] := tmp[k]
+		k := k + 1
+	FI
+	m := m + 1
+OD
+	</operation>
+	<instruction form="r32, r32, r32" name="PDEP" xed="PDEP_VGPR32d_VGPR32d_VGPR32d" />
+	<CPUID>BMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_pdep_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="mask" />
+	<description>Deposit contiguous low bits from unsigned 64-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"; all other bits in "dst" are set to zero.</description>
+	<operation>
+tmp := a
+dst := 0
+m := 0
+k := 0
+DO WHILE m &lt; 64
+	IF mask[m] == 1
+		dst[m] := tmp[k]
+		k := k + 1
+	FI
+	m := m + 1
+OD
+	</operation>
+	<instruction form="r64, r64, r64" name="PDEP" xed="PDEP_VGPR64q_VGPR64q_VGPR64q" />
+	<CPUID>BMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_pext_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="mask" />
+	<description>Extract bits from unsigned 32-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"; the remaining upper bits in "dst" are set to zero.</description>
+	<operation>
+tmp := a
+dst := 0
+m := 0
+k := 0
+DO WHILE m &lt; 32
+	IF mask[m] == 1
+		dst[k] := tmp[m]
+		k := k + 1
+	FI
+	m := m + 1
+OD
+	</operation>
+	<instruction form="r32, r32, r32" name="PEXT" xed="PEXT_VGPR32d_VGPR32d_VGPR32d" />
+	<CPUID>BMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_pext_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="mask" />
+	<description>Extract bits from unsigned 64-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"; the remaining upper bits in "dst" are set to zero.</description>
+	<operation>
+tmp := a
+dst := 0
+m := 0
+k := 0
+DO WHILE m &lt; 64
+	IF mask[m] == 1
+		dst[k] := tmp[m]
+		k := k + 1
+	FI
+	m := m + 1
+OD
+	</operation>
+	<instruction form="r64, r64, r64" name="PEXT" xed="PEXT_VGPR64q_VGPR64q_VGPR64q" />
+	<CPUID>BMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mulx_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<parameter etype="UI32" memwidth="32" type="unsigned int*" varname="hi" />
+	<description>Multiply unsigned 32-bit integers "a" and "b", store the low 32-bits of the result in "dst", and store the high 32-bits in "hi". This does not read or write arithmetic flags.</description>
+	<operation>
+dst[31:0] := (a * b)[31:0]
+MEM[hi+31:hi] := (a * b)[63:32]
+	</operation>
+	<instruction form="r32, r32, m32" name="MULX" xed="MULX_VGPR32d_VGPR32d_MEMd" />
+	<CPUID>BMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mulx_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<parameter etype="UI64" memwidth="64" type="unsigned __int64*" varname="hi" />
+	<description>Multiply unsigned 64-bit integers "a" and "b", store the low 64-bits of the result in "dst", and store the high 64-bits in "hi". This does not read or write arithmetic flags.</description>
+	<operation>
+dst[63:0] := (a * b)[63:0]
+MEM[hi+63:hi]  := (a * b)[127:64]
+	</operation>
+	<instruction form="r64, r64, m64" name="MULX" xed="MULX_VGPR64q_VGPR64q_MEMq" />
+	<CPUID>BMI2</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_incsspd" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a".</description>
+	<operation>
+SSP := SSP + a[7:0] * 4
+	</operation>
+	<instruction form="r32" name="INCSSPD" xed="INCSSPD_GPR32u8" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_incsspq" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Increment the shadow stack pointer by 8 times the value specified in bits [7:0] of "a".</description>
+	<operation>
+SSP := SSP + a[7:0] * 8
+	</operation>
+	<instruction form="r64" name="INCSSPQ" xed="INCSSPQ_GPR64u8" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_rdsspd_i32" tech="Other">
+	<return etype="UI32" type="__int32" varname="dst" />
+	<parameter type="void" />
+	<description>Read the low 32-bits of the current shadow stack pointer, and store the result in "dst".</description>
+	<operation>dst := SSP[31:0]
+	</operation>
+	<instruction form="r32" name="RDSSPD" xed="RDSSPD_GPR32u32" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_rdsspq_i64" tech="Other">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter type="void" />
+	<description>Read the current shadow stack pointer, and store the result in "dst".</description>
+	<operation>dst := SSP[63:0]
+	</operation>
+	<instruction form="r64" name="RDSSPQ" xed="RDSSPQ_GPR64u64" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_saveprevssp" tech="Other">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Save the previous shadow stack pointer context.</description>
+	<instruction name="SAVEPREVSSP" xed="SAVEPREVSSP" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_rstorssp" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="p" />
+	<description>Restore the saved shadow stack pointer from the shadow stack restore token previously created on shadow stack by saveprevssp.</description>
+	<instruction form="m64" name="RSTORSSP" xed="RSTORSSP_MEMu64" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_wrssd" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="__int32" varname="val" />
+	<parameter type="void *" varname="p" />
+	<description>Write 32-bit value in "val" to a shadow stack page in memory specified by "p".</description>
+	<instruction form="m32, r32" name="WRSSD" xed="WRSSD_MEMu32_GPR32u32" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_wrssq" tech="Other">
+	<return type="void" />
+	<parameter etype="UI64" type="__int64" varname="val" />
+	<parameter type="void *" varname="p" />
+	<description>Write 64-bit value in "val" to a shadow stack page in memory specified by "p".</description>
+	<instruction form="m64, r64" name="WRSSQ" xed="WRSSQ_MEMu64_GPR64u64" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_wrussd" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="__int32" varname="val" />
+	<parameter type="void *" varname="p" />
+	<description>Write 32-bit value in "val" to a user shadow stack page in memory specified by "p".</description>
+	<instruction form="m32, r32" name="WRUSSD" xed="WRUSSD_MEMu32_GPR32u32" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_wrussq" tech="Other">
+	<return type="void" />
+	<parameter etype="UI64" type="__int64" varname="val" />
+	<parameter type="void *" varname="p" />
+	<description>Write 64-bit value in "val" to a user shadow stack page in memory specified by "p".</description>
+	<instruction form="m64, r64" name="WRUSSQ" xed="WRUSSQ_MEMu64_GPR64u64" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_setssbsy" tech="Other">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Mark shadow stack pointed to by IA32_PL0_SSP as busy.</description>
+	<instruction name="SETSSBSY" xed="SETSSBSY" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_clrssbsy" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="p" />
+	<description>Mark shadow stack pointed to by "p" as not busy.</description>
+	<instruction form="m64" name="CLRSSBSY" xed="CLRSSBSY_MEMu64" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_get_ssp" tech="Other">
+	<return etype="UI32" type="__int32" varname="dst" />
+	<parameter type="void" />
+	<description>If CET is enabled, read the low 32-bits of the current shadow stack pointer, and store the result in "dst". Otherwise return 0.</description>
+	<operation>dst := SSP[31:0]
+	</operation>
+	<instruction form="r32" name="RDSSPD" xed="RDSSPD_GPR32u32" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_get_ssp" tech="Other">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter type="void" />
+	<description>If CET is enabled, read the current shadow stack pointer, and store the result in "dst". Otherwise return 0.</description>
+	<operation>dst := SSP[63:0]
+	</operation>
+	<instruction form="r64" name="RDSSPQ" xed="RDSSPQ_GPR64u64" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_inc_ssp" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a".</description>
+	<operation>
+SSP := SSP + a[7:0] * 4
+	</operation>
+	<instruction form="r32" name="INCSSPD" xed="INCSSPD_GPR32u8" />
+	<CPUID>CET_SS</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	
+<intrinsic name="_mm_cldemote" tech="Other">
+	<return type="void" />
+	<parameter type="void const *" varname="p" />
+	<description>Hint to hardware that the cache line that contains "p" should be demoted from the cache closest to the processor core to a level more distant from the processor core.</description>
+	<instruction form="m8" name="CLDEMOTE" xed="CLDEMOTE_MEMu8" />
+	<CPUID>CLDEMOTE</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_clflushopt" tech="Other">
+	<return type="void" />
+	<parameter type="void const *" varname="p" />
+	<description>Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy.</description>
+	<instruction form="m8" name="CLFLUSHOPT" xed="CLFLUSHOPT_MEMmprefetch" />
+	<CPUID>CLFLUSHOPT</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_clwb" tech="Other">
+	<return type="void" />
+	<parameter type="void const *" varname="p" />
+	<description>Write back to memory the cache line that contains "p" from any level of the cache hierarchy in the cache coherence domain.</description>
+	<instruction form="m8" name="CLWB" xed="CLWB_MEMmprefetch" />
+	<CPUID>CLWB</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+	<intrinsic name="_cmpccxadd_epi32" tech="Other">
+	<return etype="SI32" type="int" varname="dst" />
+	<parameter etype="SI32" type="void*" memwidth="32" varname="__A" />
+	<parameter etype="SI32" type="int" varname="__B" />
+	<parameter etype="SI32" type="int" varname="__C" />
+	<parameter etype="SI32" type="const int" varname="__D" />
+	<description>Compares the value from the memory "__A" with the value of "__B". If the specified condition "__D" is met, then add the third operand "__C" to the "__A" and write it into "__A", else the value of "__A" is unchanged. The return value is the original value of "__A".</description>
+	<operation>CASE (__D[3:0]) OF
+0: OP := _CMPCCX_O
+1: OP := _CMPCCX_NO
+2: OP := _CMPCCX_B
+3: OP := _CMPCCX_NB
+4: OP := _CMPCCX_Z
+5: OP := _CMPCCX_NZ
+6: OP := _CMPCCX_BE
+7: OP := _CMPCCX_NBE
+8: OP := _CMPCCX_S
+9: OP := _CMPCCX_NS
+10: OP := _CMPCCX_P
+11: OP := _CMPCCX_NP
+12: OP := _CMPCCX_L
+13: OP := _CMPCCX_NL
+14: OP := _CMPCCX_LE
+15: OP := _CMPCCX_NLE
+ESAC
+tmp1 := LOAD_LOCK(__A)
+tmp2 := tmp1 + __C
+IF (tmp1[31:0] OP __B[31:0])
+	STORE_UNLOCK(__A, tmp2)
+ELSE
+	STORE_UNLOCK(__A, tmp1)
+FI
+dst[31:0] := tmp1[31:0]
+	</operation>
+	<instruction name="CMPOXADD" form ="m32, r32, r32" xed="CMPOXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPNOXADD" form ="m32, r32, r32" xed="CMPNOXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPBXADD" form ="m32, r32, r32" xed="CMPBXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPNBXADD" form ="m32, r32, r32" xed="CMPNBXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPZXADD" form ="m32, r32, r32" xed="CMPZXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPNZXADD" form ="m32, r32, r32" xed="CMPNZXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPBEXADD" form ="m32, r32, r32" xed="CMPBEXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPNBEXADD" form ="m32, r32, r32" xed="CMPNBEXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPSXADD" form ="m32, r32, r32" xed="CMPSXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPNSXADD" form ="m32, r32, r32" xed="CMPNSXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPPXADD" form ="m32, r32, r32" xed="CMPPXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPNPXADD" form ="m32, r32, r32" xed="CMPNPXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPLXADD" form ="m32, r32, r32" xed="CMPLXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPNLXADD" form ="m32, r32, r32" xed="CMPNLXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPLEXADD" form ="m32, r32, r32" xed="CMPLEXADD_MEMu32_GPR32u32_GPR32u32" />
+	<instruction name="CMPNLEXADD" form ="m32, r32, r32" xed="CMPNLEXADD_MEMu32_GPR32u32_GPR32u32" />
+	<CPUID>CMPCCXADD</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_cmpccxadd_epi64" tech="Other">
+	<return etype="SI64" type="__int64" varname="dst" />
+	<parameter etype="SI64" type="void*" memwidth="32" varname="__A" />
+	<parameter etype="SI64" type="__int64" varname="__B" />
+	<parameter etype="SI64" type="__int64" varname="__C" />
+	<parameter etype="SI32" type="const int" varname="__D" />
+	<description>Compares the value from the memory "__A" with the value of "__B". If the specified condition "__D" is met, then add the third operand "__C" to the "__A" and write it into "__A", else the value of "__A" is unchanged. The return value is the original value of "__A".</description>
+	<operation>CASE (__D[3:0]) OF
+0: OP := _CMPCCX_O
+1: OP := _CMPCCX_NO
+2: OP := _CMPCCX_B
+3: OP := _CMPCCX_NB
+4: OP := _CMPCCX_Z
+5: OP := _CMPCCX_NZ
+6: OP := _CMPCCX_BE
+7: OP := _CMPCCX_NBE
+8: OP := _CMPCCX_S
+9: OP := _CMPCCX_NS
+10: OP := _CMPCCX_P
+11: OP := _CMPCCX_NP
+12: OP := _CMPCCX_L
+13: OP := _CMPCCX_NL
+14: OP := _CMPCCX_LE
+15: OP := _CMPCCX_NLE
+ESAC
+tmp1 := LOAD_LOCK(__A)
+tmp2 := tmp1 + __C
+IF (tmp1[63:0] OP __B[63:0])
+	STORE_UNLOCK(__A, tmp2)
+ELSE
+	STORE_UNLOCK(__A, tmp1)
+FI
+dst[63:0] := tmp1[63:0]
+	</operation>
+	<instruction name="CMPOXADD" form ="m64, r64, r64" xed="CMPOXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPNOXADD" form ="m64, r64, r64" xed="CMPNOXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPBXADD" form ="m64, r64, r64" xed="CMPBXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPNBXADD" form ="m64, r64, r64" xed="CMPNBXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPZXADD" form ="m64, r64, r64" xed="CMPZXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPNZXADD" form ="m64, r64, r64" xed="CMPNZXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPBEXADD" form ="m64, r64, r64" xed="CMPBEXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPNBEXADD" form ="m64, r64, r64" xed="CMPNBEXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPSXADD" form ="m64, r64, r64" xed="CMPSXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPNSXADD" form ="m64, r64, r64" xed="CMPNSXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPPXADD" form ="m64, r64, r64" xed="CMPPXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPNPXADD" form ="m64, r64, r64" xed="CMPNPXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPLXADD" form ="m64, r64, r64" xed="CMPLXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPNLXADD" form ="m64, r64, r64" xed="CMPNLXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPLEXADD" form ="m64, r64, r64" xed="CMPLEXADD_MEMu64_GPR64u64_GPR64u64" />
+	<instruction name="CMPNLEXADD" form ="m64, r64, r64" xed="CMPNLEXADD_MEMu64_GPR64u64_GPR64u64" />
+	<CPUID>CMPCCXADD</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_crc32_u8" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="crc" />
+	<parameter etype="UI8" type="unsigned char" varname="v" />
+	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst".</description>
+	<operation>tmp1[7:0] := v[0:7] // bit reflection
+tmp2[31:0] := crc[0:31] // bit reflection
+tmp3[39:0] := tmp1[7:0] &lt;&lt; 32 
+tmp4[39:0] := tmp2[31:0] &lt;&lt; 8
+tmp5[39:0] := tmp3[39:0] XOR tmp4[39:0]
+tmp6[31:0] := MOD2(tmp5[39:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
+dst[31:0] := tmp6[0:31] // bit reflection
+	</operation>
+	<instruction form="r32, r8" name="CRC32" xed="CRC32_GPRyy_GPR8b" />
+	<CPUID>CRC32</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_crc32_u16" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="crc" />
+	<parameter etype="UI16" type="unsigned short" varname="v" />
+	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst".</description>
+	<operation>tmp1[15:0] := v[0:15] // bit reflection
+tmp2[31:0] := crc[0:31] // bit reflection
+tmp3[47:0] := tmp1[15:0] &lt;&lt; 32
+tmp4[47:0] := tmp2[31:0] &lt;&lt; 16
+tmp5[47:0] := tmp3[47:0] XOR tmp4[47:0]
+tmp6[31:0] := MOD2(tmp5[47:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
+dst[31:0] := tmp6[0:31] // bit reflection
+	</operation>
+	<instruction form="r32, r16" name="CRC32" xed="CRC32_GPRyy_GPRv" />
+	<CPUID>CRC32</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_crc32_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="crc" />
+	<parameter etype="UI32" type="unsigned int" varname="v" />
+	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst".</description>
+	<operation>tmp1[31:0] := v[0:31] // bit reflection
+tmp2[31:0] := crc[0:31] // bit reflection
+tmp3[63:0] := tmp1[31:0] &lt;&lt; 32
+tmp4[63:0] := tmp2[31:0] &lt;&lt; 32
+tmp5[63:0] := tmp3[63:0] XOR tmp4[63:0]
+tmp6[31:0] := MOD2(tmp5[63:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
+dst[31:0] := tmp6[0:31] // bit reflection
+	</operation>
+	<instruction form="r32, r32" name="CRC32" xed="CRC32_GPRyy_GPRv" />
+	<CPUID>CRC32</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_crc32_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="crc" />
+	<parameter etype="UI64" type="unsigned __int64" varname="v" />
+	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst".</description>
+	<operation>tmp1[63:0] := v[0:63] // bit reflection
+tmp2[31:0] := crc[0:31] // bit reflection
+tmp3[95:0] := tmp1[31:0] &lt;&lt; 32
+tmp4[95:0] := tmp2[63:0] &lt;&lt; 64
+tmp5[95:0] := tmp3[95:0] XOR tmp4[95:0]
+tmp6[31:0] := MOD2(tmp5[95:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
+dst[31:0] := tmp6[0:31] // bit reflection
+	</operation>
+	<instruction form="r64, r64" name="CRC32" xed="CRC32_GPRyy_GPRv" />
+	<CPUID>CRC32</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_enqcmd" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter type="void*" memwidth="512" varname="__dst" />
+	<parameter type="const void*" memwidth="512" varname="__src" />
+	<description>Reads 64-byte command pointed by "__src", formats 64-byte enqueue store data, and performs 64-byte enqueue store to memory pointed by "__dst". This intrinsics may only be used in User mode.</description>
+	<instruction form="r16/r32/r64, m512" name="ENQCMD" xed="ENQCMD_GPRa_MEMu32" />
+	<CPUID>ENQCMD</CPUID>
+	<header>immintrin.h</header>
+	<category>Unknown</category>
+	</intrinsic>
+	<intrinsic name="_enqcmds" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter type="void*" memwidth="512" varname="__dst" />
+	<parameter type="const void*" memwidth="512" varname="__src" />
+	<description>Reads 64-byte command pointed by "__src", formats 64-byte enqueue store data, and performs 64-byte enqueue store to memory pointed by "__dst" This intrinsic may only be used in Privileged mode.</description>
+	<instruction form="r16/r32/r64, m512" name="ENQCMDS" xed="ENQCMDS_GPRa_MEMu32" />
+	<CPUID>ENQCMD</CPUID>
+	<header>immintrin.h</header>
+	<category>Unknown</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_cvtph_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP16" type="__m128i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	m := j*16
+	dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_YMMqq_XMMdq" />
+	<CPUID>F16C</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm256_cvtps_ph" tech="AVX_ALL">
+	<return etype="FP16" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_imm_note]</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	l := 32*j
+	dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMdq_YMMqq_IMMb" />
+	<CPUID>F16C</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtph_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP16" type="__m128i" varname="a" />
+	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	m := j*16
+	dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_XMMdq_XMMq" />
+	<CPUID>F16C</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_ph" tech="AVX_ALL">
+	<return etype="FP16" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
+	[round_imm_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := 16*j
+	l := 32*j
+	dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
+ENDFOR
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMq_XMMdq_IMMb" />
+	<CPUID>F16C</CPUID>
+	<header>immintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_fmadd_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADD132PD" xed="VFMADD132PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD213PD" xed="VFMADD213PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD231PD" xed="VFMADD231PD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmadd_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMADD132PD" xed="VFMADD132PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMADD213PD" xed="VFMADD213PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMADD231PD" xed="VFMADD231PD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADD132PS" xed="VFMADD132PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD213PS" xed="VFMADD213PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD231PS" xed="VFMADD231PS_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmadd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMADD132PS" xed="VFMADD132PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMADD213PS" xed="VFMADD213PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMADD231PS" xed="VFMADD231PS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_sd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADD132SD" xed="VFMADD132SD_XMMdq_XMMq_XMMq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD213SD" xed="VFMADD213SD_XMMdq_XMMq_XMMq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD231SD" xed="VFMADD231SD_XMMdq_XMMq_XMMq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmadd_ss" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADD132SS" xed="VFMADD132SS_XMMdq_XMMd_XMMd" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD213SS" xed="VFMADD213SS_XMMdq_XMMd_XMMd" />
+	<instruction form="xmm, xmm, xmm" name="VFMADD231SS" xed="VFMADD231SS_XMMdq_XMMd_XMMd" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmaddsub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF ((j &amp; 1) == 0) 
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmaddsub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF ((j &amp; 1) == 0) 
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	ELSE
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmaddsub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF ((j &amp; 1) == 0) 
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmaddsub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF ((j &amp; 1) == 0) 
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	ELSE
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUB132PD" xed="VFMSUB132PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB213PD" xed="VFMSUB213PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB231PD" xed="VFMSUB231PD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmsub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMSUB132PD" xed="VFMSUB132PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUB213PD" xed="VFMSUB213PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUB231PD" xed="VFMSUB231PD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUB132PS" xed="VFMSUB132PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB213PS" xed="VFMSUB213PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB231PS" xed="VFMSUB231PS_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmsub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMSUB132PS" xed="VFMSUB132PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUB213PS" xed="VFMSUB213PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUB231PS" xed="VFMSUB231PS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_sd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUB132SD" xed="VFMSUB132SD_XMMdq_XMMq_XMMq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB213SD" xed="VFMSUB213SD_XMMdq_XMMq_XMMq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB231SD" xed="VFMSUB231SD_XMMdq_XMMq_XMMq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsub_ss" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUB132SS" xed="VFMSUB132SS_XMMdq_XMMd_XMMd" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB213SS" xed="VFMSUB213SS_XMMdq_XMMd_XMMd" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUB231SS" xed="VFMSUB231SS_XMMdq_XMMd_XMMd" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsubadd_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF ((j &amp; 1) == 0) 
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmsubadd_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	IF ((j &amp; 1) == 0) 
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
+	ELSE
+		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fmsubadd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF ((j &amp; 1) == 0) 
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fmsubadd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	IF ((j &amp; 1) == 0) 
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
+	ELSE
+		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMADD132PD" xed="VFNMADD132PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD213PD" xed="VFNMADD213PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD231PD" xed="VFNMADD231PD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fnmadd_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFNMADD132PD" xed="VFNMADD132PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFNMADD213PD" xed="VFNMADD213PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFNMADD231PD" xed="VFNMADD231PD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMADD132PS" xed="VFNMADD132PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD213PS" xed="VFNMADD213PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD231PS" xed="VFNMADD231PS_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fnmadd_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFNMADD132PS" xed="VFNMADD132PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFNMADD213PS" xed="VFNMADD213PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFNMADD231PS" xed="VFNMADD231PS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_sd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMADD132SD" xed="VFNMADD132SD_XMMdq_XMMq_XMMq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD213SD" xed="VFNMADD213SD_XMMdq_XMMq_XMMq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD231SD" xed="VFNMADD231SD_XMMdq_XMMq_XMMq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmadd_ss" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMADD132SS" xed="VFNMADD132SS_XMMdq_XMMd_XMMd" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD213SS" xed="VFNMADD213SS_XMMdq_XMMd_XMMd" />
+	<instruction form="xmm, xmm, xmm" name="VFNMADD231SS" xed="VFNMADD231SS_XMMdq_XMMd_XMMd" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fnmsub_pd" tech="AVX_ALL">
+	<return etype="FP64" type="__m256d" varname="dst" />
+	<parameter etype="FP64" type="__m256d" varname="a" />
+	<parameter etype="FP64" type="__m256d" varname="b" />
+	<parameter etype="FP64" type="__m256d" varname="c" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*64
+	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB132PD" xed="VFNMSUB132PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB213PD" xed="VFNMSUB213PD_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB231PD" xed="VFNMSUB231PD_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ENDFOR	
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_XMMdq_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_XMMdq_XMMdq_XMMdq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_fnmsub_ps" tech="AVX_ALL">
+	<return etype="FP32" type="__m256" varname="dst" />
+	<parameter etype="FP32" type="__m256" varname="a" />
+	<parameter etype="FP32" type="__m256" varname="b" />
+	<parameter etype="FP32" type="__m256" varname="c" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*32
+	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
+ENDFOR	
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB132PS" xed="VFNMSUB132PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB213PS" xed="VFNMSUB213PS_YMMqq_YMMqq_YMMqq" />
+	<instruction form="ymm, ymm, ymm" name="VFNMSUB231PS" xed="VFNMSUB231PS_YMMqq_YMMqq_YMMqq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_sd" tech="AVX_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="c" />
+	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMdq_XMMq_XMMq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMdq_XMMq_XMMq" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMdq_XMMq_XMMq" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_fnmsub_ss" tech="AVX_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="c" />
+	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMdq_XMMd_XMMd" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMdq_XMMd_XMMd" />
+	<instruction form="xmm, xmm, xmm" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMdq_XMMd_XMMd" />
+	<CPUID>FMA</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_readfsbase_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<description>Read the FS segment base register and store the 32-bit result in "dst".</description>
+	<operation>dst[31:0] := FS_Segment_Base_Register
+dst[63:32] := 0
+	</operation>
+	<instruction form="r32" name="RDFSBASE" xed="RDFSBASE_GPRy" />
+	<CPUID>FSGSBASE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_readfsbase_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<description>Read the FS segment base register and store the 64-bit result in "dst".</description>
+	<operation>dst[63:0] := FS_Segment_Base_Register
+	</operation>
+	<instruction form="r64" name="RDFSBASE" xed="RDFSBASE_GPRy" />
+	<CPUID>FSGSBASE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_readgsbase_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<description>Read the GS segment base register and store the 32-bit result in "dst".</description>
+	<operation>dst[31:0] := GS_Segment_Base_Register
+dst[63:32] := 0
+	</operation>
+	<instruction form="r32" name="RDGSBASE" xed="RDGSBASE_GPRy" />
+	<CPUID>FSGSBASE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_readgsbase_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<description>Read the GS segment base register and store the 64-bit result in "dst".</description>
+	<operation>dst[63:0] := GS_Segment_Base_Register
+	</operation>
+	<instruction form="r64" name="RDGSBASE" xed="RDGSBASE_GPRy" />
+	<CPUID>FSGSBASE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_writefsbase_u32" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Write the unsigned 32-bit integer "a" to the FS segment base register.</description>
+	<operation>
+FS_Segment_Base_Register[31:0] := a[31:0]
+FS_Segment_Base_Register[63:32] := 0
+	</operation>
+	<instruction form="r32" name="WRFSBASE" xed="WRFSBASE_GPRy" />
+	<CPUID>FSGSBASE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_writefsbase_u64" tech="Other">
+	<return type="void" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Write the unsigned 64-bit integer "a" to the FS segment base register.</description>
+	<operation>
+FS_Segment_Base_Register[63:0] := a[63:0]
+	</operation>
+	<instruction form="r64" name="WRFSBASE" xed="WRFSBASE_GPRy" />
+	<CPUID>FSGSBASE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_writegsbase_u32" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Write the unsigned 32-bit integer "a" to the GS segment base register.</description>
+	<operation>
+GS_Segment_Base_Register[31:0] := a[31:0]
+GS_Segment_Base_Register[63:32] := 0
+	</operation>
+	<instruction form="r32" name="WRGSBASE" xed="WRGSBASE_GPRy" />
+	<CPUID>FSGSBASE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_writegsbase_u64" tech="Other">
+	<return type="void" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Write the unsigned 64-bit integer "a" to the GS segment base register.</description>
+	<operation>
+GS_Segment_Base_Register[63:0] := a[63:0]
+	</operation>
+	<instruction form="r64" name="WRGSBASE" xed="WRGSBASE_GPRy" />
+	<CPUID>FSGSBASE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_fxrstor" tech="Other">
+	<return type="void" />
+	<parameter memwidth="4096" type="void *" varname="mem_addr" />
+	<description>Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr". This data should have been written to memory previously using the FXSAVE instruction, and in the same format as required by the operating mode. "mem_addr" must be aligned on a 16-byte boundary.</description>
+	<operation>state_x87_fpu_mmx_sse := fxrstor(MEM[mem_addr+512*8:mem_addr])
+	</operation>
+	<instruction form="m512" name="FXRSTOR" xed="FXRSTOR_MEMmfpxenv" />
+	<CPUID>FXSR</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_fxrstor64" tech="Other">
+	<return type="void" />
+	<parameter memwidth="4096" type="void *" varname="mem_addr" />
+	<description>Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr". This data should have been written to memory previously using the FXSAVE64 instruction, and in the same format as required by the operating mode. "mem_addr" must be aligned on a 16-byte boundary.</description>
+	<operation>state_x87_fpu_mmx_sse := fxrstor64(MEM[mem_addr+512*8:mem_addr])
+	</operation>
+	<instruction form="m512" name="FXRSTOR64" xed="FXRSTOR64_MEMmfpxenv" />
+	<CPUID>FXSR</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_fxsave" tech="Other">
+	<return type="void" />
+	<parameter memwidth="4096" type="void *" varname="mem_addr" />
+	<description>Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr". The layout of the 512-byte region depends on the operating mode. Bytes [511:464] are available for software use and will not be overwritten by the processor.</description>
+	<operation>MEM[mem_addr+512*8:mem_addr] := fxsave(state_x87_fpu_mmx_sse)
+	</operation>
+	<instruction form="m512" name="FXSAVE" xed="FXSAVE_MEMmfpxenv" />
+	<CPUID>FXSR</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_fxsave64" tech="Other">
+	<return type="void" />
+	<parameter memwidth="4096" type="void *" varname="mem_addr" />
+	<description>Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr". The layout of the 512-byte region depends on the operating mode. Bytes [511:464] are available for software use and will not be overwritten by the processor.</description>
+	<operation>MEM[mem_addr+512*8:mem_addr] := fxsave64(state_x87_fpu_mmx_sse)
+	</operation>
+	<instruction form="m512" name="FXSAVE64" xed="FXSAVE64_MEMmfpxenv" />
+	<CPUID>FXSR</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_maskz_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 63
+	IF k[j]
+		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+	ELSE
+		dst.byte[j] := 0
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm" name="VGF2P8MULB" xed="VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 63
+	IF k[j]
+		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+	ELSE
+		dst.byte[j] := src.byte[j]
+	FI
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm" name="VGF2P8MULB" xed="VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m512i" varname="dst" />
+	<parameter etype="UI8" type="__m512i" varname="a" />
+	<parameter etype="UI8" type="__m512i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 63
+	dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm" name="VGF2P8MULB" xed="VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="x" />
+	<parameter etype="UI64" type="__m512i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 7
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="x" />
+	<parameter etype="UI64" type="__m512i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 7
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := src.qword[j].byte[i]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="x" />
+	<parameter etype="UI64" type="__m512i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst".</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 7
+	FOR i := 0 to 7
+		dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_maskz_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="x" />
+	<parameter etype="UI64" type="__m512i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 7
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {z}, zmm, zmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_mask_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="src" />
+	<parameter etype="MASK" type="__mmask64" varname="k" />
+	<parameter etype="UI64" type="__m512i" varname="x" />
+	<parameter etype="UI64" type="__m512i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 7
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := src.qword[j].byte[b]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm {k}, zmm, zmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm512_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m512i" varname="dst" />
+	<parameter etype="UI64" type="__m512i" varname="x" />
+	<parameter etype="UI64" type="__m512i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst".</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 7
+	FOR i := 0 to 7
+		dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+	ENDFOR
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512F</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_maskz_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 31
+	IF k[j]
+		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+	ELSE
+		dst.byte[j] := 0
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm" name="VGF2P8MULB" xed="VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 31
+	IF k[j]
+		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+	ELSE
+		dst.byte[j] := src.byte[j]
+	FI
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm" name="VGF2P8MULB" xed="VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m256i" varname="dst" />
+	<parameter etype="UI8" type="__m256i" varname="a" />
+	<parameter etype="UI8" type="__m256i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 31
+	dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm" name="VGF2P8MULB" xed="VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 15
+	IF k[j]
+		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+	ELSE
+		dst.byte[j] := 0
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm" name="VGF2P8MULB" xed="VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 15
+	IF k[j]
+		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+	ELSE
+		dst.byte[j] := src.byte[j]
+	FI
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm" name="VGF2P8MULB" xed="VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_gf2p8mul_epi8" tech="Other">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
+	<operation>
+DEFINE gf2p8mul_byte(src1byte, src2byte) {
+	tword := 0
+	FOR i := 0 to 7
+		IF src2byte.bit[i]
+			tword := tword XOR (src1byte &lt;&lt; i)
+		FI
+	ENDFOR
+	FOR i := 14 downto 8
+		p := 0x11B &lt;&lt; (i-8)
+		IF tword.bit[i]
+			tword := tword XOR p
+		FI
+	ENDFOR
+	RETURN tword.byte[0]
+}
+FOR j := 0 TO 15
+	dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm" name="VGF2P8MULB" xed="VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="x" />
+	<parameter etype="UI64" type="__m256i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 3
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="x" />
+	<parameter etype="UI64" type="__m256i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 3
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := src.qword[j].byte[i]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="x" />
+	<parameter etype="UI64" type="__m256i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst".</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 3
+	FOR i := 0 to 7
+		dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="x" />
+	<parameter etype="UI64" type="__m128i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 1
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="x" />
+	<parameter etype="UI64" type="__m128i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 1
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := src.qword[j].byte[i]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_gf2p8affine_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="x" />
+	<parameter etype="UI64" type="__m128i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst".</description>
+	<operation>
+DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 1
+	FOR i := 0 to 7
+		dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_maskz_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="x" />
+	<parameter etype="UI64" type="__m256i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 3
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {z}, ymm, ymm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_mask_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="src" />
+	<parameter etype="MASK" type="__mmask32" varname="k" />
+	<parameter etype="UI64" type="__m256i" varname="x" />
+	<parameter etype="UI64" type="__m256i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 3
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := src.qword[j].byte[i]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm {k}, ymm, ymm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm256_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m256i" varname="dst" />
+	<parameter etype="UI64" type="__m256i" varname="x" />
+	<parameter etype="UI64" type="__m256i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst".</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 3
+	FOR i := 0 to 7
+		dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+	ENDFOR
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskz_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="x" />
+	<parameter etype="UI64" type="__m128i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 1
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := 0
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mask_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="src" />
+	<parameter etype="MASK" type="__mmask16" varname="k" />
+	<parameter etype="UI64" type="__m128i" varname="x" />
+	<parameter etype="UI64" type="__m128i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 1
+	FOR i := 0 to 7
+		IF k[j*8+i]
+			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+		ELSE
+			dst.qword[j].byte[i] := src.qword[j].byte[i]
+		FI
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_gf2p8affineinv_epi64_epi8" tech="Other">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="x" />
+	<parameter etype="UI64" type="__m128i" varname="A" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
+	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst".</description>
+	<operation>DEFINE parity(x) {
+	t := 0
+	FOR i := 0 to 7
+		t := t XOR x.bit[i]
+	ENDFOR
+	RETURN t
+}
+DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
+	FOR i := 0 to 7
+		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
+	ENDFOR
+	RETURN retbyte
+}
+FOR j := 0 TO 1
+	FOR i := 0 to 7
+		dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
+	ENDFOR
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm, xmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
+	<CPUID>GFNI</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_hreset" tech="Other">
+	<return type="void" />
+	<parameter type="int" varname="__eax" etype="SI32" />
+	<description>Provides a hint to the processor to selectively reset the prediction history of the current logical processor specified by a signed 32-bit integer "__eax".</description>
+	<instruction name="HRESET" form="imm8" xed="HRESET_IMM8" />
+	<CPUID>HRESET</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+<intrinsic name="_invpcid" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="type" />
+	<parameter memwidth="128" type="void*" varname="descriptor" />
+	<description>Invalidate mappings in the Translation Lookaside Buffers (TLBs) and paging-structure caches for the processor context identifier (PCID) specified by "descriptor" based on the invalidation type specified in "type". 
+	The PCID "descriptor" is specified as a 16-byte memory operand (with no alignment restrictions) where bits [11:0] specify the PCID, and bits [127:64] specify the linear address; bits [63:12] are reserved.
+	The types supported are:
+		0) Individual-address invalidation: If "type" is 0, the logical processor invalidates mappings for a single linear address and tagged with the PCID specified in "descriptor", except global translations. The instruction may also invalidate global translations, mappings for other linear addresses, or mappings tagged with other PCIDs.
+		1) Single-context invalidation: If "type" is 1, the logical processor invalidates all mappings tagged with the PCID specified in "descriptor" except global translations. In some cases, it may invalidate mappings for other PCIDs as well.
+		2) All-context invalidation: If "type" is 2, the logical processor invalidates all mappings tagged with any PCID.
+		3) All-context invalidation, retaining global translations: If "type" is 3, the logical processor invalidates all mappings tagged with any PCID except global translations, ignoring "descriptor". The instruction may also invalidate global translations as well.</description>
+	<operation>
+CASE type[1:0] OF
+0: // individual-address invalidation retaining global translations
+	OP_PCID := MEM[descriptor+11:descriptor]
+	ADDR := MEM[descriptor+127:descriptor+64]
+	BREAK
+1: // single PCID invalidation retaining globals
+	OP_PCID := MEM[descriptor+11:descriptor]
+	// invalidate all mappings tagged with OP_PCID except global translations
+	BREAK
+2: // all PCID invalidation
+	// invalidate all mappings tagged with any PCID
+	BREAK
+3: // all PCID invalidation retaining global translations
+	// invalidate all mappings tagged with any PCID except global translations
+	BREAK
+ESAC
+	</operation>
+	<instruction form="r32, m128" name="INVPCID" xed="INVPCID_GPR32_MEMdq" />
+	<CPUID>INVPCID</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_aesdec128kl_u8" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="128" />
+		<parameter type="__m128i" varname="__idata" etype="UI8" />
+		<parameter type="const void*" varname="__h" etype="UI8" memwidth="384" />
+		<description>Decrypt 10 rounds of unsigned 8-bit integers in "__idata" using 128-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
+		<operation>MEM[__odata+127:__odata] := AES128Decrypt (__idata[127:0], __h[383:0])
+dst := ZF
+		</operation>
+		<instruction name="AESDEC128KL" form="xmm, m32" xed="AESDEC128KL_XMMu8_MEMu8" />
+	<CPUID>KEYLOCKER</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesdec256kl_u8" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="128" />
+		<parameter type="__m128i" varname="__idata" etype="UI8" />
+		<parameter type="const void*" varname="__h" etype="UI8" memwidth="512" />
+		<description>Decrypt 10 rounds of unsigned 8-bit integers in "__idata" using 256-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
+		<operation>MEM[__odata+127:__odata] := AES256Decrypt (__idata[127:0], __h[511:0])
+dst := ZF
+		</operation>
+		<instruction name="AESDEC256KL" form="xmm, m32" xed="AESDEC256KL_XMMu8_MEMu8" />
+	<CPUID>KEYLOCKER</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesenc128kl_u8" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="128" />
+		<parameter type="__m128i" varname="__idata" etype="UI8" />
+		<parameter type="const void*" varname="__h" etype="UI8" memwidth="384" />
+		<description>Encrypt 10 rounds of unsigned 8-bit integers in "__idata" using 128-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status.</description>
+		<operation>MEM[__odata+127:__odata] := AES128Encrypt (__idata[127:0], __h[383:0])
+dst := ZF
+		</operation>
+		<instruction name="AESENC128KL" form="xmm, m32" xed="AESENC128KL_XMMu8_MEMu8" />
+	<CPUID>KEYLOCKER</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesenc256kl_u8" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="128" />
+		<parameter type="__m128i" varname="__idata" etype="UI8" />
+		<parameter type="const void*" varname="__h" etype="UI8" memwidth="512" />
+		<description>Encrypt 10 rounds of unsigned 8-bit integers in "__idata" using 256-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
+		<operation>MEM[__odata+127:__odata] := AES256Encrypt (__idata[127:0], __h[511:0])
+dst := ZF
+		</operation>
+		<instruction name="AESENC256KL" form="xmm, m32" xed="AESENC256KL_XMMu8_MEMu8" />
+	<CPUID>KEYLOCKER</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_encodekey128_u32" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned int" varname="dst" etype="UI32" />
+		<parameter type="unsigned int" varname="__htype" etype="UI32" />
+		<parameter type="__m128i" varname="__key" etype="UI8" />
+		<parameter type="void*" varname="__h" etype="UI8" memwidth="768" />
+		<description>Wrap a 128-bit AES key from "__key" into a 384-bit key __h stored in "__h" and set IWKey's NoBackup and KeySource bits in "dst". The explicit source operand "__htype" specifies __h restrictions.</description>
+		<operation>__h[383:0] := WrapKey128(__key[127:0], __htype)
+dst[0] := IWKey.NoBackup
+dst[4:1] := IWKey.KeySource[3:0]
+		</operation>
+		<instruction name="ENCODEKEY128" form="r32, r32" xed="ENCODEKEY128_GPR32u8_GPR32u8" />
+	<CPUID>KEYLOCKER</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_encodekey256_u32" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned int" varname="dst" etype="UI32" />
+		<parameter type="unsigned int" varname="__htype" etype="UI32" />
+		<parameter type="__m128i" varname="__key_lo" etype="UI8" />
+		<parameter type="__m128i" varname="__key_hi" etype="UI8" />
+		<parameter type="void*" varname="__h" etype="UI8" memwidth="896" />
+		<description>Wrap a 256-bit AES key from "__key_hi" and "__key_lo" into a 512-bit key stored in "__h" and set IWKey's NoBackup and KeySource bits in "dst". The 32-bit "__htype" specifies __h restrictions.</description>
+		<operation>__h[511:0] := WrapKey256(__key_lo[127:0], __key_hi[127:0], __htype)
+dst[0] := IWKey.NoBackup
+dst[4:1] := IWKey.KeySource[3:0]
+		</operation>
+		<instruction name="ENCODEKEY256" form="r32, r32" xed="ENCODEKEY256_GPR32u8_GPR32u8" />
+	<CPUID>KEYLOCKER</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadiwkey" tech="Other">
+		<type>Flag</type>
+		<return type="void" />
+		<parameter type="unsigned int" varname="__ctl" etype="UI32" />
+		<parameter type="__m128i" varname="__intkey" etype="UI8" />
+		<parameter type="__m128i" varname="__enkey_lo" etype="UI8" />
+		<parameter type="__m128i" varname="__enkey_hi" etype="UI8" />
+		<description>Load internal wrapping key (IWKey). The 32-bit unsigned integer "__ctl" specifies IWKey's KeySource and whether backing up the key is permitted. IWKey's 256-bit encryption key is loaded from "__enkey_lo" and "__enkey_hi". IWKey's 128-bit integrity key is loaded from "__intkey".</description>
+		<instruction name="LOADIWKEY" form="xmm, xmm" xed="LOADIWKEY_XMMu8_XMMu8" />
+	<CPUID>KEYLOCKER</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+<intrinsic name="_mm_aesdecwide128kl_u8" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="1024" />
+		<parameter type="const __m128i*" varname="__idata" etype="UI8" memwidth="1024" />
+		<parameter type="const void*" varname="__h" etype="UI8" memwidth="384" />
+		<description>Decrypt 10 rounds of 8 groups of unsigned 8-bit integers in "__idata" using 128-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
+		<operation>FOR i := 0 to 7
+	__odata[i] := AES128Decrypt (__idata[i], __h[383:0])
+ENDFOR
+dst := ZF
+		</operation>
+		<instruction name="AESDECWIDE128KL" form="m32" xed="AESDECWIDE128KL_MEMu8" />
+	<CPUID>KEYLOCKER_WIDE</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesdecwide256kl_u8" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="1024" />
+		<parameter type="const __m128i*" varname="__idata" etype="UI8" memwidth="1024" />
+		<parameter type="const void*" varname="__h" etype="UI8" memwidth="512" />
+		<description>Decrypt 10 rounds of 8 groups of unsigned 8-bit integers in "__idata" using 256-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
+		<operation>FOR i := 0 to 7
+	__odata[i] := AES256Decrypt (__idata[i], __h[511:0])
+ENDFOR
+dst := ZF
+		</operation>
+		<instruction name="AESDECWIDE256KL" form="m32" xed="AESDECWIDE256KL_MEMu8" />
+	<CPUID>KEYLOCKER_WIDE</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesencwide128kl_u8" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="1024" />
+		<parameter type="const __m128i*" varname="__idata" etype="UI8" memwidth="1024" />
+		<parameter type="const void*" varname="__h" etype="UI8" memwidth="384" />
+		<description>Encrypt 10 rounds of 8 groups of unsigned 8-bit integers in "__idata" using 128-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
+		<operation>FOR i := 0 to 7
+	__odata[i] := AES128Encrypt (__idata[i], __h[383:0])
+ENDFOR
+dst := ZF
+		</operation>
+		<instruction name="AESENCWIDE128KL" form="m32" xed="AESENCWIDE128KL_MEMu8" />
+	<CPUID>KEYLOCKER_WIDE</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_aesencwide256kl_u8" tech="Other">
+		<type>Flag</type>
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="1024" />
+		<parameter type="const __m128i*" varname="__idata" etype="UI8" memwidth="1024" />
+		<parameter type="const void*" varname="__h" etype="UI8" memwidth="512" />
+		<description>Encrypt 10 rounds of 8 groups of unsigned 8-bit integers in "__idata" using 256-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
+		<operation>FOR i := 0 to 7
+	__odata[i] := AES256Encrypt (__idata[i], __h[512:0])
+ENDFOR
+dst := ZF
+		</operation>
+		<instruction name="AESENCWIDE256KL" form="m32" xed="AESENCWIDE256KL_MEMu8" />
+	<CPUID>KEYLOCKER_WIDE</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	
+<intrinsic name="_lzcnt_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Count the number of leading zero bits in unsigned 32-bit integer "a", and return that count in "dst".</description>
+	<operation>
+tmp := 31
+dst := 0
+DO WHILE (tmp &gt;= 0 AND a[tmp] == 0)
+	tmp := tmp - 1
+	dst := dst + 1
+OD
+	</operation>
+	<instruction form="r32, r32" name="LZCNT" xed="LZCNT_GPRv_GPRv" />
+	<CPUID>LZCNT</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_lzcnt_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Count the number of leading zero bits in unsigned 64-bit integer "a", and return that count in "dst".</description>
+	<operation>
+tmp := 63
+dst := 0
+DO WHILE (tmp &gt;= 0 AND a[tmp] == 0)
+	tmp := tmp - 1
+	dst := dst + 1
+OD
+	</operation>
+	<instruction form="r64, r64" name="LZCNT" xed="LZCNT_GPRv_GPRv" />
+	<CPUID>LZCNT</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_m_from_int64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Copy 64-bit integer "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="mm, r64" name="MOVQ" xed="MOVQ_MMXq_GPR64" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_m_to_int64" tech="MMX">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m64" varname="a" />
+	<description>Copy 64-bit integer "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="r64, mm" name="MOVQ" xed="MOVQ_GPR64_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_m_from_int" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+dst[63:32] := 0
+	</operation>
+	<instruction form="mm, r32" name="MOVD" xed="MOVD_MMXq_GPR32" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_m_to_int" tech="MMX">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m64" varname="a" />
+	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+	</operation>
+	<instruction form="r32, mm" name="MOVD" xed="MOVD_GPR32_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi32_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+dst[63:32] := 0
+	</operation>
+	<instruction form="mm, r32" name="MOVD" xed="MOVD_MMXq_GPR32" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi64_si32" tech="MMX">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m64" varname="a" />
+	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+	</operation>
+	<instruction form="r32, mm" name="MOVD" xed="MOVD_GPR32_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtm64_si64" tech="MMX">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m64" varname="a" />
+	<description>Copy 64-bit integer "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="r64, mm" name="MOVQ" xed="MOVQ_GPR64_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi64_m64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Copy 64-bit integer "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="mm, r64" name="MOVQ" xed="MOVQ_MMXq_GPR64" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_m_empty" tech="MMX">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions. This instruction must be used at the end of all MMX technology procedures.</description>
+	<instruction name="EMMS" xed="EMMS" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_empty" tech="MMX">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions. This instruction must be used at the end of all MMX technology procedures.</description>
+	<instruction name="EMMS" xed="EMMS" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_m_packsswb" tech="MMX">
+	<return etype="SI8" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := Saturate8(a[15:0])
+dst[15:8] := Saturate8(a[31:16])
+dst[23:16] := Saturate8(a[47:32])
+dst[31:24] := Saturate8(a[63:48])
+dst[39:32] := Saturate8(b[15:0])
+dst[47:40] := Saturate8(b[31:16])
+dst[55:48] := Saturate8(b[47:32])
+dst[63:56] := Saturate8(b[63:48])
+	</operation>
+	<instruction form="mm, mm" name="PACKSSWB" xed="PACKSSWB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_m_packssdw" tech="MMX">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[31:0])
+dst[31:16] := Saturate16(a[63:32])
+dst[47:32] := Saturate16(b[31:0])
+dst[63:48] := Saturate16(b[63:32])
+	</operation>
+	<instruction form="mm, mm" name="PACKSSDW" xed="PACKSSDW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_m_packuswb" tech="MMX">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := SaturateU8(a[15:0])
+dst[15:8] := SaturateU8(a[31:16])
+dst[23:16] := SaturateU8(a[47:32])
+dst[31:24] := SaturateU8(a[63:48])
+dst[39:32] := SaturateU8(b[15:0])
+dst[47:40] := SaturateU8(b[31:16])
+dst[55:48] := SaturateU8(b[47:32])
+dst[63:56] := SaturateU8(b[63:48])
+	</operation>
+	<instruction form="mm, mm" name="PACKUSWB" xed="PACKUSWB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_packs_pi16" tech="MMX">
+	<return etype="SI8" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := Saturate8(a[15:0])
+dst[15:8] := Saturate8(a[31:16])
+dst[23:16] := Saturate8(a[47:32])
+dst[31:24] := Saturate8(a[63:48])
+dst[39:32] := Saturate8(b[15:0])
+dst[47:40] := Saturate8(b[31:16])
+dst[55:48] := Saturate8(b[47:32])
+dst[63:56] := Saturate8(b[63:48])
+	</operation>
+	<instruction form="mm, mm" name="PACKSSWB" xed="PACKSSWB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_packs_pi32" tech="MMX">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[31:0])
+dst[31:16] := Saturate16(a[63:32])
+dst[47:32] := Saturate16(b[31:0])
+dst[63:48] := Saturate16(b[63:32])
+	</operation>
+	<instruction form="mm, mm" name="PACKSSDW" xed="PACKSSDW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_packs_pu16" tech="MMX">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := SaturateU8(a[15:0])
+dst[15:8] := SaturateU8(a[31:16])
+dst[23:16] := SaturateU8(a[47:32])
+dst[31:24] := SaturateU8(a[63:48])
+dst[39:32] := SaturateU8(b[15:0])
+dst[47:40] := SaturateU8(b[31:16])
+dst[55:48] := SaturateU8(b[47:32])
+dst[63:56] := SaturateU8(b[63:48])
+	</operation>
+	<instruction form="mm, mm" name="PACKUSWB" xed="PACKUSWB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_m_punpckhbw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[63:0], src2[63:0]) {
+	dst[7:0] := src1[39:32]
+	dst[15:8] := src2[39:32] 
+	dst[23:16] := src1[47:40]
+	dst[31:24] := src2[47:40]
+	dst[39:32] := src1[55:48]
+	dst[47:40] := src2[55:48]
+	dst[55:48] := src1[63:56]
+	dst[63:56] := src2[63:56]
+	RETURN dst[63:0]
+}
+dst[63:0] := INTERLEAVE_HIGH_BYTES(a[63:0], b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKHBW" xed="PUNPCKHBW_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_punpckhwd" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[63:0], src2[63:0]) {
+	dst[15:0] := src1[47:32]
+	dst[31:16] := src2[47:32]
+	dst[47:32] := src1[63:48]
+	dst[63:48] := src2[63:48]
+	RETURN dst[63:0]
+}
+dst[63:0] := INTERLEAVE_HIGH_WORDS(a[63:0], b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKLBW" xed="PUNPCKLBW_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_punpckhdq" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32]
+dst[63:32] := b[63:32]
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKHDQ" xed="PUNPCKHDQ_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_punpcklbw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[63:0], src2[63:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	RETURN dst[63:0]	
+}
+dst[63:0] := INTERLEAVE_BYTES(a[63:0], b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKLBW" xed="PUNPCKLBW_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_punpcklwd" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[63:0], src2[63:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	RETURN dst[63:0]	
+}
+dst[63:0] := INTERLEAVE_WORDS(a[63:0], b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKLWD" xed="PUNPCKLWD_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_punpckldq" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+dst[63:32] := b[31:0]
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKLDQ" xed="PUNPCKLDQ_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_pi8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[63:0], src2[63:0]) {
+	dst[7:0] := src1[39:32]
+	dst[15:8] := src2[39:32] 
+	dst[23:16] := src1[47:40]
+	dst[31:24] := src2[47:40]
+	dst[39:32] := src1[55:48]
+	dst[47:40] := src2[55:48]
+	dst[55:48] := src1[63:56]
+	dst[63:56] := src2[63:56]
+	RETURN dst[63:0]	
+}
+dst[63:0] := INTERLEAVE_HIGH_BYTES(a[63:0], b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKHBW" xed="PUNPCKHBW_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[63:0], src2[63:0]) {
+	dst[15:0] := src1[47:32]
+	dst[31:16] := src2[47:32]
+	dst[47:32] := src1[63:48]
+	dst[63:48] := src2[63:48]
+	RETURN dst[63:0]
+}
+dst[63:0] := INTERLEAVE_HIGH_WORDS(a[63:0], b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKLBW" xed="PUNPCKLBW_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32]
+dst[63:32] := b[63:32]
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKHDQ" xed="PUNPCKHDQ_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_pi8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[63:0], src2[63:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	RETURN dst[63:0]	
+}
+dst[63:0] := INTERLEAVE_BYTES(a[63:0], b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKLBW" xed="PUNPCKLBW_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[63:0], src2[63:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	RETURN dst[63:0]	
+}
+dst[63:0] := INTERLEAVE_WORDS(a[63:0], b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKLWD" xed="PUNPCKLWD_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+dst[63:32] := b[31:0]
+	</operation>
+	<instruction form="mm, mm" name="PUNPCKLDQ" xed="PUNPCKLDQ_MMXq_MMXd" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_paddb" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDB" xed="PADDB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_paddw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDW" xed="PADDW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_paddd" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDD" xed="PADDD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_paddsb" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDSB" xed="PADDSB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_paddsw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDSW" xed="PADDSW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_paddusb" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDUSB" xed="PADDUSB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_paddusw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDUSW" xed="PADDUSW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psubb" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBB" xed="PSUBB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psubw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBW" xed="PSUBW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psubd" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBD" xed="PSUBD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psubsb" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBSB" xed="PSUBSB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psubsw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBSW" xed="PSUBSW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psubusb" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBUSB" xed="PSUBUSB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psubusw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBUSW" xed="PSUBUSW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_pmaddwd" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMADDWD" xed="PMADDWD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_pmulhw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMULHW" xed="PMULHW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_pmullw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	tmp[31:0] := a[i+15:i] * b[i+15:i]
+	dst[i+15:i] := tmp[15:0]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMULLW" xed="PMULLW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_pi8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDB" xed="PADDB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDW" xed="PADDW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDD" xed="PADDD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_adds_pi8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI8" type="__m64" varname="a" />
+	<parameter etype="SI8" type="__m64" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDSB" xed="PADDSB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_adds_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDSW" xed="PADDSW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_adds_pu8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDUSB" xed="PADDUSB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_adds_pu16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PADDUSW" xed="PADDUSW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_pi8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBB" xed="PSUBB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBW" xed="PSUBW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBD" xed="PSUBD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_subs_pi8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI8" type="__m64" varname="a" />
+	<parameter etype="SI8" type="__m64" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBSB" xed="PSUBSB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_subs_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBSW" xed="PSUBSW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_subs_pu8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBUSB" xed="PSUBUSB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_subs_pu16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSUBUSW" xed="PSUBUSW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_madd_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMADDWD" xed="PMADDWD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mulhi_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMULHW" xed="PMULHW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mullo_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	tmp[31:0] := a[i+15:i] * b[i+15:i]
+	dst[i+15:i] := tmp[15:0]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMULLW" xed="PMULLW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psllw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSLLW" xed="PSLLW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psllwi" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSLLW" xed="PSLLW_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_pslld" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSLLD" xed="PSLLD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_pslldi" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSLLD" xed="PSLLD_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psllq" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst".</description>
+	<operation>
+IF count[63:0] &gt; 63
+	dst[63:0] := 0
+ELSE
+	dst[63:0] := ZeroExtend64(a[63:0] &lt;&lt; count[63:0])
+FI
+	</operation>
+	<instruction form="mm, mm" name="PSLLQ" xed="PSLLQ_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psllqi" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst".</description>
+	<operation>
+IF imm8[7:0] &gt; 63
+	dst[63:0] := 0
+ELSE
+	dst[63:0] := ZeroExtend64(a[63:0] &lt;&lt; imm8[7:0])
+FI
+	</operation>
+	<instruction form="mm, imm8" name="PSLLQ" xed="PSLLQ_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psraw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSRAW" xed="PSRAW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psrawi" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSRAW" xed="PSRAW_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psrad" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSRAD" xed="PSRAD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psradi" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSRAD" xed="PSRAD_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psrlw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSRLW" xed="PSRLW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psrlwi" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSRLW" xed="PSRLW_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psrld" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSRLD" xed="PSRLD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psrldi" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSRLD" xed="PSRLD_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psrlq" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift 64-bit integer "a" right by "count" while shifting in zeros, and store the result in "dst".</description>
+	<operation>
+IF count[63:0] &gt; 63
+	dst[63:0] := 0
+ELSE
+	dst[63:0] := ZeroExtend64(a[63:0] &gt;&gt; count[63:0])
+FI
+	</operation>
+	<instruction form="mm, mm" name="PSRLQ" xed="PSRLQ_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_psrlqi" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst".</description>
+	<operation>
+IF imm8[7:0] &gt; 63
+	dst[63:0] := 0
+ELSE
+	dst[63:0] := ZeroExtend64(a[63:0] &gt;&gt; imm8[7:0])
+FI
+	</operation>
+	<instruction form="mm, imm8" name="PSRLQ" xed="PSRLQ_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sll_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSLLW" xed="PSLLW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_slli_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSLLW" xed="PSLLW_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sll_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSLLD" xed="PSLLD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_slli_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSLLD" xed="PSLLD_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sll_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst".</description>
+	<operation>
+IF count[63:0] &gt; 63
+	dst[63:0] := 0
+ELSE
+	dst[63:0] := ZeroExtend64(a[63:0] &lt;&lt; count[63:0])
+FI
+	</operation>
+	<instruction form="mm, mm" name="PSLLQ" xed="PSLLQ_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_slli_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst".</description>
+	<operation>
+IF imm8[7:0] &gt; 63
+	dst[63:0] := 0
+ELSE
+	dst[63:0] := ZeroExtend64(a[63:0] &lt;&lt; imm8[7:0])
+FI
+	</operation>
+	<instruction form="mm, imm8" name="PSLLQ" xed="PSLLQ_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sra_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSRAW" xed="PSRAW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srai_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSRAW" xed="PSRAW_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sra_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSRAD" xed="PSRAD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srai_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSRAD" xed="PSRAD_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srl_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSRLW" xed="PSRLW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srli_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSRLW" xed="PSRLW_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srl_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSRLD" xed="PSRLD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srli_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, imm8" name="PSRLD" xed="PSRLD_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srl_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="count" />
+	<description>Shift 64-bit integer "a" right by "count" while shifting in zeros, and store the result in "dst".</description>
+	<operation>
+IF count[63:0] &gt; 63
+	dst[63:0] := 0
+ELSE
+	dst[63:0] := ZeroExtend64(a[63:0] &gt;&gt; count[63:0])
+FI
+	</operation>
+	<instruction form="mm, mm" name="PSRLQ" xed="PSRLQ_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srli_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst".</description>
+	<operation>
+IF imm8[7:0] &gt; 63
+	dst[63:0] := 0
+ELSE
+	dst[63:0] := ZeroExtend64(a[63:0] &gt;&gt; imm8[7:0])
+FI
+	</operation>
+	<instruction form="mm, imm8" name="PSRLQ" xed="PSRLQ_MMXq_IMMb" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_m_pand" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] AND b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PAND" xed="PAND_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_m_pandn" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := ((NOT a[63:0]) AND b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PANDN" xed="PANDN_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_m_por" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] OR b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="POR" xed="POR_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_m_pxor" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] XOR b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PXOR" xed="PXOR_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_and_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] AND b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PAND" xed="PAND_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_andnot_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := ((NOT a[63:0]) AND b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PANDN" xed="PANDN_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_or_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] OR b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="POR" xed="POR_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_xor_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] XOR b[63:0])
+	</operation>
+	<instruction form="mm, mm" name="PXOR" xed="PXOR_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_m_pcmpeqb" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPEQB" xed="PCMPEQB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_m_pcmpeqw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPEQW" xed="PCMPEQW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_m_pcmpeqd" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPEQD" xed="PCMPEQD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_m_pcmpgtb" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPGTB" xed="PCMPGTB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_m_pcmpgtw" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPGTW" xed="PCMPGTW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_m_pcmpgtd" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI64" type="__m64" varname="a" />
+	<parameter etype="SI64" type="__m64" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPGTD" xed="PCMPGTD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_pi8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPEQB" xed="PCMPEQB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPEQW" xed="PCMPEQW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPEQD" xed="PCMPEQD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_pi8" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI8" type="__m64" varname="a" />
+	<parameter etype="SI8" type="__m64" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPGTB" xed="PCMPGTB_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_pi16" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPGTW" xed="PCMPGTW_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_pi32" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PCMPGTD" xed="PCMPGTD_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_setzero_si64" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m64 with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="mm, mm" name="PXOR" xed="PXOR_MMXq_MMXq" />
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_pi32" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="int" varname="e1" />
+	<parameter etype="UI32" type="int" varname="e0" />
+	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[31:0] := e0
+dst[63:32] := e1
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_pi16" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="short" varname="e3" />
+	<parameter etype="UI16" type="short" varname="e2" />
+	<parameter etype="UI16" type="short" varname="e1" />
+	<parameter etype="UI16" type="short" varname="e0" />
+	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[15:0] := e0
+dst[31:16] := e1
+dst[47:32] := e2
+dst[63:48] := e3
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_pi8" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="char" varname="e7" />
+	<parameter etype="UI8" type="char" varname="e6" />
+	<parameter etype="UI8" type="char" varname="e5" />
+	<parameter etype="UI8" type="char" varname="e4" />
+	<parameter etype="UI8" type="char" varname="e3" />
+	<parameter etype="UI8" type="char" varname="e2" />
+	<parameter etype="UI8" type="char" varname="e1" />
+	<parameter etype="UI8" type="char" varname="e0" />
+	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[7:0] := e0
+dst[15:8] := e1
+dst[23:16] := e2
+dst[31:24] := e3
+dst[39:32] := e4
+dst[47:40] := e5
+dst[55:48] := e6
+dst[63:56] := e7
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_pi32" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_pi16" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast 16-bit integer "a" to all all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := a[15:0]
+ENDFOR
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_pi8" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := a[7:0]
+ENDFOR
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_pi32" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="int" varname="e1" />
+	<parameter etype="UI32" type="int" varname="e0" />
+	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[31:0] := e1
+dst[63:32] := e0
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_pi16" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="short" varname="e3" />
+	<parameter etype="UI16" type="short" varname="e2" />
+	<parameter etype="UI16" type="short" varname="e1" />
+	<parameter etype="UI16" type="short" varname="e0" />
+	<description>Set packed 16-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[15:0] := e3
+dst[31:16] := e2
+dst[47:32] := e1
+dst[63:48] := e0
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_pi8" sequence="TRUE" tech="MMX">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="char" varname="e7" />
+	<parameter etype="UI8" type="char" varname="e6" />
+	<parameter etype="UI8" type="char" varname="e5" />
+	<parameter etype="UI8" type="char" varname="e4" />
+	<parameter etype="UI8" type="char" varname="e3" />
+	<parameter etype="UI8" type="char" varname="e2" />
+	<parameter etype="UI8" type="char" varname="e1" />
+	<parameter etype="UI8" type="char" varname="e0" />
+	<description>Set packed 8-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[7:0] := e7
+dst[15:8] := e6
+dst[23:16] := e5
+dst[31:24] := e4
+dst[39:32] := e3
+dst[47:40] := e2
+dst[55:48] := e1
+dst[63:56] := e0
+	</operation>
+	<CPUID>MMX</CPUID>
+	<header>mmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_monitor" tech="Other">
+	<return type="void" />
+	<parameter type="void const*" varname="p" />
+	<parameter etype="UI32" type="unsigned" varname="extensions" />
+	<parameter etype="UI32" type="unsigned" varname="hints" />
+	<description>Arm address monitoring hardware using the address specified in "p". A store to an address within the specified address range triggers the monitoring hardware. Specify optional extensions in "extensions", and optional hints in "hints".</description>
+	<instruction name="MONITOR" xed="MONITOR" />
+	<CPUID>MONITOR</CPUID>
+	<header>pmmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_mwait" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned" varname="extensions" />
+	<parameter etype="UI32" type="unsigned" varname="hints" />
+	<description>Hint to the processor that it can enter an implementation-dependent-optimized state while waiting for an event or store operation to the address range specified by MONITOR.</description>
+	<instruction name="MWAIT" xed="MWAIT" />
+	<CPUID>MONITOR</CPUID>
+	<header>pmmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_loadbe_i16" tech="Other">
+	<return etype="UI16" type="short" varname="dst" />
+	<parameter etype="UI16" memwidth="16" type="void const *" varname="ptr" />
+	<description>Load 16 bits from memory, perform a byte swap operation, and store the result in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*8
+	dst[i+7:i] := MEM[ptr+15-i:ptr+8-i]
+ENDFOR
+	</operation>
+	<instruction form="r16, m16" name="MOVBE" xed="MOVBE_GPRv_MEMv" />
+	<CPUID>MOVBE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_loadbe_i32" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="void const *" varname="ptr" />
+	<description>Load 32 bits from memory, perform a byte swap operation, and store the result in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*8
+	dst[i+7:i] := MEM[ptr+31-i:ptr+24-i]
+ENDFOR
+	</operation>
+	<instruction form="r32, m32" name="MOVBE" xed="MOVBE_GPRv_MEMv" />
+	<CPUID>MOVBE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_loadbe_i64" tech="Other">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" memwidth="64" type="void const *" varname="ptr" />
+	<description>Load 64 bits from memory, perform a byte swap operation, and store the result in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := MEM[ptr+63-i:ptr+56-i]
+ENDFOR
+	</operation>
+	<instruction form="r64, m64" name="MOVBE" xed="MOVBE_GPRv_MEMv" />
+	<CPUID>MOVBE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_storebe_i16" tech="Other">
+	<return type="void" />
+	<parameter etype="UI16" memwidth="16" type="void *" varname="ptr" />
+	<parameter etype="UI16" type="short" varname="data" />
+	<description>Perform a bit swap operation of the 16 bits in "data", and store the results to memory.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*8
+	MEM[ptr+i+7:ptr+i] := data[15-i:8-i]
+ENDFOR
+	</operation>
+	<instruction form="m16, r16" name="MOVBE" xed="MOVBE_MEMv_GPRv" />
+	<CPUID>MOVBE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_storebe_i32" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="32" type="void *" varname="ptr" />
+	<parameter etype="UI32" type="int" varname="data" />
+	<description>Perform a bit swap operation of the 32 bits in "data", and store the results to memory.</description>
+	<operation>
+addr := MEM[ptr]
+FOR j := 0 to 3
+	i := j*8
+	MEM[ptr+i+7:ptr+i] := data[31-i:24-i]
+ENDFOR
+	</operation>
+	<instruction form="m32, r32" name="MOVBE" xed="MOVBE_MEMv_GPRv" />
+	<CPUID>MOVBE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_storebe_i64" tech="Other">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="64" type="void *" varname="ptr" />
+	<parameter etype="UI64" type="__int64" varname="data" />
+	<description>Perform a bit swap operation of the 64 bits in "data", and store the results to memory.</description>
+	<operation>
+addr := MEM[ptr]
+FOR j := 0 to 7
+	i := j*8
+	MEM[ptr+i+7:ptr+i] := data[63-i:56-i]
+ENDFOR
+	</operation>
+	<instruction form="m64, r64" name="MOVBE" xed="MOVBE_MEMv_GPRv" />
+	<CPUID>MOVBE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_movdir64b" tech="Other">
+	<return type="void" />
+	<parameter etype="M512" memwidth="512" type="void*" varname="dst" />
+	<parameter etype="M512" memwidth="512" type="const void*" varname="src" />
+	<description>Move 64-byte (512-bit) value using direct store from source memory address "src" to destination memory address "dst".</description>
+	<operation>
+MEM[dst+511:dst] := MEM[src+511:src]
+	</operation>
+	<instruction form="r64, m512" name="MOVDIR64B" xed="MOVDIR64B_GPRa_MEM" />
+	<CPUID>MOVDIR64B</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_directstoreu_u64" tech="Other">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="64" type="void*" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="val" />
+	<description>Store 64-bit integer from "val" into memory using direct store.</description>
+	<operation>
+MEM[dst+63:dst] := val[63:0]
+	</operation>
+	<instruction form="m64, r64" name="MOVDIRI" xed="MOVDIRI_MEMu64_GPR64u64" />
+	<CPUID>MOVDIRI</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_directstoreu_u32" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="32" type="void*" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="val" />
+	<description>Store 32-bit integer from "val" into memory using direct store.</description>
+	<operation>
+MEM[dst+31:dst] := val[31:0]
+	</operation>
+	<instruction form="m32, r32" name="MOVDIRI" xed="MOVDIRI_MEMu32_GPR32u32" />
+	<CPUID>MOVDIRI</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_bnd_set_ptr_bounds" tech="Other">
+	<return type="void *" />
+	<parameter type="const void *" varname="srcmem" />
+	<parameter etype="UI64" type="size_t" varname="size" />
+	<description>Make a pointer with the value of "srcmem" and bounds set to ["srcmem", "srcmem" + "size" - 1], and store the result in "dst".</description>
+	<operation>dst := srcmem
+dst.LB := srcmem.LB
+dst.UB := srcmem + size - 1
+	</operation>
+	<instruction form="bnd, m32" name="BNDMK" xed="BNDMK_BND_AGEN" />
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_narrow_ptr_bounds" sequence="TRUE" tech="Other">
+	<return type="void *" />
+	<parameter type="const void *" varname="q" />
+	<parameter type="const void *" varname="r" />
+	<parameter etype="UI64" type="size_t" varname="size" />
+	<description>Narrow the bounds for pointer "q" to the intersection of the bounds of "r" and the bounds ["q", "q" + "size" - 1], and store the result in "dst".</description>
+	<operation>dst := q
+IF r.LB &gt; (q + size - 1) OR r.UB &lt; q
+	dst.LB := 1
+	dst.UB := 0
+ELSE
+	dst.LB := MAX(r.LB, q)
+	dst.UB := MIN(r.UB, (q + size - 1))
+FI
+	</operation>
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_copy_ptr_bounds" sequence="TRUE" tech="Other">
+	<return type="void *" />
+	<parameter type="const void *" varname="q" />
+	<parameter type="const void *" varname="r" />
+	<description>Make a pointer with the value of "q" and bounds set to the bounds of "r" (e.g. copy the bounds of "r" to pointer "q"), and store the result in "dst".</description>
+	<operation>dst := q
+dst.LB := r.LB
+dst.UB := r.UB
+	</operation>
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_init_ptr_bounds" sequence="TRUE" tech="Other">
+	<return type="void *" />
+	<parameter type="const void *" varname="q" />
+	<description>Make a pointer with the value of "q" and open bounds, which allow the pointer to access the entire virtual address space, and store the result in "dst".</description>
+	<operation>dst := q
+dst.LB := 0
+dst.UB := 0
+	</operation>
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_store_ptr_bounds" tech="Other">
+	<return type="void" />
+	<parameter type="const void **" varname="ptr_addr" />
+	<parameter type="const void *" varname="ptr_val" />
+	<description>Stores the bounds of "ptr_val" pointer in memory at address "ptr_addr".</description>
+	<operation>MEM[ptr_addr].LB := ptr_val.LB
+MEM[ptr_addr].UB := ptr_val.UB
+	</operation>
+	<instruction form="mib, bnd" name="BNDSTX" xed="BNDSTX_MEMbnd64_BND" />
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_chk_ptr_lbounds" tech="Other">
+	<return type="void" />
+	<parameter type="const void *" varname="q" />
+	<description>Checks if "q" is within its lower bound, and throws a #BR if not.</description>
+	<operation>IF q &lt; q.LB
+	#BR
+FI
+	</operation>
+	<instruction form="bnd, m64" name="BNDCL" xed="BNDCL_BND_AGEN" />
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_chk_ptr_ubounds" tech="Other">
+	<return type="void" />
+	<parameter type="const void *" varname="q" />
+	<description>Checks if "q" is within its upper bound, and throws a #BR if not.</description>
+	<operation>IF q &gt; q.UB
+	#BR
+FI
+	</operation>
+	<instruction form="bnd, m64" name="BNDCU" xed="BNDCU_BND_AGEN" />
+	<instruction form="bnd, m64" name="BNDCN" xed="BNDCN_BND_AGEN" />
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_chk_ptr_bounds" tech="Other">
+	<return type="void" />
+	<parameter type="const void *" varname="q" />
+	<parameter etype="UI64" type="size_t" varname="size" />
+	<description>Checks if ["q", "q" + "size" - 1] is within the lower and upper bounds of "q" and throws a #BR if not.</description>
+	<operation>IF (q + size - 1) &lt; q.LB OR (q + size - 1) &gt; q.UB
+	#BR
+FI
+	</operation>
+	<instruction form="bnd, m32" name="BNDCU" xed="BNDCU_BND_AGEN" />
+	<instruction form="bnd, m32" name="BNDCN" xed="BNDCN_BND_AGEN" />
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_get_ptr_lbound" sequence="TRUE" tech="Other">
+	<return type="const void *" />
+	<parameter type="const void *" varname="q" />
+	<description>Return the lower bound of "q".</description>
+	<operation>dst := q.LB
+	</operation>
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	<intrinsic name="_bnd_get_ptr_ubound" sequence="TRUE" tech="Other">
+	<return type="const void *" />
+	<parameter type="const void *" varname="q" />
+	<description>Return the upper bound of "q".</description>
+	<operation>dst := q.UB
+	</operation>
+	<CPUID>MPX</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	<supported icx="FALSE" />
+	</intrinsic>
+	
+<intrinsic name="_bit_scan_forward" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Set "dst" to the index of the lowest set bit in 32-bit integer "a". If no bits are set in "a" then "dst" is undefined.</description>
+	<operation>
+tmp := 0
+IF a == 0
+	// dst is undefined
+ELSE
+	DO WHILE ((tmp &lt; 32) AND a[tmp] == 0)
+		tmp := tmp + 1
+	OD
+FI
+dst := tmp
+	</operation>
+	<instruction form="r32, r32" name="BSF" xed="BSF_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bit_scan_reverse" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Set "dst" to the index of the highest set bit in 32-bit integer "a". If no bits are set in "a" then "dst" is undefined.</description>
+	<operation>
+tmp := 31
+IF a == 0
+	// dst is undefined
+ELSE
+	DO WHILE ((tmp &gt; 0) AND a[tmp] == 0)
+		tmp := tmp - 1
+	OD
+FI
+dst := tmp
+	</operation>
+	<instruction form="r32, r32" name="BSR" xed="BSR_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_BitScanForward" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="unsigned __int32*" varname="index" />
+	<parameter etype="UI32" type="unsigned __int32" varname="a" />
+	<description>Set "index" to the index of the lowest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1.</description>
+	<operation>
+tmp := 0
+IF a == 0
+	// MEM[index+31:index] is undefined
+	dst := 0
+ELSE
+	DO WHILE ((tmp &lt; 32) AND a[tmp] == 0)
+		tmp := tmp + 1
+	OD
+	MEM[index+31:index] := tmp
+	dst := (tmp == 31) ? 0 : 1
+FI
+	</operation>
+	<instruction form="r32, r32" name="BSF" xed="BSF_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_BitScanReverse" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="unsigned __int32*" varname="index" />
+	<parameter etype="UI32" type="unsigned __int32" varname="a" />
+	<description>Set "index" to the index of the highest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1.</description>
+	<operation>
+tmp := 31
+IF a == 0
+	// MEM[index+31:index] is undefined
+	dst := 0
+ELSE
+	DO WHILE ((tmp &gt; 0) AND a[tmp] == 0)
+		tmp := tmp - 1
+	OD
+	MEM[index+31:index] := tmp
+	dst := (tmp == 0) ? 0 : 1
+FI
+	</operation>
+	<instruction form="r32, r32" name="BSR" xed="BSR_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_BitScanForward64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="unsigned __int32*" varname="index" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Set "index" to the index of the lowest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1.</description>
+	<operation>
+tmp := 0
+IF a == 0
+	// MEM[index+31:index] is undefined
+	dst := 0
+ELSE
+	DO WHILE ((tmp &lt; 64) AND a[tmp] == 0)
+		tmp := tmp + 1
+	OD
+	MEM[index+31:index] := tmp
+	dst := (tmp == 63) ? 0 : 1
+FI
+	</operation>
+	<instruction form="r64, r64" name="BSF" xed="BSF_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_BitScanReverse64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="unsigned __int32*" varname="index" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Set "index" to the index of the highest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1.</description>
+	<operation>
+tmp := 63
+IF a == 0
+	// MEM[index+31:index] is undefined
+	dst := 0
+ELSE
+	DO WHILE ((tmp &gt; 0) AND a[tmp] == 0)
+		tmp := tmp - 1
+	OD
+	MEM[index+31:index] := tmp
+	dst := (tmp == 0) ? 0 : 1
+FI
+	</operation>
+	<instruction form="r64, r64" name="BSR" xed="BSR_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bittest" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="__int32*" varname="a" />
+	<parameter etype="IMM" immwidth="5" type="__int32" varname="b" />
+	<description>Return the bit at index "b" of 32-bit integer "a".</description>
+	<operation>
+addr := a + ZeroExtend64(b)
+dst[0] := MEM[addr]
+	</operation>
+	<instruction form="m32, r32" name="BT" xed="BT_MEMv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bittestandcomplement" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="__int32*" varname="a" />
+	<parameter etype="IMM" immwidth="5" type="__int32" varname="b" />
+	<description>Return the bit at index "b" of 32-bit integer "a", and set that bit to its complement.</description>
+	<operation>
+addr := a + ZeroExtend64(b)
+dst[0] := MEM[addr]
+MEM[addr] := ~dst[0]
+	</operation>
+	<instruction form="m32, r32" name="BTC" xed="BTC_MEMv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bittestandreset" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="__int32*" varname="a" />
+	<parameter etype="IMM" immwidth="5" type="__int32" varname="b" />
+	<description>Return the bit at index "b" of 32-bit integer "a", and set that bit to zero.</description>
+	<operation>
+addr := a + ZeroExtend64(b)
+dst[0] := MEM[addr]
+MEM[addr] := 0
+	</operation>
+	<instruction form="m32, r32" name="BTR" xed="BTR_MEMv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bittestandset" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="__int32*" varname="a" />
+	<parameter etype="IMM" immwidth="5" type="__int32" varname="b" />
+	<description>Return the bit at index "b" of 32-bit integer "a", and set that bit to one.</description>
+	<operation>
+addr := a + ZeroExtend64(b)
+dst[0] := MEM[addr]
+MEM[addr] := 1
+	</operation>
+	<instruction form="m32, r32" name="BTS" xed="BTS_MEMv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bittest64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI64" memwidth="32" type="__int64*" varname="a" />
+	<parameter etype="IMM" immwidth="6" type="__int64" varname="b" />
+	<description>Return the bit at index "b" of 64-bit integer "a".</description>
+	<operation>
+addr := a + b
+dst[0] := MEM[addr]
+	</operation>
+	<instruction form="r64, r64" name="BT" xed="BT_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bittestandcomplement64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI64" memwidth="32" type="__int64*" varname="a" />
+	<parameter etype="IMM" immwidth="6" type="__int64" varname="b" />
+	<description>Return the bit at index "b" of 64-bit integer "a", and set that bit to its complement.</description>
+	<operation>
+addr := a + b
+dst[0] := MEM[addr]
+MEM[addr] := ~dst[0]
+	</operation>
+	<instruction form="r64, r64" name="BTC" xed="BTC_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bittestandreset64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI64" memwidth="32" type="__int64*" varname="a" />
+	<parameter etype="IMM" immwidth="6" type="__int64" varname="b" />
+	<description>Return the bit at index "b" of 64-bit integer "a", and set that bit to zero.</description>
+	<operation>
+addr := a + b
+dst[0] := MEM[addr]
+MEM[addr] := 0
+	</operation>
+	<instruction form="r64, r64" name="BTR" xed="BTR_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bittestandset64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI64" memwidth="32" type="__int64*" varname="a" />
+	<parameter etype="IMM" immwidth="6" type="__int64" varname="b" />
+	<description>Return the bit at index "b" of 64-bit integer "a", and set that bit to one.</description>
+	<operation>
+addr := a + b
+dst[0] := MEM[addr]
+MEM[addr] := 1
+	</operation>
+	<instruction form="r64, r64" name="BTS" xed="BTS_GPRv_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bswap" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Reverse the byte order of 32-bit integer "a", and store the result in "dst". This intrinsic is provided for conversion between little and big endian values.</description>
+	<operation>
+dst[7:0] := a[31:24]
+dst[15:8] := a[23:16]
+dst[23:16] := a[15:8]
+dst[31:24] := a[7:0]
+	</operation>
+	<instruction form="r32" name="BSWAP" xed="BSWAP_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_bswap64" tech="Other">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Reverse the byte order of 64-bit integer "a", and store the result in "dst". This intrinsic is provided for conversion between little and big endian values.</description>
+	<operation>
+dst[7:0] := a[63:56]
+dst[15:8] := a[55:48]
+dst[23:16] := a[47:40]
+dst[31:24] := a[39:32]
+dst[39:32] := a[31:24]
+dst[47:40] := a[23:16]
+dst[55:48] := a[15:8]
+dst[63:56] := a[7:0]
+	</operation>
+	<instruction form="r64" name="BSWAP" xed="BSWAP_GPRv" />
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_castf32_u32" tech="Other">
+	<return etype="UI32" type="unsigned __int32" varname="dst" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Cast from type float to type unsigned __int32 without conversion.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_castf64_u64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="FP64" type="double" varname="a" />
+	<description>Cast from type double to type unsigned __int64 without conversion.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_castu32_f32" tech="Other">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="UI32" type="unsigned __int32" varname="a" />
+	<description>Cast from type unsigned __int32 to type float without conversion.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_castu64_f64" tech="Other">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Cast from type unsigned __int64 to type double without conversion.
+	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<header>immintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_lrotl" tech="Other">
+	<return etype="UI32" type="unsigned long" varname="dst" />
+	<parameter etype="UI32" type="unsigned long" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="shift" />
+	<description>Shift the bits of unsigned long integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".</description>
+	<operation>// size := 32 or 64
+dst := a
+count := shift AND (size - 1)
+DO WHILE (count &gt; 0)
+	tmp[0] := dst[size - 1]
+	dst := (dst &lt;&lt; 1) OR tmp[0]
+	count := count - 1
+OD
+	</operation>
+	<instruction form="r64, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
+	<instruction form="r32, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_lrotr" tech="Other">
+	<return etype="UI32" type="unsigned long" varname="dst" />
+	<parameter etype="UI32" type="unsigned long" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="shift" />
+	<description>Shift the bits of unsigned long integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".</description>
+	<operation>// size := 32 or 64
+dst := a
+count := shift AND (size - 1)
+DO WHILE (count &gt; 0)
+	tmp[size - 1] := dst[0]
+	dst := (dst &gt;&gt; 1) OR tmp[size - 1]
+	count := count - 1
+OD
+	</operation>
+	<instruction form="r64, imm8" name="ROR" xed="ROR_GPRv_IMMb" />
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_rotl" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="IMM" immwidth="5" type="int" varname="shift" />
+	<description>Shift the bits of unsigned 32-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".</description>
+	<operation>
+dst := a
+count := shift AND 31
+DO WHILE (count &gt; 0)
+	tmp[0] := dst[31]
+	dst := (dst &lt;&lt; 1) OR tmp[0]
+	count := count - 1
+OD
+	</operation>
+	<instruction form="r32, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_rotr" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="IMM" immwidth="5" type="int" varname="shift" />
+	<description>Shift the bits of unsigned 32-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".</description>
+	<operation>
+dst := a
+count := shift AND 31
+DO WHILE (count &gt; 0)
+	tmp[31] := dst[0]
+	dst := (dst &gt;&gt; 1) OR tmp
+	count := count - 1
+OD
+	</operation>
+	<instruction form="r32, imm8" name="ROR" xed="ROR_GPRv_IMMb" />
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_rotwl" tech="Other">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="UI16" type="unsigned short" varname="a" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="shift" />
+	<description>Shift the bits of unsigned 16-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".</description>
+	<operation>
+dst := a
+count := shift AND 15
+DO WHILE (count &gt; 0)
+	tmp[0] := dst[15]
+	dst := (dst &lt;&lt; 1) OR tmp[0]
+	count := count - 1
+OD
+	</operation>
+	<instruction form="r16, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_rotwr" tech="Other">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="UI16" type="unsigned short" varname="a" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="shift" />
+	<description>Shift the bits of unsigned 16-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".</description>
+	<operation>
+dst := a
+count := shift AND 15
+DO WHILE (count &gt; 0)
+	tmp[15] := dst[0]
+	dst := (dst &gt;&gt; 1) OR tmp
+	count := count - 1
+OD
+	</operation>
+	<instruction form="r16, imm8" name="ROR" xed="ROR_GPRv_IMMb" />
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_rotl64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="IMM" immwidth="6" type="int" varname="shift" />
+	<description>Shift the bits of unsigned 64-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".</description>
+	<operation>
+dst := a
+count := shift AND 63
+DO WHILE (count &gt; 0)
+	tmp[0] := dst[63]
+	dst := (dst &lt;&lt; 1) OR tmp[0]
+	count := count - 1
+OD
+	</operation>
+	<instruction form="r64, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_rotr64" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="IMM" immwidth="6" type="int" varname="shift" />
+	<description>Shift the bits of unsigned 64-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".</description>
+	<operation>
+dst := a
+count := shift AND 63
+DO WHILE (count &gt; 0)
+	tmp[63] := dst[0]
+	dst := (dst &gt;&gt; 1) OR tmp[63]
+	count := count - 1
+OD
+	</operation>
+	<instruction form="r64, imm8" name="ROR" xed="ROR_GPRv_IMMb" />
+	<header>immintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_allow_cpu_features" sequence="TRUE" tech="Other">
+	<return type="void" />
+	<parameter etype="IMM" immwidth="8" type="unsigned __int64" varname="a" />
+	<description>Treat the processor-specific feature(s) specified in "a" as available. Multiple features may be OR'd together. See the valid feature flags below:</description>
+	<operation>
+_FEATURE_GENERIC_IA32
+_FEATURE_FPU
+_FEATURE_CMOV
+_FEATURE_MMX
+_FEATURE_FXSAVE
+_FEATURE_SSE
+_FEATURE_SSE2
+_FEATURE_SSE3
+_FEATURE_SSSE3
+_FEATURE_SSE4_1
+_FEATURE_SSE4_2
+_FEATURE_MOVBE
+_FEATURE_POPCNT
+_FEATURE_PCLMULQDQ
+_FEATURE_AES
+_FEATURE_F16C
+_FEATURE_AVX
+_FEATURE_RDRND
+_FEATURE_FMA
+_FEATURE_BMI
+_FEATURE_LZCNT
+_FEATURE_HLE
+_FEATURE_RTM
+_FEATURE_AVX2
+_FEATURE_KNCNI
+_FEATURE_AVX512F
+_FEATURE_ADX
+_FEATURE_RDSEED
+_FEATURE_AVX512ER
+_FEATURE_AVX512PF
+_FEATURE_AVX512CD
+_FEATURE_SHA
+_FEATURE_MPX
+_FEATURE_AVX512BW
+_FEATURE_AVX512VL
+_FEATURE_AVX512VBMI
+_FEATURE_AVX512_4FMAPS
+_FEATURE_AVX512_4VNNIW
+_FEATURE_AVX512_VPOPCNTDQ
+_FEATURE_AVX512_BITALG
+_FEATURE_AVX512_VBMI2
+_FEATURE_GFNI
+_FEATURE_VAES
+_FEATURE_VPCLMULQDQ
+_FEATURE_AVX512_VNNI
+_FEATURE_CLWB
+_FEATURE_RDPID
+_FEATURE_IBT
+_FEATURE_SHSTK
+_FEATURE_SGX
+_FEATURE_WBNOINVD
+_FEATURE_PCONFIG
+_FEATURE_AXV512_4VNNIB
+_FEATURE_AXV512_4FMAPH
+_FEATURE_AXV512_BITALG2
+_FEATURE_AXV512_VP2INTERSECT
+	</operation>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_may_i_use_cpu_feature" sequence="TRUE" tech="Other">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="IMM" immwidth="8" type="unsigned __int64" varname="a" />
+	<description>Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available, and return true or false (1 or 0) if the set of features is available. Multiple features may be OR'd together. This function is limited to bitmask values in the first 'page' of the libirc cpu-id information. This intrinsic does not check the processor vendor. See the valid feature flags below:</description>
+	<operation>
+_FEATURE_GENERIC_IA32
+_FEATURE_FPU
+_FEATURE_CMOV
+_FEATURE_MMX
+_FEATURE_FXSAVE
+_FEATURE_SSE
+_FEATURE_SSE2
+_FEATURE_SSE3
+_FEATURE_SSSE3
+_FEATURE_SSE4_1
+_FEATURE_SSE4_2
+_FEATURE_MOVBE
+_FEATURE_POPCNT
+_FEATURE_PCLMULQDQ
+_FEATURE_AES
+_FEATURE_F16C
+_FEATURE_AVX
+_FEATURE_RDRND
+_FEATURE_FMA
+_FEATURE_BMI
+_FEATURE_LZCNT
+_FEATURE_HLE
+_FEATURE_RTM
+_FEATURE_AVX2
+_FEATURE_KNCNI
+_FEATURE_AVX512F
+_FEATURE_ADX
+_FEATURE_RDSEED
+_FEATURE_AVX512ER
+_FEATURE_AVX512PF
+_FEATURE_AVX512CD
+_FEATURE_SHA
+_FEATURE_MPX
+_FEATURE_AVX512BW
+_FEATURE_AVX512VL
+_FEATURE_AVX512VBMI
+_FEATURE_AVX512_4FMAPS
+_FEATURE_AVX512_4VNNIW
+_FEATURE_AVX512_VPOPCNTDQ
+_FEATURE_AVX512_BITALG
+_FEATURE_AVX512_VBMI2
+_FEATURE_GFNI
+_FEATURE_VAES
+_FEATURE_VPCLMULQDQ
+_FEATURE_AVX512_VNNI
+_FEATURE_CLWB
+_FEATURE_RDPID
+_FEATURE_IBT
+_FEATURE_SHSTK
+_FEATURE_SGX
+_FEATURE_WBNOINVD
+_FEATURE_PCONFIG
+_FEATURE_AXV512_4VNNIB
+_FEATURE_AXV512_4FMAPH
+_FEATURE_AXV512_BITALG2
+_FEATURE_AXV512_VP2INTERSECT
+_FEATURE_AXV512_FP16
+	</operation>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_may_i_use_cpu_feature_ext" sequence="TRUE" tech="Other">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="IMM" immwidth="8" type="unsigned __int64" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="unsigned" varname="page" />
+	<description>Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available, and return true or false (1 or 0) if the set of features is available. Multiple features may be OR'd together. This works identically to the previous variant, except it also accepts a 'page' index that permits checking features on the 2nd page of the libirc information. When provided with a '0' in the 'page' parameter, this works identically to _may_i_use_cpu_feature. This intrinsic does not check the processor vendor. See the valid feature flags on the 2nd page below: (provided with a '1' in the 'page' parameter)</description>
+	<operation>
+_FEATURE_CLDEMOTE
+_FEATURE_MOVDIRI
+_FEATURE_MOVDIR64B
+_FEATURE_WAITPKG
+_FEATURE_AVX512_Bf16
+_FEATURE_ENQCMD
+_FEATURE_AVX_VNNI
+_FEATURE_AMX_TILE
+_FEATURE_AMX_INT8
+_FEATURE_AMX_BF16
+_FEATURE_KL
+_FEATURE_WIDE_KL
+_FEATURE_HRESET
+_FEATURE_UINTR
+_FEATURE_PREFETCHI
+_FEATURE_AVXVNNIINT8
+_FEATURE_CMPCCXADD
+_FEATURE_AVXIFMA
+_FEATURE_AVXNECONVERT
+_FEATURE_RAOINT
+_FEATURE_AMX_FP16
+_FEATURE_AMX_COMPLEX
+_FEATURE_SHA512
+_FEATURE_SM3
+_FEATURE_SM4
+_FEATURE_AVXVNNIINT16
+_FEATURE_USERMSR
+_FEATURE_AVX10_1_256
+_FEATURE_AVX10_1_512
+_FEATURE_APXF
+_FEATURE_MSRLIST
+_FEATURE_WRMSRNS
+_FEATURE_PBNDKB
+	</operation>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_may_i_use_cpu_feature_str" sequence="TRUE" tech="Other">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter type="string literal" varname="feature, ..." />
+	<description>Dynamically query the processor to determine if the processor-specific feature(s) specified a series of compile-time string literals in "feature, ..." are available, and return true or false (1 or 0) if the set of features is available. These feature names are converted to a bitmask and uses the same infrastructure as _may_i_use_cpu_feature_ext to validate it. The behavior is the same as the previous variants. This intrinsic does not check the processor vendor. Supported string literals are one-to-one corresponding in the "Operation" sections of _may_i_use_cpu_feature and _may_i_use_cpu_feature_ext. Example string literals are "avx2", "bmi", "avx512fp16", "amx-int8"...</description>
+	<operation>
+	</operation>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_rdpmc" tech="Other">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Read the Performance Monitor Counter (PMC) specified by "a", and store up to 64-bits in "dst". The width of performance counters is implementation specific.</description>
+	<operation>dst[63:0] := ReadPMC(a)
+	</operation>
+	<instruction name="RDPMC" xed="RDPMC" />
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_addcarry_u32" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="unsigned char" varname="c_in" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<parameter etype="UI32" memwidth="32" type="unsigned int *" varname="out" />
+	<description>Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
+	<operation>
+tmp[32:0] := a[31:0] + b[31:0] + (c_in &gt; 0 ? 1 : 0)
+MEM[out+31:out] := tmp[31:0]
+dst[0] := tmp[32]
+dst[7:1] := 0
+	</operation>
+	<instruction form="r32, r32" name="ADC" xed="ADC_GPRv_GPRv_11" />
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_addcarry_u64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="unsigned char" varname="c_in" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<parameter etype="UI64" memwidth="64" type="unsigned __int64 *" varname="out" />
+	<description>Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
+	<operation>
+tmp[64:0] := a[63:0] + b[63:0] + (c_in &gt; 0 ? 1 : 0)
+MEM[out+63:out] := tmp[63:0]
+dst[0] := tmp[64]
+dst[7:1] := 0
+	</operation>
+	<instruction form="r64, r64" name="ADC" xed="ADC_GPRv_GPRv_11" />
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_subborrow_u32" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="unsigned char" varname="c_in" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI32" type="unsigned int" varname="b" />
+	<parameter etype="UI32" memwidth="32" type="unsigned int *" varname="out" />
+	<description>Add unsigned 8-bit borrow "c_in" (carry flag) to unsigned 32-bit integer "b", and subtract the result from unsigned 32-bit integer "a". Store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
+	<operation>
+tmp[32:0] := a[31:0] - (b[31:0] + (c_in &gt; 0 ? 1 : 0))
+MEM[out+31:out] := tmp[31:0]
+dst[0] := tmp[32]
+dst[7:1] := 0
+	</operation>
+	<instruction form="r32, r32" name="SBB" xed="SBB_GPRv_GPRv_19" />
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_subborrow_u64" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI8" type="unsigned char" varname="c_in" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="b" />
+	<parameter etype="UI64" memwidth="64" type="unsigned __int64 *" varname="out" />
+	<description>Add unsigned 8-bit borrow "c_in" (carry flag) to unsigned 64-bit integer "b", and subtract the result from unsigned 64-bit integer "a". Store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
+	<operation>
+tmp[64:0] := a[63:0] - (b[63:0] + (c_in &gt; 0 ? 1 : 0))
+MEM[out+63:out] := tmp[63:0]
+dst[0] := tmp[64]
+dst[7:1] := 0
+	</operation>
+	<instruction form="r64, r64" name="SBB" xed="SBB_GPRv_GPRv_19" />
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_ptwrite32" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Insert the 32-bit data from "a" into a Processor Trace stream via a PTW packet. The PTW packet will be inserted if tracing is currently enabled and ptwrite is currently enabled. The current IP will also be inserted via a FUP packet if FUPonPTW is enabled.</description>
+	<instruction form="r32" name="PTWRITE" xed="PTWRITE_GPRy" />
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_ptwrite64" tech="Other">
+	<return type="void" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Insert the 64-bit data from "a" into a Processor Trace stream via a PTW packet. The PTW packet will be inserted if tracing is currently enabled and ptwrite is currently enabled. The current IP will also be inserted via a FUP packet if FUPonPTW is enabled.</description>
+	<instruction form="r64" name="PTWRITE" xed="PTWRITE_GPRy" />
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_enclu_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="const int" varname="a" />
+	<parameter etype="UI64" type="size_t*" varname="__data" />
+	<description>Invoke the Intel SGX enclave user (non-privilege) leaf function specified by "a", and return the error code. The "__data" array contains 3 32- or 64-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.</description>
+	<instruction name="ENCLU" xed="ENCLU" />
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_encls_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="const int" varname="a" />
+	<parameter etype="UI64" type="size_t*" varname="__data" />
+	<description>Invoke the Intel SGX enclave system (privileged) leaf function specified by "a", and return the error code. The "__data" array contains 3 32- or 64-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.</description>
+	<instruction name="ENCLS" xed="ENCLS" />
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_enclv_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="const int" varname="a" />
+	<parameter etype="UI64" type="size_t*" varname="__data" />
+	<description>Invoke the Intel SGX enclave virtualized (VMM) leaf function specified by "a", and return the error code. The "__data" array contains 3 32- or 64-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.</description>
+	<instruction name="ENCLV" xed="ENCLV" />
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_wbinvd" tech="Other">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Write back and flush internal caches.
+		Initiate writing-back and flushing of external
+		caches.</description>
+	<instruction name="WBINVD" xed="WBINVD" />
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_cvtsh_ss" sequence="TRUE" tech="Other">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="UI16" type="unsigned short" varname="a" />
+	<description>Convert the half-precision (16-bit) floating-point value "a" to a single-precision (32-bit) floating-point value, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP16_To_FP32(a[15:0])
+	</operation>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_cvtss_sh" sequence="TRUE" tech="Other">
+	<return etype="UI16" type="unsigned short" varname="dst" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Convert the single-precision (32-bit) floating-point value "a" to a half-precision (16-bit) floating-point value, and store the result in "dst".
+	[round_note]</description>
+	<operation>
+dst[15:0] := Convert_FP32_To_FP16(a[31:0])
+	</operation>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	
+<intrinsic name="_mm_clmulepi64_si128" vexEq="TRUE" tech="Other">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Perform a carry-less multiplication of two 64-bit integers, selected from "a" and "b" according to "imm8", and store the results in "dst".</description>
+	<operation>
+IF (imm8[0] == 0)
+	TEMP1 := a[63:0]
+ELSE
+	TEMP1 := a[127:64]
+FI 
+IF (imm8[4] == 0)
+	TEMP2 := b[63:0]
+ELSE 
+	TEMP2 := b[127:64]
+FI
+FOR i := 0 to 63
+	TEMP[i] := (TEMP1[0] and TEMP2[i])
+	FOR j := 1 to i
+		TEMP[i] := TEMP[i] XOR (TEMP1[j] AND TEMP2[i-j])
+	ENDFOR 
+	dst[i] := TEMP[i]
+ENDFOR
+FOR i := 64 to 127
+	TEMP[i] := 0
+	FOR j := (i - 63) to 63
+		TEMP[i] := TEMP[i] XOR (TEMP1[j] AND TEMP2[i-j])
+	ENDFOR
+	dst[i] := TEMP[i]
+ENDFOR
+dst[127] := 0
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCLMULQDQ" xed="PCLMULQDQ_XMMdq_XMMdq_IMMb" />
+	<CPUID>PCLMULQDQ</CPUID>
+	<header>wmmintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_pconfig_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<parameter etype="UI64" type="size_t*" varname="__data" />
+	<description>Invoke the PCONFIG leaf function specified by "a". The "__data" array contains 3 32- or 64-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx. May return the value in eax, depending on the semantics of the specified leaf function.</description>
+	<instruction name="PCONFIG" xed="PCONFIG" />
+	<CPUID>PCONFIG</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_popcnt_u32" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Count the number of bits set to 1 in unsigned 32-bit integer "a", and return that count in "dst".</description>
+	<operation>
+dst := 0
+FOR i := 0 to 31
+	IF a[i]
+		dst := dst + 1
+	FI
+ENDFOR
+	</operation>
+	<instruction form="r32, r32" name="POPCNT" xed="POPCNT_GPRv_GPRv" />
+	<CPUID>POPCNT</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_mm_popcnt_u64" tech="Other">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="a" />
+	<description>Count the number of bits set to 1 in unsigned 64-bit integer "a", and return that count in "dst".</description>
+	<operation>
+dst := 0
+FOR i := 0 to 63
+	IF a[i]
+		dst := dst + 1
+	FI
+ENDFOR
+	</operation>
+	<instruction form="r64, r64" name="POPCNT" xed="POPCNT_GPRv_GPRv" />
+	<CPUID>POPCNT</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_popcnt32" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Count the number of bits set to 1 in 32-bit integer "a", and return that count in "dst".</description>
+	<operation>
+dst := 0
+FOR i := 0 to 31
+	IF a[i]
+		dst := dst + 1
+	FI
+ENDFOR
+	</operation>
+	<instruction form="r32, r32" name="POPCNT" xed="POPCNT_GPRv_GPRv" />
+	<CPUID>POPCNT</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	<intrinsic name="_popcnt64" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Count the number of bits set to 1 in 64-bit integer "a", and return that count in "dst".</description>
+	<operation>
+dst := 0
+FOR i := 0 to 63
+	IF a[i]
+		dst := dst + 1
+	FI
+ENDFOR
+	</operation>
+	<instruction form="r64, r64" name="POPCNT" xed="POPCNT_GPRv_GPRv" />
+	<CPUID>POPCNT</CPUID>
+	<header>immintrin.h</header>
+	<category>Bit Manipulation</category>
+	</intrinsic>
+	
+	
+	<intrinsic name="_m_prefetchit0" tech="Other">
+	<return type="void" />
+	<parameter type="const void*" memwidth="32" etype="UI8" varname="__P" />
+	<description>Loads an instruction sequence containing the specified memory address into all level cache.</description>
+	<instruction form="m8" name="PREFETCHIT0" xed="PREFETCHIT0_MEMu8"/>
+	<CPUID>PREFETCHI</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_m_prefetchit1" tech="Other">
+	<return type="void" />
+	<parameter type="const void*" memwidth="32" etype="UI8" varname="__P" />
+	<description>Loads an instruction sequence containing the specified memory address into all but the first-level cache.</description>
+	<instruction form="m8" name="PREFETCHIT1" xed="PREFETCHIT1_MEMu8"/>
+	<CPUID>PREFETCHI</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+<intrinsic name="_mm_prefetch" tech="Other">
+	<return type="void" />
+	<parameter etype="UI8" type="char const*" varname="p" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="i" />
+	<description>Fetch the line of data from memory that contains address "p" to a location in the cache hierarchy specified by the locality hint "i", which can be one of:&lt;ul&gt;
+    &lt;li&gt;_MM_HINT_ET0  // 7, move data using the ET0 hint. The PREFETCHW instruction will be generated.&lt;/li&gt;
+    &lt;li&gt;_MM_HINT_T0   // 3, move data using the T0 hint. The PREFETCHT0 instruction will be generated.&lt;/li&gt;
+    &lt;li&gt;_MM_HINT_T1   // 2, move data using the T1 hint. The PREFETCHT1 instruction will be generated.&lt;/li&gt;
+    &lt;li&gt;_MM_HINT_T2   // 1, move data using the T2 hint. The PREFETCHT2 instruction will be generated.&lt;/li&gt;
+    &lt;li&gt;_MM_HINT_NTA  // 0, move data using the non-temporal access (NTA) hint. The PREFETCHNTA instruction will be generated.&lt;/li&gt;
+</description>
+	<instruction form="m8" name="PREFETCHW" />
+	<instruction form="m8" name="PREFETCHNTA" xed="PREFETCHNTA_MEMmprefetch" />
+	<instruction form="m8" name="PREFETCHT0" xed="PREFETCHT0_MEMmprefetch" />
+	<instruction form="m8" name="PREFETCHT1" xed="PREFETCHT1_MEMmprefetch" />
+	<instruction form="m8" name="PREFETCHT2" xed="PREFETCHT2_MEMmprefetch" />
+	<CPUID>PRFCHW</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_aadd_i32" tech="Other">
+		<return type="void" />
+		<description>Atomically add a 32-bit value at memory operand "__A" and a 32-bit "__B", and store the result to the same memory location.</description>
+		<instruction name="AADD" form="m32, r32" xed="AADD_MEM32_GPR32" />
+		<operation>
+MEM[__A+31:__A] := MEM[__A+31:__A] + __B[31:0]
+</operation>
+		<parameter type="int*" memwidth="32" etype="SI32" varname="__A" />
+		<parameter type="int" etype="SI32" varname="__B" />
+	<CPUID>RAO_INT</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_aadd_i64" tech="Other">
+		<return type="void" />
+		<description>Atomically add a 64-bit value at memory operand "__A" and a 64-bit "__B", and store the result to the same memory location.</description>
+		<instruction name="AADD" form="m64, r64" xed="AADD_MEM64_GPR64" />
+		<operation>
+MEM[__A+63:__A] := MEM[__A+63:__A] + __B[63:0]
+</operation>
+		<parameter type="__int64*" memwidth="64" etype="SI64" varname="__A" />
+		<parameter type="__int64" etype="SI64" varname="__B" />
+	<CPUID>RAO_INT</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_aand_i32" tech="Other">
+		<return type="void" />
+		<description>Atomically and a 32-bit value at memory operand "__A" and a 32-bit "__B", and store the result to the same memory location.</description>
+		<instruction name="AAND" form="m32, r32" xed="AAND_MEM32_GPR32" />
+		<operation>
+MEM[__A+31:__A] := MEM[__A+31:__A] AND __B[31:0]
+</operation>
+		<parameter type="int*" memwidth="32" etype="SI32" varname="__A" />
+		<parameter type="int" etype="SI32" varname="__B" />
+	<CPUID>RAO_INT</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_aand_i64" tech="Other">
+		<return type="void" />
+		<description>Atomically and a 64-bit value at memory operand "__A" and a 64-bit "__B", and store the result to the same memory location.</description>
+		<instruction name="AAND" form="m64, r64" xed="AAND_MEM64_GPR64" />
+		<operation>
+MEM[__A+63:__A] := MEM[__A+63:__A] AND __B[63:0]
+</operation>
+		<parameter type="__int64*" memwidth="64" etype="SI64" varname="__A" />
+		<parameter type="__int64" etype="SI64" varname="__B" />
+	<CPUID>RAO_INT</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_aor_i32" tech="Other">
+		<return type="void" />
+		<description>Atomically or a 32-bit value at memory operand "__A" and a 32-bit "__B", and store the result to the same memory location.</description>
+		<instruction name="AOR" form="m32, r32" xed="AOR_MEM32_GPR32" />
+		<operation>
+MEM[__A+31:__A] := MEM[__A+31:__A] OR __B[31:0]
+</operation>
+		<parameter type="int*" memwidth="32" etype="SI32" varname="__A" />
+		<parameter type="int" etype="SI32" varname="__B" />
+	<CPUID>RAO_INT</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_aor_i64" tech="Other">
+		<return type="void" />
+		<description>Atomically or a 64-bit value at memory operand "__A" and a 64-bit "__B", and store the result to the same memory location.</description>
+		<instruction name="AOR" form="m64, r64" xed="AOR_MEM64_GPR64" />
+		<operation>
+MEM[__A+63:__A] := MEM[__A+63:__A] OR __B[63:0]
+</operation>
+		<parameter type="__int64*" memwidth="64" etype="SI64" varname="__A" />
+		<parameter type="__int64" etype="SI64" varname="__B" />
+	<CPUID>RAO_INT</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_axor_i32" tech="Other">
+		<return type="void" />
+		<description>Atomically xor a 32-bit value at memory operand "__A" and a 32-bit "__B", and store the result to the same memory location.</description>
+		<instruction name="AXOR" form="m32, r32" xed="AXOR_MEM32_GPR32" />
+		<operation>
+MEM[__A+31:__A] := MEM[__A+31:__A] XOR __B[31:0]
+</operation>
+		<parameter type="int*" memwidth="32" etype="SI32" varname="__A" />
+		<parameter type="int" etype="SI32" varname="__B" />
+	<CPUID>RAO_INT</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_axor_i64" tech="Other">
+		<return type="void" />
+		<description>Atomically xor a 64-bit value at memory operand "__A" and a 64-bit "__B", and store the result to the same memory location.</description>
+		<instruction name="AXOR" form="m64, r64" xed="AXOR_MEM64_GPR64" />
+		<operation>
+MEM[__A+63:__A] := MEM[__A+63:__A] XOR __B[63:0]
+</operation>
+		<parameter type="__int64*" memwidth="64" etype="SI64" varname="__A" />
+		<parameter type="__int64" etype="SI64" varname="__B" />
+	<CPUID>RAO_INT</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+<intrinsic name="_rdpid_u32" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter type="void" />
+	<description>Copy the IA32_TSC_AUX MSR (signature value) into "dst".</description>
+	<operation>dst[31:0] := IA32_TSC_AUX[31:0]
+	</operation>
+	<instruction form="r32" name="RDPID" xed="RDPID_GPR32u32" />
+	<CPUID>RDPID</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_rdrand16_step" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI16" memwidth="16" type="unsigned short*" varname="val" />
+	<description>Read a hardware generated 16-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
+	<operation>IF HW_RND_GEN.ready == 1
+	val[15:0] := HW_RND_GEN.data
+	dst := 1
+ELSE
+	val[15:0] := 0
+	dst := 0
+FI
+	</operation>
+	<instruction form="r16" name="RDRAND" xed="RDRAND_GPRv" />
+	<CPUID>RDRAND</CPUID>
+	<header>immintrin.h</header>
+	<category>Random</category>
+	</intrinsic>
+	<intrinsic name="_rdrand32_step" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="unsigned int*" varname="val" />
+	<description>Read a hardware generated 32-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
+	<operation>IF HW_RND_GEN.ready == 1
+	val[31:0] := HW_RND_GEN.data
+	dst := 1
+ELSE
+	val[31:0] := 0
+	dst := 0
+FI
+	</operation>
+	<instruction form="r32" name="RDRAND" xed="RDRAND_GPRv" />
+	<CPUID>RDRAND</CPUID>
+	<header>immintrin.h</header>
+	<category>Random</category>
+	</intrinsic>
+	<intrinsic name="_rdrand64_step" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI64" memwidth="64" type="unsigned __int64*" varname="val" />
+	<description>Read a hardware generated 64-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
+	<operation>IF HW_RND_GEN.ready == 1
+	val[63:0] := HW_RND_GEN.data
+	dst := 1
+ELSE
+	val[63:0] := 0
+	dst := 0
+FI
+	</operation>
+	<instruction form="r64" name="RDRAND" xed="RDRAND_GPRv" />
+	<CPUID>RDRAND</CPUID>
+	<header>immintrin.h</header>
+	<category>Random</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_rdseed16_step" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI16" type="unsigned short *" varname="val" />
+	<description>Read a 16-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
+	<operation>IF HW_NRND_GEN.ready == 1
+	val[15:0] := HW_NRND_GEN.data
+	dst := 1
+ELSE
+	val[15:0] := 0
+	dst := 0
+FI
+	</operation>
+	<instruction form="r16" name="RDSEED" xed="RDSEED_GPRv" />
+	<CPUID>RDSEED</CPUID>
+	<header>immintrin.h</header>
+	<category>Random</category>
+	</intrinsic>
+	<intrinsic name="_rdseed32_step" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int *" varname="val" />
+	<description>Read a 32-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
+	<operation>IF HW_NRND_GEN.ready == 1
+	val[31:0] := HW_NRND_GEN.data
+	dst := 1
+ELSE
+	val[31:0] := 0
+	dst := 0
+FI
+	</operation>
+	<instruction form="r32" name="RDSEED" xed="RDSEED_GPRv" />
+	<CPUID>RDSEED</CPUID>
+	<header>immintrin.h</header>
+	<category>Random</category>
+	</intrinsic>
+	<intrinsic name="_rdseed64_step" tech="Other">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64 *" varname="val" />
+	<description>Read a 64-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
+	<operation>IF HW_NRND_GEN.ready == 1
+	val[63:0] := HW_NRND_GEN.data
+	dst := 1
+ELSE
+	val[63:0] := 0
+	dst := 0
+FI
+	</operation>
+	<instruction form="r64" name="RDSEED" xed="RDSEED_GPRv" />
+	<CPUID>RDSEED</CPUID>
+	<header>immintrin.h</header>
+	<category>Random</category>
+	</intrinsic>
+	
+	
+<intrinsic name="__rdtscp" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="unsigned int *" varname="mem_addr" />
+	<description>Copy the current 64-bit value of the processor's time-stamp counter into "dst", and store the IA32_TSC_AUX MSR (signature value) into memory at "mem_addr".</description>
+	<operation>dst[63:0] := TimeStampCounter
+MEM[mem_addr+31:mem_addr] := IA32_TSC_AUX[31:0]
+	</operation>
+	<instruction name="RDTSCP" xed="RDTSCP" />
+	<CPUID>RDTSCP</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_xabort" tech="Other">
+	<return type="void" />
+	<parameter etype="IMM" immwidth="8" type="const unsigned int" varname="imm8" />
+	<description>Force an RTM abort. The EAX register is updated to reflect an XABORT instruction caused the abort, and the "imm8" parameter will be provided in bits [31:24] of EAX.
+	Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction.</description>
+	<operation>IF RTM_ACTIVE == 0
+	// nop
+ELSE
+	// restore architectural register state
+	// discard memory updates performed in transaction
+	// update EAX with status and imm8 value
+	eax[31:24] := imm8[7:0]
+	RTM_NEST_COUNT := 0
+	RTM_ACTIVE := 0
+	IF _64_BIT_MODE
+		RIP := fallbackRIP
+	ELSE
+		EIP := fallbackEIP
+	FI
+FI
+	</operation>
+	<instruction form="imm8" name="XABORT" xed="XABORT_IMMb" />
+	<CPUID>RTM</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_xbegin" tech="Other">
+	<return etype="UI32" type="unsigned int" varname="k" />
+	<parameter type="void" />
+	<description>Specify the start of an RTM code region. 
+	If the logical processor was not already in transactional execution, then this call causes the logical processor to transition into transactional execution. 
+	On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution, restores architectural state, and starts execution beginning at the fallback address computed from the outermost XBEGIN instruction. Return status of ~0 (0xFFFF) if continuing inside transaction; all other codes are aborts.</description>
+	<operation>IF RTM_NEST_COUNT &lt; MAX_RTM_NEST_COUNT
+	RTM_NEST_COUNT := RTM_NEST_COUNT + 1
+	IF RTM_NEST_COUNT == 1
+		IF _64_BIT_MODE
+			fallbackRIP := RIP
+		ELSE IF _32_BIT_MODE
+			fallbackEIP := EIP
+		FI
+		
+		RTM_ACTIVE := 1
+		// enter RTM execution, record register state, start tracking memory state
+	FI
+ELSE
+	// RTM abort (see _xabort)
+FI
+	</operation>
+	<instruction form="r32" name="XBEGIN" xed="XBEGIN_RELBRz" />
+	<CPUID>RTM</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_xend" tech="Other">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Specify the end of an RTM code region.
+	If this corresponds to the outermost scope, the logical processor will attempt to commit the logical processor state atomically. 
+	If the commit fails, the logical processor will perform an RTM abort.</description>
+	<operation>IF RTM_ACTIVE == 1
+	RTM_NEST_COUNT := RTM_NEST_COUNT - 1
+	IF RTM_NEST_COUNT == 0
+		// try to commit transaction
+		IF FAIL_TO_COMMIT_TRANSACTION
+			// RTM abort (see _xabort)
+		ELSE
+			RTM_ACTIVE := 0
+		FI
+	FI
+FI
+	</operation>
+	<instruction name="XEND" xed="XEND" />
+	<CPUID>RTM</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_xtest" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter type="void" />
+	<description>Query the transactional execution status, return 1 if inside a transactionally executing RTM or HLE region, and return 0 otherwise.</description>
+	<operation>IF (RTM_ACTIVE == 1 OR HLE_ACTIVE == 1)
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction name="XTEST" xed="XTEST" />
+	<CPUID>RTM</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_serialize" tech="Other">
+	<return type="void" />
+	<description>Serialize instruction execution, ensuring all modifications to flags, registers, and memory by previous instructions are completed before the next instruction is fetched.</description>
+	<instruction name="SERIALIZE" xed="SERIALIZE" />
+	<CPUID>SERIALIZE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_sha1msg1_epu32" tech="Other">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Perform an intermediate calculation for the next four SHA1 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst".</description>
+	<operation>
+W0 := a[127:96]
+W1 := a[95:64]
+W2 := a[63:32]
+W3 := a[31:0]
+W4 := b[127:96]
+W5 := b[95:64]
+dst[127:96] := W2 XOR W0
+dst[95:64] := W3 XOR W1
+dst[63:32] := W4 XOR W2
+dst[31:0] := W5 XOR W3
+	</operation>
+	<instruction form="xmm, xmm" name="SHA1MSG1" xed="SHA1MSG1_XMMi32_XMMi32_SHA" />
+	<CPUID>SHA</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_sha1msg2_epu32" tech="Other">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Perform the final calculation for the next four SHA1 message values (unsigned 32-bit integers) using the intermediate result in "a" and the previous message values in "b", and store the result in "dst".</description>
+	<operation>
+W13 := b[95:64]
+W14 := b[63:32]
+W15 := b[31:0]
+W16 := (a[127:96] XOR W13) &lt;&lt;&lt; 1
+W17 := (a[95:64] XOR W14) &lt;&lt;&lt; 1
+W18 := (a[63:32] XOR W15) &lt;&lt;&lt; 1
+W19 := (a[31:0] XOR W16) &lt;&lt;&lt; 1
+dst[127:96] := W16
+dst[95:64] := W17
+dst[63:32] := W18
+dst[31:0] := W19
+	</operation>
+	<instruction form="xmm, xmm" name="SHA1MSG2" xed="SHA1MSG2_XMMi32_XMMi32_SHA" />
+	<CPUID>SHA</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_sha1nexte_epu32" tech="Other">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Calculate SHA1 state variable E after four rounds of operation from the current SHA1 state variable "a", add that value to the scheduled values (unsigned 32-bit integers) in "b", and store the result in "dst".</description>
+	<operation>
+tmp := (a[127:96] &lt;&lt;&lt; 30)
+dst[127:96] := b[127:96] + tmp
+dst[95:64] := b[95:64]
+dst[63:32] := b[63:32]
+dst[31:0] := b[31:0]
+	</operation>
+	<instruction form="xmm, xmm" name="SHA1NEXTE" xed="SHA1NEXTE_XMMi32_XMMi32_SHA" />
+	<CPUID>SHA</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_sha1rnds4_epu32" tech="Other">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="func" />
+	<description>Perform four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from "a" and some pre-computed sum of the next 4 round message values (unsigned 32-bit integers), and state variable E from "b", and store the updated SHA1 state (A,B,C,D) in "dst". "func" contains the logic functions and round constants.</description>
+	<operation>IF (func[1:0] == 0)
+	f := f0()
+	K := K0
+ELSE IF (func[1:0] == 1)
+	f := f1()
+	K := K1
+ELSE IF (func[1:0] == 2)
+	f := f2()
+	K := K2
+ELSE IF (func[1:0] == 3)
+	f := f3()
+	K := K3
+FI
+A := a[127:96]
+B := a[95:64]
+C := a[63:32]
+D := a[31:0]
+W[0] := b[127:96]
+W[1] := b[95:64]
+W[2] := b[63:32]
+W[3] := b[31:0]
+A[1] := f(B, C, D) + (A &lt;&lt;&lt; 5) + W[0] + K
+B[1] := A
+C[1] := B &lt;&lt;&lt; 30
+D[1] := C
+E[1] := D
+FOR i := 1 to 3
+	A[i+1] := f(B[i], C[i], D[i]) + (A[i] &lt;&lt;&lt; 5) + W[i] + E[i] + K
+	B[i+1] := A[i]
+	C[i+1] := B[i] &lt;&lt;&lt; 30
+	D[i+1] := C[i]
+	E[i+1] := D[i]
+ENDFOR
+dst[127:96] := A[4]
+dst[95:64] := B[4]
+dst[63:32] := C[4]
+dst[31:0] := D[4]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="SHA1RNDS4" xed="SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA" />
+	<CPUID>SHA</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_sha256msg1_epu32" tech="Other">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Perform an intermediate calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst".</description>
+	<operation>W4 := b[31:0]
+W3 := a[127:96]
+W2 := a[95:64]
+W1 := a[63:32]
+W0 := a[31:0]
+dst[127:96] := W3 + sigma0(W4)
+dst[95:64] := W2 + sigma0(W3)
+dst[63:32] := W1 + sigma0(W2)
+dst[31:0] := W0 + sigma0(W1)
+	</operation>
+	<instruction form="xmm, xmm" name="SHA256MSG1" xed="SHA256MSG1_XMMi32_XMMi32_SHA" />
+	<CPUID>SHA</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_sha256msg2_epu32" tech="Other">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Perform the final calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst"."</description>
+	<operation>W14 := b[95:64]
+W15 := b[127:96]
+W16 := a[31:0] + sigma1(W14)
+W17 := a[63:32] + sigma1(W15)
+W18 := a[95:64] + sigma1(W16)
+W19 := a[127:96] + sigma1(W17)
+dst[127:96] := W19
+dst[95:64] := W18
+dst[63:32] := W17
+dst[31:0] := W16
+	</operation>
+	<instruction form="xmm, xmm" name="SHA256MSG2" xed="SHA256MSG2_XMMi32_XMMi32_SHA" />
+	<CPUID>SHA</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_sha256rnds2_epu32" tech="Other">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="__m128i" varname="k" />
+	<description>Perform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from "a", an initial SHA256 state (A,B,E,F) from "b", and a pre-computed sum of the next 2 round message values (unsigned 32-bit integers) and the corresponding round constants from "k", and store the updated SHA256 state (A,B,E,F) in "dst".</description>
+	<operation>A[0] := b[127:96]
+B[0] := b[95:64]
+C[0] := a[127:96]
+D[0] := a[95:64]
+E[0] := b[63:32]
+F[0] := b[31:0]
+G[0] := a[63:32]
+H[0] := a[31:0]
+W_K[0] := k[31:0]
+W_K[1] := k[63:32]
+FOR i := 0 to 1
+	A[i+1] := Ch(E[i], F[i], G[i]) + sum1(E[i]) + W_K[i] + H[i] + Maj(A[i], B[i], C[i]) + sum0(A[i])
+	B[i+1] := A[i]
+	C[i+1] := B[i]
+	D[i+1] := C[i]
+	E[i+1] := Ch(E[i], F[i], G[i]) + sum1(E[i]) + W_K[i] + H[i] + D[i]
+	F[i+1] := E[i]
+	G[i+1] := F[i]
+	H[i+1] := G[i]
+ENDFOR
+dst[127:96] := A[2]
+dst[95:64] := B[2]
+dst[63:32] := E[2]
+dst[31:0] := F[2]
+	</operation>
+	<instruction form="xmm, xmm" name="SHA256RNDS2" xed="SHA256RNDS2_XMMi32_XMMi32_SHA" />
+	<CPUID>SHA</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_sha512msg1_epi64" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="UI64" />
+    <description>This intrinisc is one of the two SHA512 message scheduling instructions. The intrinsic performs an intermediate calculation for the next four SHA512 message qwords. The calculated results are stored in "dst".</description>
+    <instruction name="VSHA512MSG1" form="ymm, xmm" xed="VSHA512MSG1_YMMu64_XMMu64" />
+    <operation>
+DEFINE ROR64(qword, n) {
+	count := n % 64
+	dest := (qword &gt;&gt; count) | (qword &lt;&lt; (64 - count))
+	RETURN dest
+}
+DEFINE SHR64(qword, n) {
+	RETURN qword &gt;&gt; n
+}
+DEFINE s0(qword) {
+	RETURN ROR64(qword,1) ^ ROR64(qword, 8) ^ SHR64(qword, 7)
+}
+W.qword[4] := __B.qword[0]
+W.qword[3] := __A.qword[3]
+W.qword[2] := __A.qword[2]
+W.qword[1] := __A.qword[1]
+W.qword[0] := __A.qword[0]
+dst.qword[3] := W.qword[3] + s0(W.qword[4])
+dst.qword[2] := W.qword[2] + s0(W.qword[3])
+dst.qword[1] := W.qword[1] + s0(W.qword[2])
+dst.qword[0] := W.qword[0] + s0(W.qword[1])
+</operation>
+    <parameter type="__m256i" varname="__A" etype="UI64" />
+    <parameter type="__m128i" varname="__B" etype="UI64" />
+  <CPUID>SHA512</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+  <intrinsic name="_mm256_sha512msg2_epi64" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="UI64" />
+    <description>This intrinisc is one of the two SHA512 message scheduling instructions. The intrinsic performs the final calculation for the next four SHA512 message qwords. The calculated results are stored in "dst".</description>
+    <instruction name="VSHA512MSG2" form="ymm, ymm" xed="VSHA512MSG2_YMMu64_YMMu64" />
+    <operation>
+DEFINE ROR64(qword, n) {
+	count := n % 64
+	dest := (qword &gt;&gt; count) | (qword &lt;&lt; (64 - count))
+	RETURN dest
+}
+DEFINE SHR64(qword, n) {
+	RETURN qword &gt;&gt; n
+}
+DEFINE s1(qword) {
+	RETURN ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)
+}
+W.qword[14] := __B.qword[2]
+W.qword[15] := __B.qword[3]
+W.qword[16] := __A.qword[0] + s1(W.qword[14])
+W.qword[17] := __A.qword[1] + s1(W.qword[15])
+W.qword[18] := __A.qword[2] + s1(W.qword[16])
+W.qword[19] := __A.qword[3] + s1(W.qword[17])
+dst.qword[3] := W.qword[19]
+dst.qword[2] := W.qword[18]
+dst.qword[1] := W.qword[17]
+dst.qword[0] := W.qword[16]
+</operation>
+    <parameter type="__m256i" varname="__A" etype="UI64" />
+    <parameter type="__m256i" varname="__B" etype="UI64" />
+  <CPUID>SHA512</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+  <intrinsic name="_mm256_sha512rnds2_epi64" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="UI64" />
+    <description>This intrinisc performs two rounds of SHA512 operation using initial SHA512 state (C,D,G,H) from "__A", an initial SHA512 state (A,B,E,F) from "__B", and a pre-computed sum of the next two round message qwords and the corresponding round constants from "__C" (only the two lower qwords of the third operand). The updated SHA512 state (A,B,E,F) is written to "dst", and "dst" can be used as the updated state (C,D,G,H) in later rounds.</description>
+    <instruction name="VSHA512RNDS2" form="ymm, ymm, xmm" xed="VSHA512RNDS2_YMMu64_YMMu64_XMMu64" />
+    <operation>
+DEFINE ROR64(qword, n) {
+	count := n % 64
+	dest := (qword &gt;&gt; count) | (qword &lt;&lt; (64 - count))
+	RETURN dest
+}
+DEFINE SHR64(qword, n) {
+	RETURN qword &gt;&gt; n
+}
+DEFINE cap_sigma0(qword) {
+	RETURN ROR64(qword, 28) ^ ROR64(qword, 34) ^ ROR64(qword, 39)
+}
+DEFINE cap_sigma1(qword) {
+	RETURN ROR64(qword, 14) ^ ROR64(qword, 18) ^ ROR64(qword, 41)
+}
+DEFINE MAJ(a,b,c) {
+	RETURN (a &amp; b) ^ (a &amp; c) ^ (b &amp; c)
+}
+DEFINE CH(a,b,c) {
+	RETURN (a &amp; b) ^ (c &amp; ~a)
+}
+A.qword[0] := __B.qword[3]
+B.qword[0] := __B.qword[2]
+C.qword[0] := __A.qword[3]
+D.qword[0] := __A.qword[2]
+E.qword[0] := __B.qword[1]
+F.qword[0] := __B.qword[0]
+G.qword[0] := __A.qword[1]
+H.qword[0] := __A.qword[0]
+WK.qword[0]:= __C.qword[0]
+WK.qword[1]:= __C.qword[1]
+FOR i := 0 to 1
+	A.qword[i+1] := CH(E.qword[i], F.qword[i], G.qword[i]) + cap_sigma1(E.qword[i]) + WK.qword[i] + H.qword[i] + MAJ(A.qword[i], B.qword[i], C.qword[i]) + cap_sigma0(A.qword[i])
+	B.qword[i+1] := A.qword[i]
+	C.qword[i+1] := B.qword[i]
+	D.qword[i+1] := C.qword[i]
+	E.qword[i+1] := CH(E.qword[i], F.qword[i], G.qword[i]) + cap_sigma1(E.qword[i]) + WK.qword[i] + H.qword[i] + D.qword[i]
+	F.qword[i+1] := E.qword[i]
+	G.qword[i+1] := F.qword[i]
+	H.qword[i+1] := G.qword[i]
+ENDFOR
+dst.qword[3] := A.qword[2]
+dst.qword[2] := B.qword[2]
+dst.qword[1] := E.qword[2]
+dst.qword[0] := F.qword[2]
+</operation>
+    <parameter type="__m256i" varname="__A" etype="UI64" />
+    <parameter type="__m256i" varname="__B" etype="UI64" />
+    <parameter type="__m128i" varname="__C" etype="UI64" />
+  <CPUID>SHA512</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+<intrinsic name="_mm_sm3msg1_epi32" tech="AVX_ALL">
+    <return etype="UI32" type="__m128i" varname="dst" />
+    <description>The VSM3MSG1 intrinsic is one of the two SM3 message scheduling intrinsics. The intrinsic performs an initial calculation for the next four SM3 message words. The calculated results are stored in "dst".</description>
+    <instruction form="xmm, xmm, xmm" name="VSM3MSG1" xed="VSM3MSG1_XMMu32_XMMu32_XMMu32" />
+    <operation>
+DEFINE ROL32(dword, n) {
+	count := n % 32
+	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32 - count))
+	RETURN dest
+}
+DEFINE P1(x) {
+	RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
+}
+W.dword[0] := __C.dword[0]
+W.dword[1] := __C.dword[1]
+W.dword[2] := __C.dword[2]
+W.dword[3] := __C.dword[3]
+W.dword[7] := __A.dword[0]
+W.dword[8] := __A.dword[1]
+W.dword[9] := __A.dword[2]
+W.dword[10] := __A.dword[3]
+W.dword[13] := __B.dword[0]
+W.dword[14] := __B.dword[1]
+W.dword[15] := __B.dword[2]
+TMP0 := W.dword[7] ^ W.dword[0] ^ ROL32(W.dword[13], 15)
+TMP1 := W.dword[8] ^ W.dword[1] ^ ROL32(W.dword[14], 15)
+TMP2 := W.dword[9] ^ W.dword[2] ^ ROL32(W.dword[15], 15)
+TMP3 := W.dword[10] ^ W.dword[3]
+dst.dword[0] := P1(TMP0)
+dst.dword[1] := P1(TMP1)
+dst.dword[2] := P1(TMP2)
+dst.dword[3] := P1(TMP3)
+</operation>
+    <parameter etype="UI32" type="__m128i" varname="__A" />
+    <parameter etype="UI32" type="__m128i" varname="__B" />
+    <parameter etype="UI32" type="__m128i" varname="__C" />
+  <CPUID>SM3</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+  <intrinsic name="_mm_sm3msg2_epi32" tech="AVX_ALL">
+    <return etype="UI32" type="__m128i" varname="dst" />
+    <description>The VSM3MSG2 intrinsic is one of the two SM3 message scheduling intrinsics. The intrinsic performs the final calculation for the next four SM3 message words. The calculated results are stored in "dst".</description>
+    <instruction form="xmm, xmm, xmm" name="VSM3MSG2" xed="VSM3MSG2_XMMu32_XMMu32_XMMu32" />
+    <operation>
+DEFINE ROL32(dword, n) {
+	count := n % 32
+	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
+	RETURN dest
+}
+WTMP.dword[0] := __A.dword[0]
+WTMP.dword[1] := __A.dword[1]
+WTMP.dword[2] := __A.dword[2]
+WTMP.dword[3] := __A.dword[3]
+W.dword[3] := __B.dword[0]
+W.dword[4] := __B.dword[1]
+W.dword[5] := __B.dword[2]
+W.dword[6] := __B.dword[3]
+W.dword[10] := __C.dword[0]
+W.dword[11] := __C.dword[1]
+W.dword[12] := __C.dword[2]
+W.dword[13] := __C.dword[3]
+W.dword[16] := ROL32(W.dword[3], 7) ^ W.dword[10] ^ WTMP.dword[0]
+W.dword[17] := ROL32(W.dword[4], 7) ^ W.dword[11] ^ WTMP.dword[1]
+W.dword[18] := ROL32(W.dword[5], 7) ^ W.dword[12] ^ WTMP.dword[2]
+W.dword[19] := ROL32(W.dword[6], 7) ^ W.dword[13] ^ WTMP.dword[3]
+W.dword[19] := W.dword[19] ^ ROL32(W.dword[16], 6) ^ ROL32(W.dword[16], 15) ^ ROL32(W.dword[16], 30)
+dst.dword[0] := W.dword[16]
+dst.dword[1] := W.dword[17]
+dst.dword[2] := W.dword[18]
+dst.dword[3] := W.dword[19]
+</operation>
+    <parameter etype="UI32" type="__m128i" varname="__A" />
+    <parameter etype="UI32" type="__m128i" varname="__B" />
+    <parameter etype="UI32" type="__m128i" varname="__C" />
+  <CPUID>SM3</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+  <intrinsic name="_mm_sm3rnds2_epi32" tech="AVX_ALL">
+    <return etype="UI32" type="__m128i" varname="dst" />
+    <description>The intrinsic performs two rounds of SM3 operation using initial SM3 state (C, D, G, H) from "__A", an initial SM3 states (A, B, E, F) from "__B" and a pre-computed words from the "__C". "__A" with initial SM3 state of (C, D, G, H) assumes input of non-rotated left variables from previous state. The updated SM3 state (A, B, E, F) is written to "__A". The "imm8" should contain the even round number for the first of the two rounds computed by this instruction. The computation masks the "imm8" value by ANDing it with 0x3E so that only even round numbers from 0 through 62 are used for this operation. The calculated results are stored in "dst".</description>
+    <instruction form="xmm, xmm, xmm, imm8" name="VSM3RNDS2" xed="VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8" />
+    <operation>
+DEFINE ROL32(dword, n) {
+	count := n % 32
+	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
+	RETURN dest
+}
+DEFINE P0(x) {
+	RETURN x ^ ROL32(x, 9) ^ ROL32(x, 17)
+}
+DEFINE FF(x, y, z, round) {
+	IF round &lt; 16
+		RETURN (x ^ y ^ z)
+	ELSE
+		RETURN (x &amp; y) | (x &amp; z) | (y &amp; z)
+	FI
+}
+DEFINE GG(x, y, z, round){
+	IF round &lt; 16
+		RETURN (x ^ y ^ z)
+	ELSE
+		RETURN (x &amp; y) | (~x &amp; z)
+	FI
+}
+A.dword[0] := __B.dword[3]
+B.dword[0] := __B.dword[2]
+C.dword[0] := __A.dword[3]
+D.dword[0] := __A.dword[2]
+E.dword[0] := __B.dword[1]
+F.dword[0] := __B.dword[0]
+G.dword[0] := __A.dword[1]
+H.dword[0] := __A.dword[0]
+W.dword[0] := __C.dword[0]
+W.dword[1] := __C.dword[1]
+W.dword[4] := __C.dword[2]
+W.dword[5] := __C.dword[3]
+C.dword[0] := ROL32(C.dword[0], 9)
+D.dword[0] := ROL32(D.dword[0], 9)
+G.dword[0] := ROL32(G.dword[0], 19)
+H.dword[0] := ROL32(H.dword[0], 19)
+ROUND := imm8 &amp; 0x3E
+IF ROUND &lt; 16
+	CONST.dword[0] := 0x79CC4519
+ELSE
+	CONST.dword[0] := 0x7A879D8A
+FI
+CONST.dword[0] := ROL32(CONST.dword[0], ROUND)
+FOR i:= 0 to 1
+	temp.dword[0] := ROL32(A.dword[i], 12) + E.dword[i] + CONST.dword[0]
+	S1.dword[0] := ROL32(temp.dword[0], 7)
+	S2.dword[0] := S1.dword[0] ^ ROL32(A.dword[i], 12)
+	T1.dword[0] := FF(A.dword[i], B.dword[i], C.dword[i], ROUND) + D.dword[i] + S2.dword[0] + (W.dword[i] ^ W.dword[i+4])
+	T2.dword[0] := GG(E.dword[i], F.dword[i], G.dword[i], ROUND) + H.dword[i] + S1.dword[0] + W.dword[i]
+	D.dword[i+1] := C.dword[i]
+	C.dword[i+1] := ROL32(B.dword[i], 9)
+	B.dword[i+1] := A.dword[i]
+	A.dword[i+1] := T1.dword[0]
+	H.dword[i+1] := G.dword[i]
+	G.dword[i+1] := ROL32(F.dword[i], 19)
+	F.dword[i+1] := E.dword[i]
+	E.dword[i+1] := P0(T2.dword[0])
+	CONST.dword[0] := ROL32(CONST.dword[0], 1)
+ENDFOR
+dst.dword[3] := A.dword[2]
+dst.dword[2] := B.dword[2]
+dst.dword[1] := E.dword[2]
+dst.dword[0] := F.dword[2]
+</operation>
+    <parameter etype="UI32" type="__m128i" varname="__A" />
+    <parameter etype="UI32" type="__m128i" varname="__B" />
+    <parameter etype="UI32" type="__m128i" varname="__C" />
+    <parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+  <CPUID>SM3</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+<intrinsic name="_mm256_sm4key4_epi32" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="UI32" />
+    <description>This intrinsic performs four rounds of SM4 key expansion. The intrinsic operates on independent 128-bit lanes. The calculated results are stored in "dst". </description>
+    <instruction name="VSM4KEY4" form="ymm, ymm, ymm" xed="VSM4KEY4_YMMu32_YMMu32_YMMu32" />
+    <operation>
+BYTE sbox[256] = {
+0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
+0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
+0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
+0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
+0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
+0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
+0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
+0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
+0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
+0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
+0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
+0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
+0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
+0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
+0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
+}
+DEFINE ROL32(dword, n) {
+	count := n % 32
+	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
+	RETURN dest
+}
+DEFINE SBOX_BYTE(dword, i) {
+	RETURN sbox[dword.byte[i]]
+}
+DEFINE lower_t(dword) {
+	tmp.byte[0] := SBOX_BYTE(dword, 0)
+	tmp.byte[1] := SBOX_BYTE(dword, 1)
+	tmp.byte[2] := SBOX_BYTE(dword, 2)
+	tmp.byte[3] := SBOX_BYTE(dword, 3)
+	RETURN tmp
+}
+DEFINE L_KEY(dword) {
+	RETURN dword ^ ROL32(dword, 13) ^ ROL32(dword, 23)
+}
+DEFINE T_KEY(dword) {
+	RETURN L_KEY(lower_t(dword))
+}
+DEFINE F_KEY(X0, X1, X2, X3, round_key) {
+	RETURN X0 ^ T_KEY(X1 ^ X2 ^ X3 ^ round_key)
+}
+FOR i:= 0 to 1
+	P.dword[0] := __A.dword[4*i]
+	P.dword[1] := __A.dword[4*i+1]
+	P.dword[2] := __A.dword[4*i+2]
+	P.dword[3] := __A.dword[4*i+3]
+	C.dword[0] := F_KEY(P.dword[0], P.dword[1], P.dword[2], P.dword[3], __B.dword[4*i])
+	C.dword[1] := F_KEY(P.dword[1], P.dword[2], P.dword[3], C.dword[0], __B.dword[4*i+1])
+	C.dword[2] := F_KEY(P.dword[2], P.dword[3], C.dword[0], C.dword[1], __B.dword[4*i+2])
+	C.dword[3] := F_KEY(P.dword[3], C.dword[0], C.dword[1], C.dword[2], __B.dword[4*i+3])
+	dst.dword[4*i] := C.dword[0]
+	dst.dword[4*i+1] := C.dword[1]
+	dst.dword[4*i+2] := C.dword[2]
+	dst.dword[4*i+3] := C.dword[3]
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+    <parameter type="__m256i" varname="__A" etype="UI32" />
+    <parameter type="__m256i" varname="__B" etype="UI32" />
+  <CPUID>SM4</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+  <intrinsic name="_mm256_sm4rnds4_epi32" tech="AVX_ALL">
+    <return type="__m256i" varname="dst" etype="UI32" />
+    <description>This intrinisc performs four rounds of SM4 encryption. The intrinisc operates on independent 128-bit lanes. The calculated results are stored in "dst". </description>
+    <instruction name="VSM4RNDS4" form="ymm, ymm, ymm" xed="VSM4RNDS4_YMMu32_YMMu32_YMMu32" />
+    <operation>BYTE sbox[256] = {
+0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
+0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
+0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
+0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
+0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
+0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
+0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
+0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
+0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
+0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
+0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
+0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
+0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
+0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
+0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
+}
+DEFINE ROL32(dword, n) {
+	count := n % 32
+	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
+	RETURN dest
+}
+DEFINE SBOX_BYTE(dword, i) {
+	RETURN sbox[dword.byte[i]]
+}
+DEFINE lower_t(dword) {
+	tmp.byte[0] := SBOX_BYTE(dword, 0)
+	tmp.byte[1] := SBOX_BYTE(dword, 1)
+	tmp.byte[2] := SBOX_BYTE(dword, 2)
+	tmp.byte[3] := SBOX_BYTE(dword, 3)
+	RETURN tmp
+}
+DEFINE L_RND(dword) {
+	tmp := dword
+	tmp := tmp ^ ROL32(dword, 2)
+	tmp := tmp ^ ROL32(dword, 10)
+	tmp := tmp ^ ROL32(dword, 18)
+	tmp := tmp ^ ROL32(dword, 24)
+	RETURN tmp
+}
+DEFINE T_RND(dword) {
+	RETURN L_RND(lower_t(dword))
+}
+DEFINE F_RND(X0, X1, X2, X3, round_key) {
+	RETURN X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key)
+}
+FOR i:= 0 to 1
+	P.dword[0] := __A.dword[4*i]
+	P.dword[1] := __A.dword[4*i+1]
+	P.dword[2] := __A.dword[4*i+2]
+	P.dword[3] := __A.dword[4*i+3]
+	C.dword[0] := F_RND(P.dword[0], P.dword[1], P.dword[2], P.dword[3], __B.dword[4*i])
+	C.dword[1] := F_RND(P.dword[1], P.dword[2], P.dword[3], C.dword[0], __B.dword[4*i+1])
+	C.dword[2] := F_RND(P.dword[2], P.dword[3], C.dword[0], C.dword[1], __B.dword[4*i+2])
+	C.dword[3] := F_RND(P.dword[3], C.dword[0], C.dword[1], C.dword[2], __B.dword[4*i+3])
+	dst.dword[4*i] := C.dword[0]
+	dst.dword[4*i+1] := C.dword[1]
+	dst.dword[4*i+2] := C.dword[2]
+	dst.dword[4*i+3] := C.dword[3]
+ENDFOR
+dst[MAX:256] := 0
+</operation>
+    <parameter type="__m256i" varname="__A" etype="UI32" />
+    <parameter type="__m256i" varname="__B" etype="UI32" />
+  <CPUID>SM4</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+  <intrinsic name="_mm_sm4key4_epi32" tech="AVX_ALL">
+    <return type="__m128i" varname="dst" etype="UI32" />
+    <description>This intrinsic performs four rounds of SM4 key expansion. The intrinsic operates on independent 128-bit lanes. The calculated results are stored in "dst". </description>
+    <instruction name="VSM4KEY4" form="xmm, xmm, xmm" xed="VSM4KEY4_XMMu32_XMMu32_XMMu32" />
+    <operation>
+BYTE sbox[256] = {
+0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
+0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
+0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
+0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
+0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
+0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
+0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
+0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
+0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
+0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
+0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
+0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
+0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
+0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
+0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
+}
+DEFINE ROL32(dword, n) {
+	count := n % 32
+	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
+	RETURN dest
+}
+DEFINE SBOX_BYTE(dword, i) {
+	RETURN sbox[dword.byte[i]]
+}
+DEFINE lower_t(dword) {
+	tmp.byte[0] := SBOX_BYTE(dword, 0)
+	tmp.byte[1] := SBOX_BYTE(dword, 1)
+	tmp.byte[2] := SBOX_BYTE(dword, 2)
+	tmp.byte[3] := SBOX_BYTE(dword, 3)
+	RETURN tmp
+}
+DEFINE L_KEY(dword) {
+	RETURN dword ^ ROL32(dword, 13) ^ ROL32(dword, 23)
+}
+DEFINE T_KEY(dword) {
+	RETURN L_KEY(lower_t(dword))
+}
+DEFINE F_KEY(X0, X1, X2, X3, round_key) {
+	RETURN X0 ^ T_KEY(X1 ^ X2 ^ X3 ^ round_key)
+}
+P.dword[0] := __A.dword[0]
+P.dword[1] := __A.dword[1]
+P.dword[2] := __A.dword[2]
+P.dword[3] := __A.dword[3]
+C.dword[0] := F_KEY(P.dword[0], P.dword[1], P.dword[2], P.dword[3], __B.dword[0])
+C.dword[1] := F_KEY(P.dword[1], P.dword[2], P.dword[3], C.dword[0], __B.dword[1])
+C.dword[2] := F_KEY(P.dword[2], P.dword[3], C.dword[0], C.dword[1], __B.dword[2])
+C.dword[3] := F_KEY(P.dword[3], C.dword[0], C.dword[1], C.dword[2], __B.dword[3])
+dst.dword[0] := C.dword[0]
+dst.dword[1] := C.dword[1]
+dst.dword[2] := C.dword[2]
+dst.dword[3] := C.dword[3]
+dst[MAX:128] := 0
+</operation>
+    <parameter type="__m128i" varname="__A" etype="UI32" />
+    <parameter type="__m128i" varname="__B" etype="UI32" />
+  <CPUID>SM4</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+  <intrinsic name="_mm_sm4rnds4_epi32" tech="AVX_ALL">
+    <return type="__m128i" varname="dst" etype="UI32" />
+    <description>This intrinisc performs four rounds of SM4 encryption. The intrinisc operates on independent 128-bit lanes. The calculated results are stored in "dst". </description>
+    <instruction name="VSM4RNDS4" form="xmm, xmm, xmm" xed="VSM4RNDS4_XMMu32_XMMu32_XMMu32" />
+    <operation>
+BYTE sbox[256] = {
+0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
+0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
+0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
+0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
+0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
+0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
+0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
+0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
+0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
+0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
+0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
+0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
+0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
+0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
+0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
+}
+DEFINE ROL32(dword, n) {
+	count := n % 32
+	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
+	RETURN dest
+}
+DEFINE SBOX_BYTE(dword, i) {
+	RETURN sbox[dword.byte[i]]
+}
+DEFINE lower_t(dword) {
+	tmp.byte[0] := SBOX_BYTE(dword, 0)
+	tmp.byte[1] := SBOX_BYTE(dword, 1)
+	tmp.byte[2] := SBOX_BYTE(dword, 2)
+	tmp.byte[3] := SBOX_BYTE(dword, 3)
+	RETURN tmp
+}
+DEFINE L_RND(dword) {
+	tmp := dword
+	tmp := tmp ^ ROL32(dword, 2)
+	tmp := tmp ^ ROL32(dword, 10)
+	tmp := tmp ^ ROL32(dword, 18)
+	tmp := tmp ^ ROL32(dword, 24)
+	RETURN tmp
+}
+DEFINE T_RND(dword) {
+	RETURN L_RND(lower_t(dword))
+}
+DEFINE F_RND(X0, X1, X2, X3, round_key) {
+	RETURN X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key)
+}
+P.dword[0] := __A.dword[0]
+P.dword[1] := __A.dword[1]
+P.dword[2] := __A.dword[2]
+P.dword[3] := __A.dword[3]
+C.dword[0] := F_RND(P.dword[0], P.dword[1], P.dword[2], P.dword[3], __B.dword[0])
+C.dword[1] := F_RND(P.dword[1], P.dword[2], P.dword[3], C.dword[0], __B.dword[1])
+C.dword[2] := F_RND(P.dword[2], P.dword[3], C.dword[0], C.dword[1], __B.dword[2])
+C.dword[3] := F_RND(P.dword[3], C.dword[0], C.dword[1], C.dword[2], __B.dword[3])
+dst.dword[0] := C.dword[0]
+dst.dword[1] := C.dword[1]
+dst.dword[2] := C.dword[2]
+dst.dword[3] := C.dword[3]
+dst[MAX:128] := 0
+</operation>
+    <parameter type="__m128i" varname="__A" etype="UI32" />
+    <parameter type="__m128i" varname="__B" etype="UI32" />
+  <CPUID>SM4</CPUID>
+  <CPUID>AVX</CPUID>
+	<header>immintrin.h</header>
+  <category>Cryptography</category>
+  </intrinsic>
+<intrinsic name="_mm_acos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ACOS(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_acos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ACOS(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_acosh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ACOSH(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_acosh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ACOSH(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_asin_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ASIN(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_asin_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ASIN(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_asinh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ASINH(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_asinh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ASINH(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_atan_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ATAN(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_atan_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ATAN(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_atan2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_atan2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_atanh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ATANH(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_atanh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ATANH(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_cos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := COS(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_cos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := COS(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_cosd_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := COSD(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_cosd_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := COSD(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_cosh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := COSH(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_cosh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := COSH(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_hypot_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_hypot_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_sin_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SIN(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_sin_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SIN(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_sincos_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="128" type="__m128d *" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SIN(a[i+63:i])
+	MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_sincos_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="128" type="__m128 *" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SIN(a[i+31:i])
+	MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_sind_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SIND(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_sind_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SIND(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_sinh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SINH(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_sinh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SINH(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_tan_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := TAN(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_tan_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := TAN(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_tand_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := TAND(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_tand_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := TAND(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_tanh_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := TANH(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_tanh_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := TANH(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Trigonometry</category>
+	</intrinsic>
+	<intrinsic name="_mm_cbrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := CubeRoot(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_cbrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := CubeRoot(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_cexp_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+	<operation>
+DEFINE CEXP(a[31:0], b[31:0]) {
+	result[31:0]  := POW(FP32(e), a[31:0]) * COS(b[31:0])
+	result[63:32] := POW(FP32(e), a[31:0]) * SIN(b[31:0])
+	RETURN result
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := CEXP(a[i+31:i], a[i+63:i+32])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_clog_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the natural logarithm of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+	<operation>
+DEFINE CLOG(a[31:0], b[31:0]) {
+	result[31:0]  := LOG(SQRT(POW(a, 2.0) + POW(b, 2.0)))
+	result[63:32] := ATAN2(b, a)
+	RETURN result
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := CLOG(a[i+31:i], a[i+63:i+32])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_csqrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the square root of packed complex snumbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
+	<operation>
+DEFINE CSQRT(a[31:0], b[31:0]) {
+	sign[31:0] := (b &lt; 0.0) ? -FP32(1.0) : FP32(1.0)
+	result[31:0]  := SQRT((a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
+	result[63:32] := sign * SQRT((-a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
+	RETURN result
+}
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := CSQRT(a[i+31:i], a[i+63:i+32])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_exp_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := POW(e, a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_exp_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := POW(FP32(e), a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_exp10_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := POW(10.0, a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_exp10_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_exp2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := POW(2.0, a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_exp2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_expm1_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_expm1_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_invcbrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := InvCubeRoot(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_invcbrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := InvCubeRoot(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_invsqrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := InvSQRT(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_invsqrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := InvSQRT(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_log_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_log_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_log10_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_log10_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_log1p_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := LOG(1.0 + a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_log1p_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := LOG(1.0 + a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_log2_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_log2_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_logb_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_logb_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_pow_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_pow_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_svml_sqrt_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SQRT(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_svml_sqrt_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SQRT(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_cdfnorm_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := CDFNormal(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_cdfnorm_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := CDFNormal(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_cdfnorminv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := InverseCDFNormal(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_cdfnorminv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := InverseCDFNormal(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_erf_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ERF(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_erfc_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := 1.0 - ERF(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_erfc_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+63:i] := 1.0 - ERF(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_erfcinv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_erfcinv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_erfinv_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := 1.0 / ERF(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_erfinv_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+63:i] := 1.0 / ERF(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_epi8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 8*j
+	IF b[i+7:i] == 0
+		#DE
+	FI
+	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_epi16" sequence="TRUE" tech="SVML">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	IF b[i+15:i] == 0
+		#DE
+	FI
+	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_epi32" sequence="TRUE" tech="SVML">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF b[i+31:i] == 0
+		#DE
+	FI
+	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_epi64" sequence="TRUE" tech="SVML">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	IF b[i+63:i] == 0
+		#DE
+	FI
+	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_epu8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := 8*j
+	IF b[i+7:i] == 0
+		#DE
+	FI
+	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_epu16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := 16*j
+	IF b[i+15:i] == 0
+		#DE
+	FI
+	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_epu32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	IF b[i+31:i] == 0
+		#DE
+	FI
+	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_epu64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	IF b[i+63:i] == 0
+		#DE
+	FI
+	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_erf_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ERF(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_idiv_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_idivrem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" memwidth="128" type="__m128i *" varname="mem_addr" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr".</description>
+	<operation>FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_irem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rem_epi8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := 8*j
+	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rem_epi16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 16*j
+	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rem_epi64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := 64*j
+	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rem_epu8" sequence="TRUE" tech="SVML">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 15
+	i := 8*j
+	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rem_epu16" sequence="TRUE" tech="SVML">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 7
+	i := 16*j
+	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rem_epu32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_rem_epu64" sequence="TRUE" tech="SVML">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := 64*j
+	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_udiv_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_udivrem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" memwidth="128" type="__m128i *" varname="mem_addr" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr".</description>
+	<operation>FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
+	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_urem_epi32" sequence="TRUE" tech="SVML">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_svml_ceil_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := CEIL(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_svml_ceil_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := CEIL(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_svml_floor_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := FLOOR(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_svml_floor_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := FLOOR(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_svml_round_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ROUND(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_svml_round_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ROUND(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_trunc_pd" sequence="TRUE" tech="SVML">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := TRUNCATE(a[i+63:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_trunc_ps" sequence="TRUE" tech="SVML">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := TRUNCATE(a[i+31:i])
+ENDFOR
+dst[MAX:128] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_MM_TRANSPOSE4_PS" sequence="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" type="__m128" varname="row0" />
+	<parameter etype="FP32" type="__m128" varname="row1" />
+	<parameter etype="FP32" type="__m128" varname="row2" />
+	<parameter etype="FP32" type="__m128" varname="row3" />
+	<description>Macro: Transpose the 4x4 matrix formed by the 4 rows of single-precision (32-bit) floating-point elements in "row0", "row1", "row2", and "row3", and store the transposed matrix in these vectors ("row0" now contains column 0, etc.).</description>
+	<operation>
+__m128 tmp3, tmp2, tmp1, tmp0;
+tmp0 := _mm_unpacklo_ps(row0, row1);
+tmp2 := _mm_unpacklo_ps(row2, row3);
+tmp1 := _mm_unpackhi_ps(row0, row1);
+tmp3 := _mm_unpackhi_ps(row2, row3);
+row0 := _mm_movelh_ps(tmp0, tmp2);
+row1 := _mm_movehl_ps(tmp2, tmp0);
+row2 := _mm_movelh_ps(tmp1, tmp3);
+row3 := _mm_movehl_ps(tmp3, tmp1);
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_extract_pi16" tech="SSE_ALL">
+	<return etype="UI16" type="int" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".</description>
+	<operation>
+dst[15:0] := (a[63:0] &gt;&gt; (imm8[1:0] * 16))[15:0]
+dst[31:16] := 0
+	</operation>
+	<instruction form="r32, mm, imm8" name="PEXTRW" xed="PEXTRW_GPR32_MMXq_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_pextrw" tech="SSE_ALL">
+	<return etype="UI16" type="int" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".</description>
+	<operation>
+dst[15:0] := (a[63:0] &gt;&gt; (imm8[1:0] * 16))[15:0]
+dst[31:16] := 0
+	</operation>
+	<instruction form="r32, mm, imm8" name="PEXTRW" xed="PEXTRW_GPR32_MMXq_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_insert_pi16" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="int" varname="i" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[63:0] := a[63:0]
+sel := imm8[1:0]*16
+dst[sel+15:sel] := i[15:0]
+	</operation>
+	<instruction form="mm, r32, imm8" name="PINSRW" xed="PINSRW_MMXq_GPR32_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_pinsrw" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="int" varname="i" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[63:0] := a[63:0]
+sel := imm8[1:0]*16
+dst[sel+15:sel] := i[15:0]
+	</operation>
+	<instruction form="mm, r32, imm8" name="PINSRW" xed="PINSRW_MMXq_GPR32_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_shuffle_pi16" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[15:0] := src[15:0]
+	1:	tmp[15:0] := src[31:16]
+	2:	tmp[15:0] := src[47:32]
+	3:	tmp[15:0] := src[63:48]
+	ESAC
+	RETURN tmp[15:0]
+}
+dst[15:0] := SELECT4(a[63:0], imm8[1:0])
+dst[31:16] := SELECT4(a[63:0], imm8[3:2])
+dst[47:32] := SELECT4(a[63:0], imm8[5:4])
+dst[63:48] := SELECT4(a[63:0], imm8[7:6])
+	</operation>
+	<instruction form="mm, mm, imm8" name="PSHUFW" xed="PSHUFW_MMXq_MMXq_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_m_pshufw" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[15:0] := src[15:0]
+	1:	tmp[15:0] := src[31:16]
+	2:	tmp[15:0] := src[47:32]
+	3:	tmp[15:0] := src[63:48]
+	ESAC
+	RETURN tmp[15:0]
+}
+dst[15:0] := SELECT4(a[63:0], imm8[1:0])
+dst[31:16] := SELECT4(a[63:0], imm8[3:2])
+dst[47:32] := SELECT4(a[63:0], imm8[5:4])
+dst[63:48] := SELECT4(a[63:0], imm8[7:6])
+	</operation>
+	<instruction form="mm, mm, imm8" name="PSHUFW" xed="PSHUFW_MMXq_MMXq_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_shuffle_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
+	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(b[127:0], imm8[5:4])
+dst[127:96] := SELECT4(b[127:0], imm8[7:6])
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="SHUFPS" xed="SHUFPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="UNPCKHPS" xed="UNPCKHPS_XMMps_XMMdq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="UNPCKLPS" xed="UNPCKLPS_XMMps_XMMq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_getcsr" tech="SSE_ALL">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter type="void" />
+	<description>Get the unsigned 32-bit value of the MXCSR control and status register.</description>
+	<operation>dst[31:0] := MXCSR
+	</operation>
+	<instruction form="m32" name="STMXCSR" xed="STMXCSR_MEMd" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_setcsr" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Set the MXCSR control and status register with the value in unsigned 32-bit integer "a".</description>
+	<operation>
+MXCSR := a[31:0]
+	</operation>
+	<instruction form="m32" name="LDMXCSR" xed="LDMXCSR_MEMd" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_MM_GET_EXCEPTION_STATE" tech="SSE_ALL">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<description>Macro: Get the exception state bits from the MXCSR control and status register. The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT</description>
+	<operation>dst[31:0] := MXCSR &amp; _MM_EXCEPT_MASK
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_MM_SET_EXCEPTION_STATE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Macro: Set the exception state bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT</description>
+	<operation>MXCSR := a[31:0] AND ~_MM_EXCEPT_MASK
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_MM_GET_EXCEPTION_MASK" tech="SSE_ALL">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<description>Macro: Get the exception mask bits from the MXCSR control and status register. The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT</description>
+	<operation>dst[31:0] := MXCSR &amp; _MM_MASK_MASK
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_MM_SET_EXCEPTION_MASK" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Macro: Set the exception mask bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT</description>
+	<operation>MXCSR := a[31:0] AND ~_MM_MASK_MASK
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_MM_GET_ROUNDING_MODE" tech="SSE_ALL">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<description>Macro: Get the rounding mode bits from the MXCSR control and status register. The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO</description>
+	<operation>dst[31:0] := MXCSR &amp; _MM_ROUND_MASK
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_MM_SET_ROUNDING_MODE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO</description>
+	<operation>MXCSR := a[31:0] AND ~_MM_ROUND_MASK
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_MM_GET_FLUSH_ZERO_MODE" tech="SSE_ALL">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<description>Macro: Get the flush zero bits from the MXCSR control and status register. The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF</description>
+	<operation>dst[31:0] := MXCSR &amp; _MM_FLUSH_MASK
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_MM_SET_FLUSH_ZERO_MODE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Macro: Set the flush zero bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF</description>
+	<operation>MXCSR := a[31:0] AND ~_MM_FLUSH_MASK
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_prefetch" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI8" type="char const*" varname="p" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="i" />
+	<description>Fetch the line of data from memory that contains address "p" to a location in the cache hierarchy specified by the locality hint "i", which can be one of:&lt;ul&gt;
+    &lt;li&gt;_MM_HINT_T0   // 3, move data using the T0 hint. The PREFETCHT0 instruction will be generated.&lt;/li&gt;
+    &lt;li&gt;_MM_HINT_T1   // 2, move data using the T1 hint. The PREFETCHT1 instruction will be generated.&lt;/li&gt;
+    &lt;li&gt;_MM_HINT_T2   // 1, move data using the T2 hint. The PREFETCHT2 instruction will be generated.&lt;/li&gt;
+    &lt;li&gt;_MM_HINT_NTA  // 0, move data using the non-temporal access (NTA) hint. The PREFETCHNTA instruction will be generated.&lt;/li&gt;
+</description>
+	<instruction form="m8" name="PREFETCHNTA" xed="PREFETCHNTA_MEMmprefetch" />
+	<instruction form="m8" name="PREFETCHT0" xed="PREFETCHT0_MEMmprefetch" />
+	<instruction form="m8" name="PREFETCHT1" xed="PREFETCHT1_MEMmprefetch" />
+	<instruction form="m8" name="PREFETCHT2" xed="PREFETCHT2_MEMmprefetch" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_sfence" tech="SSE_ALL">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Perform a serializing operation on all store-to-memory instructions that were issued prior to this instruction. Guarantees that every store instruction that precedes, in program order, is globally visible before any store instruction which follows the fence in program order.</description>
+	<instruction name="SFENCE" xed="SFENCE" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_malloc" tech="SSE_ALL">
+	<return type="void*" />
+	<parameter etype="UI64" type="size_t" varname="size" />
+	<parameter etype="UI64" type="size_t" varname="align" />
+	<description>Allocate "size" bytes of memory, aligned to the alignment specified in "align", and return a pointer to the allocated memory. "_mm_free" should be used to free memory that is allocated with "_mm_malloc".</description>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_free" tech="SSE_ALL">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<description>Free aligned memory that was allocated with "_mm_malloc".</description>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_undefined_ps" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m128 with undefined elements.</description>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_pi16" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMAXSW" xed="PMAXSW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_m_pmaxsw" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMAXSW" xed="PMAXSW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_pu8" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMAXUB" xed="PMAXUB_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_m_pmaxub" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMAXUB" xed="PMAXUB_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_pi16" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMINSW" xed="PMINSW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_m_pminsw" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMINSW" xed="PMINSW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_pu8" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMINUB" xed="PMINUB_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_m_pminub" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMINUB" xed="PMINUB_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper element of "dst". [min_float_note]</description>
+	<operation>
+dst[31:0] := MIN(a[31:0], b[31:0])
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="MINSS" xed="MINSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="MINPS" xed="MINPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper element of "dst". [max_float_note]</description>
+	<operation>
+dst[31:0] := MAX(a[31:0], b[31:0])
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="MAXSS" xed="MAXSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="MAXPS" xed="MAXPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_mulhi_pu16" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	tmp[31:0] := a[i+15:i] * b[i+15:i]
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMULHUW" xed="PMULHUW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_pmulhuw" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	tmp[31:0] := a[i+15:i] * b[i+15:i]
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMULHUW" xed="PMULHUW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sad_pu8" tech="SSE_ALL">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
+ENDFOR
+dst[15:0] := tmp[7:0] + tmp[15:8] + tmp[23:16] + tmp[31:24] + tmp[39:32] + tmp[47:40] + tmp[55:48] + tmp[63:56]
+dst[63:16] := 0
+	</operation>
+	<instruction form="mm, mm" name="PSADBW" xed="PSADBW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_m_psadbw" tech="SSE_ALL">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
+ENDFOR
+dst[15:0] := tmp[7:0] + tmp[15:8] + tmp[23:16] + tmp[31:24] + tmp[39:32] + tmp[47:40] + tmp[55:48] + tmp[63:56]
+dst[63:16] := 0
+	</operation>
+	<instruction form="mm, mm" name="PSADBW" xed="PSADBW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] + b[31:0]
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="ADDSS" xed="ADDSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ADDPS" xed="ADDPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] - b[31:0]
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="SUBSS" xed="SUBSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="SUBPS" xed="SUBPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] * b[31:0]
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="MULSS" xed="MULSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] * b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="MULPS" xed="MULPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] / b[31:0]
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="DIVSS" xed="DIVSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := a[i+31:i] / b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="DIVPS" xed="DIVPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_avg_pu8" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PAVGB" xed="PAVGB_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_m_pavgb" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PAVGB" xed="PAVGB_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_avg_pu16" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PAVGW" xed="PAVGW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_m_pavgw" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<parameter etype="UI16" type="__m64" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PAVGW" xed="PAVGW_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi32_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, r32" name="CVTSI2SS" xed="CVTSI2SS_XMMss_GPR32d" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_si2ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, r32" name="CVTSI2SS" xed="CVTSI2SS_XMMss_GPR32d" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi64_ss" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<description>Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int64_To_FP32(b[63:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, r64" name="CVTSI2SS" xed="CVTSI2SS_XMMss_GPR64q" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpi32_ps" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Convert packed 32-bit integers in "b" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", and copy the upper 2 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[63:32] := Convert_Int32_To_FP32(b[63:32])
+dst[95:64] := a[95:64]
+dst[127:96] := a[127:96]
+	</operation>
+	<instruction form="xmm, mm" name="CVTPI2PS" xed="CVTPI2PS_XMMq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_pi2ps" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Convert packed signed 32-bit integers in "b" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", and copy the upper 2 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(b[31:0])
+dst[63:32] := Convert_Int32_To_FP32(b[63:32])
+dst[95:64] := a[95:64]
+dst[127:96] := a[127:96]
+	</operation>
+	<instruction form="xmm, mm" name="CVTPI2PS" xed="CVTPI2PS_XMMq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpi16_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<description>Convert packed 16-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	m := j*32
+	dst[m+31:m] := Convert_Int16_To_FP32(a[i+15:i])
+ENDFOR
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpu16_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="UI16" type="__m64" varname="a" />
+	<description>Convert packed unsigned 16-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	m := j*32
+	dst[m+31:m] := Convert_Int16_To_FP32(a[i+15:i])
+ENDFOR
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpi8_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="SI8" type="__m64" varname="a" />
+	<description>Convert the lower packed 8-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*8
+	m := j*32
+	dst[m+31:m] := Convert_Int8_To_FP32(a[i+7:i])
+ENDFOR
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpu8_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<description>Convert the lower packed unsigned 8-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*8
+	m := j*32
+	dst[m+31:m] := Convert_Int8_To_FP32(a[i+7:i])
+ENDFOR
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpi32x2_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", then covert the packed signed 32-bit integers in "b" to single-precision (32-bit) floating-point element, and store the results in the upper 2 elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_Int32_To_FP32(a[31:0])
+dst[63:32] := Convert_Int32_To_FP32(a[63:32])
+dst[95:64] := Convert_Int32_To_FP32(b[31:0])
+dst[127:96] := Convert_Int32_To_FP32(b[63:32])
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_si32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32(a[31:0])
+	</operation>
+	<instruction form="r32, xmm" name="CVTSS2SI" xed="CVTSS2SI_GPR32d_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_ss2si" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32(a[31:0])
+	</operation>
+	<instruction form="r32, xmm" name="CVTSS2SI" xed="CVTSS2SI_GPR32d_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_si64" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_Int64(a[31:0])
+	</operation>
+	<instruction form="r64, xmm" name="CVTSS2SI" xed="CVTSS2SI_GPR64q_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_f32" tech="SSE_ALL">
+	<return etype="FP32" type="float" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+	</operation>
+	<instruction form="m32, xmm" name="MOVSS" xed="MOVSS_MEMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_pi32" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, xmm" name="CVTPS2PI" xed="CVTPS2PI_MMXq_XMMq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvt_ps2pi" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, xmm" name="CVTPS2PI" xed="CVTPS2PI_MMXq_XMMq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttss_si32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
+	</operation>
+	<instruction form="r32, xmm" name="CVTTSS2SI" xed="CVTTSS2SI_GPR32d_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_ss2si" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
+	</operation>
+	<instruction form="r32, xmm" name="CVTTSS2SI" xed="CVTTSS2SI_GPR32d_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttss_si64" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0])
+	</operation>
+	<instruction form="r64, xmm" name="CVTTSS2SI" xed="CVTTSS2SI_GPR64q_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttps_pi32" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, xmm" name="CVTTPS2PI" xed="CVTTPS2PI_MMXq_XMMq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtt_ps2pi" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, xmm" name="CVTTPS2PI" xed="CVTTPS2PI_MMXq_XMMq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_pi16" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst". Note: this intrinsic will generate 0x7FFF, rather than 0x8000, for input values between 0x7FFF and 0x7FFFFFFF.</description>
+	<operation>
+FOR j := 0 to 3
+	i := 16*j
+	k := 32*j
+	IF a[k+31:k] &gt;= FP32(0x7FFF) &amp;&amp; a[k+31:k] &lt;= FP32(0x7FFFFFFF)
+		dst[i+15:i] := 0x7FFF
+	ELSE
+		dst[i+15:i] := Convert_FP32_To_Int16(a[k+31:k])
+	FI
+ENDFOR
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_pi8" sequence="TRUE" tech="SSE_ALL">
+	<return etype="SI8" type="__m64" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 8-bit integers, and store the results in lower 4 elements of "dst". Note: this intrinsic will generate 0x7F, rather than 0x80, for input values between 0x7F and 0x7FFFFFFF.</description>
+	<operation>
+FOR j := 0 to 3
+	i := 8*j
+	k := 32*j
+	IF a[k+31:k] &gt;= FP32(0x7F) &amp;&amp; a[k+31:k] &lt;= FP32(0x7FFFFFFF)
+		dst[i+7:i] := 0x7F
+	ELSE
+		dst[i+7:i] := Convert_FP32_To_Int8(a[k+31:k])
+	FI
+ENDFOR
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_stream_pi" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="64" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<description>Store 64-bits of integer data from "a" into memory using a non-temporal memory hint.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+	</operation>
+	<instruction form="m64, mm" name="MOVNTQ" xed="MOVNTQ_MEMq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskmove_si64" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="mask" />
+	<parameter etype="UI8" memwidth="64" type="char*" varname="mem_addr" />
+	<description>Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	IF mask[i+7]
+		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="MASKMOVQ" xed="MASKMOVQ_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_m_maskmovq" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="mask" />
+	<parameter etype="UI8" memwidth="64" type="char*" varname="mem_addr" />
+	<description>Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	IF mask[i+7]
+		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="MASKMOVQ" xed="MASKMOVQ_MMXq_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_stream_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVNTPS" xed="MOVNTPS_MEMdq_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeh_pi" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="64" type="__m64*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store the upper 2 single-precision (32-bit) floating-point elements from "a" into memory.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[95:64]
+MEM[mem_addr+63:mem_addr+32] := a[127:96]
+	</operation>
+	<instruction form="m64, xmm" name="MOVHPS" xed="MOVHPS_MEMq_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storel_pi" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="64" type="__m64*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store the lower 2 single-precision (32-bit) floating-point elements from "a" into memory.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[31:0]
+MEM[mem_addr+63:mem_addr+32] := a[63:32]
+	</operation>
+	<instruction form="m64, xmm" name="MOVLPS" xed="MOVLPS_MEMq_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="32" type="float*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store the lower single-precision (32-bit) floating-point element from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[31:0]
+	</operation>
+	<instruction form="m32, xmm" name="MOVSS" xed="MOVSS_MEMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store1_ps" sequence="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="32" type="float*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store the lower single-precision (32-bit) floating-point element from "a" into 4 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[31:0]
+MEM[mem_addr+63:mem_addr+32] := a[31:0]
+MEM[mem_addr+95:mem_addr+64] := a[31:0]
+MEM[mem_addr+127:mem_addr+96] := a[31:0]
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_ps1" sequence="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="32" type="float*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store the lower single-precision (32-bit) floating-point element from "a" into 4 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[31:0]
+MEM[mem_addr+63:mem_addr+32] := a[31:0]
+MEM[mem_addr+95:mem_addr+64] := a[31:0]
+MEM[mem_addr+127:mem_addr+96] := a[31:0]
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_ps" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="float*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory.
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVAPS" xed="MOVAPS_MEMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="float*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory.
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVUPS" xed="MOVUPS_MEMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storer_ps" sequence="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP32" memwidth="128" type="float*" varname="mem_addr" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Store 4 single-precision (32-bit) floating-point elements from "a" into memory in reverse order.
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[127:96]
+MEM[mem_addr+63:mem_addr+32] := a[95:64]
+MEM[mem_addr+95:mem_addr+64] := a[63:32]
+MEM[mem_addr+127:mem_addr+96] := a[31:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVUPS" xed="MOVUPS_MEMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_movemask_pi8" tech="SSE_ALL">
+	<return etype="UI8" type="int" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[j] := a[i+7]
+ENDFOR
+dst[MAX:8] := 0
+	</operation>
+	<instruction form="r32, mm" name="PMOVMSKB" xed="PMOVMSKB_GPR32_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_m_pmovmskb" tech="SSE_ALL">
+	<return etype="UI8" type="int" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[j] := a[i+7]
+ENDFOR
+dst[MAX:8] := 0
+	</operation>
+	<instruction form="r32, mm" name="PMOVMSKB" xed="PMOVMSKB_GPR32_MMXq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movemask_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF a[i+31]
+		dst[j] := 1
+	ELSE
+		dst[j] := 0
+	FI
+ENDFOR
+dst[MAX:4] := 0
+	</operation>
+	<instruction form="r32, xmm" name="MOVMSKPS" xed="MOVMSKPS_GPR32_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := SQRT(a[31:0])
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="SQRTSS" xed="SQRTSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SQRT(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="SQRTPS" xed="SQRTPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rcp_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+dst[31:0] := (1.0 / a[31:0])
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="RCPSS" xed="RCPSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rcp_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (1.0 / a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="RCPPS" xed="RCPPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rsqrt_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+dst[31:0] := (1.0 / SQRT(a[31:0]))
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="RSQRTSS" xed="RSQRTSS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_rsqrt_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="RSQRTPS" xed="RSQRTPS_XMMps_XMMps" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_and_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ANDPS" xed="ANDPS_XMMxud_XMMxud" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_andnot_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ANDNPS" xed="ANDNPS_XMMxud_XMMxud" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_or_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ORPS" xed="ORPS_XMMxud_XMMxud" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_xor_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="XORPS" xed="XORPS_XMMxud_XMMxud" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for equality, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := ( a[31:0] == b[31:0] ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for less-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := ( a[31:0] &lt; b[31:0] ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &lt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := ( a[31:0] &lt;= b[31:0] ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for greater-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := ( a[31:0] &gt; b[31:0] ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for greater-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := ( a[31:0] &gt;= b[31:0] ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := ( a[31:0] != b[31:0] ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] != b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnlt_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := (!( a[31:0] &lt; b[31:0] )) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnlt_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := !( a[i+31:i] &lt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnle_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := (!( a[31:0] &lt;= b[31:0] )) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnle_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (!( a[i+31:i] &lt;= b[i+31:i] )) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpngt_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := (!( a[31:0] &gt; b[31:0] )) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpngt_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (!( a[i+31:i] &gt; b[i+31:i] )) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnge_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := (!( a[31:0] &gt;= b[31:0] )) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnge_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := (!( a[i+31:i] &gt;= b[i+31:i] )) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpord_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>dst[31:0] := ( a[31:0] != NaN AND b[31:0] != NaN ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpord_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] != NaN AND b[i+31:i] != NaN ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpunord_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>dst[31:0] := ( a[31:0] == NaN OR b[31:0] == NaN ) ? 0xFFFFFFFF : 0
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpunord_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] == NaN OR b[i+31:i] == NaN ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comieq_ss" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] == b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comilt_ss" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &lt; b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comile_ss" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &lt;= b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comigt_ss" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &gt; b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comige_ss" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &gt;= b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comineq_ss" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[31:0] == NaN OR b[31:0] == NaN OR a[31:0] != b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomieq_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] == b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomilt_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &lt; b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomile_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &lt;= b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomigt_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &gt; b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomige_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &gt;= b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomineq_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[31:0] == NaN OR b[31:0] == NaN OR a[31:0] != b[31:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_ss" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Copy single-precision (32-bit) floating-point element "a" to the lower element of "dst", and zero the upper 3 elements.</description>
+	<operation>
+dst[31:0] := a[31:0]
+dst[127:32] := 0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_ps1" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="float" varname="a" />
+	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="float" varname="e3" />
+	<parameter etype="FP32" type="float" varname="e2" />
+	<parameter etype="FP32" type="float" varname="e1" />
+	<parameter etype="FP32" type="float" varname="e0" />
+	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst[31:0] := e0
+dst[63:32] := e1
+dst[95:64] := e2
+dst[127:96] := e3
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="float" varname="e3" />
+	<parameter etype="FP32" type="float" varname="e2" />
+	<parameter etype="FP32" type="float" varname="e1" />
+	<parameter etype="FP32" type="float" varname="e0" />
+	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[31:0] := e3
+dst[63:32] := e2
+dst[95:64] := e1
+dst[127:96] := e0
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setzero_ps" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m128 with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="XORPS" xed="XORPS_XMMxud_XMMxud" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadh_pi" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" memwidth="64" type="__m64 const*" varname="mem_addr" />
+	<description>Load 2 single-precision (32-bit) floating-point elements from memory into the upper 2 elements of "dst", and copy the lower 2 elements from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[31:0] := a[31:0]
+dst[63:32] := a[63:32]
+dst[95:64] := MEM[mem_addr+31:mem_addr]
+dst[127:96] := MEM[mem_addr+63:mem_addr+32]
+	</operation>
+	<instruction form="xmm, m64" name="MOVHPS" xed="MOVHPS_XMMq_MEMq" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadl_pi" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" memwidth="64" type="__m64 const*" varname="mem_addr" />
+	<description>Load 2 single-precision (32-bit) floating-point elements from memory into the lower 2 elements of "dst", and copy the upper 2 elements from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[31:0] := MEM[mem_addr+31:mem_addr]
+dst[63:32] := MEM[mem_addr+63:mem_addr+32]
+dst[95:64] := a[95:64]
+dst[127:96] := a[127:96]
+	</operation>
+	<instruction form="xmm, m64" name="MOVLPS" xed="MOVLPS_XMMq_MEMq" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="32" type="float const*" varname="mem_addr" />
+	<description>Load a single-precision (32-bit) floating-point element from memory into the lower of "dst", and zero the upper 3 elements. "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[31:0] := MEM[mem_addr+31:mem_addr]
+dst[127:32] := 0
+	</operation>
+	<instruction form="xmm, m32" name="MOVSS" xed="MOVSS_XMMdq_MEMss" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load1_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="32" type="float const*" varname="mem_addr" />
+	<description>Load a single-precision (32-bit) floating-point element from memory into all elements of "dst".</description>
+	<operation>
+dst[31:0] := MEM[mem_addr+31:mem_addr]
+dst[63:32] := MEM[mem_addr+31:mem_addr]
+dst[95:64] := MEM[mem_addr+31:mem_addr]
+dst[127:96] := MEM[mem_addr+31:mem_addr]
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_ps1" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="32" type="float const*" varname="mem_addr" />
+	<description>Load a single-precision (32-bit) floating-point element from memory into all elements of "dst".</description>
+	<operation>
+dst[31:0] := MEM[mem_addr+31:mem_addr]
+dst[63:32] := MEM[mem_addr+31:mem_addr]
+dst[95:64] := MEM[mem_addr+31:mem_addr]
+dst[127:96] := MEM[mem_addr+31:mem_addr]
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="128" type="float const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into "dst".
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVAPS" xed="MOVAPS_XMMps_MEMps" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="128" type="float const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into "dst".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVUPS" xed="MOVUPS_XMMps_MEMps" />
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadr_ps" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" memwidth="128" type="float const*" varname="mem_addr" />
+	<description>Load 4 single-precision (32-bit) floating-point elements from memory into "dst" in reverse order. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[31:0] := MEM[mem_addr+127:mem_addr+96]
+dst[63:32] := MEM[mem_addr+95:mem_addr+64]
+dst[95:64] := MEM[mem_addr+63:mem_addr+32]
+dst[127:96] := MEM[mem_addr+31:mem_addr]
+	</operation>
+	<CPUID>SSE</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_move_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := b[31:0]
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm" name="MOVSS" xed="MOVSS_XMMss_XMMss_0F10" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_movehl_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Move the upper 2 single-precision (32-bit) floating-point elements from "b" to the lower 2 elements of "dst", and copy the upper 2 elements from "a" to the upper 2 elements of "dst".</description>
+	<operation>
+dst[31:0] := b[95:64]
+dst[63:32] := b[127:96]
+dst[95:64] := a[95:64]
+dst[127:96] := a[127:96]
+	</operation>
+	<instruction form="xmm, xmm" name="MOVHLPS" xed="MOVHLPS_XMMq_XMMq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_movelh_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Move the lower 2 single-precision (32-bit) floating-point elements from "b" to the upper 2 elements of "dst", and copy the lower 2 elements from "a" to the lower 2 elements of "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+dst[63:32] := a[63:32]
+dst[95:64] := b[31:0]
+dst[127:96] := b[63:32]
+	</operation>
+	<instruction form="xmm, xmm" name="MOVLHPS" xed="MOVLHPS_XMMq_XMMq" />
+	<CPUID>SSE</CPUID>
+	<header>xmmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_undefined_pd" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m128d with undefined elements.</description>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_undefined_si128" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m128i with undefined elements.</description>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_pause" tech="SSE_ALL">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Provide a hint to the processor that the code sequence is a spin-wait loop. This can help improve the performance and power consumption of spin-wait loops.</description>
+	<instruction name="PAUSE" xed="PAUSE" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_clflush" tech="SSE_ALL">
+	<return type="void" />
+	<parameter type="void const*" varname="p" />
+	<description>Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy.</description>
+	<instruction form="m8" name="CLFLUSH" xed="CLFLUSH_MEMmprefetch" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_lfence" tech="SSE_ALL">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Perform a serializing operation on all load-from-memory instructions that were issued prior to this instruction. Guarantees that every load instruction that precedes, in program order, is globally visible before any load instruction which follows the fence in program order.</description>
+	<instruction name="LFENCE" xed="LFENCE" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_mfence" tech="SSE_ALL">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Perform a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior to this instruction. Guarantees that every memory access that precedes, in program order, the memory fence instruction is globally visible before any memory instruction which follows the fence in program order.</description>
+	<instruction name="MFENCE" xed="MFENCE" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_si64" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" memwidth="64" type="void const*" varname="mem_addr" />
+	<description>Load unaligned 64-bit integer from memory into the first element of "dst".</description>
+	<operation>
+dst[63:0] := MEM[mem_addr+63:mem_addr]
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, m64" name="MOVQ" xed="MOVQ_XMMdq_MEMq_0F6E" />
+	<CPUID>SSE2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_si16" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" memwidth="16" type="void const*" varname="mem_addr" />
+	<description>Load unaligned 16-bit integer from memory into the first element of "dst".</description>
+	<operation>
+dst[15:0] := MEM[mem_addr+15:mem_addr]
+dst[MAX:16] := 0
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>immintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_si32" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" memwidth="32" type="void const*" varname="mem_addr" />
+	<description>Load unaligned 32-bit integer from memory into the first element of "dst".</description>
+	<operation>
+dst[31:0] := MEM[mem_addr+31:mem_addr]
+dst[MAX:32] := 0
+	</operation>
+	<instruction form="xmm, m32" name="MOVD" xed="MOVD_XMMdq_MEMd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadl_epi64" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" memwidth="64" type="__m128i const*" varname="mem_addr" />
+	<description>Load 64-bit integer from memory into the first element of "dst".</description>
+	<operation>
+dst[63:0] := MEM[mem_addr+63:mem_addr]
+dst[MAX:64] := 0
+	</operation>
+	<instruction form="xmm, m64" name="MOVQ" xed="MOVQ_XMMdq_MEMq_0F7E" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="mem_addr" />
+	<description>Load 128-bits of integer data from memory into "dst". 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVDQA" xed="MOVDQA_XMMdq_MEMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="mem_addr" />
+	<description>Load 128-bits of integer data from memory into "dst".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVDQU" xed="MOVDQU_XMMdq_MEMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="128" type="double const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into "dst".
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVAPD" xed="MOVAPD_XMMpd_MEMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load1_pd" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
+	<description>Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".</description>
+	<operation>
+dst[63:0] := MEM[mem_addr+63:mem_addr]
+dst[127:64] := MEM[mem_addr+63:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVAPD" xed="MOVAPD_XMMpd_MEMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_pd1" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
+	<description>Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".</description>
+	<operation>
+dst[63:0] := MEM[mem_addr+63:mem_addr]
+dst[127:64] := MEM[mem_addr+63:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVAPD" xed="MOVAPD_XMMpd_MEMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadr_pd" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="128" type="double const*" varname="mem_addr" />
+	<description>Load 2 double-precision (64-bit) floating-point elements from memory into "dst" in reverse order. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[63:0] := MEM[mem_addr+127:mem_addr+64]
+dst[127:64] := MEM[mem_addr+63:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVAPD" xed="MOVAPD_XMMpd_MEMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadu_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="128" type="double const*" varname="mem_addr" />
+	<description>Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into "dst".
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVUPD" xed="MOVUPD_XMMpd_MEMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_load_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
+	<description>Load a double-precision (64-bit) floating-point element from memory into the lower of "dst", and zero the upper element. "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[63:0] := MEM[mem_addr+63:mem_addr]
+dst[127:64] := 0
+	</operation>
+	<instruction form="xmm, m64" name="MOVSD" xed="MOVSD_XMM_XMMdq_MEMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadh_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
+	<description>Load a double-precision (64-bit) floating-point element from memory into the upper element of "dst", and copy the lower element from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := MEM[mem_addr+63:mem_addr]
+	</operation>
+	<instruction form="xmm, m64" name="MOVHPD" xed="MOVHPD_XMMsd_MEMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loadl_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
+	<description>Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst", and copy the upper element from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+dst[63:0] := MEM[mem_addr+63:mem_addr]
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, m64" name="MOVLPD" xed="MOVLPD_XMMsd_MEMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_si16" sequence="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI16" memwidth="16" type="void*" varname="mem_addr" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Store 16-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+15:mem_addr] := a[15:0]
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_si64" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="64" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Store 64-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+	</operation>
+	<instruction form="m64, xmm" name="MOVQ" xed="MOVQ_MEMq_XMMq_0F7E" />
+	<CPUID>SSE2</CPUID>
+	<header>immintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_si32" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="32" type="void*" varname="mem_addr" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Store 32-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[31:0]
+	</operation>
+	<instruction form="m32, xmm" name="MOVD" xed="MOVD_MEMd_XMMd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_maskmoveu_si128" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="mask" />
+	<parameter etype="UI8" memwidth="128" type="char*" varname="mem_addr" />
+	<description>Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint. "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF mask[i+7]
+		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="MASKMOVDQU" xed="MASKMOVDQU_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="M128" memwidth="128" type="__m128i*" varname="mem_addr" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Store 128-bits of integer data from "a" into memory. 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVDQA" xed="MOVDQA_MEMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="M128" memwidth="128" type="__m128i*" varname="mem_addr" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Store 128-bits of integer data from "a" into memory.
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVDQU" xed="MOVDQU_MEMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storel_epi64" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="64" type="__m128i*" varname="mem_addr" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Store 64-bit integer from the first element of "a" into memory.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+	</operation>
+	<instruction form="m64, xmm" name="MOVQ" xed="MOVQ_MEMq_XMMq_0F7E" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_stream_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="M128" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Store 128-bits of integer data from "a" into memory using a non-temporal memory hint. 
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVNTDQ" xed="MOVNTDQ_MEMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_stream_si32" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI32" memwidth="32" type="void*" varname="mem_addr" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Store 32-bit integer "a" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address "mem_addr" is already in the cache, the cache will be updated.</description>
+	<operation>
+MEM[mem_addr+31:mem_addr] := a[31:0]
+	</operation>
+	<instruction form="m32, r32" name="MOVNTI" xed="MOVNTI_MEMd_GPR32" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_stream_si64" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="UI64" memwidth="64" type="void*" varname="mem_addr" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Store 64-bit integer "a" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address "mem_addr" is already in the cache, the cache will be updated.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+	</operation>
+	<instruction form="m64, r64" name="MOVNTI" xed="MOVNTI_MEMq_GPR64" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_stream_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="void*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVNTPD" xed="MOVNTPD_MEMdq_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store the lower double-precision (64-bit) floating-point element from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+	</operation>
+	<instruction form="m64, xmm" name="MOVSD" xed="MOVSD_XMM_MEMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store1_pd" sequence="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store the lower double-precision (64-bit) floating-point element from "a" into 2 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+MEM[mem_addr+127:mem_addr+64] := a[63:0]
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_pd1" sequence="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store the lower double-precision (64-bit) floating-point element from "a" into 2 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+MEM[mem_addr+127:mem_addr+64] := a[63:0]
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_store_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="double*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory.
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVAPD" xed="MOVAPD_MEMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeu_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="double*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory.
+	"mem_addr" does not need to be aligned on any particular boundary.</description>
+	<operation>
+MEM[mem_addr+127:mem_addr] := a[127:0]
+	</operation>
+	<instruction form="m128, xmm" name="MOVUPD" xed="MOVUPD_MEMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storer_pd" sequence="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="128" type="double*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store 2 double-precision (64-bit) floating-point elements from "a" into memory in reverse order.
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[127:64]
+MEM[mem_addr+127:mem_addr+64] := a[63:0]
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storeh_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store the upper double-precision (64-bit) floating-point element from "a" into memory.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[127:64]
+	</operation>
+	<instruction form="m64, xmm" name="MOVHPD" xed="MOVHPD_MEMq_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_storel_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return type="void" />
+	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Store the lower double-precision (64-bit) floating-point element from "a" into memory.</description>
+	<operation>
+MEM[mem_addr+63:mem_addr] := a[63:0]
+	</operation>
+	<instruction form="m64, xmm" name="MOVLPD" xed="MOVLPD_MEMq_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Store</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := a[i+7:i] + b[i+7:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PADDB" xed="PADDB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := a[i+15:i] + b[i+15:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PADDW" xed="PADDW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] + b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PADDD" xed="PADDD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_si64" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Add 64-bit integers "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := a[63:0] + b[63:0]
+	</operation>
+	<instruction form="mm, mm" name="PADDQ" xed="PADDQ_MMXq_MMXq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PADDQ" xed="PADDQ_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_adds_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PADDSB" xed="PADDSB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_adds_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PADDSW" xed="PADDSW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_adds_epu8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PADDUSB" xed="PADDUSB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_adds_epu16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PADDUSW" xed="PADDUSW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_madd_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMADDWD" xed="PMADDWD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mulhi_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMULHW" xed="PMULHW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mulhi_epu16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	tmp[31:0] := a[i+15:i] * b[i+15:i]
+	dst[i+15:i] := tmp[31:16]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMULHUW" xed="PMULHUW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mullo_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
+	dst[i+15:i] := tmp[15:0]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMULLW" xed="PMULLW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_su32" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI32" type="__m64" varname="a" />
+	<parameter etype="UI32" type="__m64" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from "a" and "b", and store the unsigned 64-bit result in "dst".</description>
+	<operation>
+dst[63:0] := a[31:0] * b[31:0]
+	</operation>
+	<instruction form="mm, mm" name="PMULUDQ" xed="PMULUDQ_MMXq_MMXq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_epu32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+31:i] * b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMULUDQ" xed="PMULUDQ_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sad_epu8" vexEq="TRUE" tech="SSE_ALL">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce two unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
+ENDFOR
+FOR j := 0 to 1
+	i := j*64
+	dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
+	               tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
+	dst[i+63:i+16] := 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSADBW" xed="PSADBW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := a[i+7:i] - b[i+7:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSUBB" xed="PSUBB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := a[i+15:i] - b[i+15:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSUBW" xed="PSUBW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[i+31:i] - b[i+31:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSUBD" xed="PSUBD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_si64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<parameter etype="UI64" type="__m64" varname="b" />
+	<description>Subtract 64-bit integer "b" from 64-bit integer "a", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := a[63:0] - b[63:0]
+	</operation>
+	<instruction form="mm, mm" name="PSUBQ" xed="PSUBQ_MMXq_MMXq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSUBQ" xed="PSUBQ_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_subs_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSUBSB" xed="PSUBSB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_subs_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSUBSW" xed="PSUBSW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_subs_epu8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSUBUSB" xed="PSUBUSB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_subs_epu16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSUBUSW" xed="PSUBUSW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := a[63:0] + b[63:0]
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="ADDSD" xed="ADDSD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_add_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] + b[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ADDPD" xed="ADDPD_XMMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := a[63:0] / b[63:0]
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="DIVSD" xed="DIVSD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_div_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	dst[i+63:i] := a[i+63:i] / b[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="DIVPD" xed="DIVPD_XMMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := a[63:0] * b[63:0]
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="MULSD" xed="MULSD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] * b[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="MULPD" xed="MULPD_XMMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := a[63:0] - b[63:0]
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="SUBSD" xed="SUBSD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sub_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] - b[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="SUBPD" xed="SUBPD_XMMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_avg_epu8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PAVGB" xed="PAVGB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_avg_epu16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PAVGW" xed="PAVGW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Probability/Statistics</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMAXSW" xed="PMAXSW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_epu8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMAXUB" xed="PMAXUB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMINSW" xed="PMINSW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_epu8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMINUB" xed="PMINUB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [max_float_note]</description>
+	<operation>
+dst[63:0] := MAX(a[63:0], b[63:0])
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="MAXSD" xed="MAXSD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="MAXPD" xed="MAXPD_XMMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [min_float_note]</description>
+	<operation>
+dst[63:0] := MIN(a[63:0], b[63:0])
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="MINSD" xed="MINSD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="MINPD" xed="MINPD_XMMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_slli_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
+	</operation>
+	<instruction form="xmm, imm8" name="PSLLDQ" xed="PSLLDQ_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_bslli_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
+	</operation>
+	<instruction form="xmm, imm8" name="PSLLDQ" xed="PSLLDQ_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_bsrli_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
+	</operation>
+	<instruction form="xmm, imm8" name="PSRLDQ" xed="PSRLDQ_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_slli_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, imm8" name="PSLLW" xed="PSLLW_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sll_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSLLW" xed="PSLLW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_slli_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, imm8" name="PSLLD" xed="PSLLD_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sll_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSLLD" xed="PSLLD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_slli_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, imm8" name="PSLLQ" xed="PSLLQ_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sll_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSLLQ" xed="PSLLQ_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srai_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="5" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, imm8" name="PSRAW" xed="PSRAW_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sra_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
+	ELSE
+		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSRAW" xed="PSRAW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srai_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, imm8" name="PSRAD" xed="PSRAD_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_sra_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
+	ELSE
+		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSRAD" xed="PSRAD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srli_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+tmp := imm8[7:0]
+IF tmp &gt; 15
+	tmp := 16
+FI
+dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
+	</operation>
+	<instruction form="xmm, imm8" name="PSRLDQ" xed="PSRLDQ_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srli_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF imm8[7:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, imm8" name="PSRLW" xed="PSRLW_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srl_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="count" />
+	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF count[63:0] &gt; 15
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSRLW" xed="PSRLW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srli_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF imm8[7:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, imm8" name="PSRLD" xed="PSRLD_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srl_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="count" />
+	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF count[63:0] &gt; 31
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSRLD" xed="PSRLD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srli_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF imm8[7:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, imm8" name="PSRLQ" xed="PSRLQ_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_srl_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="count" />
+	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF count[63:0] &gt; 63
+		dst[i+63:i] := 0
+	ELSE
+		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSRLQ" xed="PSRLQ_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Shift</category>
+	</intrinsic>
+	<intrinsic name="_mm_and_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[127:0] := (a[127:0] AND b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PAND" xed="PAND_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_andnot_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<description>Compute the bitwise NOT of 128 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
+	<operation>
+dst[127:0] := ((NOT a[127:0]) AND b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PANDN" xed="PANDN_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_or_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<description>Compute the bitwise OR of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[127:0] := (a[127:0] OR b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="POR" xed="POR_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_xor_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<description>Compute the bitwise XOR of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
+	<operation>
+dst[127:0] := (a[127:0] XOR b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PXOR" xed="PXOR_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_and_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ANDPD" xed="ANDPD_XMMxuq_XMMxuq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_andnot_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ANDNPD" xed="ANDNPD_XMMxuq_XMMxuq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_or_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ORPD" xed="ORPD_XMMxuq_XMMxuq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_xor_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="XORPD" xed="XORPD_XMMxuq_XMMxuq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPEQB" xed="PCMPEQB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPEQW" xed="PCMPEQW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPEQD" xed="PCMPEQD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPGTB" xed="PCMPGTB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPGTW" xed="PCMPGTW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPGTD" xed="PCMPGTD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtb instruction with the order of the operands switched.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := ( a[i+7:i] &lt; b[i+7:i] ) ? 0xFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPGTB" xed="PCMPGTB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtw instruction with the order of the operands switched.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ( a[i+15:i] &lt; b[i+15:i] ) ? 0xFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPGTW" xed="PCMPGTW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtd instruction with the order of the operands switched.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ( a[i+31:i] &lt; b[i+31:i] ) ? 0xFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPGTD" xed="PCMPGTD_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for equality, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] == b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for less-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] &lt; b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] &lt;= b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for greater-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] &gt; b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for greater-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] &gt;= b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpord_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>dst[63:0] := (a[63:0] != NaN AND b[63:0] != NaN) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpunord_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>dst[63:0] := (a[63:0] == NaN OR b[63:0] == NaN) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (a[63:0] != b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnlt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (!(a[63:0] &lt; b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnle_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (!(a[63:0] &lt;= b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpngt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (!(a[63:0] &gt; b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnge_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := (!(a[63:0] &gt;= b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] == b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmplt_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] &lt; b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmple_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] &lt;= b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] &gt; b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpge_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] &gt;= b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpord_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpunord_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpneq_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (a[i+63:i] != b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnlt_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (!(a[i+63:i] &lt; b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnle_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (!(a[i+63:i] &lt;= b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpngt_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (!(a[i+63:i] &gt; b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpnge_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := (!(a[i+63:i] &gt;= b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comieq_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] == b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comilt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &lt; b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comile_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &lt;= b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comigt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &gt; b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comige_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &gt;= b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_comineq_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1).</description>
+	<operation>RETURN ( a[63:0] == NaN OR b[63:0] == NaN OR a[63:0] != b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomieq_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] == b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomilt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &lt; b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomile_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &lt;= b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomigt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &gt; b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomige_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &gt;= b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_ucomineq_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
+	<operation>RETURN ( a[63:0] == NaN OR b[63:0] == NaN OR a[63:0] != b[63:0] ) ? 1 : 0
+	</operation>
+	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi32_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="CVTDQ2PD" xed="CVTDQ2PD_XMMpd_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi32_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="SI32" type="int" varname="b" />
+	<description>Convert the signed 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := Convert_Int32_To_FP64(b[31:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, r32" name="CVTSI2SD" xed="CVTSI2SD_XMMsd_GPR32d" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi64_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := Convert_Int64_To_FP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, r64" name="CVTSI2SD" xed="CVTSI2SD_XMMsd_GPR64q" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi64x_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="SI64" type="__int64" varname="b" />
+	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := Convert_Int64_To_FP64(b[63:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, r64" name="CVTSI2SD" xed="CVTSI2SD_XMMsd_GPR64q" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi32_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="CVTDQ2PS" xed="CVTDQ2PS_XMMps_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpi32_pd" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	m := j*64
+	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, mm" name="CVTPI2PD" xed="CVTPI2PD_XMMpd_MMXq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi32_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+dst[127:32] := 0
+	</operation>
+	<instruction form="xmm, r32" name="MOVD" xed="MOVD_XMMdq_GPR32" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi64_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element.</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := 0
+	</operation>
+	<instruction form="xmm, r64" name="MOVQ" xed="MOVQ_XMMdq_GPR64" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi64x_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element.</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := 0
+	</operation>
+	<instruction form="xmm, r64" name="MOVQ" xed="MOVQ_XMMdq_GPR64" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi128_si32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
+	<operation>
+dst[31:0] := a[31:0]
+	</operation>
+	<instruction form="r32, xmm" name="MOVD" xed="MOVD_GPR32_XMMd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi128_si64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Copy the lower 64-bit integer in "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="r64, xmm" name="MOVQ" xed="MOVQ_GPR64_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsi128_si64x" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Copy the lower 64-bit integer in "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="r64, xmm" name="MOVQ" xed="MOVQ_GPR64_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpd_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
+ENDFOR
+dst[127:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="CVTPD2PS" xed="CVTPD2PS_XMMps_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="CVTPS2PD" xed="CVTPS2PD_XMMpd_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpd_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="CVTPD2DQ" xed="CVTPD2DQ_XMMdq_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_si32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_Int32(a[63:0])
+	</operation>
+	<instruction form="r32, xmm" name="CVTSD2SI" xed="CVTSD2SI_GPR32d_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_si64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64(a[63:0])
+	</operation>
+	<instruction form="r64, xmm" name="CVTSD2SI" xed="CVTSD2SI_GPR64q_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_si64x" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64(a[63:0])
+	</operation>
+	<instruction form="r64, xmm" name="CVTSD2SI" xed="CVTSD2SI_GPR64q_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_FP32(b[63:0])
+dst[127:32] := a[127:32]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="CVTSD2SS" xed="CVTSD2SS_XMMss_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtsd_f64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="double" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="m64, xmm" name="MOVSD" xed="MOVSD_XMM_MEMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtss_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP32_To_FP64(b[31:0])
+dst[127:64] := a[127:64]
+dst[MAX:128] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="CVTSS2SD" xed="CVTSS2SD_XMMsd_XMMss" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttpd_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="CVTTPD2DQ" xed="CVTTPD2DQ_XMMdq_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsd_si32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])
+	</operation>
+	<instruction form="r32, xmm" name="CVTTSD2SI" xed="CVTTSD2SI_GPR32d_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsd_si64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
+	</operation>
+	<instruction form="r64, xmm" name="CVTTSD2SI" xed="CVTTSD2SI_GPR64q_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttsd_si64x" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
+	<operation>
+dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
+	</operation>
+	<instruction form="r64, xmm" name="CVTTSD2SI" xed="CVTTSD2SI_GPR64q_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtps_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="CVTPS2DQ" xed="CVTPS2DQ_XMMdq_XMMps" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttps_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="CVTTPS2DQ" xed="CVTTPS2DQ_XMMdq_XMMps" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtpd_pi32" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
+ENDFOR
+	</operation>
+	<instruction form="mm, xmm" name="CVTPD2PI" xed="CVTPD2PI_MMXq_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvttpd_pi32" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 32*j
+	k := 64*j
+	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
+ENDFOR
+	</operation>
+	<instruction form="mm, xmm" name="CVTTPD2PI" xed="CVTTPD2PI_MMXq_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_epi64" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="e1" />
+	<parameter etype="UI64" type="__m64" varname="e0" />
+	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[63:0] := e0
+dst[127:64] := e1
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_epi64x" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="e1" />
+	<parameter etype="UI64" type="__int64" varname="e0" />
+	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[63:0] := e0
+dst[127:64] := e1
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_epi32" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="e3" />
+	<parameter etype="UI32" type="int" varname="e2" />
+	<parameter etype="UI32" type="int" varname="e1" />
+	<parameter etype="UI32" type="int" varname="e0" />
+	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[31:0] := e0
+dst[63:32] := e1
+dst[95:64] := e2
+dst[127:96] := e3
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_epi16" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="e7" />
+	<parameter etype="UI16" type="short" varname="e6" />
+	<parameter etype="UI16" type="short" varname="e5" />
+	<parameter etype="UI16" type="short" varname="e4" />
+	<parameter etype="UI16" type="short" varname="e3" />
+	<parameter etype="UI16" type="short" varname="e2" />
+	<parameter etype="UI16" type="short" varname="e1" />
+	<parameter etype="UI16" type="short" varname="e0" />
+	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[15:0] := e0
+dst[31:16] := e1
+dst[47:32] := e2
+dst[63:48] := e3
+dst[79:64] := e4
+dst[95:80] := e5
+dst[111:96] := e6
+dst[127:112] := e7
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_epi8" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="char" varname="e15" />
+	<parameter etype="UI8" type="char" varname="e14" />
+	<parameter etype="UI8" type="char" varname="e13" />
+	<parameter etype="UI8" type="char" varname="e12" />
+	<parameter etype="UI8" type="char" varname="e11" />
+	<parameter etype="UI8" type="char" varname="e10" />
+	<parameter etype="UI8" type="char" varname="e9" />
+	<parameter etype="UI8" type="char" varname="e8" />
+	<parameter etype="UI8" type="char" varname="e7" />
+	<parameter etype="UI8" type="char" varname="e6" />
+	<parameter etype="UI8" type="char" varname="e5" />
+	<parameter etype="UI8" type="char" varname="e4" />
+	<parameter etype="UI8" type="char" varname="e3" />
+	<parameter etype="UI8" type="char" varname="e2" />
+	<parameter etype="UI8" type="char" varname="e1" />
+	<parameter etype="UI8" type="char" varname="e0" />
+	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
+	<operation>
+dst[7:0] := e0
+dst[15:8] := e1
+dst[23:16] := e2
+dst[31:24] := e3
+dst[39:32] := e4
+dst[47:40] := e5
+dst[55:48] := e6
+dst[63:56] := e7
+dst[71:64] := e8
+dst[79:72] := e9
+dst[87:80] := e10
+dst[95:88] := e11
+dst[103:96] := e12
+dst[111:104] := e13
+dst[119:112] := e14
+dst[127:120] := e15
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_epi64" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_epi64x" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__int64" varname="a" />
+	<description>Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_epi32" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="a" />
+	<description>Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastd".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := a[31:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_epi16" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="a" />
+	<description>Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate "vpbroadcastw".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := a[15:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_epi8" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="char" varname="a" />
+	<description>Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastb".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := a[7:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_epi64" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="e1" />
+	<parameter etype="UI64" type="__m64" varname="e0" />
+	<description>Set packed 64-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[63:0] := e1
+dst[127:64] := e0
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_epi32" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="int" varname="e3" />
+	<parameter etype="UI32" type="int" varname="e2" />
+	<parameter etype="UI32" type="int" varname="e1" />
+	<parameter etype="UI32" type="int" varname="e0" />
+	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[31:0] := e3
+dst[63:32] := e2
+dst[95:64] := e1
+dst[127:96] := e0
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_epi16" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="short" varname="e7" />
+	<parameter etype="UI16" type="short" varname="e6" />
+	<parameter etype="UI16" type="short" varname="e5" />
+	<parameter etype="UI16" type="short" varname="e4" />
+	<parameter etype="UI16" type="short" varname="e3" />
+	<parameter etype="UI16" type="short" varname="e2" />
+	<parameter etype="UI16" type="short" varname="e1" />
+	<parameter etype="UI16" type="short" varname="e0" />
+	<description>Set packed 16-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[15:0] := e7
+dst[31:16] := e6
+dst[47:32] := e5
+dst[63:48] := e4
+dst[79:64] := e3
+dst[95:80] := e2
+dst[111:96] := e1
+dst[127:112] := e0
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_epi8" sequence="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="char" varname="e15" />
+	<parameter etype="UI8" type="char" varname="e14" />
+	<parameter etype="UI8" type="char" varname="e13" />
+	<parameter etype="UI8" type="char" varname="e12" />
+	<parameter etype="UI8" type="char" varname="e11" />
+	<parameter etype="UI8" type="char" varname="e10" />
+	<parameter etype="UI8" type="char" varname="e9" />
+	<parameter etype="UI8" type="char" varname="e8" />
+	<parameter etype="UI8" type="char" varname="e7" />
+	<parameter etype="UI8" type="char" varname="e6" />
+	<parameter etype="UI8" type="char" varname="e5" />
+	<parameter etype="UI8" type="char" varname="e4" />
+	<parameter etype="UI8" type="char" varname="e3" />
+	<parameter etype="UI8" type="char" varname="e2" />
+	<parameter etype="UI8" type="char" varname="e1" />
+	<parameter etype="UI8" type="char" varname="e0" />
+	<description>Set packed 8-bit integers in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[7:0] := e15
+dst[15:8] := e14
+dst[23:16] := e13
+dst[31:24] := e12
+dst[39:32] := e11
+dst[47:40] := e10
+dst[55:48] := e9
+dst[63:56] := e8
+dst[71:64] := e7
+dst[79:72] := e6
+dst[87:80] := e5
+dst[95:88] := e4
+dst[103:96] := e3
+dst[111:104] := e2
+dst[119:112] := e1
+dst[127:120] := e0
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setzero_si128" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<description>Return vector of type __m128i with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="PXOR" xed="PXOR_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_sd" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="a" />
+	<description>Copy double-precision (64-bit) floating-point element "a" to the lower element of "dst", and zero the upper element.</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := 0
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set1_pd" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="a" />
+	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_pd1" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="a" />
+	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := a[63:0]
+ENDFOR
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_set_pd" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="e1" />
+	<parameter etype="FP64" type="double" varname="e0" />
+	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.</description>
+	<operation>
+dst[63:0] := e0
+dst[127:64] := e1
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setr_pd" sequence="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="double" varname="e1" />
+	<parameter etype="FP64" type="double" varname="e0" />
+	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
+	<operation>
+dst[63:0] := e1
+dst[127:64] := e0
+	</operation>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_setzero_pd" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter type="void" />
+	<description>Return vector of type __m128d with all elements set to zero.</description>
+	<operation>
+dst[MAX:0] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="XORPD" xed="XORPD_XMMxuq_XMMxuq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Set</category>
+	</intrinsic>
+	<intrinsic name="_mm_movepi64_pi64" tech="SSE_ALL">
+	<return etype="FP32" type="__m64" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Copy the lower 64-bit integer in "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+	</operation>
+	<instruction form="mm, xmm" name="MOVDQ2Q" xed="MOVDQ2Q_MMXq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_packs_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI8" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := Saturate8(a[15:0])
+dst[15:8] := Saturate8(a[31:16])
+dst[23:16] := Saturate8(a[47:32])
+dst[31:24] := Saturate8(a[63:48])
+dst[39:32] := Saturate8(a[79:64])
+dst[47:40] := Saturate8(a[95:80])
+dst[55:48] := Saturate8(a[111:96])
+dst[63:56] := Saturate8(a[127:112])
+dst[71:64] := Saturate8(b[15:0])
+dst[79:72] := Saturate8(b[31:16])
+dst[87:80] := Saturate8(b[47:32])
+dst[95:88] := Saturate8(b[63:48])
+dst[103:96] := Saturate8(b[79:64])
+dst[111:104] := Saturate8(b[95:80])
+dst[119:112] := Saturate8(b[111:96])
+dst[127:120] := Saturate8(b[127:112])
+	</operation>
+	<instruction form="xmm, xmm" name="PACKSSWB" xed="PACKSSWB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_packs_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[31:0])
+dst[31:16] := Saturate16(a[63:32])
+dst[47:32] := Saturate16(a[95:64])
+dst[63:48] := Saturate16(a[127:96])
+dst[79:64] := Saturate16(b[31:0])
+dst[95:80] := Saturate16(b[63:32])
+dst[111:96] := Saturate16(b[95:64])
+dst[127:112] := Saturate16(b[127:96])
+	</operation>
+	<instruction form="xmm, xmm" name="PACKSSDW" xed="PACKSSDW_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_packus_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
+	<operation>
+dst[7:0] := SaturateU8(a[15:0])
+dst[15:8] := SaturateU8(a[31:16])
+dst[23:16] := SaturateU8(a[47:32])
+dst[31:24] := SaturateU8(a[63:48])
+dst[39:32] := SaturateU8(a[79:64])
+dst[47:40] := SaturateU8(a[95:80])
+dst[55:48] := SaturateU8(a[111:96])
+dst[63:56] := SaturateU8(a[127:112])
+dst[71:64] := SaturateU8(b[15:0])
+dst[79:72] := SaturateU8(b[31:16])
+dst[87:80] := SaturateU8(b[47:32])
+dst[95:88] := SaturateU8(b[63:48])
+dst[103:96] := SaturateU8(b[79:64])
+dst[111:104] := SaturateU8(b[95:80])
+dst[119:112] := SaturateU8(b[111:96])
+dst[127:120] := SaturateU8(b[127:112])
+	</operation>
+	<instruction form="xmm, xmm" name="PACKUSWB" xed="PACKUSWB_XMMdq_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movemask_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="MASK" type="int" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[j] := a[i+7]
+ENDFOR
+dst[MAX:16] := 0
+	</operation>
+	<instruction form="r32, xmm" name="PMOVMSKB" xed="PMOVMSKB_GPR32_XMMdq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movemask_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="MASK" type="int" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF a[i+63]
+		dst[j] := 1
+	ELSE
+		dst[j] := 0
+	FI
+ENDFOR
+dst[MAX:2] := 0
+	</operation>
+	<instruction form="r32, xmm" name="MOVMSKPD" xed="MOVMSKPD_GPR32_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_movpi64_epi64" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m64" varname="a" />
+	<description>Copy the 64-bit integer "a" to the lower element of "dst", and zero the upper element.</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := 0
+	</operation>
+	<instruction form="xmm, mm" name="MOVQ2DQ" xed="MOVQ2DQ_XMMdq_MMXq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_move_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Copy the lower 64-bit integer in "a" to the lower element of "dst", and zero the upper element.</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="MOVQ" xed="MOVQ_XMMdq_XMMq_0F7E" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_move_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := b[63:0]
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="MOVSD" xed="MOVSD_XMM_XMMsd_XMMsd_0F10" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_extract_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="int" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="3" type="int" varname="imm8" />
+	<description>Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".</description>
+	<operation>
+dst[15:0] := (a[127:0] &gt;&gt; (imm8[2:0] * 16))[15:0]
+dst[31:16] := 0
+	</operation>
+	<instruction form="r32, xmm, imm8" name="PEXTRW" xed="PEXTRW_GPR32_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_insert_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="int" varname="i" />
+	<parameter etype="IMM" immwidth="3" type="int" varname="imm8" />
+	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[127:0] := a[127:0]
+sel := imm8[2:0]*16
+dst[sel+15:sel] := i[15:0]
+	</operation>
+	<instruction form="xmm, r32, imm8" name="PINSRW" xed="PINSRW_XMMdq_GPR32_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_shuffle_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+DEFINE SELECT4(src, control) {
+	CASE(control[1:0]) OF
+	0:	tmp[31:0] := src[31:0]
+	1:	tmp[31:0] := src[63:32]
+	2:	tmp[31:0] := src[95:64]
+	3:	tmp[31:0] := src[127:96]
+	ESAC
+	RETURN tmp[31:0]
+}
+dst[31:0] := SELECT4(a[127:0], imm8[1:0])
+dst[63:32] := SELECT4(a[127:0], imm8[3:2])
+dst[95:64] := SELECT4(a[127:0], imm8[5:4])
+dst[127:96] := SELECT4(a[127:0], imm8[7:6])
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PSHUFD" xed="PSHUFD_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_shufflehi_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
+dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
+dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
+dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PSHUFHW" xed="PSHUFHW_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_shufflelo_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
+	<description>Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst".</description>
+	<operation>
+dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
+dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
+dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
+dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PSHUFLW" xed="PSHUFLW_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[71:64] 
+	dst[15:8] := src2[71:64] 
+	dst[23:16] := src1[79:72] 
+	dst[31:24] := src2[79:72] 
+	dst[39:32] := src1[87:80] 
+	dst[47:40] := src2[87:80] 
+	dst[55:48] := src1[95:88] 
+	dst[63:56] := src2[95:88] 
+	dst[71:64] := src1[103:96] 
+	dst[79:72] := src2[103:96] 
+	dst[87:80] := src1[111:104] 
+	dst[95:88] := src2[111:104] 
+	dst[103:96] := src1[119:112] 
+	dst[111:104] := src2[119:112] 
+	dst[119:112] := src1[127:120] 
+	dst[127:120] := src2[127:120] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PUNPCKHBW" xed="PUNPCKHBW_XMMdq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[79:64]
+	dst[31:16] := src2[79:64] 
+	dst[47:32] := src1[95:80] 
+	dst[63:48] := src2[95:80] 
+	dst[79:64] := src1[111:96] 
+	dst[95:80] := src2[111:96] 
+	dst[111:96] := src1[127:112] 
+	dst[127:112] := src2[127:112] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PUNPCKHWD" xed="PUNPCKHWD_XMMdq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[95:64] 
+	dst[63:32] := src2[95:64] 
+	dst[95:64] := src1[127:96] 
+	dst[127:96] := src2[127:96] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PUNPCKHDQ" xed="PUNPCKHDQ_XMMdq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PUNPCKHQDQ" xed="PUNPCKHQDQ_XMMdq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
+	dst[7:0] := src1[7:0] 
+	dst[15:8] := src2[7:0] 
+	dst[23:16] := src1[15:8] 
+	dst[31:24] := src2[15:8] 
+	dst[39:32] := src1[23:16] 
+	dst[47:40] := src2[23:16] 
+	dst[55:48] := src1[31:24] 
+	dst[63:56] := src2[31:24] 
+	dst[71:64] := src1[39:32]
+	dst[79:72] := src2[39:32] 
+	dst[87:80] := src1[47:40] 
+	dst[95:88] := src2[47:40] 
+	dst[103:96] := src1[55:48] 
+	dst[111:104] := src2[55:48] 
+	dst[119:112] := src1[63:56] 
+	dst[127:120] := src2[63:56] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PUNPCKLBW" xed="PUNPCKLBW_XMMdq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
+	dst[15:0] := src1[15:0] 
+	dst[31:16] := src2[15:0] 
+	dst[47:32] := src1[31:16] 
+	dst[63:48] := src2[31:16] 
+	dst[79:64] := src1[47:32] 
+	dst[95:80] := src2[47:32] 
+	dst[111:96] := src1[63:48] 
+	dst[127:112] := src2[63:48] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PUNPCKLWD" xed="PUNPCKLWD_XMMdq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
+	dst[31:0] := src1[31:0] 
+	dst[63:32] := src2[31:0] 
+	dst[95:64] := src1[63:32] 
+	dst[127:96] := src2[63:32] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PUNPCKLDQ" xed="PUNPCKLDQ_XMMdq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="PUNPCKLQDQ" xed="PUNPCKLQDQ_XMMdq_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpackhi_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[127:64] 
+	dst[127:64] := src2[127:64] 
+	RETURN dst[127:0]	
+}
+dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="UNPCKHPD" xed="UNPCKHPD_XMMpd_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_unpacklo_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst".</description>
+	<operation>
+DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
+	dst[63:0] := src1[63:0] 
+	dst[127:64] := src2[63:0] 
+	RETURN dst[127:0]
+}
+dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
+	</operation>
+	<instruction form="xmm, xmm" name="UNPCKLPD" xed="UNPCKLPD_XMMpd_XMMq" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_shuffle_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
+	<description>Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst".</description>
+	<operation>
+dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
+dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="SHUFPD" xed="SHUFPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := SQRT(b[63:0])
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="SQRTSD" xed="SQRTSD_XMMsd_XMMsd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_sqrt_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SQRT(a[i+63:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="SQRTPD" xed="SQRTPD_XMMpd_XMMpd" />
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Elementary Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_castpd_ps" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Cast vector of type __m128d to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castpd_si128" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Cast vector of type __m128d to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castps_pd" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Cast vector of type __m128 to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castps_si128" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Cast vector of type __m128 to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castsi128_pd" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<description>Cast vector of type __m128i to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	<intrinsic name="_mm_castsi128_ps" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Cast vector of type __m128i to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
+	<CPUID>SSE2</CPUID>
+	<header>emmintrin.h</header>
+	<category>Cast</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_addsub_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF ((j &amp; 1) == 0)
+		dst[i+31:i] := a[i+31:i] - b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i] + b[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ADDSUBPS" xed="ADDSUBPS_XMMps_XMMps" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_addsub_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF ((j &amp; 1) == 0)
+		dst[i+63:i] := a[i+63:i] - b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i] + b[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="ADDSUBPD" xed="ADDSUBPD_XMMpd_XMMpd" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hadd_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+	<operation>
+dst[63:0] := a[127:64] + a[63:0]
+dst[127:64] := b[127:64] + b[63:0]
+	</operation>
+	<instruction form="xmm, xmm" name="HADDPD" xed="HADDPD_XMMpd_XMMpd" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hadd_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32] + a[31:0]
+dst[63:32] := a[127:96] + a[95:64]
+dst[95:64] := b[63:32] + b[31:0]
+dst[127:96] := b[127:96] + b[95:64]
+	</operation>
+	<instruction form="xmm, xmm" name="HADDPS" xed="HADDPS_XMMps_XMMps" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hsub_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+	<operation>
+dst[63:0] := a[63:0] - a[127:64]
+dst[127:64] := b[63:0] - b[127:64]
+	</operation>
+	<instruction form="xmm, xmm" name="HSUBPD" xed="HSUBPD_XMMpd_XMMpd" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hsub_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] - a[63:32]
+dst[63:32] := a[95:64] - a[127:96]
+dst[95:64] := b[31:0] - b[63:32]
+dst[127:96] := b[95:64] - b[127:96]
+	</operation>
+	<instruction form="xmm, xmm" name="HSUBPS" xed="HSUBPS_XMMps_XMMps" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_lddqu_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="mem_addr" />
+	<description>Load 128-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm_loadu_si128" when the data crosses a cache line boundary.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="LDDQU" xed="LDDQU_XMMpd_MEMdq" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_loaddup_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
+	<description>Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".</description>
+	<operation>
+dst[63:0] := MEM[mem_addr+63:mem_addr]
+dst[127:64] := MEM[mem_addr+63:mem_addr]
+	</operation>
+	<instruction form="xmm, m64" name="MOVDDUP" xed="MOVDDUP_XMMdq_MEMq" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	<intrinsic name="_mm_movedup_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Duplicate the low double-precision (64-bit) floating-point element from "a", and store the results in "dst".</description>
+	<operation>
+dst[63:0] := a[63:0]
+dst[127:64] := a[63:0]
+	</operation>
+	<instruction form="xmm, xmm" name="MOVDDUP" xed="MOVDDUP_XMMdq_XMMq" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_movehdup_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32] 
+dst[63:32] := a[63:32]
+dst[95:64] := a[127:96] 
+dst[127:96] := a[127:96]
+	</operation>
+	<instruction form="xmm, xmm" name="MOVSHDUP" xed="MOVSHDUP_XMMps_XMMps" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	<intrinsic name="_mm_moveldup_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] 
+dst[63:32] := a[31:0]
+dst[95:64] := a[95:64] 
+dst[127:96] := a[95:64]
+	</operation>
+	<instruction form="xmm, xmm" name="MOVSLDUP" xed="MOVSLDUP_XMMps_XMMps" />
+	<CPUID>SSE3</CPUID>
+	<header>pmmintrin.h</header>
+	<category>Move</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_blend_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF imm8[j]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="BLENDPD" xed="BLENDPD_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_blend_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF imm8[j]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="BLENDPS" xed="BLENDPS_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_blendv_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="FP64" type="__m128d" varname="mask" />
+	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	IF mask[i+63]
+		dst[i+63:i] := b[i+63:i]
+	ELSE
+		dst[i+63:i] := a[i+63:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="BLENDVPD" xed="BLENDVPD_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_blendv_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="FP32" type="__m128" varname="mask" />
+	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF mask[i+31]
+		dst[i+31:i] := b[i+31:i]
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="BLENDVPS" xed="BLENDVPS_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_blendv_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="UI8" type="__m128i" varname="mask" />
+	<description>Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF mask[i+7]
+		dst[i+7:i] := b[i+7:i]
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PBLENDVB" xed="PBLENDVB_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_blend_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Blend packed 16-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF imm8[j]
+		dst[i+15:i] := b[i+15:i]
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PBLENDW" xed="PBLENDW_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_extract_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Extract a single-precision (32-bit) floating-point element from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+dst[31:0] := (a[127:0] &gt;&gt; (imm8[1:0] * 32))[31:0]
+	</operation>
+	<instruction form="r32, xmm, imm8" name="EXTRACTPS" xed="EXTRACTPS_GPR32d_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_extract_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="int" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Extract an 8-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".</description>
+	<operation>
+dst[7:0] := (a[127:0] &gt;&gt; (imm8[3:0] * 8))[7:0]
+dst[31:8] := 0
+	</operation>
+	<instruction form="r32, xmm, imm8" name="PEXTRB" xed="PEXTRB_GPR32d_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_extract_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Extract a 32-bit integer from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+dst[31:0] := (a[127:0] &gt;&gt; (imm8[1:0] * 32))[31:0]
+	</operation>
+	<instruction form="r32, xmm, imm8" name="PEXTRD" xed="PEXTRD_GPR32d_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_extract_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Extract a 64-bit integer from "a", selected with "imm8", and store the result in "dst".</description>
+	<operation>
+dst[63:0] := (a[127:0] &gt;&gt; (imm8[0] * 64))[63:0]
+	</operation>
+	<instruction form="r64, xmm, imm8" name="PEXTRQ" xed="PEXTRQ_GPR64q_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_insert_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Copy "a" to "tmp", then insert a single-precision (32-bit) floating-point element from "b" into "tmp" using the control in "imm8". Store "tmp" to "dst" using the mask in "imm8" (elements are zeroed out when the corresponding bit is set).</description>
+	<operation>
+tmp2[127:0] := a[127:0]
+CASE (imm8[7:6]) OF
+0: tmp1[31:0] := b[31:0]
+1: tmp1[31:0] := b[63:32]
+2: tmp1[31:0] := b[95:64]
+3: tmp1[31:0] := b[127:96]
+ESAC
+CASE (imm8[5:4]) OF
+0: tmp2[31:0] := tmp1[31:0]
+1: tmp2[63:32] := tmp1[31:0]
+2: tmp2[95:64] := tmp1[31:0]
+3: tmp2[127:96] := tmp1[31:0]
+ESAC
+FOR j := 0 to 3
+	i := j*32
+	IF imm8[j%8]
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := tmp2[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="INSERTPS" xed="INSERTPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_insert_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="int" varname="i" />
+	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
+	<description>Copy "a" to "dst", and insert the lower 8-bit integer from "i" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[127:0] := a[127:0]
+sel := imm8[3:0]*8
+dst[sel+7:sel] := i[7:0]
+	</operation>
+	<instruction form="xmm, r32, imm8" name="PINSRB" xed="PINSRB_XMMdq_GPR32d_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_insert_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="int" varname="i" />
+	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
+	<description>Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[127:0] := a[127:0]
+sel := imm8[1:0]*32
+dst[sel+31:sel] := i[31:0]
+	</operation>
+	<instruction form="xmm, r32, imm8" name="PINSRD" xed="PINSRD_XMMdq_GPR32d_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_insert_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__int64" varname="i" />
+	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
+	<description>Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "imm8".</description>
+	<operation>
+dst[127:0] := a[127:0]
+sel := imm8[0]*64
+dst[sel+63:sel] := i[63:0]
+	</operation>
+	<instruction form="xmm, r64, imm8" name="PINSRQ" xed="PINSRQ_XMMdq_GPR64q_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_dp_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Conditionally multiply the packed double-precision (64-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".</description>
+	<operation>
+DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
+	FOR j := 0 to 1
+		i := j*64
+		IF imm8[(4+j)%8]
+			temp[i+63:i] := a[i+63:i] * b[i+63:i]
+		ELSE
+			temp[i+63:i] := 0.0
+		FI
+	ENDFOR
+	
+	sum[63:0] := temp[127:64] + temp[63:0]
+	
+	FOR j := 0 to 1
+		i := j*64
+		IF imm8[j%8]
+			tmpdst[i+63:i] := sum[63:0]
+		ELSE
+			tmpdst[i+63:i] := 0.0
+		FI
+	ENDFOR
+	RETURN tmpdst[127:0]
+}
+dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="DPPD" xed="DPPD_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_dp_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".</description>
+	<operation>
+DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
+	FOR j := 0 to 3
+		i := j*32
+		IF imm8[(4+j)%8]
+			temp[i+31:i] := a[i+31:i] * b[i+31:i]
+		ELSE
+			temp[i+31:i] := 0
+		FI
+	ENDFOR
+	
+	sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0])
+	
+	FOR j := 0 to 3
+		i := j*32
+		IF imm8[j%8]
+			tmpdst[i+31:i] := sum[31:0]
+		ELSE
+			tmpdst[i+31:i] := 0
+		FI
+	ENDFOR
+	RETURN tmpdst[127:0]
+}
+dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="DPPS" xed="DPPS_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mul_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMULDQ" xed="PMULDQ_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mullo_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	tmp[63:0] := a[i+31:i] * b[i+31:i]
+	dst[i+31:i] := tmp[31:0]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMULLD" xed="PMULLD_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mpsadbw_epu8" vexEq="TRUE" tech="SSE_ALL">
+	<category>Miscellaneous</category>
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
+	Eight SADs are performed using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8".</description>
+	<operation>
+DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) {
+	a_offset := imm8[2]*32
+	b_offset := imm8[1:0]*32
+	FOR j := 0 to 7
+		i := j*8
+		k := a_offset+i
+		l := b_offset
+		tmp[i*2+15:i*2] := ABS(Signed(a[k+7:k] - b[l+7:l])) + ABS(Signed(a[k+15:k+8] - b[l+15:l+8])) + \
+		                   ABS(Signed(a[k+23:k+16] - b[l+23:l+16])) + ABS(Signed(a[k+31:k+24] - b[l+31:l+24]))
+	ENDFOR
+	RETURN tmp[127:0]
+}
+dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0])
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="MPSADBW" xed="MPSADBW_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMAXSB" xed="PMAXSB_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMAXSD" xed="PMAXSD_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_epu32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMAXUD" xed="PMAXUD_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_max_epu16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMAXUW" xed="PMAXUW_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMINSB" xed="PMINSB_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMINSD" xed="PMINSD_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_epu32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMINUD" xed="PMINUD_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_min_epu16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<parameter etype="UI16" type="__m128i" varname="b" />
+	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMINUW" xed="PMINUW_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_round_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ROUND(a[i+63:i], rounding)
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDPD" xed="ROUNDPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_floor_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := FLOOR(a[i+63:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDPD" xed="ROUNDPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_ceil_pd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := CEIL(a[i+63:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDPD" xed="ROUNDPD_XMMpd_XMMpd_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_round_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst".
+	[round_note]</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ROUND(a[i+31:i], rounding)
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDPS" xed="ROUNDPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_floor_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := FLOOR(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDPS" xed="ROUNDPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_ceil_ps" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := CEIL(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDPS" xed="ROUNDPS_XMMps_XMMps_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_round_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" using the "rounding" parameter, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
+	[round_note]</description>
+	<operation>
+dst[63:0] := ROUND(b[63:0], rounding)
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDSD" xed="ROUNDSD_XMMq_XMMq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_floor_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" down to an integer value, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := FLOOR(b[63:0])
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDSD" xed="ROUNDSD_XMMq_XMMq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_ceil_sd" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP64" type="__m128d" varname="dst" />
+	<parameter etype="FP64" type="__m128d" varname="a" />
+	<parameter etype="FP64" type="__m128d" varname="b" />
+	<description>Round the lower double-precision (64-bit) floating-point element in "b" up to an integer value, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
+	<operation>
+dst[63:0] := CEIL(b[63:0])
+dst[127:64] := a[127:64]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDSD" xed="ROUNDSD_XMMq_XMMq_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_round_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" using the "rounding" parameter, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
+	[round_note]</description>
+	<operation>
+dst[31:0] := ROUND(b[31:0], rounding)
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDSS" xed="ROUNDSS_XMMd_XMMd_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_floor_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" down to an integer value, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := FLOOR(b[31:0])
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDSS" xed="ROUNDSS_XMMd_XMMd_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_ceil_ss" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="FP32" type="__m128" varname="dst" />
+	<parameter etype="FP32" type="__m128" varname="a" />
+	<parameter etype="FP32" type="__m128" varname="b" />
+	<description>Round the lower single-precision (32-bit) floating-point element in "b" up to an integer value, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
+	<operation>
+dst[31:0] := CEIL(b[31:0])
+dst[127:32] := a[127:32]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="ROUNDSS" xed="ROUNDSS_XMMd_XMMd_IMMb" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_packus_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<category>Miscellaneous</category>
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".</description>
+	<operation>
+dst[15:0] := SaturateU16(a[31:0])
+dst[31:16] := SaturateU16(a[63:32])
+dst[47:32] := SaturateU16(a[95:64])
+dst[63:48] := SaturateU16(a[127:96])
+dst[79:64] := SaturateU16(b[31:0])
+dst[95:80] := SaturateU16(b[63:32])
+dst[111:96] := SaturateU16(b[95:64])
+dst[127:112] := SaturateU16(b[127:96])
+	</operation>
+	<instruction form="xmm, xmm" name="PACKUSDW" xed="PACKUSDW_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi8_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	l := j*16
+	dst[l+15:l] := SignExtend16(a[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVSXBW" xed="PMOVSXBW_XMMdq_XMMq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi8_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 8*j
+	dst[i+31:i] := SignExtend32(a[k+7:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVSXBD" xed="PMOVSXBD_XMMdq_XMMd" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi8_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 8*j
+	dst[i+63:i] := SignExtend64(a[k+7:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVSXBQ" xed="PMOVSXBQ_XMMdq_XMMw" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi16_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 16*j
+	dst[i+31:i] := SignExtend32(a[k+15:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVSXWD" xed="PMOVSXWD_XMMdq_XMMq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi16_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 16*j
+	dst[i+63:i] := SignExtend64(a[k+15:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVSXWQ" xed="PMOVSXWQ_XMMdq_XMMd" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepi32_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI64" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := SignExtend64(a[k+31:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVSXDQ" xed="PMOVSXDQ_XMMdq_XMMq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu8_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	l := j*16
+	dst[l+15:l] := ZeroExtend16(a[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVZXBW" xed="PMOVZXBW_XMMdq_XMMq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu8_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 8*j
+	dst[i+31:i] := ZeroExtend32(a[k+7:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVZXBD" xed="PMOVZXBD_XMMdq_XMMd" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu8_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 8*j
+	dst[i+63:i] := ZeroExtend64(a[k+7:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVZXBQ" xed="PMOVZXBQ_XMMdq_XMMw" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu16_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := 32*j
+	k := 16*j
+	dst[i+31:i] := ZeroExtend32(a[k+15:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVZXWD" xed="PMOVZXWD_XMMdq_XMMq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu16_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 16*j
+	dst[i+63:i] := ZeroExtend64(a[k+15:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVZXWQ" xed="PMOVZXWQ_XMMdq_XMMd" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cvtepu32_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI32" type="__m128i" varname="a" />
+	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := 64*j
+	k := 32*j
+	dst[i+63:i] := ZeroExtend64(a[k+31:k])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMOVZXDQ" xed="PMOVZXDQ_XMMdq_XMMq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Convert</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpeq_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="UI64" type="__m128i" varname="a" />
+	<parameter etype="UI64" type="__m128i" varname="b" />
+	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPEQQ" xed="PCMPEQQ_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_testz_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
+	<operation>
+IF ((a[127:0] AND b[127:0]) == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+IF (((NOT a[127:0]) AND b[127:0]) == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+RETURN ZF
+	</operation>
+	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_testc_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="k" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
+	<operation>
+IF ((a[127:0] AND b[127:0]) == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+IF (((NOT a[127:0]) AND b[127:0]) == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+RETURN CF
+	</operation>
+	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_testnzc_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+	<operation>
+IF ((a[127:0] AND b[127:0]) == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+IF (((NOT a[127:0]) AND b[127:0]) == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+IF (ZF == 0 &amp;&amp; CF == 0)
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_test_all_zeros" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="mask" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and return 1 if the result is zero, otherwise return 0.</description>
+	<operation>
+IF ((a[127:0] AND mask[127:0]) == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+dst := ZF
+	</operation>
+	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_test_mix_ones_zeros" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="mask" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "mask", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
+	<operation>
+IF ((a[127:0] AND mask[127:0]) == 0)
+	ZF := 1
+ELSE
+	ZF := 0
+FI
+IF (((NOT a[127:0]) AND mask[127:0]) == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+IF (ZF == 0 &amp;&amp; CF == 0)
+	dst := 1
+ELSE
+	dst := 0
+FI
+	</operation>
+	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_test_all_ones" sequence="TRUE" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<description>Compute the bitwise NOT of "a" and then AND with a 128-bit vector containing all 1's, and return 1 if the result is zero, otherwise return 0.</description>
+	<operation>
+FOR j := 0 to 127
+	tmp[j] := 1
+ENDFOR
+IF (((NOT a[127:0]) AND tmp[127:0]) == 0)
+	CF := 1
+ELSE
+	CF := 0
+FI
+dst := CF
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPEQD" xed="PCMPEQD_XMMdq_XMMdq" />
+	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Logical</category>
+	</intrinsic>
+	<intrinsic name="_mm_minpos_epu16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="UI16" type="__m128i" varname="a" />
+	<description>Horizontally compute the minimum amongst the packed unsigned 16-bit integers in "a", store the minimum and index in "dst", and zero the remaining bits in "dst".</description>
+	<operation>
+index[2:0] := 0
+min[15:0] := a[15:0]
+FOR j := 0 to 7
+	i := j*16
+	IF a[i+15:i] &lt; min[15:0]
+		index[2:0] := j
+		min[15:0] := a[i+15:i]
+	FI
+ENDFOR
+dst[15:0] := min[15:0]
+dst[18:16] := index[2:0]
+dst[127:19] := 0
+	</operation>
+	<instruction form="xmm, xmm" name="PHMINPOSUW" xed="PHMINPOSUW_XMMdq_XMMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_stream_load_si128" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" memwidth="128" type="void*" varname="mem_addr" />
+	<description>Load 128-bits of integer data from memory into "dst" using a non-temporal memory hint.
+	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
+	<operation>
+dst[127:0] := MEM[mem_addr+127:mem_addr]
+	</operation>
+	<instruction form="xmm, m128" name="MOVNTDQA" xed="MOVNTDQA_XMMdq_MEMdq" />
+	<CPUID>SSE4.1</CPUID>
+	<header>smmintrin.h</header>
+	<category>Load</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_cmpistrm" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated mask in "dst".
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF a[m+size-1:m] == 0
+			aInvalid := 1
+		FI
+		IF b[n+size-1:n] == 0
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+bInvalid := 0
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF b[n+size-1:n] == 0
+				bInvalid := 1
+			FI
+			IF bInvalid // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+IF imm8[6] // byte / word mask
+	FOR i := 0 to UpperBound
+		j := i*size
+		IF IntRes2[i]
+			dst[j+size-1:j] := (imm8[0] ? 0xFF : 0xFFFF)
+		ELSE
+			dst[j+size-1:j] := 0
+		FI
+	ENDFOR
+ELSE // bit mask
+	dst[UpperBound:0] := IntRes2[UpperBound:0]
+	dst[127:UpperBound+1] := 0
+FI
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPISTRM" xed="PCMPISTRM_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpistri" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated index in "dst".
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF a[m+size-1:m] == 0
+			aInvalid := 1
+		FI
+		IF b[n+size-1:n] == 0
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+bInvalid := 0
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF b[n+size-1:n] == 0
+				bInvalid := 1
+			FI
+			IF bInvalid // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+IF imm8[6] // most significant bit
+	tmp := UpperBound
+	dst := tmp
+	DO WHILE ((tmp &gt;= 0) AND a[tmp] == 0)
+		tmp := tmp - 1
+		dst := tmp
+	OD
+ELSE // least significant bit
+	tmp := 0
+	dst := tmp
+	DO WHILE ((tmp &lt;= UpperBound) AND a[tmp] == 0)
+		tmp := tmp + 1
+		dst := tmp
+	OD
+FI
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpistrz" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" hint="TRUE" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if any character in "b" was null, and 0 otherwise.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+bInvalid := 0
+FOR j := 0 to UpperBound
+	n := j*size
+	IF b[n+size-1:n] == 0
+		bInvalid := 1
+	FI
+ENDFOR
+dst := bInvalid
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpistrc" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if the resulting mask was non-zero, and 0 otherwise.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF a[m+size-1:m] == 0
+			aInvalid := 1
+		FI
+		IF b[n+size-1:n] == 0
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+bInvalid := 0
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF b[n+size-1:n] == 0
+				bInvalid := 1
+			FI
+			IF bInvalid // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+dst := (IntRes2 != 0)
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpistrs" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" hint="TRUE" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if any character in "a" was null, and 0 otherwise.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+aInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	IF a[m+size-1:m] == 0
+		aInvalid := 1
+	FI
+ENDFOR
+dst := aInvalid
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpistro" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns bit 0 of the resulting bit mask.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF a[m+size-1:m] == 0
+			aInvalid := 1
+		FI
+		IF b[n+size-1:n] == 0
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+bInvalid := 0
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF b[n+size-1:n] == 0
+				bInvalid := 1
+			FI
+			IF bInvalid // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+dst := IntRes2[0]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpistra" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if "b" did not contain a null character and the resulting mask was zero, and 0 otherwise.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF a[m+size-1:m] == 0
+			aInvalid := 1
+		FI
+		IF b[n+size-1:n] == 0
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+bInvalid := 0
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF b[n+size-1:n] == 0
+				bInvalid := 1
+			FI
+			IF bInvalid // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+dst := (IntRes2 == 0) AND bInvalid
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpestrm" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="M128" type="__m128i" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="int" varname="la" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="int" varname="lb" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated mask in "dst".
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF i == la
+			aInvalid := 1
+		FI
+		IF j == lb
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF i &gt;= lb // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+IF imm8[6] // byte / word mask
+	FOR i := 0 to UpperBound
+		j := i*size
+		IF IntRes2[i]
+			dst[j+size-1:j] := (imm8[0] ? 0xFF : 0xFFFF)
+		ELSE
+			dst[j+size-1:j] := 0
+		FI
+	ENDFOR
+ELSE // bit mask
+	dst[UpperBound:0] := IntRes2[UpperBound:0]
+	dst[127:UpperBound+1] := 0
+FI
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPESTRM" xed="PCMPESTRM_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpestri" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="int" varname="la" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="int" varname="lb" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated index in "dst".
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF i == la
+			aInvalid := 1
+		FI
+		IF j == lb
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF i &gt;= lb // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+IF imm8[6] // most significant bit
+	tmp := UpperBound
+	dst := tmp
+	DO WHILE ((tmp &gt;= 0) AND a[tmp] == 0)
+		tmp := tmp - 1
+		dst := tmp
+	OD
+ELSE // least significant bit
+	tmp := 0
+	dst := tmp
+	DO WHILE ((tmp &lt;= UpperBound) AND a[tmp] == 0)
+		tmp := tmp + 1
+		dst := tmp
+	OD
+FI
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpestrz" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" hint="TRUE" type="__m128i" varname="a" />
+	<parameter etype="UI32" hint="TRUE" type="int" varname="la" />
+	<parameter etype="M128" hint="TRUE" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="int" varname="lb" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if any character in "b" was null, and 0 otherwise.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+dst := (lb &lt;= UpperBound)
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpestrc" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="int" varname="la" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="int" varname="lb" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if the resulting mask was non-zero, and 0 otherwise.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF i == la
+			aInvalid := 1
+		FI
+		IF j == lb
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF i &gt;= lb // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+dst := (IntRes2 != 0)
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpestrs" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" hint="TRUE" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="int" varname="la" />
+	<parameter etype="M128" hint="TRUE" type="__m128i" varname="b" />
+	<parameter etype="UI32" hint="TRUE" type="int" varname="lb" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if any character in "a" was null, and 0 otherwise.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+dst := (la &lt;= UpperBound)
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpestro" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="int" varname="la" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="int" varname="lb" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns bit 0 of the resulting bit mask.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF i == la
+			aInvalid := 1
+		FI
+		IF j == lb
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF i &gt;= lb // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+dst := IntRes2[0]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpestra" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="int" varname="dst" />
+	<parameter etype="M128" type="__m128i" varname="a" />
+	<parameter etype="UI32" type="int" varname="la" />
+	<parameter etype="M128" type="__m128i" varname="b" />
+	<parameter etype="UI32" type="int" varname="lb" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
+	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if "b" did not contain a null character and the resulting mask was zero, and 0 otherwise.
+	[strcmp_note]</description>
+	<operation>
+size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
+UpperBound := (128 / size) - 1
+BoolRes := 0
+// compare all characters
+aInvalid := 0
+bInvalid := 0
+FOR i := 0 to UpperBound
+	m := i*size
+	FOR j := 0 to UpperBound
+		n := j*size
+		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
+		
+		// invalidate characters after EOS
+		IF i == la
+			aInvalid := 1
+		FI
+		IF j == lb
+			bInvalid := 1
+		FI
+		
+		// override comparisons for invalid characters
+		CASE (imm8[3:2]) OF
+		0:  // equal any
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		1:  // ranges
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			FI
+		2:  // equal each
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		3:  // equal ordered
+			IF (!aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 0
+			ELSE IF (aInvalid &amp;&amp; !bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			ELSE IF (aInvalid &amp;&amp; bInvalid)
+				BoolRes.word[i].bit[j] := 1
+			FI
+		ESAC
+	ENDFOR
+ENDFOR
+// aggregate results
+CASE (imm8[3:2]) OF
+0:  // equal any
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
+		ENDFOR
+	ENDFOR
+1:  // ranges
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		FOR j := 0 to UpperBound
+			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
+			j += 2
+		ENDFOR
+	ENDFOR
+2:  // equal each
+	IntRes1 := 0
+	FOR i := 0 to UpperBound
+		IntRes1[i] := BoolRes.word[i].bit[i]
+	ENDFOR
+3:  // equal ordered
+	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
+	FOR i := 0 to UpperBound
+		k := i
+		FOR j := 0 to UpperBound-i
+			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
+			k := k+1
+		ENDFOR
+	ENDFOR
+ESAC
+// optionally negate results
+FOR i := 0 to UpperBound
+	IF imm8[4]
+		IF imm8[5] // only negate valid
+			IF i &gt;= lb // invalid, don't negate
+				IntRes2[i] := IntRes1[i]
+			ELSE // valid, negate
+				IntRes2[i] := -1 XOR IntRes1[i]
+			FI
+		ELSE // negate all
+			IntRes2[i] := -1 XOR IntRes1[i]
+		FI
+	ELSE // don't negate
+		IntRes2[i] := IntRes1[i]
+	FI
+ENDFOR
+// output
+dst := (IntRes2 == 0) AND (lb &gt; UpperBound)
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>String Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_cmpgt_epi64" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI64" type="__m128i" varname="dst" />
+	<parameter etype="SI64" type="__m128i" varname="a" />
+	<parameter etype="SI64" type="__m128i" varname="b" />
+	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*64
+	dst[i+63:i] := ( a[i+63:i] &gt; b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PCMPGTQ" xed="PCMPGTQ_XMMdq_XMMdq" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Compare</category>
+	</intrinsic>
+	<intrinsic name="_mm_crc32_u8" tech="SSE_ALL">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="crc" />
+	<parameter etype="UI8" type="unsigned char" varname="v" />
+	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst".</description>
+	<operation>tmp1[7:0] := v[0:7] // bit reflection
+tmp2[31:0] := crc[0:31] // bit reflection
+tmp3[39:0] := tmp1[7:0] &lt;&lt; 32 
+tmp4[39:0] := tmp2[31:0] &lt;&lt; 8
+tmp5[39:0] := tmp3[39:0] XOR tmp4[39:0]
+tmp6[31:0] := MOD2(tmp5[39:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
+dst[31:0] := tmp6[0:31] // bit reflection
+	</operation>
+	<instruction form="r32, r8" name="CRC32" xed="CRC32_GPRyy_GPR8b" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_crc32_u16" tech="SSE_ALL">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="crc" />
+	<parameter etype="UI16" type="unsigned short" varname="v" />
+	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst".</description>
+	<operation>tmp1[15:0] := v[0:15] // bit reflection
+tmp2[31:0] := crc[0:31] // bit reflection
+tmp3[47:0] := tmp1[15:0] &lt;&lt; 32
+tmp4[47:0] := tmp2[31:0] &lt;&lt; 16
+tmp5[47:0] := tmp3[47:0] XOR tmp4[47:0]
+tmp6[31:0] := MOD2(tmp5[47:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
+dst[31:0] := tmp6[0:31] // bit reflection
+	</operation>
+	<instruction form="r32, r16" name="CRC32" xed="CRC32_GPRyy_GPRv" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_crc32_u32" tech="SSE_ALL">
+	<return etype="UI32" type="unsigned int" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="crc" />
+	<parameter etype="UI32" type="unsigned int" varname="v" />
+	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst".</description>
+	<operation>tmp1[31:0] := v[0:31] // bit reflection
+tmp2[31:0] := crc[0:31] // bit reflection
+tmp3[63:0] := tmp1[31:0] &lt;&lt; 32
+tmp4[63:0] := tmp2[31:0] &lt;&lt; 32
+tmp5[63:0] := tmp3[63:0] XOR tmp4[63:0]
+tmp6[31:0] := MOD2(tmp5[63:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
+dst[31:0] := tmp6[0:31] // bit reflection
+	</operation>
+	<instruction form="r32, r32" name="CRC32" xed="CRC32_GPRyy_GPRv" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm_crc32_u64" tech="SSE_ALL">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI64" type="unsigned __int64" varname="crc" />
+	<parameter etype="UI64" type="unsigned __int64" varname="v" />
+	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst".</description>
+	<operation>tmp1[63:0] := v[0:63] // bit reflection
+tmp2[31:0] := crc[0:31] // bit reflection
+tmp3[95:0] := tmp1[31:0] &lt;&lt; 32
+tmp4[95:0] := tmp2[63:0] &lt;&lt; 64
+tmp5[95:0] := tmp3[95:0] XOR tmp4[95:0]
+tmp6[31:0] := MOD2(tmp5[95:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
+dst[31:0] := tmp6[0:31] // bit reflection
+	</operation>
+	<instruction form="r64, r64" name="CRC32" xed="CRC32_GPRyy_GPRv" />
+	<CPUID>SSE4.2</CPUID>
+	<header>nmmintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm_abs_pi8" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="SI8" type="__m64" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	dst[i+7:i] := ABS(Int(a[i+7:i]))
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PABSB" xed="PABSB_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_abs_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	dst[i+7:i] := ABS(a[i+7:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PABSB" xed="PABSB_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_abs_pi16" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := ABS(Int(a[i+15:i]))
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PABSW" xed="PABSW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_abs_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := ABS(a[i+15:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PABSW" xed="PABSW_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_abs_pi32" tech="SSE_ALL">
+	<return etype="UI32" type="__m64" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	dst[i+31:i] := ABS(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PABSD" xed="PABSD_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_abs_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	dst[i+31:i] := ABS(a[i+31:i])
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PABSD" xed="PABSD_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Special Math Functions</category>
+	</intrinsic>
+	<intrinsic name="_mm_shuffle_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF b[i+7] == 1
+		dst[i+7:i] := 0
+	ELSE
+		index[3:0] := b[i+3:i]
+		dst[i+7:i] := a[index*8+7:index*8]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSHUFB" xed="PSHUFB_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_shuffle_pi8" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	IF b[i+7] == 1
+		dst[i+7:i] := 0
+	ELSE
+		index[2:0] := b[i+2:i]
+		dst[i+7:i] := a[index*8+7:index*8]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSHUFB" xed="PSHUFB_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Swizzle</category>
+	</intrinsic>
+	<intrinsic name="_mm_alignr_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="UI8" type="__m128i" varname="b" />
+	<parameter etype="IMM" immwidth="5" type="int" varname="imm8" />
+	<description>Concatenate 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
+	<operation>
+tmp[255:0] := ((a[127:0] &lt;&lt; 128)[255:0] OR b[127:0]) &gt;&gt; (imm8*8)
+dst[127:0] := tmp[127:0]
+	</operation>
+	<instruction form="xmm, xmm, imm8" name="PALIGNR" xed="PALIGNR_XMMdq_XMMdq_IMMb" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_alignr_pi8" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="UI8" type="__m64" varname="b" />
+	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
+	<description>Concatenate 8-byte blocks in "a" and "b" into a 16-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
+	<operation>
+tmp[127:0] := ((a[63:0] &lt;&lt; 64)[127:0] OR b[63:0]) &gt;&gt; (imm8*8)
+dst[63:0] := tmp[63:0]
+	</operation>
+	<instruction form="mm, mm, imm8" name="PALIGNR" xed="PALIGNR_MMXq_MMXq_IMMb" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_mm_hadd_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := a[31:16] + a[15:0]
+dst[31:16] := a[63:48] + a[47:32]
+dst[47:32] := a[95:80] + a[79:64]
+dst[63:48] := a[127:112] + a[111:96]
+dst[79:64] := b[31:16] + b[15:0]
+dst[95:80] := b[63:48] + b[47:32]
+dst[111:96] := b[95:80] + b[79:64]
+dst[127:112] := b[127:112] + b[111:96]
+	</operation>
+	<instruction form="xmm, xmm" name="PHADDW" xed="PHADDW_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hadds_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[31:16] + a[15:0])
+dst[31:16] := Saturate16(a[63:48] + a[47:32])
+dst[47:32] := Saturate16(a[95:80] + a[79:64])
+dst[63:48] := Saturate16(a[127:112] + a[111:96])
+dst[79:64] := Saturate16(b[31:16] + b[15:0])
+dst[95:80] := Saturate16(b[63:48] + b[47:32])
+dst[111:96] := Saturate16(b[95:80] + b[79:64])
+dst[127:112] := Saturate16(b[127:112] + b[111:96])
+	</operation>
+	<instruction form="xmm, xmm" name="PHADDSW" xed="PHADDSW_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hadd_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32] + a[31:0]
+dst[63:32] := a[127:96] + a[95:64]
+dst[95:64] := b[63:32] + b[31:0]
+dst[127:96] := b[127:96] + b[95:64]
+	</operation>
+	<instruction form="xmm, xmm" name="PHADDD" xed="PHADDD_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hadd_pi16" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := a[31:16] + a[15:0]
+dst[31:16] := a[63:48] + a[47:32]
+dst[47:32] := b[31:16] + b[15:0]
+dst[63:48] := b[63:48] + b[47:32]
+	</operation>
+	<instruction form="mm, mm" name="PHADDW" xed="PHADDW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hadd_pi32" tech="SSE_ALL">
+	<return etype="SI32" type="__m64" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
+	<operation>
+dst[31:0] := a[63:32] + a[31:0]
+dst[63:32] := b[63:32] + b[31:0]
+	</operation>
+	<instruction form="mm, mm" name="PHADDW" xed="PHADDW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hadds_pi16" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[31:16] + a[15:0])
+dst[31:16] := Saturate16(a[63:48] + a[47:32])
+dst[47:32] := Saturate16(b[31:16] + b[15:0])
+dst[63:48] := Saturate16(b[63:48] + b[47:32])
+	</operation>
+	<instruction form="mm, mm" name="PHADDSW" xed="PHADDSW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hsub_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := a[15:0] - a[31:16]
+dst[31:16] := a[47:32] - a[63:48]
+dst[47:32] := a[79:64] - a[95:80]
+dst[63:48] := a[111:96] - a[127:112]
+dst[79:64] := b[15:0] - b[31:16]
+dst[95:80] := b[47:32] - b[63:48]
+dst[111:96] := b[79:64] - b[95:80]
+dst[127:112] := b[111:96] - b[127:112]
+	</operation>
+	<instruction form="xmm, xmm" name="PHSUBW" xed="PHSUBW_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hsubs_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[15:0] - a[31:16])
+dst[31:16] := Saturate16(a[47:32] - a[63:48])
+dst[47:32] := Saturate16(a[79:64] - a[95:80])
+dst[63:48] := Saturate16(a[111:96] - a[127:112])
+dst[79:64] := Saturate16(b[15:0] - b[31:16])
+dst[95:80] := Saturate16(b[47:32] - b[63:48])
+dst[111:96] := Saturate16(b[79:64] - b[95:80])
+dst[127:112] := Saturate16(b[111:96] - b[127:112])
+	</operation>
+	<instruction form="xmm, xmm" name="PHSUBSW" xed="PHSUBSW_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hsub_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] - a[63:32]
+dst[63:32] := a[95:64] - a[127:96]
+dst[95:64] := b[31:0] - b[63:32]
+dst[127:96] := b[95:64] - b[127:96]
+	</operation>
+	<instruction form="xmm, xmm" name="PHSUBD" xed="PHSUBD_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hsub_pi16" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := a[15:0] - a[31:16]
+dst[31:16] := a[47:32] - a[63:48]
+dst[47:32] := b[15:0] - b[31:16]
+dst[63:48] := b[47:32] - b[63:48]
+	</operation>
+	<instruction form="mm, mm" name="PHSUBW" xed="PHSUBW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hsub_pi32" tech="SSE_ALL">
+	<return etype="SI32" type="__m64" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
+	<operation>
+dst[31:0] := a[31:0] - a[63:32]
+dst[63:32] := b[31:0] - b[63:32]
+	</operation>
+	<instruction form="mm, mm" name="PHSUBD" xed="PHSUBD_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_hsubs_pi16" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
+	<operation>
+dst[15:0] := Saturate16(a[15:0] - a[31:16])
+dst[31:16] := Saturate16(a[47:32] - a[63:48])
+dst[47:32] := Saturate16(b[15:0] - b[31:16])
+dst[63:48] := Saturate16(b[47:32] - b[63:48])
+	</operation>
+	<instruction form="mm, mm" name="PHSUBSW" xed="PHSUBSW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maddubs_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="SI16" type="__m128i" varname="dst" />
+	<parameter etype="UI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMADDUBSW" xed="PMADDUBSW_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_maddubs_pi16" tech="SSE_ALL">
+	<return etype="SI16" type="__m64" varname="dst" />
+	<parameter etype="UI8" type="__m64" varname="a" />
+	<parameter etype="SI8" type="__m64" varname="b" />
+	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMADDUBSW" xed="PMADDUBSW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mulhrs_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+	dst[i+15:i] := tmp[16:1]
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PMULHRSW" xed="PMULHRSW_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_mulhrs_pi16" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
+	dst[i+15:i] := tmp[16:1]
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PMULHRSW" xed="PMULHRSW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sign_epi8" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI8" type="__m128i" varname="dst" />
+	<parameter etype="SI8" type="__m128i" varname="a" />
+	<parameter etype="SI8" type="__m128i" varname="b" />
+	<description>Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 15
+	i := j*8
+	IF b[i+7:i] &lt; 0
+		dst[i+7:i] := -(a[i+7:i])
+	ELSE IF b[i+7:i] == 0
+		dst[i+7:i] := 0
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSIGNB" xed="PSIGNB_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sign_epi16" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI16" type="__m128i" varname="dst" />
+	<parameter etype="SI16" type="__m128i" varname="a" />
+	<parameter etype="SI16" type="__m128i" varname="b" />
+	<description>Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*16
+	IF b[i+15:i] &lt; 0
+		dst[i+15:i] := -(a[i+15:i])
+	ELSE IF b[i+15:i] == 0
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSIGNW" xed="PSIGNW_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sign_epi32" vexEq="TRUE" tech="SSE_ALL">
+	<return etype="UI32" type="__m128i" varname="dst" />
+	<parameter etype="SI32" type="__m128i" varname="a" />
+	<parameter etype="SI32" type="__m128i" varname="b" />
+	<description>Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*32
+	IF b[i+31:i] &lt; 0
+		dst[i+31:i] := -(a[i+31:i])
+	ELSE IF b[i+31:i] == 0
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="xmm, xmm" name="PSIGND" xed="PSIGND_XMMdq_XMMdq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sign_pi8" tech="SSE_ALL">
+	<return etype="UI8" type="__m64" varname="dst" />
+	<parameter etype="SI8" type="__m64" varname="a" />
+	<parameter etype="SI8" type="__m64" varname="b" />
+	<description>Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 7
+	i := j*8
+	IF b[i+7:i] &lt; 0
+		dst[i+7:i] := -(a[i+7:i])
+	ELSE IF b[i+7:i] == 0
+		dst[i+7:i] := 0
+	ELSE
+		dst[i+7:i] := a[i+7:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSIGNB" xed="PSIGNB_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sign_pi16" tech="SSE_ALL">
+	<return etype="UI16" type="__m64" varname="dst" />
+	<parameter etype="SI16" type="__m64" varname="a" />
+	<parameter etype="SI16" type="__m64" varname="b" />
+	<description>Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 3
+	i := j*16
+	IF b[i+15:i] &lt; 0
+		dst[i+15:i] := -(a[i+15:i])
+	ELSE IF b[i+15:i] == 0
+		dst[i+15:i] := 0
+	ELSE
+		dst[i+15:i] := a[i+15:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSIGNW" xed="PSIGNW_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	<intrinsic name="_mm_sign_pi32" tech="SSE_ALL">
+	<return etype="UI32" type="__m64" varname="dst" />
+	<parameter etype="SI32" type="__m64" varname="a" />
+	<parameter etype="SI32" type="__m64" varname="b" />
+	<description>Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
+	<operation>
+FOR j := 0 to 1
+	i := j*32
+	IF b[i+31:i] &lt; 0
+		dst[i+31:i] := -(a[i+31:i])
+	ELSE IF b[i+31:i] == 0
+		dst[i+31:i] := 0
+	ELSE
+		dst[i+31:i] := a[i+31:i]
+	FI
+ENDFOR
+	</operation>
+	<instruction form="mm, mm" name="PSIGND" xed="PSIGND_MMXq_MMXq" />
+	<CPUID>SSSE3</CPUID>
+	<header>tmmintrin.h</header>
+	<category>Arithmetic</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_rdtsc" tech="Other">
+	<return etype="UI64" type="__int64" varname="dst" />
+	<parameter type="void" />
+	<description>Copy the current 64-bit value of the processor's time-stamp counter into "dst".</description>
+	<operation>dst[63:0] := TimeStampCounter
+	</operation>
+	<instruction name="RDTSC" xed="RDTSC" />
+	<CPUID>TSC</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_xsusldtrk" tech="Other">
+	<return type="void" />
+	<description>Mark the start of a TSX (HLE/RTM) suspend load address tracking region. If this is used inside a transactional region, subsequent loads are not added to the read set of the transaction. If this is used inside a suspend load address tracking region it will cause transaction abort. If this is used outside of a transactional region it behaves like a NOP.</description>
+	<instruction name="XSUSLDTRK" xed="XSUSLDTRK" />
+	<CPUID>TSXLDTRK</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_xresldtrk" tech="Other">
+	<return type="void" />
+	<description>Mark the end of a TSX (HLE/RTM) suspend load address tracking region. If this is used inside a suspend load address tracking region it will end the suspend region and all following load addresses will be added to the transaction read set. If this is used inside an active transaction but not in a suspend region it will cause transaction abort. If this is used outside of a transactional region it behaves like a NOP.</description>
+	<instruction name="XRESLDTRK" xed="XRESLDTRK" />
+	<CPUID>TSXLDTRK</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_clui" tech="Other">
+		<return type="void" />
+		<parameter type="void" />
+		<description>Clear the user interrupt flag (UIF).</description>
+		<instruction name="CLUI" xed="CLUI" />
+	<CPUID>UINTR</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_senduipi" tech="Other">
+		<return type="void" />
+		<parameter type="unsigned __int64" varname="__a" etype="UI64" />
+		<description>Send user interprocessor interrupts specified in unsigned 64-bit integer "__a".</description>
+		<instruction name="SENDUIPI" form="r32" xed="SENDUIPI_GPR32u32" />
+	<CPUID>UINTR</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_stui" tech="Other">
+		<return type="void" />
+		<parameter type="void" />
+		<description>Sets the user interrupt flag (UIF).</description>
+		<instruction name="STUI" xed="STUI" />
+	<CPUID>UINTR</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	<intrinsic name="_testui" tech="Other">
+		<return type="unsigned char" varname="dst" etype="UI8" />
+		<parameter type="void" />
+		<description>Store the current user interrupt flag (UIF) in unsigned 8-bit integer "dst".</description>
+		<instruction name="TESTUI" xed="TESTUI" />
+	<CPUID>UINTR</CPUID>
+	<header>immintrin.h</header>
+	<category>General Support</category>
+	</intrinsic>
+	
+<intrinsic name="_urdmsr" tech="Other">
+	<return type="unsigned __int64" etype="UI64"/>
+	<parameter type="unsigned __int64" varname="__A" etype="UI64" />
+	<description>Reads the contents of a 64-bit MSR specified in "__A" into "dst".</description>
+	<operation>DEST := MSR[__A]
+	</operation>
+	<instruction name="URDMSR" form="r64 r64" xed="URDMSR_GPR64u64_GPR64u64" />
+	<CPUID>USER_MSR</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>General Support</category>
+</intrinsic>
+<intrinsic name="_uwrmsr" tech="Other">
+	<return type="void"/>
+	<parameter type="unsigned __int64" varname="__A" etype="UI64" />
+	<parameter type="unsigned __int64" varname="__B" etype="UI64" />
+	<description>Writes the contents of "__B" into the 64-bit MSR specified in "__A".</description>
+	<operation>MSR[__A] := __B
+	</operation>
+	<instruction name="UWRMSR" form="r64 r64" xed="UWRMSR_GPR64u64_GPR64u64" />
+	<CPUID>USER_MSR</CPUID>
+	<header>x86gprintrin.h</header>
+	<category>General Support</category>
+</intrinsic>
+<intrinsic name="_mm256_aesenclast_epi128" tech="Other">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="M128" type="__m256i" varname="RoundKey" />
+	<description>Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
+	<operation>FOR j := 0 to 1
+	i := j*128
+	a[i+127:i] := ShiftRows(a[i+127:i])
+	a[i+127:i] := SubBytes(a[i+127:i])
+	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VAESENCLAST" xed="VAESENCLAST_YMMu128_YMMu128_YMMu128" />
+	<CPUID>VAES</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm256_aesenc_epi128" tech="Other">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="M128" type="__m256i" varname="RoundKey" />
+	<description>Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
+	<operation>FOR j := 0 to 1
+	i := j*128
+	a[i+127:i] := ShiftRows(a[i+127:i])
+	a[i+127:i] := SubBytes(a[i+127:i])
+	a[i+127:i] := MixColumns(a[i+127:i])
+	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VAESENC" xed="VAESENC_YMMu128_YMMu128_YMMu128" />
+	<CPUID>VAES</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm256_aesdeclast_epi128" tech="Other">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="M128" type="__m256i" varname="RoundKey" />
+	<description>Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*128
+	a[i+127:i] := InvShiftRows(a[i+127:i])
+	a[i+127:i] := InvSubBytes(a[i+127:i])
+	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VAESDECLAST" xed="VAESDECLAST_YMMu128_YMMu128_YMMu128" />
+	<CPUID>VAES</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	<intrinsic name="_mm256_aesdec_epi128" tech="Other">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="a" />
+	<parameter etype="M128" type="__m256i" varname="RoundKey" />
+	<description>Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
+	<operation>FOR j := 0 to 1
+	i := j*128
+	a[i+127:i] := InvShiftRows(a[i+127:i])
+	a[i+127:i] := InvSubBytes(a[i+127:i])
+	a[i+127:i] := InvMixColumns(a[i+127:i])
+	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm" name="VAESDEC" xed="VAESDEC_YMMu128_YMMu128_YMMu128" />
+	<CPUID>VAES</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Cryptography</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm256_clmulepi64_epi128" tech="Other">
+	<return etype="M128" type="__m256i" varname="dst" />
+	<parameter etype="M128" type="__m256i" varname="b" />
+	<parameter etype="M128" type="__m256i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="Imm8" />
+	<description>Carry-less multiplication of one quadword of
+		'b' by one quadword of 'c', stores
+		the 128-bit result in 'dst'. The immediate 'Imm8' is
+		used to determine which quadwords of 'b'
+		and 'c' should be used.</description>
+	<operation>
+DEFINE PCLMUL128(X,Y) {
+	FOR i := 0 to 63
+		TMP[i] := X[ 0 ] and Y[ i ]
+		FOR j := 1 to i
+			TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ])
+		ENDFOR
+		DEST[ i ] := TMP[ i ]
+	ENDFOR
+	FOR i := 64 to 126
+		TMP[i] := 0
+		FOR j := i - 63 to 63
+			TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ])
+		ENDFOR
+		DEST[ i ] := TMP[ i ]
+	ENDFOR
+	DEST[127] := 0
+	RETURN DEST // 128b vector
+}
+FOR i := 0 to 1
+	IF Imm8[0] == 0
+		TEMP1 := b.m128[i].qword[0]
+	ELSE
+		TEMP1 := b.m128[i].qword[1]
+	FI
+	IF Imm8[4] == 0
+		TEMP2 := c.m128[i].qword[0]
+	ELSE
+		TEMP2 := c.m128[i].qword[1]
+	FI
+	dst.m128[i] := PCLMUL128(TEMP1, TEMP2)
+ENDFOR
+dst[MAX:256] := 0
+	</operation>
+	<instruction form="ymm, ymm, ymm, imm8" name="VPCLMULQDQ" xed="VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512" />
+	<CPUID>VPCLMULQDQ</CPUID>
+	<CPUID>AVX512VL</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_mm512_clmulepi64_epi128" tech="Other">
+	<return etype="M128" type="__m512i" varname="dst" />
+	<parameter etype="M128" type="__m512i" varname="b" />
+	<parameter etype="M128" type="__m512i" varname="c" />
+	<parameter etype="IMM" immwidth="8" type="const int" varname="Imm8" />
+	<description>Carry-less multiplication of one quadword of
+		'b' by one quadword of 'c', stores
+		the 128-bit result in 'dst'. The immediate 'Imm8' is
+		used to determine which quadwords of 'b'
+		and 'c' should be used.</description>
+	<operation>
+DEFINE PCLMUL128(X,Y) {
+	FOR i := 0 to 63
+		TMP[i] := X[ 0 ] and Y[ i ]
+		FOR j := 1 to i
+			TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ])
+		ENDFOR
+		DEST[ i ] := TMP[ i ]
+	ENDFOR
+	FOR i := 64 to 126
+		TMP[i] := 0
+		FOR j := i - 63 to 63
+			TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ])
+		ENDFOR
+		DEST[ i ] := TMP[ i ]
+	ENDFOR
+	DEST[127] := 0
+	RETURN DEST // 128b vector
+}
+FOR i := 0 to 3
+	IF Imm8[0] == 0
+		TEMP1 := b.m128[i].qword[0]
+	ELSE
+		TEMP1 := b.m128[i].qword[1]
+	FI
+	IF Imm8[4] == 0
+		TEMP2 := c.m128[i].qword[0]
+	ELSE
+		TEMP2 := c.m128[i].qword[1]
+	FI
+	dst.m128[i] := PCLMUL128(TEMP1, TEMP2)
+ENDFOR
+dst[MAX:512] := 0
+	</operation>
+	<instruction form="zmm, zmm, zmm, imm8" name="VPCLMULQDQ" xed="VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512" />
+	<CPUID>VPCLMULQDQ</CPUID>
+	<header>immintrin.h</header>
+	<category>Application-Targeted</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_tpause" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="ctrl" />
+	<parameter etype="UI64" type="unsigned __int64" varname="counter" />
+	<description>Directs the processor to enter an implementation-dependent optimized state until the TSC reaches or exceeds the value specified in "counter". Bit 0 of "ctrl" selects between a lower power (cleared) or faster wakeup (set) optimized state. Returns the carry flag (CF). If the processor that executed a UMWAIT instruction wakes due to the expiration of the operating system timelimit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.</description>
+	<instruction form="r32" name="TPAUSE" xed="TPAUSE_GPR32u32" />
+	<CPUID>WAITPKG</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_umwait" tech="Other">
+	<return etype="UI8" type="unsigned char" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="ctrl" />
+	<parameter etype="UI64" type="unsigned __int64" varname="counter" />
+	<description>Directs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The instruction wakes up when the TSC reaches or exceeds the value specified in "counter" (if the monitoring hardware did not trigger beforehand). Bit 0 of "ctrl" selects between a lower power (cleared) or faster wakeup (set) optimized state. Returns the carry flag (CF). If the processor that executed a UMWAIT instruction wakes due to the expiration of the operating system timelimit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.</description>
+	<instruction form="r32" name="UMWAIT" xed="UMWAIT_GPR32" />
+	<CPUID>WAITPKG</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	<intrinsic name="_umonitor" tech="Other">
+	<return type="void" />
+	<parameter type="void*" varname="a" />
+	<description>Sets up a linear address range to be
+		monitored by hardware and activates the
+		monitor. The address range should be a writeback
+		memory caching type. The address is
+		contained in "a".</description>
+	<instruction form="r16/r32/r64" name="UMONITOR" xed="UMONITOR_GPRa" />
+	<CPUID>WAITPKG</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_wbnoinvd" tech="Other">
+	<return type="void" />
+	<parameter type="void" />
+	<description>Write back and do not flush internal caches.
+		Initiate writing-back without flushing of external
+		caches.</description>
+	<instruction name="WBNOINVD" xed="WBNOINVD" />
+	<CPUID>WBNOINVD</CPUID>
+	<header>immintrin.h</header>
+	<category>Miscellaneous</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_xsavec" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
+	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsavec differs from xsave in that it uses compaction and that it may use init optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
+FOR i := 0 to 62
+	IF mask[i]
+		CASE (i) OF
+		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
+		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
+		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
+		ESAC
+		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XSAVEC" xed="XSAVEC_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<CPUID>XSAVEC</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xsavec64" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
+	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsavec differs from xsave in that it uses compaction and that it may use init optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
+FOR i := 0 to 62
+	IF mask[i]
+		CASE (i) OF
+		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
+		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
+		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
+		ESAC
+		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XSAVEC64" xed="XSAVEC64_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<CPUID>XSAVEC</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_xsaveopt" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
+	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. The hardware may optimize the manner in which data is saved. The performance of this instruction will be equal to or better than using the XSAVE instruction.</description>
+	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
+FOR i := 0 to 62
+	IF mask[i]
+		CASE (i) OF
+		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
+		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
+		2: mem_addr.EXT_SAVE_Area2[YMM] := ProcessorState[YMM]
+		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
+		ESAC
+		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XSAVEOPT" xed="XSAVEOPT_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<CPUID>XSAVEOPT</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xsaveopt64" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
+	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. The hardware may optimize the manner in which data is saved. The performance of this instruction will be equal to or better than using the XSAVE64 instruction.</description>
+	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
+FOR i := 0 to 62
+	IF mask[i]
+		CASE (i) OF
+		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
+		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
+		2: mem_addr.EXT_SAVE_Area2[YMM] := ProcessorState[YMM]
+		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
+		ESAC
+		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XSAVEOPT64" xed="XSAVEOPT64_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<CPUID>XSAVEOPT</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_xsaves" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
+	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsaves differs from xsave in that it can save state components corresponding to bits set in IA32_XSS MSR and that it may use the modified optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
+FOR i := 0 to 62
+	IF mask[i]
+		CASE (i) OF
+		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
+		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
+		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
+		ESAC
+		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XSAVES" xed="XSAVES_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<CPUID>XSS</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xsaves64" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
+	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsaves differs from xsave in that it can save state components corresponding to bits set in IA32_XSS MSR and that it may use the modified optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
+FOR i := 0 to 62
+	IF mask[i]
+		CASE (i) OF
+		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
+		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
+		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
+		ESAC
+		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XSAVEC64" xed="XSAVEC64_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<CPUID>XSS</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xrstors" tech="Other">
+	<return type="void" />
+	<parameter type="const void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="rs_mask" />
+	<description>Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". xrstors differs from xrstor in that it can restore state components corresponding to bits set in the IA32_XSS MSR; xrstors cannot restore from an xsave area in which the extended region is in the standard form. State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
+FOR i := 0 to 62
+	IF (rs_mask[i] AND XCR0[i])
+		IF st_mask[i]
+			CASE (i) OF
+			0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
+			1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
+			DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
+			ESAC
+		ELSE
+			// ProcessorExtendedState := Processor Supplied Values
+			CASE (i) OF
+			1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
+			ESAC
+		FI
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XRSTORS" xed="XRSTORS_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<CPUID>XSS</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xrstors64" tech="Other">
+	<return type="void" />
+	<parameter type="const void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="rs_mask" />
+	<description>Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". xrstors differs from xrstor in that it can restore state components corresponding to bits set in the IA32_XSS MSR; xrstors cannot restore from an xsave area in which the extended region is in the standard form. State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
+FOR i := 0 to 62
+	IF (rs_mask[i] AND XCR0[i])
+		IF st_mask[i]
+			CASE (i) OF
+			0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
+			1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
+			DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
+			ESAC
+		ELSE
+			// ProcessorExtendedState := Processor Supplied Values
+			CASE (i) OF
+			1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
+			ESAC
+		FI
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XRSTORS64" xed="XRSTORS64_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<CPUID>XSS</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	
+	
+<intrinsic name="_xgetbv" tech="Other">
+	<return etype="UI64" type="unsigned __int64" varname="dst" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<description>Copy up to 64-bits from the value of the extended control register (XCR) specified by "a" into "dst". Currently only XFEATURE_ENABLED_MASK XCR is supported.</description>
+	<operation>dst[63:0] := XCR[a]
+	</operation>
+	<instruction name="XGETBV" xed="XGETBV" />
+	<CPUID>XSAVE</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xrstor" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="rs_mask" />
+	<description>Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
+FOR i := 0 to 62
+	IF (rs_mask[i] AND XCR0[i])
+		IF st_mask[i]
+			CASE (i) OF
+			0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
+			1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
+			DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
+			ESAC
+		ELSE
+			// ProcessorExtendedState := Processor Supplied Values
+			CASE (i) OF
+			1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
+			ESAC
+		FI
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XRSTOR" xed="XRSTOR_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xrstor64" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="rs_mask" />
+	<description>Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
+FOR i := 0 to 62
+	IF (rs_mask[i] AND XCR0[i])
+		IF st_mask[i]
+			CASE (i) OF
+			0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
+			1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
+			DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
+			ESAC
+		ELSE
+			// ProcessorExtendedState := Processor Supplied Values
+			CASE (i) OF
+			1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
+			ESAC
+		FI
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XRSTOR64" xed="XRSTOR64_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xsave" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
+	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
+FOR i := 0 to 62
+	IF mask[i]
+		CASE (i) OF
+		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
+		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
+		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
+		ESAC
+		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XSAVE" xed="XSAVE_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xsave64" tech="Other">
+	<return type="void" />
+	<parameter type="void *" varname="mem_addr" />
+	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
+	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
+	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
+FOR i := 0 to 62
+	IF mask[i]
+		CASE (i) OF
+		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
+		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
+		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
+		ESAC
+		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
+	FI
+	i := i + 1
+ENDFOR
+	</operation>
+	<instruction form="m8" name="XSAVE64" xed="XSAVE64_MEMmxsave" />
+	<CPUID>XSAVE</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	<intrinsic name="_xsetbv" tech="Other">
+	<return type="void" />
+	<parameter etype="UI32" type="unsigned int" varname="a" />
+	<parameter etype="UI64" type="unsigned __int64" varname="val" />
+	<description>Copy 64-bits from "val" to the extended control register (XCR) specified by "a". Currently only XFEATURE_ENABLED_MASK XCR is supported.</description>
+	<operation>
+XCR[a] := val[63:0]
+	</operation>
+	<instruction name="XSETBV" xed="XSETBV" />
+	<CPUID>XSAVE</CPUID>
+	<header>immintrin.h</header>
+	<category>OS-Targeted</category>
+	</intrinsic>
+	
+	
+</intrinsics_list>
\ No newline at end of file

From 08541d8af5d4f6c8ab32c5dbc6c294b1b952389c Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 5 Aug 2025 21:56:48 +0530
Subject: [PATCH 11/73] fix: update arch flags being sent to the x86
 compilation command

---
 crates/intrinsic-test/src/x86/compile.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index e8c2262b85..8baf581596 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -6,7 +6,7 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
 
     // -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations
     let mut command = CompilationCommandBuilder::new()
-        .add_arch_flags(vec![
+        .add_arch_flags([
             "avx",
             "avx2",
             "avx512f",

From ccdba428e82900e105c098b11d3e98654e669e24 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 5 Aug 2025 23:12:38 +0530
Subject: [PATCH 12/73] fix: set default value for varname and type fields of
 the parameters/return value of an intrinsic

---
 crates/intrinsic-test/src/x86/xml_parser.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index 0b422bddb5..71788785ef 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -39,9 +39,9 @@ struct XMLIntrinsic {
 
 #[derive(Debug, PartialEq, Clone, Deserialize)]
 pub struct Parameter {
-    #[serde(rename = "@varname")]
+    #[serde(rename = "@varname", default)]
     pub var_name: String,
-    #[serde(rename = "@type")]
+    #[serde(rename = "@type", default)]
     pub type_data: String,
     #[serde(rename = "@etype", default)]
     pub etype: String,

From a447a1d88d36471f5d3847ae8e5f33be412f6fb9 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 5 Aug 2025 23:28:46 +0530
Subject: [PATCH 13/73] fix: correcting semantical logic for setting vec_len

---
 crates/intrinsic-test/src/x86/types.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 542d1ad3fa..17980798ea 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -220,7 +220,7 @@ impl X86IntrinsicType {
                     data.vec_len = match str::parse::<u32>(type_processed.as_str()) {
                         // If bit_len is None, vec_len will be None.
                         // Else vec_len will be (num_bits / bit_len).
-                        Ok(num_bits) => data.bit_len.and(Some(num_bits / data.bit_len.unwrap())),
+                        Ok(num_bits) => data.bit_len.and_then(|bit_len| Some(num_bits / bit_len)),
                         Err(_) => None,
                     };
                 }

From 781135b50cf8d583153d8f18aa9c1a10e84c121d Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Fri, 5 Sep 2025 14:11:38 +0530
Subject: [PATCH 14/73] fix: more support for Mask types

---
 .../src/common/intrinsic_helpers.rs              |  5 +++--
 crates/intrinsic-test/src/x86/types.rs           | 15 +++++++++------
 crates/intrinsic-test/src/x86/xml_parser.rs      | 16 +++++++++++++++-
 3 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index 7bc1015a38..7a2a1ecdc9 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -131,7 +131,7 @@ impl IntrinsicType {
         if let Some(bl) = self.bit_len {
             bl
         } else {
-            unreachable!("")
+            unreachable!("{:#?}", self)
         }
     }
 
@@ -222,7 +222,8 @@ impl IntrinsicType {
         match self {
             IntrinsicType {
                 bit_len: Some(bit_len @ (8 | 16 | 32 | 64)),
-                kind: kind @ (TypeKind::Int(_) | TypeKind::Poly | TypeKind::Char(_)),
+                kind:
+                    kind @ (TypeKind::Int(_) | TypeKind::Poly | TypeKind::Char(_) | TypeKind::Mask),
                 simd_len,
                 vec_len,
                 ..
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 17980798ea..cf1c56f04d 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -5,6 +5,7 @@ use itertools::Itertools;
 use regex::Regex;
 
 use super::intrinsic::X86IntrinsicType;
+use crate::common::argument::Argument;
 use crate::common::cli::Language;
 use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind};
 use crate::x86::xml_parser::Parameter;
@@ -18,7 +19,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
 
     fn c_single_vector_type(&self) -> String {
         // matches __m128, __m256 and similar types
-        let re = Regex::new(r"\__m\d+\").unwrap();
+        let re = Regex::new(r"__m\d+").unwrap();
         if re.is_match(self.param.type_data.as_str()) {
             self.param.type_data.clone()
         } else {
@@ -129,8 +130,6 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
 impl X86IntrinsicType {
     fn from_c(s: &str) -> Result<IntrinsicType, String> {
         let mut s_copy = s.to_string();
-        let mut metadata: HashMap<String, String> = HashMap::new();
-        metadata.insert("type".to_string(), s.to_string());
         s_copy = s_copy
             .replace("*", "")
             .replace("_", "")
@@ -196,6 +195,9 @@ impl X86IntrinsicType {
                 let mut etype_processed = param.etype.clone();
                 etype_processed.retain(|c| c.is_numeric());
 
+                let mut type_processed = param.type_data.clone();
+                type_processed.retain(|c| c.is_numeric());
+
                 match str::parse::<u32>(etype_processed.as_str()) {
                     Ok(value) => data.bit_len = Some(value),
                     Err(_) => {
@@ -209,14 +211,16 @@ impl X86IntrinsicType {
                     }
                 }
 
+                if param.type_data.matches("__mmask").next().is_some() {
+                    data.bit_len = str::parse::<u32>(type_processed.as_str()).ok();
+                }
+
                 // then check the param.type and extract numeric part if there are double
                 // underscores. divide this number with bit-len and set this as simd-len.
                 // Only __m<int> types can have a simd-len.
                 if param.type_data.matches("__m").next().is_some()
                     && param.type_data.matches("__mmask").next().is_none()
                 {
-                    let mut type_processed = param.type_data.clone();
-                    type_processed.retain(|c| c.is_numeric());
                     data.vec_len = match str::parse::<u32>(type_processed.as_str()) {
                         // If bit_len is None, vec_len will be None.
                         // Else vec_len will be (num_bits / bit_len).
@@ -235,7 +239,6 @@ impl X86IntrinsicType {
                 // if param.etype == IMM, then it is a constant.
                 // else it stays unchanged.
                 data.constant |= param.etype == "IMM";
-
                 Ok(X86IntrinsicType {
                     data,
                     param: param.clone(),
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index 71788785ef..7465cb72d5 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -3,6 +3,7 @@ use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
 use crate::x86::constraint::map_constraints;
 
+use regex::Regex;
 use serde::{Deserialize, Deserializer};
 use std::path::Path;
 
@@ -96,11 +97,24 @@ fn xml_to_intrinsic(
     if args.iter().any(|elem| elem.is_none()) {
         return Err(Box::from("intrinsic isn't fully supported in this test!"));
     }
-    let args = args
+    let mut args = args
         .into_iter()
         .map(|e| e.unwrap())
         .filter(|arg| arg.ty.ptr || arg.ty.kind != TypeKind::Void)
         .collect::<Vec<_>>();
+
+    let mut args_test = args.iter();
+
+    // if one of the args has etype="MASK" and type="__m<int>d",
+    // then set the bit_len and vec_len accordingly
+    let re = Regex::new(r"__m\d+").unwrap();
+    let is_mask = |arg: &Argument<X86IntrinsicType>| arg.ty.param.etype.as_str() == "MASK";
+    let is_vector = |arg: &Argument<X86IntrinsicType>| re.is_match(arg.ty.param.type_data.as_str());
+    let pos = args_test.position(|arg| is_mask(arg) && is_vector(arg));
+    if let Some(index) = pos {
+        args[index].ty.bit_len = args[0].ty.bit_len;
+    }
+
     let arguments = ArgumentList::<X86IntrinsicType> { args };
 
     if let Err(message) = result {

From a232857aa89ccb28a967ea0e42bb4f68e5dcffa1 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 7 Sep 2025 00:02:28 +0530
Subject: [PATCH 15/73] fix: remove unused imports

---
 crates/intrinsic-test/src/x86/types.rs | 2 --
 1 file changed, 2 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index cf1c56f04d..4d5a0a5b7c 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -1,11 +1,9 @@
-use std::collections::HashMap;
 use std::str::FromStr;
 
 use itertools::Itertools;
 use regex::Regex;
 
 use super::intrinsic::X86IntrinsicType;
-use crate::common::argument::Argument;
 use crate::common::cli::Language;
 use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind};
 use crate::x86::xml_parser::Parameter;

From 71d4636b2d24c4e5842b5891b0afba542a7c78f3 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 7 Sep 2025 16:33:05 +0530
Subject: [PATCH 16/73] feat: implemented print_result_c in the case the target
 type is Mask-based

---
 crates/intrinsic-test/src/x86/intrinsic.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/crates/intrinsic-test/src/x86/intrinsic.rs b/crates/intrinsic-test/src/x86/intrinsic.rs
index 169394b793..a4de1e3bdb 100644
--- a/crates/intrinsic-test/src/x86/intrinsic.rs
+++ b/crates/intrinsic-test/src/x86/intrinsic.rs
@@ -83,6 +83,7 @@ impl IntrinsicDefinition<X86IntrinsicType> for Intrinsic<X86IntrinsicType> {
                     TypeKind::Void => "void".to_string(),
                     TypeKind::Float if self.results().inner_size() == 64 => "double".to_string(),
                     TypeKind::Float if self.results().inner_size() == 32 => "float".to_string(),
+                    TypeKind::Mask => format!("__mmask{}", self.results.bit_len.unwrap()),
                     // TypeKind::Float if self.results().inner_size() == 16 => "float16_t".to_string(),
                     // TypeKind::Int(true) if self.results().inner_size() == 64 => "long".to_string(),
                     // TypeKind::Int(false) if self.results().inner_size() == 64 => "unsigned long".to_string(),

From 372d615fd88378179583be1a88715c7031d7de15 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 7 Sep 2025 23:45:43 +0530
Subject: [PATCH 17/73] feat: implemented get_lane_function for x86

---
 crates/intrinsic-test/src/x86/config.rs | 40 +++++++++++++++++++++++++
 crates/intrinsic-test/src/x86/mod.rs    |  4 +--
 crates/intrinsic-test/src/x86/types.rs  | 24 ++++++++++++++-
 3 files changed, 65 insertions(+), 3 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 427ec183a9..cf831bddd0 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -14,6 +14,46 @@ pub const F16_FORMATTING_DEF: &str = r#"
 struct Hex<T>(T);
  "#;
 
+pub const LANE_FUNCTION_HELPERS: &str = r#"
+int mm512_extract(__m512i m, int vec_len, int bit_len, int index) {
+    int lane_len = 128;
+    int max_major_index = vec_len / lane_len;
+    int max_minor_index = lane_len / bit_len;
+
+    int major_index = index / max_major_index;
+    int minor_index = index % max_minor_index;
+
+    __m128i lane = _mm512_extracti64x2_epi64(m, major_index);
+
+    switch(bit_len){
+        case 8:
+            return _mm_extract_epi8(lane, minor_index);
+        case 16:
+            return _mm_extract_epi16(lane, minor_index);
+        case 32:
+            return _mm_extract_epi32(lane, minor_index);
+        case 64:
+            return _mm_extract_epi64(lane, minor_index);
+    }
+}
+
+int _mm512_extract_intrinsic_test_epi8(__m512i m, int lane) {
+    return mm512_extract(m, 512, 8, lane)
+}
+
+int _mm512_extract_intrinsic_test_epi16(__m512i m, int lane) {
+    return mm512_extract(m, 512, 16, lane)
+}
+
+int mm512_extract_intrinsic_test_epi16(__m512i m, int lane) {
+    return mm512_extract(m, 512, 16, lane)
+}
+
+int mm512_extract_intrinsic_test_epi64(__m512i m, int lane) {
+    return mm512_extract(m, 512, 64, lane)
+}
+"#;
+
 pub const X86_CONFIGURATIONS: &str = r#"
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_bf16))]
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_f16))]
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 5515e68385..514783a3e0 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -17,7 +17,7 @@ use crate::common::gen_rust::{
 use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
 use crate::common::intrinsic_helpers::TypeKind;
 use crate::common::{SupportedArchitectureTest, chunk_info};
-use crate::x86::config::{F16_FORMATTING_DEF, X86_CONFIGURATIONS};
+use crate::x86::config::{F16_FORMATTING_DEF, LANE_FUNCTION_HELPERS, X86_CONFIGURATIONS};
 use config::build_notices;
 use intrinsic::X86IntrinsicType;
 use xml_parser::get_xml_intrinsics;
@@ -137,7 +137,7 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             &mut main_rs,
             chunk_count,
             X86_CONFIGURATIONS,
-            "",
+            LANE_FUNCTION_HELPERS,
             self.intrinsics.iter().map(|i| i.name.as_str()),
         )
         .unwrap();
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 4d5a0a5b7c..6ca151308e 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -121,7 +121,29 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
 
     /// Determines the get lane function for this type.
     fn get_lane_function(&self) -> String {
-        todo!("get_lane_function for X86IntrinsicType needs to be implemented!");
+        let total_vector_bits: Option<u32> = self
+            .vec_len
+            .zip(self.bit_len)
+            .and_then(|(vec_len, bit_len)| Some(vec_len * bit_len));
+
+        match (self.bit_len, total_vector_bits) {
+            (Some(8), Some(128)) => String::from("_mm_extract_epi8"),
+            (Some(16), Some(128)) => String::from("_mm_extract_epi16"),
+            (Some(32), Some(128)) => String::from("_mm_extract_epi32"),
+            (Some(64), Some(128)) => String::from("_mm_extract_epi64"),
+            (Some(8), Some(256)) => String::from("_mm256_extract_epi8"),
+            (Some(16), Some(256)) => String::from("_mm256_extract_epi16"),
+            (Some(32), Some(256)) => String::from("_mm256_extract_epi32"),
+            (Some(64), Some(256)) => String::from("_mm256_extract_epi64"),
+            (Some(8), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi8"),
+            (Some(16), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi16"),
+            (Some(32), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi32"),
+            (Some(64), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi64"),
+            _ => unreachable!(
+                "invalid length for vector argument: {:?}, {:?}",
+                self.bit_len, self.vec_len
+            ),
+        }
     }
 }
 

From a3de32e5e4179bea5086bb694ec428a8586818df Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Mon, 8 Sep 2025 00:47:07 +0530
Subject: [PATCH 18/73] chore: update c_prefix for mask and print_result_c for
 vector type

---
 crates/intrinsic-test/src/common/intrinsic_helpers.rs | 1 +
 crates/intrinsic-test/src/x86/intrinsic.rs            | 1 +
 2 files changed, 2 insertions(+)

diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index 7a2a1ecdc9..1351ca345b 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -75,6 +75,7 @@ impl TypeKind {
             Self::Float => "float",
             Self::Int(Sign::Signed) => "int",
             Self::Int(Sign::Unsigned) => "uint",
+            Self::Mask => "uint",
             Self::Poly => "poly",
             Self::Char(Sign::Signed) => "char",
             _ => unreachable!("Not used: {:#?}", self),
diff --git a/crates/intrinsic-test/src/x86/intrinsic.rs b/crates/intrinsic-test/src/x86/intrinsic.rs
index a4de1e3bdb..d3a01ec227 100644
--- a/crates/intrinsic-test/src/x86/intrinsic.rs
+++ b/crates/intrinsic-test/src/x86/intrinsic.rs
@@ -84,6 +84,7 @@ impl IntrinsicDefinition<X86IntrinsicType> for Intrinsic<X86IntrinsicType> {
                     TypeKind::Float if self.results().inner_size() == 64 => "double".to_string(),
                     TypeKind::Float if self.results().inner_size() == 32 => "float".to_string(),
                     TypeKind::Mask => format!("__mmask{}", self.results.bit_len.unwrap()),
+                    TypeKind::Vector => format!("__m{}i", self.results.bit_len.unwrap()),
                     // TypeKind::Float if self.results().inner_size() == 16 => "float16_t".to_string(),
                     // TypeKind::Int(true) if self.results().inner_size() == 64 => "long".to_string(),
                     // TypeKind::Int(false) if self.results().inner_size() == 64 => "unsigned long".to_string(),

From 13733a718ae75f4a06cb9fb19109fec2c430fe9d Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Mon, 8 Sep 2025 20:02:03 +0530
Subject: [PATCH 19/73] feat: handled extraction for 64-bit vector elements

---
 crates/intrinsic-test/src/x86/config.rs | 5 +++++
 crates/intrinsic-test/src/x86/types.rs  | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index cf831bddd0..bf139e5e53 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -52,6 +52,11 @@ int mm512_extract_intrinsic_test_epi16(__m512i m, int lane) {
 int mm512_extract_intrinsic_test_epi64(__m512i m, int lane) {
     return mm512_extract(m, 512, 64, lane)
 }
+
+int mm64_extract_intrinsic_test_epi32(__m64 m, int lane) {
+    int bit_shift_amount = lane * 32;
+    return _m_to_int(m >> bit_shift_amount);
+}
 "#;
 
 pub const X86_CONFIGURATIONS: &str = r#"
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 6ca151308e..2bb1ecb9f6 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -139,6 +139,8 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             (Some(16), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi16"),
             (Some(32), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi32"),
             (Some(64), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi64"),
+            (Some(16), Some(64)) => String::from("_mm_extract_pi16"),
+            (Some(32), Some(64)) => String::from("mm64_extract_intrinsic_test_epi32"),
             _ => unreachable!(
                 "invalid length for vector argument: {:?}, {:?}",
                 self.bit_len, self.vec_len

From dcca5062be466e5aec3c1e45d154052ac0a3a1e1 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 9 Sep 2025 00:54:50 +0530
Subject: [PATCH 20/73] feat: add 8x8 case for get_lane_function for 64-bit
 vector

---
 crates/intrinsic-test/src/x86/config.rs | 7 +++++++
 crates/intrinsic-test/src/x86/types.rs  | 1 +
 2 files changed, 8 insertions(+)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index bf139e5e53..d0c5981122 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -53,6 +53,13 @@ int mm512_extract_intrinsic_test_epi64(__m512i m, int lane) {
     return mm512_extract(m, 512, 64, lane)
 }
 
+int mm64_extract_intrinsic_test_epi8(__m64 m, int lane) {
+    int real_lane_shift = lane / 2;
+    int real_bit_shift = (lane % 2) * 8;
+    int result = _mm_extract_pi16(m, lane / 2);
+    return (result >> real_bit_shift);
+}
+
 int mm64_extract_intrinsic_test_epi32(__m64 m, int lane) {
     int bit_shift_amount = lane * 32;
     return _m_to_int(m >> bit_shift_amount);
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 2bb1ecb9f6..7e96657977 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -139,6 +139,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             (Some(16), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi16"),
             (Some(32), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi32"),
             (Some(64), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi64"),
+            (Some(8), Some(64)) => String::from("mm64_extract_intrinsic_test_epi8"),
             (Some(16), Some(64)) => String::from("_mm_extract_pi16"),
             (Some(32), Some(64)) => String::from("mm64_extract_intrinsic_test_epi32"),
             _ => unreachable!(

From 180d6f0f6e2d88af5b76b41229c5fafb03e13a88 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 10 Sep 2025 00:00:07 +0530
Subject: [PATCH 21/73] debug: printing self incase print_result_c fails.

---
 crates/intrinsic-test/src/x86/intrinsic.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/intrinsic.rs b/crates/intrinsic-test/src/x86/intrinsic.rs
index d3a01ec227..79f119b0e0 100644
--- a/crates/intrinsic-test/src/x86/intrinsic.rs
+++ b/crates/intrinsic-test/src/x86/intrinsic.rs
@@ -83,8 +83,8 @@ impl IntrinsicDefinition<X86IntrinsicType> for Intrinsic<X86IntrinsicType> {
                     TypeKind::Void => "void".to_string(),
                     TypeKind::Float if self.results().inner_size() == 64 => "double".to_string(),
                     TypeKind::Float if self.results().inner_size() == 32 => "float".to_string(),
-                    TypeKind::Mask => format!("__mmask{}", self.results.bit_len.unwrap()),
-                    TypeKind::Vector => format!("__m{}i", self.results.bit_len.unwrap()),
+                    TypeKind::Mask => format!("__mmask{}", self.results.bit_len.expect(format!("self: {:#?}", self).as_str())),
+                    TypeKind::Vector => format!("__m{}i", self.results.bit_len.expect(format!("self: {:#?}", self).as_str())),
                     // TypeKind::Float if self.results().inner_size() == 16 => "float16_t".to_string(),
                     // TypeKind::Int(true) if self.results().inner_size() == 64 => "long".to_string(),
                     // TypeKind::Int(false) if self.results().inner_size() == 64 => "unsigned long".to_string(),

From 838e925d32c4f0d7edb124e517f935312e5ab7bb Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 10 Sep 2025 11:28:02 +0530
Subject: [PATCH 22/73] chore: update x86 module, removed intrinsicDefinition
 trait, formatting updates

---
 Cargo.lock                                 |   5 +-
 crates/intrinsic-test/src/main.rs          |   1 +
 crates/intrinsic-test/src/x86/config.rs    |  13 +-
 crates/intrinsic-test/src/x86/intrinsic.rs |  90 +----------
 crates/intrinsic-test/src/x86/mod.rs       | 165 ++++-----------------
 crates/intrinsic-test/src/x86/types.rs     |  79 +++++++++-
 6 files changed, 115 insertions(+), 238 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 26a4223271..70f09adf2c 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -998,17 +998,16 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
 
 [[package]]
-<<<<<<< HEAD
 name = "windows_x86_64_msvc"
 version = "0.53.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486"
-=======
+
+[[package]]
 name = "xml-rs"
 version = "0.8.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "6fd8403733700263c6eb89f192880191f1b83e332f7a20371ddcf421c4a337c7"
->>>>>>> 3283a857 (feat: updated intrinsics creation)
 
 [[package]]
 name = "yaml-rust"
diff --git a/crates/intrinsic-test/src/main.rs b/crates/intrinsic-test/src/main.rs
index d780e35160..ed3a50067d 100644
--- a/crates/intrinsic-test/src/main.rs
+++ b/crates/intrinsic-test/src/main.rs
@@ -20,6 +20,7 @@ fn main() {
         | "armv7-unknown-linux-gnueabihf"
         | "aarch64_be-unknown-linux-gnu" => run(ArmArchitectureTest::create(processed_cli_options)),
 
+        "x86_64-unknown-linux-gnu" => run(X86ArchitectureTest::create(processed_cli_options)),
         _ => std::process::exit(0),
     }
 }
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index d0c5981122..f1e9e9932e 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -1,12 +1,7 @@
-pub fn build_notices(line_prefix: &str) -> String {
-    format!(
-        "\
-{line_prefix}This is a transient test file, not intended for distribution. Some aspects of the
-{line_prefix}test are derived from an XML specification, published under the same license as the
-{line_prefix}`intrinsic-test` crate.\n
-"
-    )
-}
+pub const NOTICE: &str = "\
+// This is a transient test file, not intended for distribution. Some aspects of the
+// test are derived from an XML specification, published under the same license as the
+// `intrinsic-test` crate.\n";
 
 // Format f16 values (and vectors containing them) in a way that is consistent with C.
 pub const F16_FORMATTING_DEF: &str = r#"
diff --git a/crates/intrinsic-test/src/x86/intrinsic.rs b/crates/intrinsic-test/src/x86/intrinsic.rs
index 79f119b0e0..1417c51ea1 100644
--- a/crates/intrinsic-test/src/x86/intrinsic.rs
+++ b/crates/intrinsic-test/src/x86/intrinsic.rs
@@ -1,7 +1,4 @@
-use crate::common::argument::ArgumentList;
-use crate::common::indentation::Indentation;
-use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
-use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, TypeKind};
+use crate::common::intrinsic_helpers::IntrinsicType;
 use crate::x86::xml_parser::Parameter;
 use std::ops::{Deref, DerefMut};
 
@@ -24,88 +21,3 @@ impl DerefMut for X86IntrinsicType {
         &mut self.data
     }
 }
-
-impl IntrinsicDefinition<X86IntrinsicType> for Intrinsic<X86IntrinsicType> {
-    fn arguments(&self) -> ArgumentList<X86IntrinsicType> {
-        self.arguments.clone()
-    }
-
-    fn results(&self) -> X86IntrinsicType {
-        self.results.clone()
-    }
-
-    fn name(&self) -> String {
-        self.name.clone()
-    }
-
-    /// Generates a std::cout for the intrinsics results that will match the
-    /// rust debug output format for the return type. The generated line assumes
-    /// there is an int i in scope which is the current pass number.
-    fn print_result_c(&self, indentation: Indentation, additional: &str) -> String {
-        let lanes = if self.results().num_vectors() > 1 {
-            (0..self.results().num_vectors())
-                .map(|vector| {
-                    format!(
-                        r#""{ty}(" << {lanes} << ")""#,
-                        ty = self.results().c_single_vector_type(),
-                        lanes = (0..self.results().num_lanes())
-                            .map(move |idx| -> std::string::String {
-                                format!(
-                                    "{cast}{lane_fn}(__return_value.val[{vector}], {lane})",
-                                    cast = self.results().c_promotion(),
-                                    lane_fn = self.results().get_lane_function(),
-                                    lane = idx,
-                                    vector = vector,
-                                )
-                            })
-                            .collect::<Vec<_>>()
-                            .join(r#" << ", " << "#)
-                    )
-                })
-                .collect::<Vec<_>>()
-                .join(r#" << ", " << "#)
-        } else if self.results().num_lanes() > 1 {
-            (0..self.results().num_lanes())
-                .map(|idx| -> std::string::String {
-                    format!(
-                        "{cast}{lane_fn}(__return_value, {lane})",
-                        cast = self.results().c_promotion(),
-                        lane_fn = self.results().get_lane_function(),
-                        lane = idx
-                    )
-                })
-                .collect::<Vec<_>>()
-                .join(r#" << ", " << "#)
-        } else {
-            format!(
-                "{promote}cast<{cast}>(__return_value)",
-                cast = match self.results.kind() {
-                    TypeKind::Void => "void".to_string(),
-                    TypeKind::Float if self.results().inner_size() == 64 => "double".to_string(),
-                    TypeKind::Float if self.results().inner_size() == 32 => "float".to_string(),
-                    TypeKind::Mask => format!("__mmask{}", self.results.bit_len.expect(format!("self: {:#?}", self).as_str())),
-                    TypeKind::Vector => format!("__m{}i", self.results.bit_len.expect(format!("self: {:#?}", self).as_str())),
-                    // TypeKind::Float if self.results().inner_size() == 16 => "float16_t".to_string(),
-                    // TypeKind::Int(true) if self.results().inner_size() == 64 => "long".to_string(),
-                    // TypeKind::Int(false) if self.results().inner_size() == 64 => "unsigned long".to_string(),
-                    // TypeKind::Int(true) if self.results().inner_size() == 32 => "int".to_string(),
-                    // TypeKind::Int(false) if self.results().inner_size() == 32 => "unsigned int".to_string(),
-                    // TypeKind::Int(true) if self.results().inner_size() == 16 => "short".to_string(),
-                    // TypeKind::Int(false) if self.results().inner_size() == 16 => "unsigned short".to_string(),
-                    _ => self.results.c_scalar_type(),
-                },
-                promote = self.results().c_promotion(),
-            )
-        };
-
-        format!(
-            r#"{indentation}std::cout << "Result {additional}-" << i+1 << ": {ty}" << std::fixed << std::setprecision(150) <<  {lanes} << "{close}" << std::endl;"#,
-            ty = if self.results().is_simd() {
-                format!("{}(", self.results().c_type())
-            } else {
-                String::from("")
-            },
-            close = if self.results.is_simd() { ")" } else { "" },
-        )
-    }
-}
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 514783a3e0..e73ceb5084 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -5,20 +5,12 @@ mod intrinsic;
 mod types;
 mod xml_parser;
 
-use rayon::prelude::*;
-use std::fs::{self, File};
-
+use crate::common::SupportedArchitectureTest;
 use crate::common::cli::ProcessedCli;
 use crate::common::compare::compare_outputs;
-use crate::common::gen_c::{write_main_cpp, write_mod_cpp};
-use crate::common::gen_rust::{
-    compile_rust_programs, write_bin_cargo_toml, write_lib_cargo_toml, write_lib_rs, write_main_rs,
-};
-use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
+use crate::common::compile_c::CppCompilation;
+use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
-use crate::common::{SupportedArchitectureTest, chunk_info};
-use crate::x86::config::{F16_FORMATTING_DEF, LANE_FUNCTION_HELPERS, X86_CONFIGURATIONS};
-use config::build_notices;
 use intrinsic::X86IntrinsicType;
 use xml_parser::get_xml_intrinsics;
 
@@ -28,7 +20,30 @@ pub struct X86ArchitectureTest {
 }
 
 impl SupportedArchitectureTest for X86ArchitectureTest {
-    fn create(cli_options: ProcessedCli) -> Box<Self> {
+    type IntrinsicImpl = X86IntrinsicType;
+
+    fn cli_options(&self) -> &ProcessedCli {
+        &self.cli_options
+    }
+
+    fn intrinsics(&self) -> &[Intrinsic<X86IntrinsicType>] {
+        &self.intrinsics
+    }
+
+    fn cpp_compilation(&self) -> Option<CppCompilation> {
+        compile::build_cpp_compilation(&self.cli_options)
+    }
+
+    const NOTICE: &str = config::NOTICE;
+
+    const PLATFORM_C_HEADERS: &[&str] = &["immintrin.h"];
+    const PLATFORM_C_DEFINITIONS: &str = config::LANE_FUNCTION_HELPERS;
+    const PLATFORM_C_FORWARD_DECLARATIONS: &str = "";
+
+    const PLATFORM_RUST_DEFINITIONS: &str = config::F16_FORMATTING_DEF;
+    const PLATFORM_RUST_CFGS: &str = config::X86_CONFIGURATIONS;
+
+    fn create(cli_options: ProcessedCli) -> Self {
         let intrinsics =
             get_xml_intrinsics(&cli_options.filename).expect("Error parsing input file");
 
@@ -37,7 +52,7 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             // Not sure how we would compare intrinsic that returns void.
             .filter(|i| i.results.kind() != TypeKind::Void)
             .filter(|i| i.results.kind() != TypeKind::BFloat)
-            .filter(|i| i.arguments().args.len() > 0)
+            .filter(|i| i.arguments.args.len() > 0)
             .filter(|i| !i.arguments.iter().any(|a| a.ty.kind() == TypeKind::BFloat))
             // Skip pointers for now, we would probably need to look at the return
             // type to work out how many elements we need to point to.
@@ -47,132 +62,10 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             .collect::<Vec<_>>();
 
         intrinsics.sort_by(|a, b| a.name.cmp(&b.name));
-        Box::new(Self {
+        Self {
             intrinsics: intrinsics,
             cli_options: cli_options,
-        })
-    }
-
-    fn build_c_file(&self) -> bool {
-        let c_target = "x86_64";
-        let platform_headers = &["immintrin.h"];
-
-        let (chunk_size, chunk_count) = chunk_info(self.intrinsics.len());
-
-        let cpp_compiler_wrapped = compile::build_cpp_compilation(&self.cli_options);
-
-        let notice = &build_notices("// ");
-        fs::create_dir_all("c_programs").unwrap();
-        self.intrinsics
-            .par_chunks(chunk_size)
-            .enumerate()
-            .map(|(i, chunk)| {
-                let c_filename = format!("c_programs/mod_{i}.cpp");
-                let mut file = File::create(&c_filename).unwrap();
-                write_mod_cpp(&mut file, notice, c_target, platform_headers, chunk).unwrap();
-
-                // compile this cpp file into a .o file.
-                //
-                // This is done because `cpp_compiler_wrapped` is None when
-                // the --generate-only flag is passed
-                if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
-                    let output = cpp_compiler
-                        .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"))?;
-                    assert!(output.status.success(), "{output:?}");
-                }
-
-                Ok(())
-            })
-            .collect::<Result<(), std::io::Error>>()
-            .unwrap();
-
-        let mut file = File::create("c_programs/main.cpp").unwrap();
-        write_main_cpp(
-            &mut file,
-            c_target,
-            "\n",
-            self.intrinsics.iter().map(|i| i.name.as_str()),
-        )
-        .unwrap();
-
-        // This is done because `cpp_compiler_wrapped` is None when
-        // the --generate-only flag is passed
-        if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
-            // compile this cpp file into a .o file
-            info!("compiling main.cpp");
-            let output = cpp_compiler
-                .compile_object_file("main.cpp", "intrinsic-test-programs.o")
-                .unwrap();
-            assert!(output.status.success(), "{output:?}");
-
-            let object_files = (0..chunk_count)
-                .map(|i| format!("mod_{i}.o"))
-                .chain(["intrinsic-test-programs.o".to_owned()]);
-
-            let output = cpp_compiler
-                .link_executable(object_files, "intrinsic-test-programs")
-                .unwrap();
-            assert!(output.status.success(), "{output:?}");
         }
-
-        true
-    }
-
-    fn build_rust_file(&self) -> bool {
-        std::fs::create_dir_all("rust_programs/src").unwrap();
-
-        let architecture = if self.cli_options.target.contains("v7") {
-            "arm"
-        } else {
-            "aarch64"
-        };
-
-        let (chunk_size, chunk_count) = chunk_info(self.intrinsics.len());
-
-        let mut cargo = File::create("rust_programs/Cargo.toml").unwrap();
-        write_bin_cargo_toml(&mut cargo, chunk_count).unwrap();
-
-        let mut main_rs = File::create("rust_programs/src/main.rs").unwrap();
-        write_main_rs(
-            &mut main_rs,
-            chunk_count,
-            X86_CONFIGURATIONS,
-            LANE_FUNCTION_HELPERS,
-            self.intrinsics.iter().map(|i| i.name.as_str()),
-        )
-        .unwrap();
-
-        let target = &self.cli_options.target;
-        let toolchain = self.cli_options.toolchain.as_deref();
-        let linker = self.cli_options.linker.as_deref();
-
-        let notice = &build_notices("// ");
-        self.intrinsics
-            .par_chunks(chunk_size)
-            .enumerate()
-            .map(|(i, chunk)| {
-                std::fs::create_dir_all(format!("rust_programs/mod_{i}/src"))?;
-
-                let rust_filename = format!("rust_programs/mod_{i}/src/lib.rs");
-                trace!("generating `{rust_filename}`");
-                let mut file = File::create(rust_filename)?;
-
-                let cfg = X86_CONFIGURATIONS;
-                let definitions = F16_FORMATTING_DEF;
-                write_lib_rs(&mut file, architecture, notice, cfg, definitions, chunk)?;
-
-                let toml_filename = format!("rust_programs/mod_{i}/Cargo.toml");
-                trace!("generating `{toml_filename}`");
-                let mut file = File::create(toml_filename).unwrap();
-
-                write_lib_cargo_toml(&mut file, &format!("mod_{i}"))?;
-
-                Ok(())
-            })
-            .collect::<Result<(), std::io::Error>>()
-            .unwrap();
-
-        compile_rust_programs(toolchain, target, linker)
     }
 
     fn compare_outputs(&self) -> bool {
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 7e96657977..bb7ea59dbe 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -5,6 +5,7 @@ use regex::Regex;
 
 use super::intrinsic::X86IntrinsicType;
 use crate::common::cli::Language;
+use crate::common::indentation::Indentation;
 use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind};
 use crate::x86::xml_parser::Parameter;
 
@@ -116,7 +117,83 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             // then typecast it.
             format!("({type_value})")
         }
-        // Look for edge cases (constexpr, literal, etc)
+    }
+
+    /// Generates a std::cout for the intrinsics results that will match the
+    /// rust debug output format for the return type. The generated line assumes
+    /// there is an int i in scope which is the current pass number.
+    fn print_result_c(&self, indentation: Indentation, additional: &str) -> String {
+        let lanes = if self.num_vectors() > 1 {
+            (0..self.num_vectors())
+                .map(|vector| {
+                    format!(
+                        r#""{ty}(" << {lanes} << ")""#,
+                        ty = self.c_single_vector_type(),
+                        lanes = (0..self.num_lanes())
+                            .map(move |idx| -> std::string::String {
+                                format!(
+                                    "{cast}{lane_fn}(__return_value.val[{vector}], {lane})",
+                                    cast = self.c_promotion(),
+                                    lane_fn = self.get_lane_function(),
+                                    lane = idx,
+                                    vector = vector,
+                                )
+                            })
+                            .collect::<Vec<_>>()
+                            .join(r#" << ", " << "#)
+                    )
+                })
+                .collect::<Vec<_>>()
+                .join(r#" << ", " << "#)
+        } else if self.num_lanes() > 1 {
+            (0..self.num_lanes())
+                .map(|idx| -> std::string::String {
+                    format!(
+                        "{cast}{lane_fn}(__return_value, {lane})",
+                        cast = self.c_promotion(),
+                        lane_fn = self.get_lane_function(),
+                        lane = idx
+                    )
+                })
+                .collect::<Vec<_>>()
+                .join(r#" << ", " << "#)
+        } else {
+            format!(
+                "{promote}cast<{cast}>(__return_value)",
+                cast = match self.kind() {
+                    TypeKind::Void => "void".to_string(),
+                    TypeKind::Float if self.inner_size() == 64 => "double".to_string(),
+                    TypeKind::Float if self.inner_size() == 32 => "float".to_string(),
+                    TypeKind::Mask => format!(
+                        "__mmask{}",
+                        self.bit_len.expect(format!("self: {:#?}", self).as_str())
+                    ),
+                    TypeKind::Vector => format!(
+                        "__m{}i",
+                        self.bit_len.expect(format!("self: {:#?}", self).as_str())
+                    ),
+                    // TypeKind::Float if self.results().inner_size() == 16 => "float16_t".to_string(),
+                    // TypeKind::Int(true) if self.results().inner_size() == 64 => "long".to_string(),
+                    // TypeKind::Int(false) if self.results().inner_size() == 64 => "unsigned long".to_string(),
+                    // TypeKind::Int(true) if self.results().inner_size() == 32 => "int".to_string(),
+                    // TypeKind::Int(false) if self.results().inner_size() == 32 => "unsigned int".to_string(),
+                    // TypeKind::Int(true) if self.results().inner_size() == 16 => "short".to_string(),
+                    // TypeKind::Int(false) if self.results().inner_size() == 16 => "unsigned short".to_string(),
+                    _ => self.c_scalar_type(),
+                },
+                promote = self.c_promotion(),
+            )
+        };
+
+        format!(
+            r#"{indentation}std::cout << "Result {additional}-" << i+1 << ": {ty}" << std::fixed << std::setprecision(150) <<  {lanes} << "{close}" << std::endl;"#,
+            ty = if self.is_simd() {
+                format!("{}(", self.c_type())
+            } else {
+                String::from("")
+            },
+            close = if self.is_simd() { ")" } else { "" },
+        )
     }
 
     /// Determines the get lane function for this type.

From e3ad0e474dab06be830a837f20d790feab48113e Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sat, 13 Sep 2025 23:04:08 +0530
Subject: [PATCH 23/73] fixed errors that caused errors with cpp file
 generation (un-handled edge cases for Vector and Mask types)

---
 crates/intrinsic-test/src/common/cli.rs       |  4 +-
 crates/intrinsic-test/src/common/gen_rust.rs  |  6 +--
 .../src/common/intrinsic_helpers.rs           | 44 +++++++++++++++----
 crates/intrinsic-test/src/common/mod.rs       |  9 ++++
 crates/intrinsic-test/src/x86/mod.rs          | 19 --------
 crates/intrinsic-test/src/x86/types.rs        | 20 +++++++++
 6 files changed, 70 insertions(+), 32 deletions(-)

diff --git a/crates/intrinsic-test/src/common/cli.rs b/crates/intrinsic-test/src/common/cli.rs
index beae6a4b04..f8125128ea 100644
--- a/crates/intrinsic-test/src/common/cli.rs
+++ b/crates/intrinsic-test/src/common/cli.rs
@@ -44,7 +44,9 @@ pub struct Cli {
     pub generate_only: bool,
 
     /// Pass a target the test suite
-    #[arg(long, default_value_t = String::from("armv7-unknown-linux-gnueabihf"))]
+    /// x86_64-unknown-linux-gnu
+    /// armv7-unknown-linux-gnueabihf
+    #[arg(long, default_value_t = String::from("x86_64-unknown-linux-gnu"))]
     pub target: String,
 
     /// Set the linker
diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index d659cbc4aa..e97b745c59 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -191,7 +191,7 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
     w: &mut impl std::io::Write,
     intrinsic: &Intrinsic<T>,
     indentation: Indentation,
-    specializations: &[Vec<u8>],
+    specializations: &[Vec<i64>],
     passes: u32,
 ) -> std::io::Result<()> {
     let intrinsic_name = &intrinsic.name;
@@ -256,7 +256,7 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
 /// Generate the specializations (unique sequences of const-generic arguments) for this intrinsic.
 fn generate_rust_specializations(
     constraints: &mut impl Iterator<Item = impl Iterator<Item = i64>>,
-) -> Vec<Vec<u8>> {
+) -> Vec<Vec<i64>> {
     let mut specializations = vec![vec![]];
 
     for constraint in constraints {
@@ -264,7 +264,7 @@ fn generate_rust_specializations(
             .flat_map(|right| {
                 specializations.iter().map(move |left| {
                     let mut left = left.clone();
-                    left.push(u8::try_from(right).unwrap());
+                    left.push(i64::try_from(right).unwrap());
                     left
                 })
             })
diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index 1351ca345b..7403b81df8 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -78,6 +78,7 @@ impl TypeKind {
             Self::Mask => "uint",
             Self::Poly => "poly",
             Self::Char(Sign::Signed) => "char",
+            Self::Vector => "int",
             _ => unreachable!("Not used: {:#?}", self),
         }
     }
@@ -155,6 +156,7 @@ impl IntrinsicType {
     pub fn c_scalar_type(&self) -> String {
         match self.kind() {
             TypeKind::Char(_) => String::from("char"),
+            TypeKind::Vector => String::from("int32_t"),
             _ => format!(
                 "{prefix}{bits}_t",
                 prefix = self.kind().c_prefix(),
@@ -163,14 +165,6 @@ impl IntrinsicType {
         }
     }
 
-    pub fn rust_scalar_type(&self) -> String {
-        format!(
-            "{prefix}{bits}",
-            prefix = self.kind().rust_prefix(),
-            bits = self.inner_size()
-        )
-    }
-
     pub fn c_promotion(&self) -> &str {
         match *self {
             IntrinsicType {
@@ -285,6 +279,29 @@ impl IntrinsicType {
                         )))
                 )
             }
+            IntrinsicType {
+                kind: TypeKind::Vector,
+                bit_len: Some(bit_len @ (128 | 256 | 512)),
+                simd_len,
+                ..
+            } => {
+                let (prefix, suffix) = match language {
+                    Language::Rust => ("[", "]"),
+                    Language::C => ("{", "}"),
+                };
+                let body_indentation = indentation.nested();
+                let effective_bit_len = 32;
+                let effective_vec_len = bit_len / effective_bit_len;
+                format!(
+                    "{prefix}\n{body}\n{indentation}{suffix}",
+                    body = (0..(simd_len.unwrap_or(1) * effective_vec_len + loads - 1))
+                        .format_with(",\n", |i, fmt| {
+                            let src = value_for_array(effective_bit_len, i);
+                            assert!(src == 0 || src.ilog2() < *bit_len);
+                            fmt(&format_args!("{body_indentation}{src:#x}"))
+                        })
+                )
+            }
             _ => unimplemented!("populate random: {:#?}", self),
         }
     }
@@ -300,7 +317,7 @@ impl IntrinsicType {
                 kind: TypeKind::Int(_) | TypeKind::Poly,
                 ..
             } => true,
-            _ => unimplemented!(),
+            _ => true,
         }
     }
 
@@ -332,4 +349,13 @@ pub trait IntrinsicTypeDefinition: Deref<Target = IntrinsicType> {
     /// rust debug output format for the return type. The generated line assumes
     /// there is an int i in scope which is the current pass number.
     fn print_result_c(&self, indentation: Indentation, additional: &str) -> String;
+
+    /// To enable architecture-specific logic
+    fn rust_scalar_type(&self) -> String {
+        format!(
+            "{prefix}{bits}",
+            prefix = self.kind().rust_prefix(),
+            bits = self.inner_size()
+        )
+    }
 }
diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index 666b3885c1..cb422c9cac 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -1,4 +1,5 @@
 use std::fs::File;
+use std::io::{self, Write};
 
 use rayon::prelude::*;
 
@@ -76,6 +77,14 @@ pub trait SupportedArchitectureTest {
                 if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
                     let output = cpp_compiler
                         .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"))?;
+                    if !output.status.success() {
+                        io::stdout()
+                            .write_all(&output.stdout)
+                            .expect("Failed to write to stdout!");
+                        io::stderr()
+                            .write_all(&output.stderr)
+                            .expect("Failed to write to stderr!");
+                    }
                     assert!(output.status.success(), "{output:?}");
                 }
 
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index e73ceb5084..13ae627e66 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -7,7 +7,6 @@ mod xml_parser;
 
 use crate::common::SupportedArchitectureTest;
 use crate::common::cli::ProcessedCli;
-use crate::common::compare::compare_outputs;
 use crate::common::compile_c::CppCompilation;
 use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
@@ -67,22 +66,4 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             cli_options: cli_options,
         }
     }
-
-    fn compare_outputs(&self) -> bool {
-        if self.cli_options.toolchain.is_some() {
-            let intrinsics_name_list = self
-                .intrinsics
-                .iter()
-                .map(|i| i.name.clone())
-                .collect::<Vec<_>>();
-
-            compare_outputs(
-                &intrinsics_name_list,
-                &self.cli_options.runner,
-                &self.cli_options.target,
-            )
-        } else {
-            true
-        }
-    }
 }
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index bb7ea59dbe..127dd38e6f 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -225,6 +225,20 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             ),
         }
     }
+
+    fn rust_scalar_type(&self) -> String {
+        let re = Regex::new(r"\__m\d+[a-z]*").unwrap();
+        if let Some(match_type) = re.find(self.param.type_data.as_str()) {
+            match_type.as_str().to_string()
+        } else {
+            let prefix = match self.data.kind {
+                TypeKind::Mask => String::from("__mmask"),
+                _ => self.kind().rust_prefix().to_string(),
+            };
+
+            format!("{prefix}{bits}", bits = self.inner_size())
+        }
+    }
 }
 
 impl X86IntrinsicType {
@@ -336,6 +350,12 @@ impl X86IntrinsicType {
                     data.bit_len = Some(8);
                 }
 
+                // default settings for "void *" parameters
+                // often used by intrinsics to denote memory address or so.
+                if data.kind == TypeKind::Mask && data.bit_len.is_none() {
+                    data.bit_len = Some(32);
+                }
+
                 // if param.etype == IMM, then it is a constant.
                 // else it stays unchanged.
                 data.constant |= param.etype == "IMM";

From 2e05d598e9e2b7f14c5f1bd156eda7c740b096f5 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <f20200049@pilani.bits-pilani.ac.in>
Date: Sun, 14 Sep 2025 21:50:57 +0530
Subject: [PATCH 24/73] feat: correcting errors with generated C artifacts

---
 crates/intrinsic-test/src/arm/mod.rs         | 12 +++-
 crates/intrinsic-test/src/common/argument.rs |  2 +-
 crates/intrinsic-test/src/common/gen_c.rs    | 16 ++---
 crates/intrinsic-test/src/common/mod.rs      |  1 +
 crates/intrinsic-test/src/x86/compile.rs     | 16 +----
 crates/intrinsic-test/src/x86/config.rs      | 63 +++++++-------------
 crates/intrinsic-test/src/x86/mod.rs         | 12 +++-
 crates/intrinsic-test/src/x86/types.rs       | 16 ++++-
 8 files changed, 63 insertions(+), 75 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/mod.rs b/crates/intrinsic-test/src/arm/mod.rs
index 08dc2d3870..a915d0d883 100644
--- a/crates/intrinsic-test/src/arm/mod.rs
+++ b/crates/intrinsic-test/src/arm/mod.rs
@@ -31,7 +31,17 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
 
     const NOTICE: &str = config::NOTICE;
 
-    const PLATFORM_C_HEADERS: &[&str] = &["arm_neon.h", "arm_acle.h", "arm_fp16.h"];
+    const PLATFORM_C_HEADERS: &[&str] = &[
+        "iostream",
+        "cstring",
+        "iomanip",
+        "sstream",
+        "cstddef",
+        "cstdint",
+        "arm_neon.h",
+        "arm_acle.h",
+        "arm_fp16.h",
+    ];
     const PLATFORM_C_DEFINITIONS: &str = config::POLY128_OSTREAM_DEF;
     const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::POLY128_OSTREAM_DECL;
 
diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index f38515e40a..871e3d2243 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -108,7 +108,7 @@ where
         for arg in self.iter().filter(|&arg| !arg.has_constraint()) {
             writeln!(
                 w,
-                "{indentation}const {ty} {name}_vals[] = {values};",
+                "{indentation}alignas(64) const {ty} {name}_vals[] = {values};",
                 ty = arg.ty.c_scalar_type(),
                 name = arg.name,
                 values = arg.ty.populate_random(indentation, loads, &Language::C)
diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index 28902b3dfe..b7651dce59 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -47,7 +47,7 @@ pub fn generate_c_constraint_blocks<'a, T: IntrinsicTypeDefinition + 'a>(
         let ty = current.ty.c_type();
 
         writeln!(w, "{indentation}{{")?;
-        writeln!(w, "{body_indentation}{ty} {} = {i};", current.name)?;
+        writeln!(w, "{body_indentation}const {ty} {} = {i};", current.name)?;
 
         generate_c_constraint_blocks(
             w,
@@ -103,14 +103,11 @@ pub fn write_mod_cpp<T: IntrinsicTypeDefinition>(
         writeln!(w, "#include <{header}>")?;
     }
 
+    writeln!(w, "{}", forward_declarations)?;
+
     writeln!(
         w,
         r#"
-#include <iostream>
-#include <cstring>
-#include <iomanip>
-#include <sstream>
-
 template<typename T1, typename T2> T1 cast(T2 x) {{
   static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same");
   T1 ret{{}};
@@ -120,13 +117,9 @@ template<typename T1, typename T2> T1 cast(T2 x) {{
 
 std::ostream& operator<<(std::ostream& os, float16_t value);
 
-
-
 "#
     )?;
 
-    writeln!(w, "{}", forward_declarations)?;
-
     for intrinsic in intrinsics {
         create_c_test_function(w, intrinsic)?;
     }
@@ -137,12 +130,13 @@ std::ostream& operator<<(std::ostream& os, float16_t value);
 pub fn write_main_cpp<'a>(
     w: &mut impl std::io::Write,
     arch_specific_definitions: &str,
+    arch_specific_headers: &[&str],
     intrinsics: impl Iterator<Item = &'a str> + Clone,
 ) -> std::io::Result<()> {
     writeln!(w, "#include <iostream>")?;
     writeln!(w, "#include <string>")?;
 
-    for header in ["arm_neon.h", "arm_acle.h", "arm_fp16.h"] {
+    for header in arch_specific_headers {
         writeln!(w, "#include <{header}>")?;
     }
 
diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index cb422c9cac..5966bc2aec 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -97,6 +97,7 @@ pub trait SupportedArchitectureTest {
         write_main_cpp(
             &mut file,
             Self::PLATFORM_C_DEFINITIONS,
+            Self::PLATFORM_C_HEADERS,
             self.intrinsics().iter().map(|i| i.name.as_str()),
         )
         .unwrap();
diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index 8baf581596..3e08a491a0 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -6,21 +6,7 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
 
     // -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations
     let mut command = CompilationCommandBuilder::new()
-        .add_arch_flags([
-            "avx",
-            "avx2",
-            "avx512f",
-            "avx512cd",
-            "avx512dq",
-            "avx512vl",
-            "avx512bw",
-            "avx512bf16",
-            "avx512bitalg",
-            "lzcnt",
-            "popcnt",
-            "adx",
-            "aes",
-        ])
+        .add_arch_flags(["icelake-client"])
         .set_compiler(cpp_compiler)
         .set_target(&config.target)
         .set_opt_level("2")
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index f1e9e9932e..e43fd33093 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -10,62 +10,41 @@ struct Hex<T>(T);
  "#;
 
 pub const LANE_FUNCTION_HELPERS: &str = r#"
-int mm512_extract(__m512i m, int vec_len, int bit_len, int index) {
-    int lane_len = 128;
-    int max_major_index = vec_len / lane_len;
-    int max_minor_index = lane_len / bit_len;
+typedef float float16_t;
+typedef float float32_t;
+typedef double float64_t;
 
-    int major_index = index / max_major_index;
-    int minor_index = index % max_minor_index;
+#define __int64 long long
 
-    __m128i lane = _mm512_extracti64x2_epi64(m, major_index);
+#define _mm512_extract_intrinsic_test_epi8(m, lane) \
+    _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
 
-    switch(bit_len){
-        case 8:
-            return _mm_extract_epi8(lane, minor_index);
-        case 16:
-            return _mm_extract_epi16(lane, minor_index);
-        case 32:
-            return _mm_extract_epi32(lane, minor_index);
-        case 64:
-            return _mm_extract_epi64(lane, minor_index);
-    }
-}
+#define _mm512_extract_intrinsic_test_epi16(m, lane) \
+    _mm_extract_epi16(_mm512_extracti64x2_epi64((m), (lane) / 8), (lane) % 8)
 
-int _mm512_extract_intrinsic_test_epi8(__m512i m, int lane) {
-    return mm512_extract(m, 512, 8, lane)
-}
+#define _mm512_extract_intrinsic_test_epi32(m, lane) \
+    _mm_extract_epi32(_mm512_extracti64x2_epi64((m), (lane) / 4), (lane) % 4)
 
-int _mm512_extract_intrinsic_test_epi16(__m512i m, int lane) {
-    return mm512_extract(m, 512, 16, lane)
-}
+#define _mm512_extract_intrinsic_test_epi64(m, lane) \
+    _mm_extract_epi64(_mm512_extracti64x2_epi64((m), (lane) / 2), (lane) % 2)
 
-int mm512_extract_intrinsic_test_epi16(__m512i m, int lane) {
-    return mm512_extract(m, 512, 16, lane)
-}
+#define _mm64_extract_intrinsic_test_epi8(m, lane) \
+    ((_mm_extract_pi16((m), (lane) / 2) >> (((lane) % 2) * 8)) & 0xFF)
 
-int mm512_extract_intrinsic_test_epi64(__m512i m, int lane) {
-    return mm512_extract(m, 512, 64, lane)
-}
-
-int mm64_extract_intrinsic_test_epi8(__m64 m, int lane) {
-    int real_lane_shift = lane / 2;
-    int real_bit_shift = (lane % 2) * 8;
-    int result = _mm_extract_pi16(m, lane / 2);
-    return (result >> real_bit_shift);
-}
-
-int mm64_extract_intrinsic_test_epi32(__m64 m, int lane) {
-    int bit_shift_amount = lane * 32;
-    return _m_to_int(m >> bit_shift_amount);
-}
+#define _mm64_extract_intrinsic_test_epi32(m, lane) \
+    _mm_cvtsi64_si32(_mm_srli_si64(m, (lane) * 32))
 "#;
 
 pub const X86_CONFIGURATIONS: &str = r#"
+#![cfg_attr(target_arch = "x86", feature(avx))]
+#![cfg_attr(target_arch = "x86", feature(sse))]
+#![cfg_attr(target_arch = "x86", feature(sse2))]
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_bf16))]
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_f16))]
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))]
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))]
+#![cfg_attr(target_arch = "x86_64", feature(sse))]
+#![cfg_attr(target_arch = "x86_64", feature(sse2))]
 #![cfg_attr(target_arch = "x86_64", feature(x86_amx_intrinsics))]
 #![cfg_attr(target_arch = "x86_64", feature(stdarch_x86_avx512_f16))]
 #![feature(fmt_helpers_for_derive)]
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 13ae627e66..2ed3296169 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -35,9 +35,17 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
 
     const NOTICE: &str = config::NOTICE;
 
-    const PLATFORM_C_HEADERS: &[&str] = &["immintrin.h"];
+    const PLATFORM_C_HEADERS: &[&str] = &[
+        "immintrin.h",
+        "iostream",
+        "cstring",
+        "iomanip",
+        "sstream",
+        "cstddef",
+        "cstdint",
+    ];
     const PLATFORM_C_DEFINITIONS: &str = config::LANE_FUNCTION_HELPERS;
-    const PLATFORM_C_FORWARD_DECLARATIONS: &str = "";
+    const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::LANE_FUNCTION_HELPERS;
 
     const PLATFORM_RUST_DEFINITIONS: &str = config::F16_FORMATTING_DEF;
     const PLATFORM_RUST_CFGS: &str = config::X86_CONFIGURATIONS;
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 127dd38e6f..a1dc5623ca 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -110,7 +110,17 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                 .filter(|c| c.is_numeric())
                 .join("")
                 .replace("128", "");
-            format!("_mm{type_val_filtered}_set1_epi64")
+            {
+                if type_value.ends_with("d") {
+                    format!("_mm{type_val_filtered}_loadu_pd")
+                } else if type_value.ends_with("h") {
+                    format!("_mm{type_val_filtered}_loadu_ph")
+                } else if type_value.ends_with("i") {
+                    format!("_mm{type_val_filtered}_loadu_epi16")
+                } else {
+                    format!("_mm{type_val_filtered}_loadu_ps")
+                }
+            }
         } else {
             // if it is a pointer, then rely on type conversion
             // If it is not any of the above type (__int<num>, __bfloat16, unsigned short, etc)
@@ -216,9 +226,9 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             (Some(16), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi16"),
             (Some(32), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi32"),
             (Some(64), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi64"),
-            (Some(8), Some(64)) => String::from("mm64_extract_intrinsic_test_epi8"),
+            (Some(8), Some(64)) => String::from("_mm64_extract_intrinsic_test_epi8"),
             (Some(16), Some(64)) => String::from("_mm_extract_pi16"),
-            (Some(32), Some(64)) => String::from("mm64_extract_intrinsic_test_epi32"),
+            (Some(32), Some(64)) => String::from("_mm64_extract_intrinsic_test_epi32"),
             _ => unreachable!(
                 "invalid length for vector argument: {:?}, {:?}",
                 self.bit_len, self.vec_len

From e977009da425950c81a1c8cd8846f8213cfdc2b5 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <f20200049@pilani.bits-pilani.ac.in>
Date: Mon, 15 Sep 2025 01:03:48 +0530
Subject: [PATCH 25/73] fix: vec_len -> simd_len (an error was present due to
 setting vec_len instead of simd_len for AVX register types)

---
 crates/intrinsic-test/src/x86/config.rs     |  1 +
 crates/intrinsic-test/src/x86/types.rs      | 12 ++++++------
 crates/intrinsic-test/src/x86/xml_parser.rs |  2 +-
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index e43fd33093..58fabcbd0e 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -15,6 +15,7 @@ typedef float float32_t;
 typedef double float64_t;
 
 #define __int64 long long
+#define __int32 int
 
 #define _mm512_extract_intrinsic_test_epi8(m, lane) \
     _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index a1dc5623ca..99c52551ad 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -209,9 +209,9 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
     /// Determines the get lane function for this type.
     fn get_lane_function(&self) -> String {
         let total_vector_bits: Option<u32> = self
-            .vec_len
+            .simd_len
             .zip(self.bit_len)
-            .and_then(|(vec_len, bit_len)| Some(vec_len * bit_len));
+            .and_then(|(simd_len, bit_len)| Some(simd_len * bit_len));
 
         match (self.bit_len, total_vector_bits) {
             (Some(8), Some(128)) => String::from("_mm_extract_epi8"),
@@ -231,7 +231,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             (Some(32), Some(64)) => String::from("_mm64_extract_intrinsic_test_epi32"),
             _ => unreachable!(
                 "invalid length for vector argument: {:?}, {:?}",
-                self.bit_len, self.vec_len
+                self.bit_len, self.simd_len
             ),
         }
     }
@@ -345,9 +345,9 @@ impl X86IntrinsicType {
                 if param.type_data.matches("__m").next().is_some()
                     && param.type_data.matches("__mmask").next().is_none()
                 {
-                    data.vec_len = match str::parse::<u32>(type_processed.as_str()) {
-                        // If bit_len is None, vec_len will be None.
-                        // Else vec_len will be (num_bits / bit_len).
+                    data.simd_len = match str::parse::<u32>(type_processed.as_str()) {
+                        // If bit_len is None, simd_len will be None.
+                        // Else simd_len will be (num_bits / bit_len).
                         Ok(num_bits) => data.bit_len.and_then(|bit_len| Some(num_bits / bit_len)),
                         Err(_) => None,
                     };
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index 7465cb72d5..808f594a8c 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -106,7 +106,7 @@ fn xml_to_intrinsic(
     let mut args_test = args.iter();
 
     // if one of the args has etype="MASK" and type="__m<int>d",
-    // then set the bit_len and vec_len accordingly
+    // then set the bit_len and simd_len accordingly
     let re = Regex::new(r"__m\d+").unwrap();
     let is_mask = |arg: &Argument<X86IntrinsicType>| arg.ty.param.etype.as_str() == "MASK";
     let is_vector = |arg: &Argument<X86IntrinsicType>| re.is_match(arg.ty.param.type_data.as_str());

From c1d971069c188aafed03b2dde123002a4b8021a9 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <f20200049@pilani.bits-pilani.ac.in>
Date: Tue, 16 Sep 2025 17:08:35 +0530
Subject: [PATCH 26/73] chore: revert default target

---
 crates/intrinsic-test/src/common/cli.rs | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/crates/intrinsic-test/src/common/cli.rs b/crates/intrinsic-test/src/common/cli.rs
index f8125128ea..beae6a4b04 100644
--- a/crates/intrinsic-test/src/common/cli.rs
+++ b/crates/intrinsic-test/src/common/cli.rs
@@ -44,9 +44,7 @@ pub struct Cli {
     pub generate_only: bool,
 
     /// Pass a target the test suite
-    /// x86_64-unknown-linux-gnu
-    /// armv7-unknown-linux-gnueabihf
-    #[arg(long, default_value_t = String::from("x86_64-unknown-linux-gnu"))]
+    #[arg(long, default_value_t = String::from("armv7-unknown-linux-gnueabihf"))]
     pub target: String,
 
     /// Set the linker

From 91eb33115bfe41231bc5c9d4dd34bed0f0f9b008 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <f20200049@pilani.bits-pilani.ac.in>
Date: Wed, 17 Sep 2025 23:58:20 +0530
Subject: [PATCH 27/73] chore: adding comments about memory alignment of
 variables and bash scripts that will be used in CI

---
 crates/intrinsic-test/src/arm/mod.rs         | 2 --
 crates/intrinsic-test/src/common/argument.rs | 2 ++
 crates/intrinsic-test/src/common/gen_rust.rs | 6 +++---
 crates/intrinsic-test/src/common/mod.rs      | 9 ---------
 4 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/mod.rs b/crates/intrinsic-test/src/arm/mod.rs
index a915d0d883..8f8289a7ec 100644
--- a/crates/intrinsic-test/src/arm/mod.rs
+++ b/crates/intrinsic-test/src/arm/mod.rs
@@ -36,8 +36,6 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
         "cstring",
         "iomanip",
         "sstream",
-        "cstddef",
-        "cstdint",
         "arm_neon.h",
         "arm_acle.h",
         "arm_fp16.h",
diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index 871e3d2243..0ab01e4144 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -106,6 +106,8 @@ where
         loads: u32,
     ) -> std::io::Result<()> {
         for arg in self.iter().filter(|&arg| !arg.has_constraint()) {
+            // Setting the variables on an aligned boundary to make it easier to pick
+            // functions (of a specific architecture) that would help load the values.
             writeln!(
                 w,
                 "{indentation}alignas(64) const {ty} {name}_vals[] = {values};",
diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index e97b745c59..3b330879e0 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -191,7 +191,7 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
     w: &mut impl std::io::Write,
     intrinsic: &Intrinsic<T>,
     indentation: Indentation,
-    specializations: &[Vec<i64>],
+    specializations: &[Vec<i32>],
     passes: u32,
 ) -> std::io::Result<()> {
     let intrinsic_name = &intrinsic.name;
@@ -256,7 +256,7 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
 /// Generate the specializations (unique sequences of const-generic arguments) for this intrinsic.
 fn generate_rust_specializations(
     constraints: &mut impl Iterator<Item = impl Iterator<Item = i64>>,
-) -> Vec<Vec<i64>> {
+) -> Vec<Vec<i32>> {
     let mut specializations = vec![vec![]];
 
     for constraint in constraints {
@@ -264,7 +264,7 @@ fn generate_rust_specializations(
             .flat_map(|right| {
                 specializations.iter().map(move |left| {
                     let mut left = left.clone();
-                    left.push(i64::try_from(right).unwrap());
+                    left.push(i32::try_from(right).unwrap());
                     left
                 })
             })
diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index 5966bc2aec..da9c75f5a0 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -1,5 +1,4 @@
 use std::fs::File;
-use std::io::{self, Write};
 
 use rayon::prelude::*;
 
@@ -77,14 +76,6 @@ pub trait SupportedArchitectureTest {
                 if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
                     let output = cpp_compiler
                         .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"))?;
-                    if !output.status.success() {
-                        io::stdout()
-                            .write_all(&output.stdout)
-                            .expect("Failed to write to stdout!");
-                        io::stderr()
-                            .write_all(&output.stderr)
-                            .expect("Failed to write to stderr!");
-                    }
                     assert!(output.status.success(), "{output:?}");
                 }
 

From 1cf7c54a09f38375edf80cf93dfcb729931e89b8 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <f20200049@pilani.bits-pilani.ac.in>
Date: Thu, 18 Sep 2025 01:39:51 +0530
Subject: [PATCH 28/73] chore: add compilation flags

---
 crates/intrinsic-test/src/x86/compile.rs | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index 3e08a491a0..9f3a76c4c1 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -12,7 +12,14 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
         .set_opt_level("2")
         .set_cxx_toolchain_dir(config.cxx_toolchain_dir.as_deref())
         .set_project_root("c_programs")
-        .add_extra_flags(vec!["-ffp-contract=off", "-Wno-narrowing"]);
+        .add_extra_flags(vec![
+            "-ffp-contract=off",
+            "-Wno-narrowing",
+            "-mavx",
+            "-mavx2",
+            "-mavx512f",
+            "-msse2",
+        ]);
 
     if !cpp_compiler.contains("clang") {
         command = command.add_extra_flag("-flax-vector-conversions");

From 5b6f2f13292f8d579639171b97f35d658f3b2775 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 18 Sep 2025 13:41:46 +0530
Subject: [PATCH 29/73] chore: add better error handling when writing and
 compiling mod_{i}.cpp, neatly organize C++ headers

---
 crates/intrinsic-test/src/arm/mod.rs      | 10 +---------
 crates/intrinsic-test/src/common/gen_c.rs | 12 +++---------
 crates/intrinsic-test/src/common/mod.rs   | 20 +++++++++++++-------
 crates/intrinsic-test/src/x86/mod.rs      | 10 +---------
 4 files changed, 18 insertions(+), 34 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/mod.rs b/crates/intrinsic-test/src/arm/mod.rs
index 8f8289a7ec..08dc2d3870 100644
--- a/crates/intrinsic-test/src/arm/mod.rs
+++ b/crates/intrinsic-test/src/arm/mod.rs
@@ -31,15 +31,7 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
 
     const NOTICE: &str = config::NOTICE;
 
-    const PLATFORM_C_HEADERS: &[&str] = &[
-        "iostream",
-        "cstring",
-        "iomanip",
-        "sstream",
-        "arm_neon.h",
-        "arm_acle.h",
-        "arm_fp16.h",
-    ];
+    const PLATFORM_C_HEADERS: &[&str] = &["arm_neon.h", "arm_acle.h", "arm_fp16.h"];
     const PLATFORM_C_DEFINITIONS: &str = config::POLY128_OSTREAM_DEF;
     const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::POLY128_OSTREAM_DECL;
 
diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index b7651dce59..25e4e210c3 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -6,6 +6,7 @@ use super::intrinsic_helpers::IntrinsicTypeDefinition;
 
 // The number of times each intrinsic will be called.
 const PASSES: u32 = 20;
+const COMMON_HEADERS: [&str; 5] = ["iostream", "string", "cstring", "iomanip", "sstream"];
 
 pub fn generate_c_test_loop<T: IntrinsicTypeDefinition + Sized>(
     w: &mut impl std::io::Write,
@@ -99,7 +100,7 @@ pub fn write_mod_cpp<T: IntrinsicTypeDefinition>(
 ) -> std::io::Result<()> {
     write!(w, "{notice}")?;
 
-    for header in platform_headers {
+    for header in COMMON_HEADERS.iter().chain(platform_headers.iter()) {
         writeln!(w, "#include <{header}>")?;
     }
 
@@ -133,20 +134,13 @@ pub fn write_main_cpp<'a>(
     arch_specific_headers: &[&str],
     intrinsics: impl Iterator<Item = &'a str> + Clone,
 ) -> std::io::Result<()> {
-    writeln!(w, "#include <iostream>")?;
-    writeln!(w, "#include <string>")?;
-
-    for header in arch_specific_headers {
+    for header in COMMON_HEADERS.iter().chain(arch_specific_headers.iter()) {
         writeln!(w, "#include <{header}>")?;
     }
 
     writeln!(
         w,
         r#"
-#include <cstring>
-#include <iomanip>
-#include <sstream>
-
 std::ostream& operator<<(std::ostream& os, float16_t value) {{
     uint16_t temp = 0;
     memcpy(&temp, &value, sizeof(float16_t));
diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index da9c75f5a0..37a48654e4 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -60,28 +60,34 @@ pub trait SupportedArchitectureTest {
             .map(|(i, chunk)| {
                 let c_filename = format!("c_programs/mod_{i}.cpp");
                 let mut file = File::create(&c_filename).unwrap();
-                write_mod_cpp(
+                let mod_file_write_result = write_mod_cpp(
                     &mut file,
                     Self::NOTICE,
                     Self::PLATFORM_C_HEADERS,
                     Self::PLATFORM_C_FORWARD_DECLARATIONS,
                     chunk,
-                )
-                .unwrap();
+                );
+
+                if let Err(error) = mod_file_write_result {
+                    return Err(format!("Error writing to mod_{i}.cpp: {error:?}"));
+                }
 
                 // compile this cpp file into a .o file.
                 //
                 // This is done because `cpp_compiler_wrapped` is None when
                 // the --generate-only flag is passed
                 if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
-                    let output = cpp_compiler
-                        .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"))?;
-                    assert!(output.status.success(), "{output:?}");
+                    let compile_output = cpp_compiler
+                        .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"));
+
+                    if let Err(compile_error) = compile_output {
+                        return Err(format!("Error compiling mod_{i}.cpp: {compile_error:?}"));
+                    }
                 }
 
                 Ok(())
             })
-            .collect::<Result<(), std::io::Error>>()
+            .collect::<Result<(), String>>()
             .unwrap();
 
         let mut file = File::create("c_programs/main.cpp").unwrap();
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 2ed3296169..e4c9742f8d 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -35,15 +35,7 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
 
     const NOTICE: &str = config::NOTICE;
 
-    const PLATFORM_C_HEADERS: &[&str] = &[
-        "immintrin.h",
-        "iostream",
-        "cstring",
-        "iomanip",
-        "sstream",
-        "cstddef",
-        "cstdint",
-    ];
+    const PLATFORM_C_HEADERS: &[&str] = &["immintrin.h", "cstddef", "cstdint"];
     const PLATFORM_C_DEFINITIONS: &str = config::LANE_FUNCTION_HELPERS;
     const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::LANE_FUNCTION_HELPERS;
 

From d9ff321fd4119c7ab5fbfc6fdb35f51de95936f6 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sat, 20 Sep 2025 15:14:43 +0530
Subject: [PATCH 30/73] feat: Fixed FP16 errors, made the loading function
 generation more accurate

---
 crates/intrinsic-test/src/arm/config.rs       | 10 ++++
 crates/intrinsic-test/src/common/argument.rs  | 14 ++++--
 crates/intrinsic-test/src/common/gen_c.rs     | 23 ++--------
 .../src/common/intrinsic_helpers.rs           |  5 +-
 crates/intrinsic-test/src/common/values.rs    | 25 ++++++++++
 crates/intrinsic-test/src/x86/compile.rs      |  6 +++
 crates/intrinsic-test/src/x86/config.rs       | 13 +++++-
 crates/intrinsic-test/src/x86/types.rs        | 46 ++++++++++++++-----
 crates/intrinsic-test/src/x86/xml_parser.rs   |  2 +
 9 files changed, 107 insertions(+), 37 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/config.rs b/crates/intrinsic-test/src/arm/config.rs
index d9024eabfa..46706e009e 100644
--- a/crates/intrinsic-test/src/arm/config.rs
+++ b/crates/intrinsic-test/src/arm/config.rs
@@ -6,6 +6,7 @@ pub const NOTICE: &str = "\
 pub const POLY128_OSTREAM_DECL: &str = r#"
 #ifdef __aarch64__
 std::ostream& operator<<(std::ostream& os, poly128_t value);
+std::ostream& operator<<(std::ostream& os, float16_t value);
 #endif
 "#;
 
@@ -23,6 +24,15 @@ std::ostream& operator<<(std::ostream& os, poly128_t value) {
     os << res;
     return os;
 }
+
+std::ostream& operator<<(std::ostream& os, float16_t value) {
+    uint16_t temp = 0;
+    memcpy(&temp, &value, sizeof(float16_t));
+    std::stringstream ss;
+    ss << "0x" << std::setfill('0') << std::setw(4) << std::hex << temp;
+    os << ss.str();
+    return os;
+}
 #endif
 "#;
 
diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index 0ab01e4144..986c383ee1 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -33,6 +33,10 @@ where
         self.ty.c_type()
     }
 
+    pub fn generate_name(&self) -> String {
+        format!("{}_val", self.name)
+    }
+
     pub fn is_simd(&self) -> bool {
         self.ty.is_simd()
     }
@@ -64,7 +68,7 @@ where
     }
 
     fn as_call_param_c(&self) -> String {
-        self.ty.as_call_param_c(&self.name)
+        self.ty.as_call_param_c(&self.generate_name())
     }
 }
 
@@ -91,7 +95,7 @@ where
     pub fn as_call_param_rust(&self) -> String {
         self.iter()
             .filter(|a| !a.has_constraint())
-            .map(|arg| arg.name.clone())
+            .map(|arg| arg.generate_name())
             .collect::<Vec<String>>()
             .join(", ")
     }
@@ -112,7 +116,7 @@ where
                 w,
                 "{indentation}alignas(64) const {ty} {name}_vals[] = {values};",
                 ty = arg.ty.c_scalar_type(),
-                name = arg.name,
+                name = arg.generate_name(),
                 values = arg.ty.populate_random(indentation, loads, &Language::C)
             )?
         }
@@ -155,7 +159,7 @@ where
                 format!(
                     "{indentation}{ty} {name} = cast<{ty}>({load}(&{name}_vals[i]));\n",
                     ty = arg.to_c_type(),
-                    name = arg.name,
+                    name = arg.generate_name(),
                     load = if arg.is_simd() {
                         arg.ty.get_load_function(Language::C)
                     } else {
@@ -175,7 +179,7 @@ where
             .map(|arg| {
                 format!(
                     "{indentation}let {name} = {load}({vals_name}.as_ptr().offset(i));\n",
-                    name = arg.name,
+                    name = arg.generate_name(),
                     vals_name = arg.rust_vals_array_name(),
                     load = if arg.is_simd() {
                         arg.ty.get_load_function(Language::Rust)
diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index 25e4e210c3..aeb94176f5 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -48,7 +48,11 @@ pub fn generate_c_constraint_blocks<'a, T: IntrinsicTypeDefinition + 'a>(
         let ty = current.ty.c_type();
 
         writeln!(w, "{indentation}{{")?;
-        writeln!(w, "{body_indentation}const {ty} {} = {i};", current.name)?;
+        writeln!(
+            w,
+            "{body_indentation}const {ty} {} = {i};",
+            current.generate_name()
+        )?;
 
         generate_c_constraint_blocks(
             w,
@@ -115,9 +119,6 @@ template<typename T1, typename T2> T1 cast(T2 x) {{
   memcpy(&ret, &x, sizeof(T1));
   return ret;
 }}
-
-std::ostream& operator<<(std::ostream& os, float16_t value);
-
 "#
     )?;
 
@@ -138,20 +139,6 @@ pub fn write_main_cpp<'a>(
         writeln!(w, "#include <{header}>")?;
     }
 
-    writeln!(
-        w,
-        r#"
-std::ostream& operator<<(std::ostream& os, float16_t value) {{
-    uint16_t temp = 0;
-    memcpy(&temp, &value, sizeof(float16_t));
-    std::stringstream ss;
-    ss << "0x" << std::setfill('0') << std::setw(4) << std::hex << temp;
-    os << ss.str();
-    return os;
-}}
-"#
-    )?;
-
     // NOTE: It's assumed that this value contains the required `ifdef`s.
     writeln!(w, "{arch_specific_definitions }")?;
 
diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index 7403b81df8..5d930eea2f 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -1,3 +1,4 @@
+use std::cmp;
 use std::fmt;
 use std::ops::Deref;
 use std::str::FromStr;
@@ -131,7 +132,7 @@ impl IntrinsicType {
 
     pub fn inner_size(&self) -> u32 {
         if let Some(bl) = self.bit_len {
-            bl
+            cmp::max(bl, 8)
         } else {
             unreachable!("{:#?}", self)
         }
@@ -216,7 +217,7 @@ impl IntrinsicType {
     ) -> String {
         match self {
             IntrinsicType {
-                bit_len: Some(bit_len @ (8 | 16 | 32 | 64)),
+                bit_len: Some(bit_len @ (1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 16 | 32 | 64)),
                 kind:
                     kind @ (TypeKind::Int(_) | TypeKind::Poly | TypeKind::Char(_) | TypeKind::Mask),
                 simd_len,
diff --git a/crates/intrinsic-test/src/common/values.rs b/crates/intrinsic-test/src/common/values.rs
index 1b614a742e..6c94ef2c22 100644
--- a/crates/intrinsic-test/src/common/values.rs
+++ b/crates/intrinsic-test/src/common/values.rs
@@ -4,6 +4,13 @@
 pub fn value_for_array(bits: u32, index: u32) -> u64 {
     let index = index as usize;
     match bits {
+        1 => VALUES_8[index % 2].into(),
+        2 => VALUES_8[index % 4].into(),
+        3 => VALUES_8[index % 8].into(),
+        4 => VALUES_8[index % 16].into(),
+        5 => VALUES_5[index % VALUES_5.len()].into(),
+        6 => VALUES_6[index % VALUES_6.len()].into(),
+        7 => VALUES_7[index % VALUES_7.len()].into(),
         8 => VALUES_8[index % VALUES_8.len()].into(),
         16 => VALUES_16[index % VALUES_16.len()].into(),
         32 => VALUES_32[index % VALUES_32.len()].into(),
@@ -12,6 +19,24 @@ pub fn value_for_array(bits: u32, index: u32) -> u64 {
     }
 }
 
+pub const VALUES_5: &[u8] = &[
+    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x019, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e,
+    0x1f,
+];
+
+pub const VALUES_6: &[u8] = &[
+    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x039, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e,
+    0x3f,
+];
+
+pub const VALUES_7: &[u8] = &[
+    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+    0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x079, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e,
+    0x7f,
+];
+
 pub const VALUES_8: &[u8] = &[
     0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
     0xf0, 0x80, 0x3b, 0xff,
diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index 9f3a76c4c1..6eaab86150 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -19,6 +19,12 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
             "-mavx2",
             "-mavx512f",
             "-msse2",
+            "-mavx512vl",
+            "-mavx512bw",
+            "-mavx512dq",
+            "-mavx512cd",
+            "-mavx512fp16",
+            "-ferror-limit=1000",
         ]);
 
     if !cpp_compiler.contains("clang") {
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 58fabcbd0e..32a9b586c0 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -10,13 +10,24 @@ struct Hex<T>(T);
  "#;
 
 pub const LANE_FUNCTION_HELPERS: &str = r#"
-typedef float float16_t;
+typedef _Float16 float16_t;
 typedef float float32_t;
 typedef double float64_t;
 
 #define __int64 long long
 #define __int32 int
 
+std::ostream& operator<<(std::ostream& os, _Float16 value);
+
+std::ostream& operator<<(std::ostream& os, _Float16 value) {
+    uint16_t temp = 0;
+    memcpy(&temp, &value, sizeof(_Float16));
+    std::stringstream ss;
+    ss << "0x" << std::setfill('0') << std::setw(4) << std::hex << temp;
+    os << ss.str();
+    return os;
+}
+
 #define _mm512_extract_intrinsic_test_epi8(m, lane) \
     _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
 
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 99c52551ad..dfaf2adaf4 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -13,7 +13,17 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
     /// Gets a string containing the type in C format.
     /// This function assumes that this value is present in the metadata hashmap.
     fn c_type(&self) -> String {
-        self.param.type_data.clone()
+        self.param
+            .type_data
+            .replace("unsigned __int64", "uint64_t")
+            .replace("unsigned __int32", "uint32_t")
+            .replace("unsigned __int16", "uint16_t")
+            .replace("unsigned __int8", "uint8_t")
+            .replace("__int64", "int64_t")
+            .replace("__int32", "int32_t")
+            .replace("__int16", "int16_t")
+            .replace("__int8", "int8_t")
+            .replace("const ", "")
     }
 
     fn c_single_vector_type(&self) -> String {
@@ -109,17 +119,22 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                 .chars()
                 .filter(|c| c.is_numeric())
                 .join("")
-                .replace("128", "");
+                .replace("128", "")
+                .replace("64", "");
             {
-                if type_value.ends_with("d") {
-                    format!("_mm{type_val_filtered}_loadu_pd")
-                } else if type_value.ends_with("h") {
-                    format!("_mm{type_val_filtered}_loadu_ph")
-                } else if type_value.ends_with("i") {
-                    format!("_mm{type_val_filtered}_loadu_epi16")
-                } else {
-                    format!("_mm{type_val_filtered}_loadu_ps")
-                }
+                let suffix = match (self.bit_len, self.kind) {
+                    (Some(bit_len @ (8 | 16 | 32 | 64)), TypeKind::Int(_)) => {
+                        format!("epi{bit_len}")
+                    }
+                    (Some(16), TypeKind::Float) => format!("ph"),
+                    (Some(32), TypeKind::Float) => format!("ps"),
+                    (Some(64), TypeKind::Float) => format!("pd"),
+                    (Some(128), TypeKind::Vector) => format!("si128"),
+                    (Some(256), TypeKind::Vector) => format!("si256"),
+                    (Some(512), TypeKind::Vector) => format!("si512"),
+                    _ => unreachable!("Invalid element type for a vector type! {:?}", self.param),
+                };
+                format!("_mm{type_val_filtered}_loadu_{suffix}")
             }
         } else {
             // if it is a pointer, then rely on type conversion
@@ -366,6 +381,15 @@ impl X86IntrinsicType {
                     data.bit_len = Some(32);
                 }
 
+                // default settings for IMM parameters
+                if param.etype == "IMM" && param.imm_width > 0 {
+                    data.bit_len = Some(param.imm_width);
+                }
+
+                if param.etype == "IMM" || param.imm_width > 0 || param.imm_type.len() > 0 {
+                    data.constant = true;
+                }
+
                 // if param.etype == IMM, then it is a constant.
                 // else it stays unchanged.
                 data.constant |= param.etype == "IMM";
diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index 808f594a8c..157a37fc9d 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -48,6 +48,8 @@ pub struct Parameter {
     pub etype: String,
     #[serde(rename = "@memwidth", default, deserialize_with = "string_to_u32")]
     pub memwidth: u32,
+    #[serde(rename = "@immwidth", default, deserialize_with = "string_to_u32")]
+    pub imm_width: u32,
     #[serde(rename = "@immtype", default)]
     pub imm_type: String,
 }

From 48c6ed13a65799975897c90b4deb3a47e26b8498 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 24 Sep 2025 22:07:45 +0530
Subject: [PATCH 31/73] chore: Ensuring "const" appears for constant arguments
 to intrinsics.

Extra changes: 1. Using "as _" to allow for implicit typecasting
---
 crates/intrinsic-test/src/common/argument.rs | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index 986c383ee1..5963abef2f 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -30,7 +30,8 @@ where
     }
 
     pub fn to_c_type(&self) -> String {
-        self.ty.c_type()
+        let prefix = if self.ty.constant { "const " } else { "" };
+        format!("{}{}", prefix, self.ty.c_type())
     }
 
     pub fn generate_name(&self) -> String {
@@ -95,7 +96,7 @@ where
     pub fn as_call_param_rust(&self) -> String {
         self.iter()
             .filter(|a| !a.has_constraint())
-            .map(|arg| arg.generate_name())
+            .map(|arg| arg.generate_name() + " as _")
             .collect::<Vec<String>>()
             .join(", ")
     }
@@ -177,15 +178,16 @@ where
         self.iter()
             .filter(|&arg| !arg.has_constraint())
             .map(|arg| {
+                let load = if arg.is_simd() {
+                    arg.ty.get_load_function(Language::Rust)
+                } else {
+                    "*".to_string()
+                };
+                let typecast = if load.len() > 2 { "as _" } else { "" };
                 format!(
-                    "{indentation}let {name} = {load}({vals_name}.as_ptr().offset(i));\n",
+                    "{indentation}let {name} = {load}({vals_name}.as_ptr().offset(i){typecast});\n",
                     name = arg.generate_name(),
                     vals_name = arg.rust_vals_array_name(),
-                    load = if arg.is_simd() {
-                        arg.ty.get_load_function(Language::Rust)
-                    } else {
-                        "*".to_string()
-                    },
                 )
             })
             .collect()

From 45d097f5a463fc4aa58a6f819be9c382607532b9 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 24 Sep 2025 22:10:34 +0530
Subject: [PATCH 32/73] chore: allowing cast() function to allow implicity type
 conversion for certain cases (like uint32_t to uint64_t)

extras: 1. added more C++ headers 2. typecasting integer constants (for
example, the MM_FROUND arguments) for type compatibility
---
 crates/intrinsic-test/src/common/gen_c.rs | 30 ++++++++++++++++++-----
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index aeb94176f5..965e229da5 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -6,7 +6,15 @@ use super::intrinsic_helpers::IntrinsicTypeDefinition;
 
 // The number of times each intrinsic will be called.
 const PASSES: u32 = 20;
-const COMMON_HEADERS: [&str; 5] = ["iostream", "string", "cstring", "iomanip", "sstream"];
+const COMMON_HEADERS: [&str; 7] = [
+    "iostream",
+    "string",
+    "cstring",
+    "iomanip",
+    "sstream",
+    "type_traits",
+    "cassert",
+];
 
 pub fn generate_c_test_loop<T: IntrinsicTypeDefinition + Sized>(
     w: &mut impl std::io::Write,
@@ -48,9 +56,13 @@ pub fn generate_c_constraint_blocks<'a, T: IntrinsicTypeDefinition + 'a>(
         let ty = current.ty.c_type();
 
         writeln!(w, "{indentation}{{")?;
+
+        // TODO: Move to actually specifying the enum value
+        // instead of typecasting integers, for better clarity
+        // of generated code.
         writeln!(
             w,
-            "{body_indentation}const {ty} {} = {i};",
+            "{body_indentation}const {ty} {} = ({ty}){i};",
             current.generate_name()
         )?;
 
@@ -113,11 +125,17 @@ pub fn write_mod_cpp<T: IntrinsicTypeDefinition>(
     writeln!(
         w,
         r#"
+// T1 is the `To` type, T2 is the `From` type
 template<typename T1, typename T2> T1 cast(T2 x) {{
-  static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same");
-  T1 ret{{}};
-  memcpy(&ret, &x, sizeof(T1));
-  return ret;
+  if (std::is_convertible<T2, T1>::value) {{
+      return x;
+  }} else if (sizeof(T1) == sizeof(T2)) {{
+    T1 ret{{}};
+    memcpy(&ret, &x, sizeof(T1));
+    return ret;
+  }} else {{
+    assert("T2 must either be convertable to T1, or have the same size as T1!");
+  }}
 }}
 "#
     )?;

From 5553fdd3602b67c4c92670f07b9b2d4e4cf1fc95 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 24 Sep 2025 22:13:10 +0530
Subject: [PATCH 33/73] feat: matching the expected number of elements for
 array to load arguments, accommodating for signed variables too

---
 .../src/common/intrinsic_helpers.rs           | 22 +++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index 5d930eea2f..43a0e3f5d1 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -284,6 +284,7 @@ impl IntrinsicType {
                 kind: TypeKind::Vector,
                 bit_len: Some(bit_len @ (128 | 256 | 512)),
                 simd_len,
+                vec_len,
                 ..
             } => {
                 let (prefix, suffix) = match language {
@@ -292,14 +293,27 @@ impl IntrinsicType {
                 };
                 let body_indentation = indentation.nested();
                 let effective_bit_len = 32;
-                let effective_vec_len = bit_len / effective_bit_len;
                 format!(
                     "{prefix}\n{body}\n{indentation}{suffix}",
-                    body = (0..(simd_len.unwrap_or(1) * effective_vec_len + loads - 1))
+                    body = (0..(vec_len.unwrap_or(1) * simd_len.unwrap_or(1) + loads - 1))
                         .format_with(",\n", |i, fmt| {
                             let src = value_for_array(effective_bit_len, i);
-                            assert!(src == 0 || src.ilog2() < *bit_len);
-                            fmt(&format_args!("{body_indentation}{src:#x}"))
+                            assert!(src == 0 || src.ilog2() < effective_bit_len);
+                            if (src >> (effective_bit_len - 1)) != 0 {
+                                // `src` is a two's complement representation of a negative value.
+                                let mask = !0u64 >> (64 - effective_bit_len);
+                                let ones_compl = src ^ mask;
+                                let twos_compl = ones_compl + 1;
+                                if (twos_compl == src) && (language == &Language::C) {
+                                    // `src` is INT*_MIN. C requires `-0x7fffffff - 1` to avoid
+                                    // undefined literal overflow behaviour.
+                                    fmt(&format_args!("{body_indentation}-{ones_compl:#x} - 1"))
+                                } else {
+                                    fmt(&format_args!("{body_indentation}-{twos_compl:#x}"))
+                                }
+                            } else {
+                                fmt(&format_args!("{body_indentation}{src:#x}"))
+                            }
                         })
                 )
             }

From 39a0e45ffb784b8398a3907ceae39204ce4bdca0 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 24 Sep 2025 22:14:20 +0530
Subject: [PATCH 34/73] feat: updated with debug printing and ostream
 implementation for vector types

---
 crates/intrinsic-test/src/x86/config.rs | 100 +++++++++++++++++++++++-
 1 file changed, 98 insertions(+), 2 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 32a9b586c0..a199a58ff2 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -5,8 +5,64 @@ pub const NOTICE: &str = "\
 
 // Format f16 values (and vectors containing them) in a way that is consistent with C.
 pub const F16_FORMATTING_DEF: &str = r#"
+use std::arch::x86_64::*;
+
+#[inline]
+fn debug_simd_finish<T: core::fmt::Debug, const N: usize>(
+    formatter: &mut core::fmt::Formatter<'_>,
+    type_name: &str,
+    array: &[T; N],
+) -> core::fmt::Result {
+    core::fmt::Formatter::debug_tuple_fields_finish(
+        formatter,
+        type_name,
+        &core::array::from_fn::<&dyn core::fmt::Debug, N, _>(|i| &array[i]),
+    )
+}
+
 #[repr(transparent)]
 struct Hex<T>(T);
+
+impl<T: DebugHexF16> core::fmt::Debug for Hex<T> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        <T as DebugHexF16>::fmt(&self.0, f)
+    }
+}
+
+fn debug_f16<T: DebugHexF16>(x: T) -> impl core::fmt::Debug {
+    Hex(x)
+}
+
+trait DebugHexF16 {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result;
+}
+
+impl DebugHexF16 for f16 {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{:#06x?}", self.to_bits())
+    }
+}
+
+impl DebugHexF16 for __m128h {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 8]>(*self) };
+        debug_simd_finish(f, "__m128h", &array)
+    }
+}
+
+impl DebugHexF16 for __m256h {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 16]>(*self) };
+        debug_simd_finish(f, "__m256h", &array)
+    }
+}
+
+impl DebugHexF16 for __m512h {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 32]>(*self) };
+        debug_simd_finish(f, "__m512h", &array)
+    }
+}
  "#;
 
 pub const LANE_FUNCTION_HELPERS: &str = r#"
@@ -18,6 +74,9 @@ typedef double float64_t;
 #define __int32 int
 
 std::ostream& operator<<(std::ostream& os, _Float16 value);
+std::ostream& operator<<(std::ostream& os, __m128i value);
+std::ostream& operator<<(std::ostream& os, __m256i value);
+std::ostream& operator<<(std::ostream& os, __m512i value);
 
 std::ostream& operator<<(std::ostream& os, _Float16 value) {
     uint16_t temp = 0;
@@ -28,6 +87,45 @@ std::ostream& operator<<(std::ostream& os, _Float16 value) {
     return os;
 }
 
+std::ostream& operator<<(std::ostream& os, __m128i value) {
+    void* temp = malloc(sizeof(__m128i));
+    _mm_storeu_si128((__m128i*)temp, value);
+    std::stringstream ss;
+    
+    ss << "0x";
+    for(int i = 0; i < 16; i++) {
+        ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i];
+    }
+    os << ss.str();
+    return os;
+}
+
+std::ostream& operator<<(std::ostream& os, __m256i value) {
+    void* temp = malloc(sizeof(__m256i));
+    _mm256_storeu_si256((__m256i*)temp, value);
+    std::stringstream ss;
+    
+    ss << "0x";
+    for(int i = 0; i < 32; i++) {
+        ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i];
+    }
+    os << ss.str();
+    return os;
+}
+
+std::ostream& operator<<(std::ostream& os, __m512i value) {
+    void* temp = malloc(sizeof(__m512i));
+    _mm512_storeu_si512((__m512i*)temp, value);
+    std::stringstream ss;
+    
+    ss << "0x";
+    for(int i = 0; i < 64; i++) {
+        ss << std::setfill('0') << std::setw(2) << std::hex << ((char*)temp)[i];
+    }
+    os << ss.str();
+    return os;
+}
+
 #define _mm512_extract_intrinsic_test_epi8(m, lane) \
     _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
 
@@ -55,8 +153,6 @@ pub const X86_CONFIGURATIONS: &str = r#"
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512_f16))]
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))]
 #![cfg_attr(target_arch = "x86", feature(stdarch_x86_rtm))]
-#![cfg_attr(target_arch = "x86_64", feature(sse))]
-#![cfg_attr(target_arch = "x86_64", feature(sse2))]
 #![cfg_attr(target_arch = "x86_64", feature(x86_amx_intrinsics))]
 #![cfg_attr(target_arch = "x86_64", feature(stdarch_x86_avx512_f16))]
 #![feature(fmt_helpers_for_derive)]

From 2742d33180cbc3a484ac409a030a668ae4724436 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 24 Sep 2025 22:15:39 +0530
Subject: [PATCH 35/73] chore: corrected the legal range of values for
 constrained arguments such as _MM_FROUND_SAE and _MM_ROUND_MODE

---
 crates/intrinsic-test/src/x86/constraint.rs | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/constraint.rs b/crates/intrinsic-test/src/x86/constraint.rs
index 1f06988388..72f5da3b3f 100644
--- a/crates/intrinsic-test/src/x86/constraint.rs
+++ b/crates/intrinsic-test/src/x86/constraint.rs
@@ -1,19 +1,29 @@
 use crate::common::constraint::Constraint;
 
-pub fn map_constraints(imm_type: &String) -> Option<Constraint> {
+pub fn map_constraints(imm_type: &String, imm_width: u32) -> Option<Constraint> {
+    if imm_width > 0 {
+        let max: i64 = 2i64.pow(imm_width);
+        return Some(Constraint::Range(0..max));
+    }
     match imm_type.as_str() {
-        "_MM_FROUND" => Some(Constraint::Range(0..4)),
+        // Legal values for variables of `_MM_FROUND` type are:
+        // 8 =>  (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions
+        // 9 =>  (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)     // round down, and suppress exceptions
+        // 10 => (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)     // round up, and suppress exceptions
+        // 11 => (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)        // truncate, and suppress exceptions
+        // 4 =>   _MM_FROUND_CUR_DIRECTION                      // use MXCSR.RC; see _MM_SET_ROUNDING_MODE
+        "_MM_FROUND" => Some(Constraint::Set(vec![4, 8, 9, 10, 11])),
         "_MM_INDEX_SCALE" => Some(Constraint::Set(vec![1, 2, 4, 8])),
         "_MM_CMPINT" => Some(Constraint::Range(0..8)),
         "_MM_REDUCE" => Some(Constraint::Range(0..8)),
-        "_MM_FROUND_SAE" => Some(Constraint::Range(0..8)),
+        "_MM_FROUND_SAE" => Some(Constraint::Equal(8)),
         "_MM_MANTISSA_NORM" => Some(Constraint::Range(0..4)),
         "_MM_MANTISSA_NORM_ENUM" => Some(Constraint::Range(0..4)),
         "_MM_MANTISSA_SIGN" => Some(Constraint::Range(0..3)),
         "_MM_PERM" => Some(Constraint::Range(0..256)),
         "_MM_PERM_ENUM" => Some(Constraint::Range(0..256)),
         "_MM_CMPINT_ENUM" => Some(Constraint::Range(0..8)),
-        "_MM_ROUND_MODE" => Some(Constraint::Set(vec![0, 0x2000, 0x4000, 0x6000])),
+        "_MM_ROUND_MODE" => Some(Constraint::Set(vec![0, 0x2, 0x4, 0x6])),
         "_CMP_" => Some(Constraint::Range(0..32)),
         _ => None,
     }

From 18caf69df05ac49612f6b1fa7d8104b5bb631ed3 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 24 Sep 2025 22:16:23 +0530
Subject: [PATCH 36/73] feat: filter for duplicates in the definition of
 intrinsics

---
 crates/intrinsic-test/src/x86/mod.rs | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index e4c9742f8d..d5ebd960b3 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -11,6 +11,7 @@ use crate::common::compile_c::CppCompilation;
 use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
 use intrinsic::X86IntrinsicType;
+use itertools::Itertools;
 use xml_parser::get_xml_intrinsics;
 
 pub struct X86ArchitectureTest {
@@ -58,6 +59,7 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             .filter(|i| !i.arguments.iter().any(|a| a.is_ptr()))
             .filter(|i| !i.arguments.iter().any(|a| a.ty.inner_size() == 128))
             .filter(|i| !cli_options.skip.contains(&i.name))
+            .unique_by(|i| i.name.clone())
             .collect::<Vec<_>>();
 
         intrinsics.sort_by(|a, b| a.name.cmp(&b.name));

From 6702469fcec5c68d8aedf99af5a94b7fc7c57360 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 24 Sep 2025 22:23:30 +0530
Subject: [PATCH 37/73] chore: vector types cannot be the type of an individual
 element in an array.

Extra: 1. Added better load fuctions 2. Added an update_simd_len()
function to support cases where the bit_len of the element need to be
inferred from its partner arguments before calculating the simd_len
---
 crates/intrinsic-test/src/x86/types.rs | 113 +++++++++++++++++--------
 1 file changed, 77 insertions(+), 36 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index dfaf2adaf4..b07726656a 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -115,6 +115,10 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             // if "type" starts with __m<num>{h/i/<null>},
             // then use either _mm_set1_epi64,
             // _mm256_set1_epi64 or _mm512_set1_epi64
+            if type_value.contains("__m64") {
+                return String::from("*(__m64*)");
+            }
+
             let type_val_filtered = type_value
                 .chars()
                 .filter(|c| c.is_numeric())
@@ -126,12 +130,11 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                     (Some(bit_len @ (8 | 16 | 32 | 64)), TypeKind::Int(_)) => {
                         format!("epi{bit_len}")
                     }
+                    (Some(bit_len), TypeKind::Mask) => format!("epi{bit_len}"),
                     (Some(16), TypeKind::Float) => format!("ph"),
                     (Some(32), TypeKind::Float) => format!("ps"),
                     (Some(64), TypeKind::Float) => format!("pd"),
-                    (Some(128), TypeKind::Vector) => format!("si128"),
-                    (Some(256), TypeKind::Vector) => format!("si256"),
-                    (Some(512), TypeKind::Vector) => format!("si512"),
+                    (Some(128 | 256 | 512), TypeKind::Vector) => format!("epi32"),
                     _ => unreachable!("Invalid element type for a vector type! {:?}", self.param),
                 };
                 format!("_mm{type_val_filtered}_loadu_{suffix}")
@@ -252,17 +255,18 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
     }
 
     fn rust_scalar_type(&self) -> String {
-        let re = Regex::new(r"\__m\d+[a-z]*").unwrap();
-        if let Some(match_type) = re.find(self.param.type_data.as_str()) {
-            match_type.as_str().to_string()
-        } else {
-            let prefix = match self.data.kind {
-                TypeKind::Mask => String::from("__mmask"),
-                _ => self.kind().rust_prefix().to_string(),
-            };
+        let prefix = match self.data.kind {
+            TypeKind::Mask => String::from("__mmask"),
+            TypeKind::Vector => String::from("i"),
+            _ => self.kind().rust_prefix().to_string(),
+        };
 
-            format!("{prefix}{bits}", bits = self.inner_size())
-        }
+        let bits = if self.inner_size() >= 128 {
+            32
+        } else {
+            self.inner_size()
+        };
+        format!("{prefix}{bits}")
     }
 }
 
@@ -311,6 +315,26 @@ impl X86IntrinsicType {
         })
     }
 
+    pub fn update_simd_len(&mut self) {
+        let mut type_processed = self.param.type_data.clone();
+        type_processed.retain(|c| c.is_numeric());
+
+        // check the param.type and extract numeric part if there are double
+        // underscores. divide this number with bit-len and set this as simd-len.
+        // Only __m<int> types can have a simd-len.
+        if self.param.type_data.contains("__m") && !self.param.type_data.contains("__mmask") {
+            self.data.simd_len = match str::parse::<u32>(type_processed.as_str()) {
+                // If bit_len is None, simd_len will be None.
+                // Else simd_len will be (num_bits / bit_len).
+                Ok(num_bits) => self
+                    .data
+                    .bit_len
+                    .and_then(|bit_len| Some(num_bits / bit_len)),
+                Err(_) => None,
+            };
+        }
+    }
+
     pub fn from_param(param: &Parameter) -> Result<Self, String> {
         match Self::from_c(param.type_data.as_str()) {
             Err(message) => Err(message),
@@ -350,22 +374,26 @@ impl X86IntrinsicType {
                     }
                 }
 
-                if param.type_data.matches("__mmask").next().is_some() {
+                if param.type_data.contains("__mmask") {
                     data.bit_len = str::parse::<u32>(type_processed.as_str()).ok();
                 }
 
-                // then check the param.type and extract numeric part if there are double
-                // underscores. divide this number with bit-len and set this as simd-len.
-                // Only __m<int> types can have a simd-len.
-                if param.type_data.matches("__m").next().is_some()
-                    && param.type_data.matches("__mmask").next().is_none()
-                {
-                    data.simd_len = match str::parse::<u32>(type_processed.as_str()) {
-                        // If bit_len is None, simd_len will be None.
-                        // Else simd_len will be (num_bits / bit_len).
-                        Ok(num_bits) => data.bit_len.and_then(|bit_len| Some(num_bits / bit_len)),
-                        Err(_) => None,
-                    };
+                if vec!["M512", "M256", "M128"].contains(&param.etype.as_str()) {
+                    match param.type_data.chars().last() {
+                        Some('i') => {
+                            data.kind = TypeKind::Int(Sign::Signed);
+                            data.bit_len = Some(32);
+                        }
+                        Some('h') => {
+                            data.kind = TypeKind::Float;
+                            data.bit_len = Some(16);
+                        }
+                        Some('d') => {
+                            data.kind = TypeKind::Float;
+                            data.bit_len = Some(64);
+                        }
+                        _ => (),
+                    }
                 }
 
                 // default settings for "void *" parameters
@@ -381,22 +409,35 @@ impl X86IntrinsicType {
                     data.bit_len = Some(32);
                 }
 
-                // default settings for IMM parameters
-                if param.etype == "IMM" && param.imm_width > 0 {
-                    data.bit_len = Some(param.imm_width);
-                }
-
                 if param.etype == "IMM" || param.imm_width > 0 || param.imm_type.len() > 0 {
+                    data.kind = TypeKind::Int(Sign::Unsigned);
                     data.constant = true;
                 }
 
-                // if param.etype == IMM, then it is a constant.
-                // else it stays unchanged.
-                data.constant |= param.etype == "IMM";
-                Ok(X86IntrinsicType {
+                // Rust defaults to signed variants, unless they are explicitly mentioned
+                // the `type` field are C++ types.
+                if data.kind == TypeKind::Int(Sign::Unsigned)
+                    && !(param.type_data.contains("unsigned") || param.type_data.contains("uint"))
+                {
+                    data.kind = TypeKind::Int(Sign::Signed)
+                }
+
+                // default settings for IMM parameters
+                if param.etype == "IMM" {
+                    data.bit_len = if param.imm_width > 0 {
+                        Some(param.imm_width)
+                    } else {
+                        Some(8)
+                    }
+                }
+
+                let mut result = X86IntrinsicType {
                     data,
                     param: param.clone(),
-                })
+                };
+
+                result.update_simd_len();
+                Ok(result)
             }
         }
         // Tile types won't currently reach here, since the intrinsic that involve them

From 4cba53aac2050aa8549b0a8245e840e97a1ca17c Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 24 Sep 2025 22:25:58 +0530
Subject: [PATCH 38/73] chore: accomodate for `immwidth` field for constraints

extras: 1. call update_simd_len() after inferring bit_len for arguments
of certain intrinsics

2. handle the effective bit_len for _mm_mpsadbw_epu8 intrinsic's `imm8`
argument which has only 3 bits that are used
---
 crates/intrinsic-test/src/x86/xml_parser.rs | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index 157a37fc9d..90bafbee54 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -84,7 +84,7 @@ fn xml_to_intrinsic(
         if ty.is_err() {
             None
         } else {
-            let constraint = map_constraints(&param.imm_type);
+            let constraint = map_constraints(&param.imm_type, param.imm_width);
             let arg = Argument::<X86IntrinsicType>::new(
                 i,
                 param.var_name.clone(),
@@ -117,11 +117,20 @@ fn xml_to_intrinsic(
         args[index].ty.bit_len = args[0].ty.bit_len;
     }
 
+    args.iter_mut().for_each(|arg| arg.ty.update_simd_len());
+
+    if name == "_mm_mpsadbw_epu8" {
+        args.iter_mut()
+            .filter(|arg| arg.name.contains("imm8"))
+            .for_each(|arg| arg.ty.bit_len = Some(3));
+    }
+
     let arguments = ArgumentList::<X86IntrinsicType> { args };
 
     if let Err(message) = result {
         return Err(Box::from(message));
     }
+
     Ok(Intrinsic {
         name,
         arguments,

From a42841592285515d7d8ff08f6b4894b790ffb04f Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 25 Sep 2025 00:52:58 +0530
Subject: [PATCH 39/73] feat: defined more load functions that are natively not
 defined (such as arguments with UI16 etype and __m128d type)

---
 crates/intrinsic-test/src/x86/config.rs | 143 ++++++++++++++++++++++++
 crates/intrinsic-test/src/x86/types.rs  |  24 ++++
 2 files changed, 167 insertions(+)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index a199a58ff2..76317db5e4 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -7,6 +7,128 @@ pub const NOTICE: &str = "\
 pub const F16_FORMATTING_DEF: &str = r#"
 use std::arch::x86_64::*;
 
+#[inline]
+unsafe fn _mm_loadu_ph_to___m128i(mem_addr: *const f16) -> __m128i {
+    _mm_castph_si128(_mm_loadu_ph(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_ph_to___m256i(mem_addr: *const f16) -> __m256i {
+    _mm256_castph_si256(_mm256_loadu_ph(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_ph_to___mm512i(mem_addr: *const f16) -> __m512i {
+    _mm512_castph_si512(_mm512_loadu_ph(mem_addr))
+}
+
+
+#[inline]
+unsafe fn _mm_loadu_ps_to___m128h(mem_addr: *const f32) -> __m128h {
+    _mm_castps_ph(_mm_loadu_ps(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_ps_to___m256h(mem_addr: *const f32) -> __m256h {
+    _mm256_castps_ph(_mm256_loadu_ps(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_ps_to___m512h(mem_addr: *const f32) -> __m512h {
+    _mm512_castps_ph(_mm512_loadu_ps(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi16_to___m128d(mem_addr: *const i16) -> __m128d {
+    _mm_castsi128_pd(_mm_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi16_to___m256d(mem_addr: *const i16) -> __m256d {
+    _mm256_castsi256_pd(_mm256_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi16_to___m512d(mem_addr: *const i16) -> __m512d {
+    _mm512_castsi512_pd(_mm512_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi32_to___m128d(mem_addr: *const i32) -> __m128d {
+    _mm_castsi128_pd(_mm_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi32_to___m256d(mem_addr: *const i32) -> __m256d {
+    _mm256_castsi256_pd(_mm256_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi32_to___m512d(mem_addr: *const i32) -> __m512d {
+    _mm512_castsi512_pd(_mm512_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi64_to___m128d(mem_addr: *const i64) -> __m128d {
+    _mm_castsi128_pd(_mm_loadu_epi64(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi64_to___m256d(mem_addr: *const i64) -> __m256d {
+    _mm256_castsi256_pd(_mm256_loadu_epi64(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi64_to___m512d(mem_addr: *const i64) -> __m512d {
+    _mm512_castsi512_pd(_mm512_loadu_epi64(mem_addr))
+}
+
+// === 
+#[inline]
+unsafe fn _mm_loadu_epi16_to___m128(mem_addr: *const i16) -> __m128 {
+    _mm_castsi128_ps(_mm_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi16_to___m256(mem_addr: *const i16) -> __m256 {
+    _mm256_castsi256_ps(_mm256_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi16_to___m512(mem_addr: *const i16) -> __m512 {
+    _mm512_castsi512_ps(_mm512_loadu_epi16(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi32_to___m128(mem_addr: *const i32) -> __m128 {
+    _mm_castsi128_ps(_mm_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi32_to___m256(mem_addr: *const i32) -> __m256 {
+    _mm256_castsi256_ps(_mm256_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi32_to___m512(mem_addr: *const i32) -> __m512 {
+    _mm512_castsi512_ps(_mm512_loadu_epi32(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm_loadu_epi64_to___m128(mem_addr: *const i64) -> __m128 {
+    _mm_castsi128_ps(_mm_loadu_epi64(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm256_loadu_epi64_to___m256(mem_addr: *const i64) -> __m256 {
+    _mm256_castsi256_ps(_mm256_loadu_epi64(mem_addr))
+}
+
+#[inline]
+unsafe fn _mm512_loadu_epi64_to___m512(mem_addr: *const i64) -> __m512 {
+    _mm512_castsi512_ps(_mm512_loadu_epi64(mem_addr))
+}
+
 #[inline]
 fn debug_simd_finish<T: core::fmt::Debug, const N: usize>(
     formatter: &mut core::fmt::Formatter<'_>,
@@ -50,6 +172,13 @@ impl DebugHexF16 for __m128h {
     }
 }
 
+impl DebugHexF16 for __m128i {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 8]>(*self) };
+        debug_simd_finish(f, "__m128i", &array)
+    }
+}
+
 impl DebugHexF16 for __m256h {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 16]>(*self) };
@@ -57,12 +186,26 @@ impl DebugHexF16 for __m256h {
     }
 }
 
+impl DebugHexF16 for __m256i {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 16]>(*self) };
+        debug_simd_finish(f, "__m256i", &array)
+    }
+}
+
 impl DebugHexF16 for __m512h {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 32]>(*self) };
         debug_simd_finish(f, "__m512h", &array)
     }
 }
+
+impl DebugHexF16 for __m512i {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [Hex<f16>; 32]>(*self) };
+        debug_simd_finish(f, "__m512i", &array)
+    }
+}
  "#;
 
 pub const LANE_FUNCTION_HELPERS: &str = r#"
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index b07726656a..e4b6e12876 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -127,6 +127,30 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                 .replace("64", "");
             {
                 let suffix = match (self.bit_len, self.kind) {
+                    (Some(16), TypeKind::Float)
+                        if ["__m128i", "__m256i", "__m512i"]
+                            .contains(&self.param.type_data.as_str()) =>
+                    {
+                        format!("ph_to_{}", self.param.type_data)
+                    }
+                    (Some(32), TypeKind::Float)
+                        if ["__m128h", "__m256h", "__m512h"]
+                            .contains(&self.param.type_data.as_str()) =>
+                    {
+                        format!("ps_to_{}", self.param.type_data)
+                    }
+                    (Some(bit_len @ (16 | 32 | 64)), TypeKind::Int(_) | TypeKind::Mask)
+                        if ["__m128d", "__m256d", "__m512d"]
+                            .contains(&self.param.type_data.as_str()) =>
+                    {
+                        format!("epi{bit_len}_to_{}", self.param.type_data)
+                    }
+                    (Some(bit_len @ (16 | 32 | 64)), TypeKind::Int(_) | TypeKind::Mask)
+                        if ["__m128", "__m256", "__m512"]
+                            .contains(&self.param.type_data.as_str()) =>
+                    {
+                        format!("epi{bit_len}_to_{}", self.param.type_data)
+                    }
                     (Some(bit_len @ (8 | 16 | 32 | 64)), TypeKind::Int(_)) => {
                         format!("epi{bit_len}")
                     }

From c57e9a2c85286c5ad0e2cdeaa7f78b8babb72972 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 25 Sep 2025 00:53:36 +0530
Subject: [PATCH 40/73] chore: corrected the imm-width correction location for
 _mm_mpsadbw_epu8 intrinsic

---
 crates/intrinsic-test/src/x86/xml_parser.rs | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/xml_parser.rs b/crates/intrinsic-test/src/x86/xml_parser.rs
index 90bafbee54..af85118b8a 100644
--- a/crates/intrinsic-test/src/x86/xml_parser.rs
+++ b/crates/intrinsic-test/src/x86/xml_parser.rs
@@ -84,7 +84,12 @@ fn xml_to_intrinsic(
         if ty.is_err() {
             None
         } else {
-            let constraint = map_constraints(&param.imm_type, param.imm_width);
+            let effective_imm_width = if name == "_mm_mpsadbw_epu8" && param.var_name == "imm8" {
+                3
+            } else {
+                param.imm_width
+            };
+            let constraint = map_constraints(&param.imm_type, effective_imm_width);
             let arg = Argument::<X86IntrinsicType>::new(
                 i,
                 param.var_name.clone(),
@@ -119,12 +124,6 @@ fn xml_to_intrinsic(
 
     args.iter_mut().for_each(|arg| arg.ty.update_simd_len());
 
-    if name == "_mm_mpsadbw_epu8" {
-        args.iter_mut()
-            .filter(|arg| arg.name.contains("imm8"))
-            .for_each(|arg| arg.ty.bit_len = Some(3));
-    }
-
     let arguments = ArgumentList::<X86IntrinsicType> { args };
 
     if let Err(message) = result {

From f58777f792bc9ee021872bbd3296bb7bc79c2a9b Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 25 Sep 2025 00:57:01 +0530
Subject: [PATCH 41/73] feat: added exclusion list to intrinsic-test CI
 pipeline

---
 ci/run.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/ci/run.sh b/ci/run.sh
index d8af9b7697..dc5a78723b 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -93,6 +93,7 @@ case ${TARGET} in
         TEST_CPPFLAGS="-fuse-ld=lld -I/usr/include/x86_64-linux-gnu/"
         TEST_CXX_COMPILER="clang++-19"
         TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
+        TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
         export STDARCH_DISABLE_ASSERT_INSTR=1
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"

From d9be63f190e7a55979e693ad7f472b882a90b9a7 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 25 Sep 2025 01:01:40 +0530
Subject: [PATCH 42/73] chore: clean up unused variables

---
 crates/intrinsic-test/src/common/intrinsic_helpers.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index 43a0e3f5d1..c52bccb693 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -282,7 +282,7 @@ impl IntrinsicType {
             }
             IntrinsicType {
                 kind: TypeKind::Vector,
-                bit_len: Some(bit_len @ (128 | 256 | 512)),
+                bit_len: Some(128 | 256 | 512),
                 simd_len,
                 vec_len,
                 ..

From d6f7ca80e30e46ef9989288afd056b18cf309d10 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sat, 27 Sep 2025 15:29:54 +0530
Subject: [PATCH 43/73] feat: moved cast<T1, T2> to architecture-specific
 definitions

---
 crates/intrinsic-test/src/arm/config.rs   |  8 ++++++++
 crates/intrinsic-test/src/common/gen_c.rs | 18 ------------------
 crates/intrinsic-test/src/x86/config.rs   | 13 +++++++++++++
 3 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/config.rs b/crates/intrinsic-test/src/arm/config.rs
index 46706e009e..daef7b9b0e 100644
--- a/crates/intrinsic-test/src/arm/config.rs
+++ b/crates/intrinsic-test/src/arm/config.rs
@@ -8,6 +8,14 @@ pub const POLY128_OSTREAM_DECL: &str = r#"
 std::ostream& operator<<(std::ostream& os, poly128_t value);
 std::ostream& operator<<(std::ostream& os, float16_t value);
 #endif
+
+// T1 is the `To` type, T2 is the `From` type
+template<typename T1, typename T2> T1 cast(T2 x) {{
+  static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same");
+  T1 ret{{}};
+  memcpy(&ret, &x, sizeof(T1));
+  return ret;
+}}
 "#;
 
 pub const POLY128_OSTREAM_DEF: &str = r#"
diff --git a/crates/intrinsic-test/src/common/gen_c.rs b/crates/intrinsic-test/src/common/gen_c.rs
index 965e229da5..04741e4f80 100644
--- a/crates/intrinsic-test/src/common/gen_c.rs
+++ b/crates/intrinsic-test/src/common/gen_c.rs
@@ -122,24 +122,6 @@ pub fn write_mod_cpp<T: IntrinsicTypeDefinition>(
 
     writeln!(w, "{}", forward_declarations)?;
 
-    writeln!(
-        w,
-        r#"
-// T1 is the `To` type, T2 is the `From` type
-template<typename T1, typename T2> T1 cast(T2 x) {{
-  if (std::is_convertible<T2, T1>::value) {{
-      return x;
-  }} else if (sizeof(T1) == sizeof(T2)) {{
-    T1 ret{{}};
-    memcpy(&ret, &x, sizeof(T1));
-    return ret;
-  }} else {{
-    assert("T2 must either be convertable to T1, or have the same size as T1!");
-  }}
-}}
-"#
-    )?;
-
     for intrinsic in intrinsics {
         create_c_test_function(w, intrinsic)?;
     }
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 76317db5e4..cb4c994066 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -269,6 +269,19 @@ std::ostream& operator<<(std::ostream& os, __m512i value) {
     return os;
 }
 
+// T1 is the `To` type, T2 is the `From` type
+template<typename T1, typename T2> T1 cast(T2 x) {{
+  if (std::is_convertible<T2, T1>::value) {{
+      return x;
+  }} else if (sizeof(T1) == sizeof(T2)) {{
+    T1 ret{{}};
+    memcpy(&ret, &x, sizeof(T1));
+    return ret;
+  }} else {{
+    assert("T2 must either be convertable to T1, or have the same size as T1!");
+  }}
+}}
+
 #define _mm512_extract_intrinsic_test_epi8(m, lane) \
     _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
 

From ff776c49750c800d6c20756ba6f8493382f4d00e Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sat, 27 Sep 2025 16:27:13 +0530
Subject: [PATCH 44/73] fix: remove extra brackets for cast definition in
 arm/config.rs

---
 crates/intrinsic-test/src/arm/config.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/config.rs b/crates/intrinsic-test/src/arm/config.rs
index daef7b9b0e..7421a6da38 100644
--- a/crates/intrinsic-test/src/arm/config.rs
+++ b/crates/intrinsic-test/src/arm/config.rs
@@ -10,12 +10,12 @@ std::ostream& operator<<(std::ostream& os, float16_t value);
 #endif
 
 // T1 is the `To` type, T2 is the `From` type
-template<typename T1, typename T2> T1 cast(T2 x) {{
+template<typename T1, typename T2> T1 cast(T2 x) {
   static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same");
-  T1 ret{{}};
+  T1 ret{};
   memcpy(&ret, &x, sizeof(T1));
   return ret;
-}}
+}
 "#;
 
 pub const POLY128_OSTREAM_DEF: &str = r#"

From 1047f810b75152a15a1bf6a6e1a2b9afbe55790c Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sat, 27 Sep 2025 16:34:08 +0530
Subject: [PATCH 45/73] make `std::ostream& operator<<(std::ostream& os,
 float16_t value);` definition available for armv7 also

---
 crates/intrinsic-test/src/arm/config.rs | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/config.rs b/crates/intrinsic-test/src/arm/config.rs
index 7421a6da38..354d8f50b4 100644
--- a/crates/intrinsic-test/src/arm/config.rs
+++ b/crates/intrinsic-test/src/arm/config.rs
@@ -6,9 +6,10 @@ pub const NOTICE: &str = "\
 pub const POLY128_OSTREAM_DECL: &str = r#"
 #ifdef __aarch64__
 std::ostream& operator<<(std::ostream& os, poly128_t value);
-std::ostream& operator<<(std::ostream& os, float16_t value);
 #endif
 
+std::ostream& operator<<(std::ostream& os, float16_t value);
+
 // T1 is the `To` type, T2 is the `From` type
 template<typename T1, typename T2> T1 cast(T2 x) {
   static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same");
@@ -33,6 +34,8 @@ std::ostream& operator<<(std::ostream& os, poly128_t value) {
     return os;
 }
 
+#endif
+
 std::ostream& operator<<(std::ostream& os, float16_t value) {
     uint16_t temp = 0;
     memcpy(&temp, &value, sizeof(float16_t));
@@ -41,7 +44,6 @@ std::ostream& operator<<(std::ostream& os, float16_t value) {
     os << ss.str();
     return os;
 }
-#endif
 "#;
 
 // Format f16 values (and vectors containing them) in a way that is consistent with C.

From cc28ab03665352f8e1f0680a8968a8a720877550 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sat, 27 Sep 2025 23:36:44 +0530
Subject: [PATCH 46/73] feat: add missing_x86.txt to filter out intrinsics that
 cannot be tested currently

---
 crates/intrinsic-test/missing_x86.txt | 874 ++++++++++++++++++++++++++
 1 file changed, 874 insertions(+)
 create mode 100644 crates/intrinsic-test/missing_x86.txt

diff --git a/crates/intrinsic-test/missing_x86.txt b/crates/intrinsic-test/missing_x86.txt
new file mode 100644
index 0000000000..824d36f605
--- /dev/null
+++ b/crates/intrinsic-test/missing_x86.txt
@@ -0,0 +1,874 @@
+# Are defined under a similar name
+
+#__bswap_64
+_bswap64
+
+# Provides pointer to allocated memory, which is difficult to test
+_mm_malloc
+
+# requires target feature 'waitpkg', but would be inlined into function that is compiled without support for 'waitpkg'
+_tpause
+_umwait
+
+# `use of undeclared identifier` error in Clang
+_bit_scan_forward
+_bit_scan_reverse
+_bswap
+_castf32_u32
+_castf64_u64
+_castu32_f32
+_castu64_f64
+_lrotl
+_lrotr
+_may_i_use_cpu_feature
+_may_i_use_cpu_feature_ext
+_mm256_acos_pd
+_mm256_acos_ph
+_mm256_acos_ps
+_mm256_acosh_pd
+_mm256_acosh_ph
+_mm256_acosh_ps
+_mm256_asin_pd
+_mm256_asin_ph
+_mm256_asin_ps
+_mm256_asinh_pd
+_mm256_asinh_ph
+_mm256_asinh_ps
+_mm256_atan_pd
+_mm256_atan_ps
+_mm256_atan_ph
+_mm256_atan2_pd
+_mm256_atan2_ph
+_mm256_atan2_ps
+_mm256_atanh_pd
+_mm256_atanh_ph
+_mm256_atanh_ps
+_mm256_cbrt_pd
+_mm256_cbrt_ph
+_mm256_cbrt_ps
+_mm256_cdfnorm_pd
+_mm256_cdfnorm_ph
+_mm256_cdfnorm_ps
+_mm256_cdfnorminv_pd
+_mm256_cdfnorminv_ph
+_mm256_cdfnorminv_ps
+_mm256_cexp_ps
+_mm256_cos_pd
+_mm256_cos_ph
+_mm256_cos_ps
+_mm256_cosd_pd
+_mm256_cosd_ph
+_mm256_cosd_ps
+_mm256_cosh_pd
+_mm256_cosh_ph
+_mm256_cosh_ps
+_mm256_csqrt_ps
+_mm256_div_epi16
+_mm256_div_epi32
+_mm256_div_epi64
+_mm256_div_epi8
+_mm256_div_epu16
+_mm256_div_epu32
+_mm256_div_epu64
+_mm256_div_epu8
+_mm256_dpbssd_epi32
+_mm256_dpbssds_epi32
+_mm256_dpbsud_epi32
+_mm256_dpbsuds_epi32
+_mm256_dpbuud_epi32
+_mm256_dpbuuds_epi32
+_mm256_dpwsud_epi32
+_mm256_dpwsuds_epi32
+_mm256_dpwusd_epi32
+_mm256_dpwusds_epi32
+_mm256_dpwuud_epi32
+_mm256_dpwuuds_epi32
+_mm256_erf_pd
+_mm256_erf_ps
+_mm256_erfc_pd
+_mm256_erfc_ph
+_mm256_erfc_ps
+_mm256_erfcinv_pd
+_mm256_erfcinv_ph
+_mm256_erfcinv_ps
+_mm256_erfinv_pd
+_mm256_erfinv_ph
+_mm256_erfinv_ps
+_mm256_exp10_pd
+_mm256_exp10_ph
+_mm256_exp10_ps
+_mm256_exp2_pd
+_mm256_exp2_ph
+_mm256_exp2_ps
+_mm256_exp_pd
+_mm256_exp_ph
+_mm256_exp_ps
+_mm256_expm1_pd
+_mm256_expm1_ph
+_mm256_expm1_ps
+_mm256_hypot_pd
+_mm256_hypot_ph
+_mm256_hypot_ps
+_mm256_idiv_epi32
+_mm256_invcbrt_pd
+_mm256_invcbrt_ph
+_mm256_invcbrt_ps
+_mm256_invsqrt_pd
+_mm256_invsqrt_ph
+_mm256_invsqrt_ps
+_mm256_irem_epi32
+_mm256_log10_pd
+_mm256_log10_ph
+_mm256_log10_ps
+_mm256_log1p_pd
+_mm256_log1p_ph
+_mm256_log1p_ps
+_mm256_log2_pd
+_mm256_log2_ph
+_mm256_log2_ps
+_mm256_log_pd
+_mm256_log_ph
+_mm256_log_ps
+_mm256_logb_pd
+_mm256_logb_ph
+_mm256_logb_ps
+_mm256_clog_ps
+_mm256_madd52hi_avx_epu64
+_mm256_madd52lo_avx_epu64
+_mm256_erf_ph
+_mm256_mask_reduce_add_epi16
+_mm256_mask_reduce_add_epi8
+_mm256_mask_reduce_and_epi16
+_mm256_mask_reduce_and_epi8
+_mm256_mask_reduce_max_epi16
+_mm256_mask_reduce_max_epi8
+_mm256_mask_reduce_max_epu16
+_mm256_mask_reduce_max_epu8
+_mm256_mask_reduce_min_epi16
+_mm256_mask_reduce_min_epi8
+_mm256_mask_reduce_min_epu16
+_mm256_mask_reduce_min_epu8
+_mm256_mask_reduce_mul_epi16
+_mm256_mask_reduce_mul_epi8
+_mm256_mask_reduce_or_epi16
+_mm256_mask_reduce_or_epi8
+_mm512_cosd_ph
+_mm512_cosd_ps
+_mm512_cosh_pd
+_mm512_cosh_ph
+_mm512_cosh_ps
+_mm512_div_epi16
+_mm512_div_epi32
+_mm512_div_epi64
+_mm512_div_epi8
+_mm512_div_epu16
+_mm512_div_epu32
+_mm512_div_epu64
+_mm512_div_epu8
+_mm512_erf_pd
+_mm512_erf_ph
+_mm512_erf_ps
+_mm512_erfc_pd
+_mm512_erfc_ph
+_mm512_erfc_ps
+_mm512_erfcinv_pd
+_mm512_erfcinv_ph
+_mm512_erfcinv_ps
+_mm512_erfinv_pd
+_mm512_erfinv_ph
+_mm512_erfinv_ps
+_mm512_exp10_pd
+_mm512_exp10_ph
+_mm512_exp10_ps
+_mm512_exp2_pd
+_mm512_exp2_ph
+_mm512_exp2_ps
+_mm512_exp_pd
+_mm512_exp_ph
+_mm512_exp_ps
+_mm512_expm1_pd
+_mm512_expm1_ph
+_mm512_expm1_ps
+_mm512_floor_ph
+_mm512_hypot_pd
+_mm512_hypot_ph
+_mm512_hypot_ps
+_mm512_invsqrt_pd
+_mm512_invsqrt_ph
+_mm512_invsqrt_ps
+_mm512_log10_pd
+_mm512_log10_ph
+_mm512_log10_ps
+_mm512_log1p_pd
+_mm512_log1p_ph
+_mm512_log1p_ps
+_mm512_log2_pd
+_mm512_log2_ph
+_mm512_log2_ps
+_mm512_log_pd
+_mm512_log_ph
+_mm512_log_ps
+_mm512_logb_pd
+_mm512_logb_ph
+_mm512_logb_ps
+_mm512_mask_acos_pd
+_mm512_mask_acos_ph
+_mm512_mask_acos_ps
+_mm512_mask_acosh_pd
+_mm512_mask_acosh_ph
+_mm512_mask_acosh_ps
+_mm512_mask_asin_pd
+_mm512_mask_asin_ph
+_mm512_mask_asin_ps
+_mm512_mask_asinh_pd
+_mm512_mask_asinh_ph
+_mm512_mask_asinh_ps
+_mm512_mask_atan2_pd
+_mm512_mask_atan2_ps
+_mm512_mask_atan_pd
+_mm512_mask_atan_ph
+_mm512_mask_atan_ph
+_mm512_mask_atanh_pd
+_mm512_mask_atanh_ph
+_mm512_mask_atanh_ps
+_mm512_mask_cbrt_pd
+_mm512_mask_cbrt_ph
+_mm512_mask_cbrt_ps
+_mm512_mask_cdfnorm_pd
+_mm512_mask_cdfnorm_ph
+_mm512_mask_cdfnorm_ps
+_mm512_mask_cdfnorminv_pd
+_mm512_mask_cdfnorminv_ph
+_mm512_mask_cdfnorminv_ps
+_mm512_mask_ceil_ph
+_mm512_mask_cos_pd
+_mm512_mask_cos_ph
+_mm512_mask_cos_ps
+_mm512_mask_cosd_pd
+_mm512_mask_cosd_ph
+_mm512_mask_cosd_ps
+_mm512_mask_cosh_pd
+_mm512_mask_cosh_ph
+_mm512_mask_cosh_ps
+_mm512_mask_atan_ps
+_mm512_cosd_pd
+_mm512_cos_ps
+_mm512_cos_ph
+_mm512_cos_pd
+_mm512_mask_div_epi32
+_mm512_mask_div_epu32
+_mm512_mask_erf_pd
+_mm512_mask_erf_ph
+_mm512_mask_erf_ps
+_mm512_mask_erfc_pd
+_mm512_mask_erfc_ph
+_mm512_mask_erfc_ps
+_mm512_mask_erfcinv_pd
+_mm512_mask_erfcinv_ph
+_mm512_mask_erfcinv_ps
+_mm512_mask_erfinv_pd
+_mm512_mask_erfinv_ph
+_mm512_mask_erfinv_ps
+_mm512_mask_exp10_pd
+_mm512_mask_exp10_ph
+_mm512_mask_exp10_ps
+_mm512_mask_exp2_pd
+_mm512_mask_exp2_ph
+_mm512_mask_exp2_ps
+_mm512_mask_exp_pd
+_mm512_mask_exp_ph
+_mm512_mask_exp_ps
+_mm512_mask_expm1_pd
+_mm512_mask_expm1_ph
+_mm512_mask_expm1_ps
+_mm512_mask_floor_ph
+_mm512_mask_hypot_pd
+_mm512_mask_hypot_ps
+_mm512_mask_invsqrt_pd
+_mm512_mask_invsqrt_ph
+_mm512_mask_invsqrt_ps
+_mm512_mask_log10_pd
+_mm512_mask_log10_ph
+_mm512_mask_log10_ps
+_mm512_mask_log1p_pd
+_mm512_mask_log1p_ph
+_mm512_mask_log1p_ps
+_mm512_mask_log2_pd
+_mm512_mask_log2_ph
+_mm512_mask_log2_ps
+_mm512_mask_log_pd
+_mm512_mask_log_ph
+_mm512_mask_log_ps
+_mm512_mask_logb_pd
+_mm512_mask_logb_ph
+_mm512_mask_logb_ps
+_mm512_mask_nearbyint_pd
+_mm512_mask_nearbyint_ph
+_mm512_mask_nearbyint_ps
+_mm512_mask_pow_pd
+_mm512_mask_pow_ps
+_mm512_mask_recip_pd
+_mm512_mask_recip_ph
+_mm512_mask_recip_ps
+_mm512_mask_rem_epi32
+_mm512_mask_rem_epu32
+_mm512_mask_rint_pd
+_mm512_mask_rint_ph
+_mm512_mask_rint_ps
+_mm512_mask_sin_pd
+_mm512_mask_sin_ph
+_mm512_mask_sin_ps
+_mm512_mask_sind_pd
+_mm512_mask_sind_ph
+_mm512_mask_sind_ps
+_mm512_mask_sinh_pd
+_mm512_mask_sinh_ph
+_mm512_mask_sinh_ps
+_mm512_mask_svml_round_pd
+_mm512_mask_svml_round_ph
+_mm512_mask_tan_pd
+_mm512_mask_tan_ph
+_mm512_mask_tan_ps
+_mm512_mask_tand_pd
+_mm512_mask_tand_ph
+_mm512_mask_tand_ps
+_mm512_mask_tanh_pd
+_mm512_mask_tanh_ph
+_mm512_mask_tanh_ps
+_mm512_mask_trunc_pd
+_mm512_mask_trunc_ph
+_mm512_mask_trunc_ps
+_mm512_nearbyint_pd
+_mm512_nearbyint_ph
+_mm512_nearbyint_ps
+_mm512_pow_pd
+_mm512_pow_ph
+_mm512_pow_ps
+_mm512_recip_pd
+_mm512_recip_ph
+_mm512_recip_ps
+_mm512_rem_epi16
+_mm512_rem_epi32
+_mm512_rem_epi64
+_mm512_rem_epi8
+_mm512_rem_epu16
+_mm512_rem_epu32
+_mm512_rem_epu64
+_mm512_rem_epu8
+_mm512_rint_pd
+_mm512_rint_ph
+_mm512_rint_ps
+_mm512_sin_pd
+_mm512_sin_ph
+_mm512_sin_ps
+_mm512_sind_pd
+_mm512_sind_ph
+_mm512_sind_ps
+_mm512_sinh_pd
+_mm512_sinh_ph
+_mm512_sinh_ps
+_mm512_svml_round_pd
+_mm512_svml_round_ph
+_mm512_tan_pd
+_mm512_tan_ph
+_mm512_tan_ps
+_mm512_tand_pd
+_mm512_tand_ph
+_mm512_tand_ps
+_mm512_tanh_pd
+_mm512_tanh_ph
+_mm512_tanh_ps
+_mm512_trunc_pd
+_mm512_trunc_ph
+_mm512_trunc_ps
+_mm_acos_pd
+_mm_acos_ph
+_mm_acos_ps
+_mm_acosh_pd
+_mm_acosh_ph
+_mm_acosh_ps
+_mm_asin_pd
+_mm_asin_ph
+_mm_asin_ps
+_mm_asinh_pd
+_mm_asinh_ph
+_mm_asinh_ps
+_mm_atan2_pd
+_mm_atan2_ph
+_mm_atan2_ps
+_mm_atan_pd
+_mm_atan_ph
+_mm_atan_ps
+_mm_atanh_pd
+_mm_atanh_ph
+_mm_atanh_ps
+_mm_cbrt_pd
+_mm_cbrt_ph
+_mm_cbrt_ps
+_mm_cdfnorm_pd
+_mm_cdfnorm_ph
+_mm_cdfnorm_ps
+_mm_cdfnorminv_pd
+_mm_cdfnorminv_ph
+_mm_cdfnorminv_ps
+_mm_cexp_ps
+_mm_clog_ps
+_mm_cos_pd
+_mm_cos_ph
+_mm_cos_ps
+_mm_cosd_pd
+_mm_cosd_ph
+_mm_cosd_ps
+_mm_cosh_pd
+_mm_cosh_ph
+_mm_cosh_ps
+_mm_csqrt_ps
+_mm_cvtsd_si64x
+_mm_cvtsi128_si64x
+_mm_cvtsi64x_sd
+_mm_cvtsi64x_si128
+_mm_cvttsd_si64x
+_mm_div_epi16
+_mm_div_epi32
+_mm_div_epi64
+_mm_div_epi8
+_mm_div_epu16
+_mm_div_epu32
+_mm_div_epu64
+_mm_div_epu8
+_mm_dpbssd_epi32
+_mm_dpbssds_epi32
+_mm_dpbsud_epi32
+_mm_dpbsuds_epi32
+_mm_dpbuud_epi32
+_mm_dpbuuds_epi32
+_mm_dpwsud_epi32
+_mm_dpwsuds_epi32
+_mm_dpwusd_epi32
+_mm_dpwusds_epi32
+_mm_dpwuud_epi32
+_mm_dpwuuds_epi32
+_mm_erf_pd
+_mm_erf_ph
+_mm_erf_ps
+_mm_erfc_pd
+_mm_erfc_ph
+_mm_erfc_ps
+_mm_erfcinv_pd
+_mm_erfcinv_ph
+_mm_erfcinv_ps
+_mm_erfinv_pd
+_mm_erfinv_ph
+_mm_erfinv_ps
+_mm_exp10_pd
+_mm_exp10_ph
+_mm_exp10_ps
+_mm_exp2_pd
+_mm_exp2_ph
+_mm_exp2_ps
+_mm_exp_pd
+_mm_exp_ph
+_mm_exp_ps
+_mm_expm1_pd
+_mm_expm1_ph
+_mm_expm1_ps
+_mm_hypot_pd
+_mm_hypot_ph
+_mm_hypot_ps
+_mm_idiv_epi32
+_mm_invcbrt_pd
+_mm_invcbrt_ph
+_mm_invcbrt_ps
+_mm_invsqrt_pd
+_mm_invsqrt_ph
+_mm_invsqrt_ps
+_mm_irem_epi32
+_mm_log10_pd
+_mm_log10_ph
+_mm_log10_ps
+_mm_log1p_pd
+_mm_log1p_ph
+_mm_log1p_ps
+_mm_log2_pd
+_mm_log2_ph
+_mm_log2_ps
+_mm_log_pd
+_mm_log_ph
+_mm_log_ps
+_mm_logb_pd
+_mm_logb_ph
+_mm_logb_ps
+_mm_madd52hi_avx_epu64
+_mm_madd52lo_avx_epu64
+_mm_mask_reduce_add_epi16
+_mm_mask_reduce_add_epi8
+_mm_mask_reduce_and_epi16
+_mm_mask_reduce_and_epi8
+_mm_mask_reduce_max_epi16
+_mm_mask_reduce_max_epi8
+_mm_mask_reduce_max_epu16
+_mm_mask_reduce_max_epu8
+_mm_mask_reduce_min_epi16
+_mm_mask_reduce_min_epi8
+_mm_mask_reduce_min_epu16
+_mm_mask_reduce_min_epu8
+_mm_mask_reduce_mul_epi16
+_mm_mask_reduce_mul_epi8
+_mm_mask_reduce_or_epi16
+_mm_mask_reduce_or_epi8
+_mm_pow_pd
+_mm_pow_ph
+_mm_pow_ps
+_mm_reduce_add_epi16
+_mm_reduce_add_epi8
+_mm_reduce_and_epi16
+_mm_reduce_and_epi8
+_mm_reduce_max_epi16
+_mm_reduce_max_epi8
+_mm_reduce_max_epu16
+_mm_reduce_max_epu8
+_mm_reduce_min_epi16
+_mm_reduce_min_epi8
+_mm_reduce_min_epu16
+_mm_reduce_min_epu8
+_mm_reduce_mul_epi16
+_mm_reduce_mul_epi8
+_mm_reduce_or_epi16
+_mm_reduce_or_epi8
+_mm_rem_epi16
+_mm_rem_epi32
+_mm_rem_epi64
+_mm_rem_epi8
+_mm_rem_epu16
+_mm_rem_epu32
+_mm_rem_epu64
+_mm_rem_epu8
+_mm_sin_pd
+_mm_sin_ph
+_mm_sin_ps
+_mm_sind_pd
+_mm_sind_ph
+_mm_sind_ps
+_mm_sinh_pd
+_mm_sinh_ph
+_mm_sinh_ps
+_mm_sm3msg1_epi32
+_mm_sm3msg2_epi32
+_mm_sm3rnds2_epi32
+_mm_sm4key4_epi32
+_mm_sm4rnds4_epi32
+_mm_svml_ceil_pd
+_mm_svml_ceil_ph
+_mm_svml_ceil_ps
+_mm_svml_floor_pd
+_mm_svml_floor_ph
+_mm_svml_floor_ps
+_mm_svml_round_pd
+_mm_svml_round_ph
+_mm_svml_round_ps
+_mm_svml_sqrt_pd
+_mm_svml_sqrt_ph
+_mm_svml_sqrt_ps
+_mm_tan_pd
+_mm_tan_ph
+_mm_tan_ps
+_mm_tand_pd
+_mm_tand_ph
+_mm_tand_ps
+_mm_tanh_pd
+_mm_tanh_ph
+_mm_tanh_ps
+_mm_trunc_pd
+_mm_trunc_ph
+_mm_trunc_ps
+_mm_udiv_epi32
+_mm_urem_epi32
+_popcnt32
+_popcnt64
+_rdpmc
+_rotl
+_rotl64
+_rotr
+_rotr64
+_rotwl
+_rotwr
+_urdmsr
+
+# Cannot find value in this scope (in Rust testfiles)
+_mm512_set1_pch
+_mm_abs_pi16
+_mm_abs_pi32
+_mm_abs_pi8
+_mm_add_pi16
+_mm_add_pi32
+_mm_add_pi8
+_mm_add_si64
+_mm_adds_pi16
+_mm_adds_pi8
+_mm_adds_pu16
+_mm_adds_pu8
+_mm_alignr_pi8
+_mm_and_si64
+_mm_andnot_si64
+_mm_avg_pu16
+_mm_avg_pu8
+_mm_cmpeq_pi16
+_mm_cmpeq_pi32
+_mm_cmpeq_pi8
+_mm_cmpgt_pi16
+_mm_cmpgt_pi32
+_mm_cmpgt_pi8
+_mm_cvt_pi2ps
+_mm_cvt_ps2pi
+_mm_cvtm64_si64
+_mm_cvtpd_pi32
+_mm_cvtpi16_ps
+_mm_cvtpi32_pd
+_mm_cvtpi32_ps
+_mm_cvtpi32x2_ps
+_mm_cvtpi8_ps
+_mm_cvtps_pi16
+_mm_cvtps_pi32
+_mm_cvtps_pi8
+_mm_cvtpu16_ps
+_mm_cvtpu8_ps
+_mm_cvtsi32_si64
+_mm_cvtsi64_m64
+_mm_cvtsi64_si32
+_mm_cvtt_ps2pi
+_mm_cvttpd_pi32
+_mm512_cbrt_pd
+_mm512_cbrt_ph
+_mm512_cbrt_ps
+_mm512_cdfnorm_pd
+_mm512_cdfnorm_ph
+_mm512_cdfnorm_ps
+_mm512_cdfnorminv_pd
+_mm512_cdfnorminv_ph
+_mm512_cdfnorminv_ps
+_mm512_ceil_pd
+_mm512_ceil_ph
+_mm512_ceil_ps
+_mm512_floor_pd
+_mm512_floor_ps
+_mm512_mask_ceil_pd
+_mm512_mask_ceil_ps
+_mm_max_pi16
+_mm_max_pu8
+_mm_min_pi16
+_mm_min_pu8
+_mm_movemask_pi8
+_mm_movepi64_pi64
+_mm_movpi64_epi64
+_mm_mul_su32
+_mm_mulhi_pi16
+_mm_mulhi_pu16
+_mm_mulhrs_pi16
+_mm_mullo_pi16
+_mm_or_si64
+_mm_packs_pi16
+_mm_packs_pi32
+_mm_packs_pu16
+_mm_popcnt_u32
+_mm_popcnt_u64
+_mm_sad_pu8
+_mm_set1_epi64
+_mm_set1_pch
+_mm_set1_pi16
+_mm_set1_pi32
+_mm_set1_pi8
+_mm_set_epi64
+_mm_set_pi16
+_mm_set_pi32
+_mm_set_pi8
+_mm_setr_epi64
+_mm_setr_pi16
+_mm_setr_pi32
+_mm_setr_pi8
+_mm_shuffle_pi16
+_mm_shuffle_pi8
+_mm_sign_pi16
+_mm_sign_pi32
+_mm_sign_pi8
+_mm_sll_pi16
+_mm_sll_pi32
+_mm_sll_si64
+_mm_slli_pi16
+_mm_slli_pi32
+_mm_slli_si64
+_mm_sra_pi16
+_mm_sra_pi32
+_mm_srai_pi16
+_mm_srai_pi32
+_mm_srl_pi16
+_mm_srl_pi32
+_mm_srl_si64
+_mm_srli_pi16
+_mm_srli_pi32
+_mm_srli_si64
+_mm_sub_pi16
+_mm_sub_pi32
+_mm_sub_pi8
+_mm_sub_si64
+_mm_subs_pi16
+_mm_subs_pi8
+_mm_subs_pu16
+_mm_subs_pu8
+_mm_unpackhi_pi16
+_mm_unpackhi_pi32
+_mm_unpackhi_pi8
+_mm_unpacklo_pi16
+_mm_unpacklo_pi32
+_mm_unpacklo_pi8
+_mm_xor_si64
+_mm256_pow_pd
+_mm256_pow_ph
+_mm256_pow_ps
+_mm256_rem_epi16
+_mm256_rem_epi32
+_mm256_rem_epi64
+_mm256_rem_epi8
+_mm256_rem_epu16
+_mm256_rem_epu32
+_mm256_rem_epu64
+_mm256_rem_epu8
+_mm256_set1_pch
+_mm256_sin_pd
+_mm256_sin_ph
+_mm256_sin_ps
+_mm256_sind_pd
+_mm256_sind_ph
+_mm256_sind_ps
+_mm256_sinh_pd
+_mm256_sinh_ph
+_mm256_sinh_ps
+_mm256_svml_ceil_pd
+_mm256_svml_ceil_ph
+_mm256_svml_ceil_ps
+_mm256_svml_floor_pd
+_mm256_svml_floor_ph
+_mm256_svml_floor_ps
+_mm256_svml_round_pd
+_mm256_svml_round_ph
+_mm256_svml_round_ps
+_mm256_svml_sqrt_pd
+_mm256_svml_sqrt_ph
+_mm256_svml_sqrt_ps
+_mm256_tan_pd
+_mm256_tan_ph
+_mm256_tan_ps
+_mm256_tand_pd
+_mm256_tand_ph
+_mm256_tand_ps
+_mm256_tanh_pd
+_mm256_tanh_ph
+_mm256_tanh_ps
+_mm256_trunc_pd
+_mm256_trunc_ph
+_mm256_trunc_ps
+_mm256_udiv_epi32
+_mm256_urem_epi32
+_mm512_acos_pd
+_mm512_acos_ph
+_mm512_acos_ps
+_mm512_acosh_pd
+_mm512_acosh_ph
+_mm512_acosh_ps
+_mm_cvttps_pi32
+_mm_extract_pi16
+_mm_hadd_pi16
+_mm_hadd_pi32
+_mm_hadds_pi16
+_mm_hsub_pi16
+_mm_hsub_pi32
+_mm_hsubs_pi16
+_mm_insert_pi16
+_mm_madd_pi16
+_mm_maddubs_pi16
+_mm512_asin_pd
+_mm512_asin_ph
+_mm512_asin_ps
+_mm512_asinh_pd
+_mm512_asinh_ph
+_mm512_asinh_ps
+_mm512_atan2_pd
+_mm512_atan2_ph
+_mm512_atan2_ps
+_mm512_atan_pd
+_mm512_atan_ph
+_mm512_atan_ps
+_mm512_atanh_pd
+_mm512_atanh_ph
+_mm512_atanh_ps
+_cvtsh_ss
+_cvtss_sh
+_m_from_int
+_m_from_int64
+_m_packssdw
+_m_packsswb
+_m_packuswb
+_m_paddb
+_m_paddd
+_m_paddsb
+_m_paddsw
+_m_paddusb
+_m_paddusw
+_m_paddw
+_m_pand
+_m_pandn
+_m_pavgb
+_m_pavgw
+_m_pcmpeqb
+_m_pcmpeqd
+_m_pcmpeqw
+_m_pcmpgtb
+_m_pcmpgtd
+_m_pcmpgtw
+_m_pextrw
+_m_pinsrw
+_m_pmaddwd
+_m_pmaxsw
+_m_pmaxub
+_m_pminsw
+_m_pminub
+_m_pmovmskb
+_m_pmulhuw
+_m_pmulhw
+_m_pmullw
+_m_por
+_m_psadbw
+_m_pshufw
+_m_pslld
+_m_pslldi
+_m_psllq
+_m_psllqi
+_m_psllw
+_m_psllwi
+_m_psrad
+_m_psradi
+_m_psraw
+_m_psrawi
+_m_psrld
+_m_psrldi
+_m_psrlq
+_m_psrlqi
+_m_psrlw
+_m_psrlwi
+_m_psubb
+_m_psubd
+_m_psubsb
+_m_psubsw
+_m_psubusb
+_m_psubusw
+_m_psubw
+_m_punpckhbw
+_m_punpckhdq
+_m_punpckhwd
+_m_punpcklbw
+_m_punpckldq
+_m_punpcklwd
+_m_pxor
+_m_to_int
+_m_to_int64
+_mm512_mask_floor_pd
+_mm512_mask_floor_ps
\ No newline at end of file

From 153191f1b99232f41933a18c366103440fc68759 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 28 Sep 2025 01:37:09 +0530
Subject: [PATCH 47/73] feat: added custom helper functions (that helped load
 intrinsic arguments in Rust) to C++ testfiles. Also added extra compilation
 flags

---
 crates/intrinsic-test/src/x86/compile.rs |  2 +
 crates/intrinsic-test/src/x86/config.rs  | 51 ++++++++++++++++++++----
 2 files changed, 46 insertions(+), 7 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index 6eaab86150..c0d2b12d0e 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -24,6 +24,8 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
             "-mavx512dq",
             "-mavx512cd",
             "-mavx512fp16",
+            "-msha512",
+            "-msm4",
             "-ferror-limit=1000",
         ]);
 
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index cb4c994066..778448a3bd 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -270,17 +270,17 @@ std::ostream& operator<<(std::ostream& os, __m512i value) {
 }
 
 // T1 is the `To` type, T2 is the `From` type
-template<typename T1, typename T2> T1 cast(T2 x) {{
-  if (std::is_convertible<T2, T1>::value) {{
+template<typename T1, typename T2> T1 cast(T2 x) {
+  if (std::is_convertible<T2, T1>::value) {
       return x;
-  }} else if (sizeof(T1) == sizeof(T2)) {{
-    T1 ret{{}};
+  } else if (sizeof(T1) == sizeof(T2)) {
+    T1 ret{};
     memcpy(&ret, &x, sizeof(T1));
     return ret;
-  }} else {{
+  } else {
     assert("T2 must either be convertable to T1, or have the same size as T1!");
-  }}
-}}
+  }
+}
 
 #define _mm512_extract_intrinsic_test_epi8(m, lane) \
     _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
@@ -299,6 +299,43 @@ template<typename T1, typename T2> T1 cast(T2 x) {{
 
 #define _mm64_extract_intrinsic_test_epi32(m, lane) \
     _mm_cvtsi64_si32(_mm_srli_si64(m, (lane) * 32))
+    
+// Load f16 (__m128h) and cast to integer (__m128i)
+#define _mm_loadu_ph_to___m128i(mem_addr) _mm_castph_si128(_mm_loadu_ph(mem_addr))
+#define _mm256_loadu_ph_to___m256i(mem_addr) _mm256_castph_si256(_mm256_loadu_ph(mem_addr))
+#define _mm512_loadu_ph_to___m512i(mem_addr) _mm512_castph_si512(_mm512_loadu_ph(mem_addr))
+
+// Load f32 (__m128) and cast to f16 (__m128h)
+#define _mm_loadu_ps_to___m128h(mem_addr) _mm_castps_ph(_mm_loadu_ps(mem_addr))
+#define _mm256_loadu_ps_to___m256h(mem_addr) _mm256_castps_ph(_mm256_loadu_ps(mem_addr))
+#define _mm512_loadu_ps_to___m512h(mem_addr) _mm512_castps_ph(_mm512_loadu_ps(mem_addr))
+
+// Load integer types and cast to double (__m128d, __m256d, __m512d)
+#define _mm_loadu_epi16_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
+#define _mm256_loadu_epi16_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+#define _mm512_loadu_epi16_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+
+#define _mm_loadu_epi32_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
+#define _mm256_loadu_epi32_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+#define _mm512_loadu_epi32_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+
+#define _mm_loadu_epi64_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
+#define _mm256_loadu_epi64_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+#define _mm512_loadu_epi64_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+
+// Load integer types and cast to float (__m128, __m256, __m512)
+#define _mm_loadu_epi16_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
+#define _mm256_loadu_epi16_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+#define _mm512_loadu_epi16_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+
+#define _mm_loadu_epi32_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
+#define _mm256_loadu_epi32_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+#define _mm512_loadu_epi32_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+
+#define _mm_loadu_epi64_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
+#define _mm256_loadu_epi64_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+#define _mm512_loadu_epi64_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+
 "#;
 
 pub const X86_CONFIGURATIONS: &str = r#"

From 527adddff3abbcd2568f57cc72ac4c85d603936a Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 28 Sep 2025 13:24:06 +0530
Subject: [PATCH 48/73] chore: add more compiler flags for compiling x86
 intrinsics in C++

---
 crates/intrinsic-test/src/x86/compile.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index c0d2b12d0e..27fd5d831c 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -26,7 +26,15 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
             "-mavx512fp16",
             "-msha512",
             "-msm4",
+            "-mavxvnni",
+            "-mavx512bitalg",
+            "-mavx512ifma",
+            "-mavx512vbmi",
+            "-mavx512vbmi2",
+            "-mavx512vnni",
+            "-mavx512vpopcntdq",
             "-ferror-limit=1000",
+            "-std=c++17",
         ]);
 
     if !cpp_compiler.contains("clang") {

From 525249f47d8a69fffc3f1b1e070b686ccc1163f9 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Mon, 29 Sep 2025 00:13:53 +0530
Subject: [PATCH 49/73] chore: add verbose cli option to C++ compiler

---
 crates/intrinsic-test/src/common/compile_c.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/common/compile_c.rs b/crates/intrinsic-test/src/common/compile_c.rs
index 258e418165..fa78b332a7 100644
--- a/crates/intrinsic-test/src/common/compile_c.rs
+++ b/crates/intrinsic-test/src/common/compile_c.rs
@@ -119,7 +119,7 @@ impl CppCompilation {
         output: &str,
     ) -> std::io::Result<std::process::Output> {
         let mut cmd = clone_command(&self.0);
-        cmd.args([input, "-c", "-o", output]);
+        cmd.args([input, "-v", "-c", "-o", output]);
         cmd.output()
     }
 

From d9f8159f5a3e8cf25e8b833b426e0b63e1802df2 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Mon, 29 Sep 2025 01:23:15 +0530
Subject: [PATCH 50/73] feat: add clang to dockerfile and change clang++-19 to
 clang++

---
 ci/docker/x86_64-unknown-linux-gnu/Dockerfile | 4 +++-
 ci/run.sh                                     | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
index bbebe2d7fa..a35136a9c1 100644
--- a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
@@ -6,7 +6,9 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   make \
   ca-certificates \
   wget \
-  xz-utils
+  xz-utils \
+  clang \
+  lld
 
 RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-9.58.0-2025-06-16-lin.tar.xz -O sde.tar.xz
 RUN mkdir intel-sde
diff --git a/ci/run.sh b/ci/run.sh
index dc5a78723b..c8dc6a2e8b 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -91,7 +91,7 @@ fi
 case ${TARGET} in
     x86_64-unknown-linux-gnu)
         TEST_CPPFLAGS="-fuse-ld=lld -I/usr/include/x86_64-linux-gnu/"
-        TEST_CXX_COMPILER="clang++-19"
+        TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
         export STDARCH_DISABLE_ASSERT_INSTR=1

From 3f3e3c4fb07822964a15ad3abbcc55c39696b924 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Mon, 29 Sep 2025 01:45:13 +0530
Subject: [PATCH 51/73] fix: add `libstdc++-dev` to fix `iostream not found`
 error

---
 ci/docker/x86_64-unknown-linux-gnu/Dockerfile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
index a35136a9c1..2743896375 100644
--- a/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
+++ b/ci/docker/x86_64-unknown-linux-gnu/Dockerfile
@@ -8,6 +8,8 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
   wget \
   xz-utils \
   clang \
+  libstdc++-14-dev \
+  build-essential \
   lld
 
 RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-9.58.0-2025-06-16-lin.tar.xz -O sde.tar.xz

From 72750f7bce65c6bf1e49a84591cb420f37196b12 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Mon, 29 Sep 2025 16:22:37 +0530
Subject: [PATCH 52/73] fix: making compilation step run one by one to prevent
 the process from being killed. Also separated declarations and definitions
 for C++ testfiles.

---
 crates/intrinsic-test/src/common/mod.rs |  12 +-
 crates/intrinsic-test/src/x86/config.rs | 165 ++++++++++++------------
 crates/intrinsic-test/src/x86/mod.rs    |   4 +-
 3 files changed, 99 insertions(+), 82 deletions(-)

diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index 37a48654e4..f38f0e5a7c 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -72,19 +72,29 @@ pub trait SupportedArchitectureTest {
                     return Err(format!("Error writing to mod_{i}.cpp: {error:?}"));
                 }
 
+                println!("Finished writing mod_{i}.cpp");
+
+                Ok(())
+            })
+            .collect::<Result<(), String>>()
+            .unwrap();
+
+        (0..chunk_count)
+            .map(|i| {
                 // compile this cpp file into a .o file.
                 //
                 // This is done because `cpp_compiler_wrapped` is None when
                 // the --generate-only flag is passed
+                println!("compiling mod_{i}.cpp");
                 if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
                     let compile_output = cpp_compiler
                         .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"));
 
+                    println!("finished compiling mod_{i}.cpp");
                     if let Err(compile_error) = compile_output {
                         return Err(format!("Error compiling mod_{i}.cpp: {compile_error:?}"));
                     }
                 }
-
                 Ok(())
             })
             .collect::<Result<(), String>>()
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 778448a3bd..159851c104 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -208,18 +208,93 @@ impl DebugHexF16 for __m512i {
 }
  "#;
 
-pub const LANE_FUNCTION_HELPERS: &str = r#"
-typedef _Float16 float16_t;
-typedef float float32_t;
-typedef double float64_t;
-
-#define __int64 long long
-#define __int32 int
+pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#"
+#ifndef X86_DECLARATIONS
+#define X86_DECLARATIONS
+    typedef _Float16 float16_t;
+    typedef float float32_t;
+    typedef double float64_t;
+    
+    #define __int64 long long
+    #define __int32 int
 
-std::ostream& operator<<(std::ostream& os, _Float16 value);
-std::ostream& operator<<(std::ostream& os, __m128i value);
-std::ostream& operator<<(std::ostream& os, __m256i value);
-std::ostream& operator<<(std::ostream& os, __m512i value);
+    std::ostream& operator<<(std::ostream& os, _Float16 value);
+    std::ostream& operator<<(std::ostream& os, __m128i value);
+    std::ostream& operator<<(std::ostream& os, __m256i value);
+    std::ostream& operator<<(std::ostream& os, __m512i value);
+    
+    #define _mm512_extract_intrinsic_test_epi8(m, lane) \
+        _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
+    
+    #define _mm512_extract_intrinsic_test_epi16(m, lane) \
+        _mm_extract_epi16(_mm512_extracti64x2_epi64((m), (lane) / 8), (lane) % 8)
+    
+    #define _mm512_extract_intrinsic_test_epi32(m, lane) \
+        _mm_extract_epi32(_mm512_extracti64x2_epi64((m), (lane) / 4), (lane) % 4)
+    
+    #define _mm512_extract_intrinsic_test_epi64(m, lane) \
+        _mm_extract_epi64(_mm512_extracti64x2_epi64((m), (lane) / 2), (lane) % 2)
+    
+    #define _mm64_extract_intrinsic_test_epi8(m, lane) \
+        ((_mm_extract_pi16((m), (lane) / 2) >> (((lane) % 2) * 8)) & 0xFF)
+    
+    #define _mm64_extract_intrinsic_test_epi32(m, lane) \
+        _mm_cvtsi64_si32(_mm_srli_si64(m, (lane) * 32))
+        
+    // Load f16 (__m128h) and cast to integer (__m128i)
+    #define _mm_loadu_ph_to___m128i(mem_addr) _mm_castph_si128(_mm_loadu_ph(mem_addr))
+    #define _mm256_loadu_ph_to___m256i(mem_addr) _mm256_castph_si256(_mm256_loadu_ph(mem_addr))
+    #define _mm512_loadu_ph_to___m512i(mem_addr) _mm512_castph_si512(_mm512_loadu_ph(mem_addr))
+    
+    // Load f32 (__m128) and cast to f16 (__m128h)
+    #define _mm_loadu_ps_to___m128h(mem_addr) _mm_castps_ph(_mm_loadu_ps(mem_addr))
+    #define _mm256_loadu_ps_to___m256h(mem_addr) _mm256_castps_ph(_mm256_loadu_ps(mem_addr))
+    #define _mm512_loadu_ps_to___m512h(mem_addr) _mm512_castps_ph(_mm512_loadu_ps(mem_addr))
+    
+    // Load integer types and cast to double (__m128d, __m256d, __m512d)
+    #define _mm_loadu_epi16_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
+    #define _mm256_loadu_epi16_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+    #define _mm512_loadu_epi16_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+    
+    #define _mm_loadu_epi32_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
+    #define _mm256_loadu_epi32_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+    #define _mm512_loadu_epi32_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+    
+    #define _mm_loadu_epi64_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
+    #define _mm256_loadu_epi64_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+    #define _mm512_loadu_epi64_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+    
+    // Load integer types and cast to float (__m128, __m256, __m512)
+    #define _mm_loadu_epi16_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
+    #define _mm256_loadu_epi16_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+    #define _mm512_loadu_epi16_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+    
+    #define _mm_loadu_epi32_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
+    #define _mm256_loadu_epi32_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+    #define _mm512_loadu_epi32_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+    
+    #define _mm_loadu_epi64_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
+    #define _mm256_loadu_epi64_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
+    #define _mm512_loadu_epi64_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
+    
+    
+    // T1 is the `To` type, T2 is the `From` type
+    template<typename T1, typename T2> T1 cast(T2 x) {
+      if constexpr (std::is_convertible_v<T2, T1>) {
+          return x;
+      } else if constexpr (sizeof(T1) == sizeof(T2)) {
+        T1 ret{};
+        std::memcpy(&ret, &x, sizeof(T1));
+        return ret;
+      } else {
+        static_assert(sizeof(T1) == sizeof(T2) || std::is_convertible_v<T2, T1>,
+                              "T2 must either be convertible to T1, or have the same size as T1!");
+        return T1{};
+      }
+    }
+#endif
+"#;
+pub const PLATFORM_C_DEFINITIONS: &str = r#"
 
 std::ostream& operator<<(std::ostream& os, _Float16 value) {
     uint16_t temp = 0;
@@ -268,74 +343,6 @@ std::ostream& operator<<(std::ostream& os, __m512i value) {
     os << ss.str();
     return os;
 }
-
-// T1 is the `To` type, T2 is the `From` type
-template<typename T1, typename T2> T1 cast(T2 x) {
-  if (std::is_convertible<T2, T1>::value) {
-      return x;
-  } else if (sizeof(T1) == sizeof(T2)) {
-    T1 ret{};
-    memcpy(&ret, &x, sizeof(T1));
-    return ret;
-  } else {
-    assert("T2 must either be convertable to T1, or have the same size as T1!");
-  }
-}
-
-#define _mm512_extract_intrinsic_test_epi8(m, lane) \
-    _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
-
-#define _mm512_extract_intrinsic_test_epi16(m, lane) \
-    _mm_extract_epi16(_mm512_extracti64x2_epi64((m), (lane) / 8), (lane) % 8)
-
-#define _mm512_extract_intrinsic_test_epi32(m, lane) \
-    _mm_extract_epi32(_mm512_extracti64x2_epi64((m), (lane) / 4), (lane) % 4)
-
-#define _mm512_extract_intrinsic_test_epi64(m, lane) \
-    _mm_extract_epi64(_mm512_extracti64x2_epi64((m), (lane) / 2), (lane) % 2)
-
-#define _mm64_extract_intrinsic_test_epi8(m, lane) \
-    ((_mm_extract_pi16((m), (lane) / 2) >> (((lane) % 2) * 8)) & 0xFF)
-
-#define _mm64_extract_intrinsic_test_epi32(m, lane) \
-    _mm_cvtsi64_si32(_mm_srli_si64(m, (lane) * 32))
-    
-// Load f16 (__m128h) and cast to integer (__m128i)
-#define _mm_loadu_ph_to___m128i(mem_addr) _mm_castph_si128(_mm_loadu_ph(mem_addr))
-#define _mm256_loadu_ph_to___m256i(mem_addr) _mm256_castph_si256(_mm256_loadu_ph(mem_addr))
-#define _mm512_loadu_ph_to___m512i(mem_addr) _mm512_castph_si512(_mm512_loadu_ph(mem_addr))
-
-// Load f32 (__m128) and cast to f16 (__m128h)
-#define _mm_loadu_ps_to___m128h(mem_addr) _mm_castps_ph(_mm_loadu_ps(mem_addr))
-#define _mm256_loadu_ps_to___m256h(mem_addr) _mm256_castps_ph(_mm256_loadu_ps(mem_addr))
-#define _mm512_loadu_ps_to___m512h(mem_addr) _mm512_castps_ph(_mm512_loadu_ps(mem_addr))
-
-// Load integer types and cast to double (__m128d, __m256d, __m512d)
-#define _mm_loadu_epi16_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
-#define _mm256_loadu_epi16_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
-#define _mm512_loadu_epi16_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
-
-#define _mm_loadu_epi32_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
-#define _mm256_loadu_epi32_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
-#define _mm512_loadu_epi32_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
-
-#define _mm_loadu_epi64_to___m128d(mem_addr) _mm_castsi128_pd(_mm_loadu_si128((__m128i const*)(mem_addr)))
-#define _mm256_loadu_epi64_to___m256d(mem_addr) _mm256_castsi256_pd(_mm256_loadu_si256((__m256i const*)(mem_addr)))
-#define _mm512_loadu_epi64_to___m512d(mem_addr) _mm512_castsi512_pd(_mm512_loadu_si512((__m512i const*)(mem_addr)))
-
-// Load integer types and cast to float (__m128, __m256, __m512)
-#define _mm_loadu_epi16_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
-#define _mm256_loadu_epi16_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
-#define _mm512_loadu_epi16_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
-
-#define _mm_loadu_epi32_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
-#define _mm256_loadu_epi32_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
-#define _mm512_loadu_epi32_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
-
-#define _mm_loadu_epi64_to___m128(mem_addr) _mm_castsi128_ps(_mm_loadu_si128((__m128i const*)(mem_addr)))
-#define _mm256_loadu_epi64_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
-#define _mm512_loadu_epi64_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
-
 "#;
 
 pub const X86_CONFIGURATIONS: &str = r#"
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index d5ebd960b3..1eac6fb5f9 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -37,8 +37,8 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
     const NOTICE: &str = config::NOTICE;
 
     const PLATFORM_C_HEADERS: &[&str] = &["immintrin.h", "cstddef", "cstdint"];
-    const PLATFORM_C_DEFINITIONS: &str = config::LANE_FUNCTION_HELPERS;
-    const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::LANE_FUNCTION_HELPERS;
+    const PLATFORM_C_DEFINITIONS: &str = config::PLATFORM_C_DEFINITIONS;
+    const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::PLATFORM_C_FORWARD_DECLARATIONS;
 
     const PLATFORM_RUST_DEFINITIONS: &str = config::F16_FORMATTING_DEF;
     const PLATFORM_RUST_CFGS: &str = config::X86_CONFIGURATIONS;

From f188d95948c698510069be91d6863f69929d0b3e Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 30 Sep 2025 01:38:52 +0530
Subject: [PATCH 53/73] feat: attempting compilation of smaller chunks for
 faster parallel processing

---
 crates/intrinsic-test/src/common/mod.rs | 23 +++++++++--------------
 1 file changed, 9 insertions(+), 14 deletions(-)

diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index f38f0e5a7c..67bc81f99c 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -49,7 +49,7 @@ pub trait SupportedArchitectureTest {
     fn cpp_compilation(&self) -> Option<CppCompilation>;
 
     fn build_c_file(&self) -> bool {
-        let (chunk_size, chunk_count) = chunk_info(self.intrinsics().len());
+        let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 100);
 
         let cpp_compiler_wrapped = self.cpp_compilation();
 
@@ -72,15 +72,6 @@ pub trait SupportedArchitectureTest {
                     return Err(format!("Error writing to mod_{i}.cpp: {error:?}"));
                 }
 
-                println!("Finished writing mod_{i}.cpp");
-
-                Ok(())
-            })
-            .collect::<Result<(), String>>()
-            .unwrap();
-
-        (0..chunk_count)
-            .map(|i| {
                 // compile this cpp file into a .o file.
                 //
                 // This is done because `cpp_compiler_wrapped` is None when
@@ -135,7 +126,7 @@ pub trait SupportedArchitectureTest {
     fn build_rust_file(&self) -> bool {
         std::fs::create_dir_all("rust_programs/src").unwrap();
 
-        let (chunk_size, chunk_count) = chunk_info(self.intrinsics().len());
+        let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 100);
 
         let mut cargo = File::create("rust_programs/Cargo.toml").unwrap();
         write_bin_cargo_toml(&mut cargo, chunk_count).unwrap();
@@ -205,9 +196,13 @@ pub trait SupportedArchitectureTest {
     }
 }
 
-pub fn chunk_info(intrinsic_count: usize) -> (usize, usize) {
-    let available_parallelism = std::thread::available_parallelism().unwrap().get();
-    let chunk_size = intrinsic_count.div_ceil(Ord::min(available_parallelism, intrinsic_count));
+// pub fn chunk_info(intrinsic_count: usize) -> (usize, usize) {
+//     let available_parallelism = std::thread::available_parallelism().unwrap().get();
+//     let chunk_size = intrinsic_count.div_ceil(Ord::min(available_parallelism, intrinsic_count));
+
+//     (chunk_size, intrinsic_count.div_ceil(chunk_size))
+// }
 
+pub fn manual_chunk(intrinsic_count: usize, chunk_size: usize) -> (usize, usize) {
     (chunk_size, intrinsic_count.div_ceil(chunk_size))
 }

From 4cb147070880b0fd27c9973767a8032cb2c5ffcc Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Tue, 30 Sep 2025 14:32:14 +0530
Subject: [PATCH 54/73] feat: add c_programs to PATH and increase chunk size to
 400

---
 ci/run.sh                               | 2 ++
 crates/intrinsic-test/src/common/mod.rs | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/ci/run.sh b/ci/run.sh
index c8dc6a2e8b..a74769c56d 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -95,6 +95,8 @@ case ${TARGET} in
         TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
         export STDARCH_DISABLE_ASSERT_INSTR=1
+        PATH="$PATH":"$(pwd)"/c_programs
+        export PATH
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
         cargo_test "${PROFILE}"
diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index 67bc81f99c..86a7876807 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -49,7 +49,7 @@ pub trait SupportedArchitectureTest {
     fn cpp_compilation(&self) -> Option<CppCompilation>;
 
     fn build_c_file(&self) -> bool {
-        let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 100);
+        let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 400);
 
         let cpp_compiler_wrapped = self.cpp_compilation();
 
@@ -126,7 +126,7 @@ pub trait SupportedArchitectureTest {
     fn build_rust_file(&self) -> bool {
         std::fs::create_dir_all("rust_programs/src").unwrap();
 
-        let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 100);
+        let (chunk_size, chunk_count) = manual_chunk(self.intrinsics().len(), 400);
 
         let mut cargo = File::create("rust_programs/Cargo.toml").unwrap();
         write_bin_cargo_toml(&mut cargo, chunk_count).unwrap();

From 41263b47f497bce2762bed8b0059b6a0ba9779cd Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Fri, 3 Oct 2025 01:17:03 +0530
Subject: [PATCH 55/73] feat: display __mmask8 values so that non-utf8 values
 are not displayed

---
 crates/intrinsic-test/src/x86/config.rs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 159851c104..2f859af464 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -222,6 +222,7 @@ pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#"
     std::ostream& operator<<(std::ostream& os, __m128i value);
     std::ostream& operator<<(std::ostream& os, __m256i value);
     std::ostream& operator<<(std::ostream& os, __m512i value);
+    std::ostream& operator<<(std::ostream& os, __mmask8 value);
     
     #define _mm512_extract_intrinsic_test_epi8(m, lane) \
         _mm_extract_epi8(_mm512_extracti64x2_epi64((m), (lane) / 16), (lane) % 16)
@@ -343,6 +344,11 @@ std::ostream& operator<<(std::ostream& os, __m512i value) {
     os << ss.str();
     return os;
 }
+
+std::ostream& operator<<(std::ostream& os, __mmask8 value) {
+    os << static_cast<int>(value);
+    return os;
+}
 "#;
 
 pub const X86_CONFIGURATIONS: &str = r#"

From b68d5575a4ca0ec94ac98591d9a5d50ff7341ab4 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Fri, 3 Oct 2025 18:39:53 +0530
Subject: [PATCH 56/73] feat: add formatting for __m128i, __m256i, __m512i
 types that is similar to C++ version of the same.

---
 crates/intrinsic-test/src/common/gen_rust.rs  |  3 +-
 crates/intrinsic-test/src/common/intrinsic.rs | 16 +------
 .../src/common/intrinsic_helpers.rs           | 18 ++++++++
 crates/intrinsic-test/src/x86/config.rs       | 44 ++++++++++++++++++-
 crates/intrinsic-test/src/x86/types.rs        | 12 +++++
 5 files changed, 75 insertions(+), 18 deletions(-)

diff --git a/crates/intrinsic-test/src/common/gen_rust.rs b/crates/intrinsic-test/src/common/gen_rust.rs
index 3b330879e0..27f49a37b1 100644
--- a/crates/intrinsic-test/src/common/gen_rust.rs
+++ b/crates/intrinsic-test/src/common/gen_rust.rs
@@ -4,7 +4,6 @@ use std::process::Command;
 use crate::common::intrinsic::Intrinsic;
 
 use super::indentation::Indentation;
-use super::intrinsic::format_f16_return_value;
 use super::intrinsic_helpers::IntrinsicTypeDefinition;
 
 // The number of times each intrinsic will be called.
@@ -233,7 +232,6 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
         }
     }
 
-    let return_value = format_f16_return_value(intrinsic);
     let indentation2 = indentation.nested();
     let indentation3 = indentation2.nested();
     writeln!(
@@ -250,6 +248,7 @@ pub fn generate_rust_test_loop<T: IntrinsicTypeDefinition>(
             }}",
         loaded_args = intrinsic.arguments.load_values_rust(indentation3),
         args = intrinsic.arguments.as_call_param_rust(),
+        return_value = intrinsic.results.print_result_rust(),
     )
 }
 
diff --git a/crates/intrinsic-test/src/common/intrinsic.rs b/crates/intrinsic-test/src/common/intrinsic.rs
index 95276d19b7..81f6d6d8b5 100644
--- a/crates/intrinsic-test/src/common/intrinsic.rs
+++ b/crates/intrinsic-test/src/common/intrinsic.rs
@@ -1,5 +1,5 @@
 use super::argument::ArgumentList;
-use super::intrinsic_helpers::{IntrinsicTypeDefinition, TypeKind};
+use super::intrinsic_helpers::IntrinsicTypeDefinition;
 
 /// An intrinsic
 #[derive(Debug, PartialEq, Clone)]
@@ -16,17 +16,3 @@ pub struct Intrinsic<T: IntrinsicTypeDefinition> {
     /// Any architecture-specific tags.
     pub arch_tags: Vec<String>,
 }
-
-pub fn format_f16_return_value<T: IntrinsicTypeDefinition>(intrinsic: &Intrinsic<T>) -> String {
-    // the `intrinsic-test` crate compares the output of C and Rust intrinsics. Currently, It uses
-    // a string representation of the output value to compare. In C, f16 values are currently printed
-    // as hexadecimal integers. Since https://github.com/rust-lang/rust/pull/127013, rust does print
-    // them as decimal floating point values. To keep the intrinsics tests working, for now, format
-    // vectors containing f16 values like C prints them.
-    let return_value = match intrinsic.results.kind() {
-        TypeKind::Float if intrinsic.results.inner_size() == 16 => "debug_f16(__return_value)",
-        _ => "format_args!(\"{__return_value:.150?}\")",
-    };
-
-    String::from(return_value)
-}
diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index c52bccb693..c0b9ed2535 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -365,6 +365,24 @@ pub trait IntrinsicTypeDefinition: Deref<Target = IntrinsicType> {
     /// there is an int i in scope which is the current pass number.
     fn print_result_c(&self, indentation: Indentation, additional: &str) -> String;
 
+    /// Generates a std::cout for the intrinsics results that will match the
+    /// rust debug output format for the return type. The generated line assumes
+    /// there is an int i in scope which is the current pass number.
+    ///
+    /// The `intrinsic-test` crate compares the output of C and Rust intrinsics. Currently, It uses
+    /// a string representation of the output value to compare. In C, f16 values are currently printed
+    /// as hexadecimal integers. Since https://github.com/rust-lang/rust/pull/127013, rust does print
+    /// them as decimal floating point values. To keep the intrinsics tests working, for now, format
+    /// vectors containing f16 values like C prints them.
+    fn print_result_rust(&self) -> String {
+        let return_value = match self.kind() {
+            TypeKind::Float if self.inner_size() == 16 => "debug_f16(__return_value)",
+            _ => "format_args!(\"{__return_value:.150?}\")",
+        };
+
+        String::from(return_value)
+    }
+
     /// To enable architecture-specific logic
     fn rust_scalar_type(&self) -> String {
         format!(
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 2f859af464..bf2a37d78e 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -206,7 +206,49 @@ impl DebugHexF16 for __m512i {
         debug_simd_finish(f, "__m512i", &array)
     }
 }
- "#;
+
+trait DebugI16 {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result;
+}
+
+impl DebugI16 for i16 {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{}", self)
+    }
+}
+
+impl DebugI16 for __m128i {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [i16; 8]>(*self) };
+        debug_simd_finish(f, "__m128i", &array)
+    }
+}
+
+impl DebugI16 for __m256i {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [i16; 16]>(*self) };
+        debug_simd_finish(f, "__m256i", &array)
+    }
+}
+
+impl DebugI16 for __m512i {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let array = unsafe { core::mem::transmute::<_, [i16; 32]>(*self) };
+        debug_simd_finish(f, "__m512i", &array)
+    }
+}
+
+fn debug_i16<T: DebugI16>(x: T) -> impl core::fmt::Debug {
+    struct DebugWrapper<T>(T);
+    impl<T: DebugI16> core::fmt::Debug for DebugWrapper<T> {
+        fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+            self.0.fmt(f)
+        }
+    }
+    DebugWrapper(x)
+}
+
+"#;
 
 pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#"
 #ifndef X86_DECLARATIONS
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index e4b6e12876..5631a01824 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -292,6 +292,18 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
         };
         format!("{prefix}{bits}")
     }
+
+    fn print_result_rust(&self) -> String {
+        let return_value = match self.kind() {
+            TypeKind::Float if self.inner_size() == 16 => "debug_f16(__return_value)",
+            _ if ["__m128i", "__m256i", "__m512i"].contains(&self.param.type_data.as_str()) => {
+                "debug_i16(__return_value)"
+            }
+            _ => "format_args!(\"{__return_value:.150?}\")",
+        };
+
+        String::from(return_value)
+    }
 }
 
 impl X86IntrinsicType {

From e13929947ea5fcd423c1d99478bc07196f7e5972 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Mon, 6 Oct 2025 00:18:44 +0530
Subject: [PATCH 57/73] feat: make the debug_i16 into a generic debug_as
 function that adapts to base type

---
 crates/intrinsic-test/src/x86/config.rs | 54 ++++++++++++-------------
 crates/intrinsic-test/src/x86/types.rs  | 12 +++---
 2 files changed, 34 insertions(+), 32 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index bf2a37d78e..bf9f066404 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -207,45 +207,45 @@ impl DebugHexF16 for __m512i {
     }
 }
 
-trait DebugI16 {
+trait DebugAs<T> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result;
 }
 
-impl DebugI16 for i16 {
+impl<T: core::fmt::Display> DebugAs<T> for T {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "{}", self)
     }
 }
 
-impl DebugI16 for __m128i {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [i16; 8]>(*self) };
-        debug_simd_finish(f, "__m128i", &array)
-    }
-}
-
-impl DebugI16 for __m256i {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [i16; 16]>(*self) };
-        debug_simd_finish(f, "__m256i", &array)
-    }
-}
-
-impl DebugI16 for __m512i {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        let array = unsafe { core::mem::transmute::<_, [i16; 32]>(*self) };
-        debug_simd_finish(f, "__m512i", &array)
-    }
-}
-
-fn debug_i16<T: DebugI16>(x: T) -> impl core::fmt::Debug {
-    struct DebugWrapper<T>(T);
-    impl<T: DebugI16> core::fmt::Debug for DebugWrapper<T> {
+macro_rules! impl_debug_as {
+    ($simd:ty, $name:expr, $bits:expr, [$($type:ty),+]) => {
+        $(
+            impl DebugAs<$type> for $simd {
+                fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+                    const ELEMENT_BITS: usize = core::mem::size_of::<$type>() * 8;
+                    const NUM_ELEMENTS: usize = $bits / ELEMENT_BITS;
+                    let array = unsafe { core::mem::transmute::<_, [$type; NUM_ELEMENTS]>(*self) };
+                    debug_simd_finish(f, $name, &array)
+                }
+            }
+        )+
+    };
+}
+
+impl_debug_as!(__m128i, "__m128i", 128, [u8, i8, u16, i16, u32, i32, u64, i64]);
+impl_debug_as!(__m256i, "__m256i", 256, [u8, i8, u16, i16, u32, i32, u64, i64]);
+impl_debug_as!(__m512i, "__m512i", 512, [u8, i8, u16, i16, u32, i32, u64, i64]);
+
+fn debug_as<V, T>(x: V) -> impl core::fmt::Debug 
+where V: DebugAs<T>
+{
+    struct DebugWrapper<V, T>(V, core::marker::PhantomData<T>);
+    impl<V: DebugAs<T>, T> core::fmt::Debug for DebugWrapper<V, T> {
         fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
             self.0.fmt(f)
         }
     }
-    DebugWrapper(x)
+    DebugWrapper(x, core::marker::PhantomData)
 }
 
 "#;
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 5631a01824..94600c989d 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -295,14 +295,16 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
 
     fn print_result_rust(&self) -> String {
         let return_value = match self.kind() {
-            TypeKind::Float if self.inner_size() == 16 => "debug_f16(__return_value)",
-            _ if ["__m128i", "__m256i", "__m512i"].contains(&self.param.type_data.as_str()) => {
-                "debug_i16(__return_value)"
+            TypeKind::Float if self.inner_size() == 16 => "debug_f16(__return_value)".to_string(),
+            TypeKind::Int(_)
+                if ["__m128i", "__m256i", "__m512i"].contains(&self.param.type_data.as_str()) =>
+            {
+                format!("debug_as::<_, u{}>(__return_value)", self.inner_size())
             }
-            _ => "format_args!(\"{__return_value:.150?}\")",
+            _ => "format_args!(\"{__return_value:.150?}\")".to_string(),
         };
 
-        String::from(return_value)
+        return_value
     }
 }
 

From c2294ff6a1a2b169badd4da5011b788fbec6cf2a Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 8 Oct 2025 18:14:18 +0530
Subject: [PATCH 58/73] feat: casting the results of the lane function by
 preserving the bits instead of letting C++ do it (and potentially change the
 bits)

---
 crates/intrinsic-test/src/arm/types.rs        | 19 +++++-------
 .../src/common/intrinsic_helpers.rs           | 29 ++++++++++++-------
 crates/intrinsic-test/src/x86/types.rs        | 22 +++++---------
 3 files changed, 34 insertions(+), 36 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/types.rs b/crates/intrinsic-test/src/arm/types.rs
index e86a2c5189..c798cbe42d 100644
--- a/crates/intrinsic-test/src/arm/types.rs
+++ b/crates/intrinsic-test/src/arm/types.rs
@@ -112,12 +112,10 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
                         ty = self.c_single_vector_type(),
                         lanes = (0..self.num_lanes())
                             .map(move |idx| -> std::string::String {
+                                let lane_fn = self.get_lane_function();
+                                let final_cast = self.generate_final_type_cast();
                                 format!(
-                                    "{cast}{lane_fn}(__return_value.val[{vector}], {lane})",
-                                    cast = self.c_promotion(),
-                                    lane_fn = self.get_lane_function(),
-                                    lane = idx,
-                                    vector = vector,
+                                    "{final_cast}{lane_fn}(__return_value.val[{vector}], {idx})"
                                 )
                             })
                             .collect::<Vec<_>>()
@@ -129,12 +127,9 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
         } else if self.num_lanes() > 1 {
             (0..self.num_lanes())
                 .map(|idx| -> std::string::String {
-                    format!(
-                        "{cast}{lane_fn}(__return_value, {lane})",
-                        cast = self.c_promotion(),
-                        lane_fn = self.get_lane_function(),
-                        lane = idx
-                    )
+                    let lane_fn = self.get_lane_function();
+                    let final_cast = self.generate_final_type_cast();
+                    format!("{final_cast}{lane_fn}(__return_value, {idx})")
                 })
                 .collect::<Vec<_>>()
                 .join(r#" << ", " << "#)
@@ -150,7 +145,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
                     TypeKind::Poly => format!("poly{}_t", self.inner_size()),
                     ty => todo!("print_result_c - Unknown type: {:#?}", ty),
                 },
-                promote = self.c_promotion(),
+                promote = self.generate_final_type_cast(),
             )
         };
 
diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index c0b9ed2535..aa8613206e 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -173,9 +173,9 @@ impl IntrinsicType {
                 bit_len: Some(8),
                 ..
             } => match kind {
-                TypeKind::Int(Sign::Signed) => "(int)",
-                TypeKind::Int(Sign::Unsigned) => "(unsigned int)",
-                TypeKind::Poly => "(unsigned int)(uint8_t)",
+                TypeKind::Int(Sign::Signed) => "int",
+                TypeKind::Int(Sign::Unsigned) => "unsigned int",
+                TypeKind::Poly => "uint8_t",
                 _ => "",
             },
             IntrinsicType {
@@ -184,9 +184,9 @@ impl IntrinsicType {
                 ..
             } => match bit_len {
                 8 => unreachable!("handled above"),
-                16 => "(uint16_t)",
-                32 => "(uint32_t)",
-                64 => "(uint64_t)",
+                16 => "uint16_t",
+                32 => "uint32_t",
+                64 => "uint64_t",
                 128 => "",
                 _ => panic!("invalid bit_len"),
             },
@@ -195,16 +195,16 @@ impl IntrinsicType {
                 bit_len: Some(bit_len),
                 ..
             } => match bit_len {
-                16 => "(float16_t)",
-                32 => "(float)",
-                64 => "(double)",
+                16 => "float16_t",
+                32 => "float",
+                64 => "double",
                 128 => "",
                 _ => panic!("invalid bit_len"),
             },
             IntrinsicType {
                 kind: TypeKind::Char(_),
                 ..
-            } => "(char)",
+            } => "char",
             _ => "",
         }
     }
@@ -391,4 +391,13 @@ pub trait IntrinsicTypeDefinition: Deref<Target = IntrinsicType> {
             bits = self.inner_size()
         )
     }
+
+    fn generate_final_type_cast(&self) -> String {
+        let type_data = self.c_promotion();
+        if type_data.len() > 2 {
+            format!("({type_data})")
+        } else {
+            String::new()
+        }
+    }
 }
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 94600c989d..4ade0fa136 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -185,7 +185,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                             .map(move |idx| -> std::string::String {
                                 format!(
                                     "{cast}{lane_fn}(__return_value.val[{vector}], {lane})",
-                                    cast = self.c_promotion(),
+                                    cast = self.generate_final_type_cast(),
                                     lane_fn = self.get_lane_function(),
                                     lane = idx,
                                     vector = vector,
@@ -200,12 +200,13 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
         } else if self.num_lanes() > 1 {
             (0..self.num_lanes())
                 .map(|idx| -> std::string::String {
-                    format!(
-                        "{cast}{lane_fn}(__return_value, {lane})",
-                        cast = self.c_promotion(),
-                        lane_fn = self.get_lane_function(),
-                        lane = idx
-                    )
+                    let cast_type = self.c_promotion();
+                    let lane_fn = self.get_lane_function();
+                    if cast_type.len() > 2 {
+                        format!("({cast_type})({lane_fn}(__return_value, {idx}))")
+                    } else {
+                        format!("{lane_fn}(__return_value, {idx})")
+                    }
                 })
                 .collect::<Vec<_>>()
                 .join(r#" << ", " << "#)
@@ -224,13 +225,6 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                         "__m{}i",
                         self.bit_len.expect(format!("self: {:#?}", self).as_str())
                     ),
-                    // TypeKind::Float if self.results().inner_size() == 16 => "float16_t".to_string(),
-                    // TypeKind::Int(true) if self.results().inner_size() == 64 => "long".to_string(),
-                    // TypeKind::Int(false) if self.results().inner_size() == 64 => "unsigned long".to_string(),
-                    // TypeKind::Int(true) if self.results().inner_size() == 32 => "int".to_string(),
-                    // TypeKind::Int(false) if self.results().inner_size() == 32 => "unsigned int".to_string(),
-                    // TypeKind::Int(true) if self.results().inner_size() == 16 => "short".to_string(),
-                    // TypeKind::Int(false) if self.results().inner_size() == 16 => "unsigned short".to_string(),
                     _ => self.c_scalar_type(),
                 },
                 promote = self.c_promotion(),

From 717a3ade78bd69362db0f9a66988a354be7341ff Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 8 Oct 2025 19:59:39 +0530
Subject: [PATCH 59/73] fix: update the display of uint8_t type in C++

---
 crates/intrinsic-test/src/arm/config.rs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/crates/intrinsic-test/src/arm/config.rs b/crates/intrinsic-test/src/arm/config.rs
index 354d8f50b4..e2bc501127 100644
--- a/crates/intrinsic-test/src/arm/config.rs
+++ b/crates/intrinsic-test/src/arm/config.rs
@@ -9,6 +9,7 @@ std::ostream& operator<<(std::ostream& os, poly128_t value);
 #endif
 
 std::ostream& operator<<(std::ostream& os, float16_t value);
+std::ostream& operator<<(std::ostream& os, uint8_t value);
 
 // T1 is the `To` type, T2 is the `From` type
 template<typename T1, typename T2> T1 cast(T2 x) {
@@ -44,6 +45,11 @@ std::ostream& operator<<(std::ostream& os, float16_t value) {
     os << ss.str();
     return os;
 }
+
+std::ostream& operator<<(std::ostream& os, uint8_t value) {
+    os << (unsigned int) value;
+    return os;
+}
 "#;
 
 // Format f16 values (and vectors containing them) in a way that is consistent with C.

From 88921ac857694fde58c939de01b750dbdeb3178f Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 8 Oct 2025 22:48:37 +0530
Subject: [PATCH 60/73] Explicitly cast bits instead of allowing C++ to
 automatically cast the same (during typecasting)

---
 crates/intrinsic-test/src/x86/types.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index 4ade0fa136..f28d4d4988 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -203,7 +203,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                     let cast_type = self.c_promotion();
                     let lane_fn = self.get_lane_function();
                     if cast_type.len() > 2 {
-                        format!("({cast_type})({lane_fn}(__return_value, {idx}))")
+                        format!("cast<{cast_type}>({lane_fn}(__return_value, {idx}))")
                     } else {
                         format!("{lane_fn}(__return_value, {idx})")
                     }
@@ -227,7 +227,7 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                     ),
                     _ => self.c_scalar_type(),
                 },
-                promote = self.c_promotion(),
+                promote = self.generate_final_type_cast(),
             )
         };
 

From ab9e103804ee3227da793a0ddf7ddc4fe5b717ef Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 9 Oct 2025 21:16:44 +0530
Subject: [PATCH 61/73] feat: update cast<> function to reduce spurious cast
 functions (cases like integer to float or vice versa)

---
 crates/intrinsic-test/src/x86/config.rs | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index bf9f066404..28c1a7d3ad 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -320,10 +320,9 @@ pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#"
     #define _mm256_loadu_epi64_to___m256(mem_addr) _mm256_castsi256_ps(_mm256_loadu_si256((__m256i const*)(mem_addr)))
     #define _mm512_loadu_epi64_to___m512(mem_addr) _mm512_castsi512_ps(_mm512_loadu_si512((__m512i const*)(mem_addr)))
     
-    
     // T1 is the `To` type, T2 is the `From` type
     template<typename T1, typename T2> T1 cast(T2 x) {
-      if constexpr (std::is_convertible_v<T2, T1>) {
+      if constexpr ((std::is_integral_v<T1> && std::is_integral_v<T2>) || (std::is_floating_point_v<T1> && std::is_floating_point_v<T2>)) {
           return x;
       } else if constexpr (sizeof(T1) == sizeof(T2)) {
         T1 ret{};

From b3acb490b87de8ebc12725e2f2bef72092581c33 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 9 Oct 2025 21:19:35 +0530
Subject: [PATCH 62/73] Feat: Compile C++ testfiles using C++23 standard

---
 crates/intrinsic-test/src/x86/compile.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/x86/compile.rs b/crates/intrinsic-test/src/x86/compile.rs
index 27fd5d831c..60997a1278 100644
--- a/crates/intrinsic-test/src/x86/compile.rs
+++ b/crates/intrinsic-test/src/x86/compile.rs
@@ -34,7 +34,7 @@ pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
             "-mavx512vnni",
             "-mavx512vpopcntdq",
             "-ferror-limit=1000",
-            "-std=c++17",
+            "-std=c++23",
         ]);
 
     if !cpp_compiler.contains("clang") {

From cc319934f12f42e33467c419025ddbda0d973b82 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Fri, 10 Oct 2025 02:18:08 +0530
Subject: [PATCH 63/73] Feat: allow downcasting (useful for certain cases where
 uint32_t needs to be cast to float16_t because the bits are stored in the
 lower half of the type)

---
 crates/intrinsic-test/src/x86/config.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 28c1a7d3ad..6be3f1b133 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -324,7 +324,7 @@ pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#"
     template<typename T1, typename T2> T1 cast(T2 x) {
       if constexpr ((std::is_integral_v<T1> && std::is_integral_v<T2>) || (std::is_floating_point_v<T1> && std::is_floating_point_v<T2>)) {
           return x;
-      } else if constexpr (sizeof(T1) == sizeof(T2)) {
+      } else if constexpr (sizeof(T1) <= sizeof(T2)) {
         T1 ret{};
         std::memcpy(&ret, &x, sizeof(T1));
         return ret;

From 400be7f3f2cf1efd306575d6c42abd96751aba45 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Fri, 10 Oct 2025 12:49:30 +0530
Subject: [PATCH 64/73] feat: explicitly casting the result of the lane
 function to unsigned variants for compatibility with the Rust version

---
 crates/intrinsic-test/src/x86/types.rs | 30 +++++++++++++-------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index f28d4d4988..cdfc6bfa98 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -250,21 +250,21 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
             .and_then(|(simd_len, bit_len)| Some(simd_len * bit_len));
 
         match (self.bit_len, total_vector_bits) {
-            (Some(8), Some(128)) => String::from("_mm_extract_epi8"),
-            (Some(16), Some(128)) => String::from("_mm_extract_epi16"),
-            (Some(32), Some(128)) => String::from("_mm_extract_epi32"),
-            (Some(64), Some(128)) => String::from("_mm_extract_epi64"),
-            (Some(8), Some(256)) => String::from("_mm256_extract_epi8"),
-            (Some(16), Some(256)) => String::from("_mm256_extract_epi16"),
-            (Some(32), Some(256)) => String::from("_mm256_extract_epi32"),
-            (Some(64), Some(256)) => String::from("_mm256_extract_epi64"),
-            (Some(8), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi8"),
-            (Some(16), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi16"),
-            (Some(32), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi32"),
-            (Some(64), Some(512)) => String::from("_mm512_extract_intrinsic_test_epi64"),
-            (Some(8), Some(64)) => String::from("_mm64_extract_intrinsic_test_epi8"),
-            (Some(16), Some(64)) => String::from("_mm_extract_pi16"),
-            (Some(32), Some(64)) => String::from("_mm64_extract_intrinsic_test_epi32"),
+            (Some(8), Some(128)) => String::from("(uint8_t)_mm_extract_epi8"),
+            (Some(16), Some(128)) => String::from("(uint16_t)_mm_extract_epi16"),
+            (Some(32), Some(128)) => String::from("(uint32_t)_mm_extract_epi32"),
+            (Some(64), Some(128)) => String::from("(uint64_t)_mm_extract_epi64"),
+            (Some(8), Some(256)) => String::from("(uint8_t)_mm256_extract_epi8"),
+            (Some(16), Some(256)) => String::from("(uint16_t)_mm256_extract_epi16"),
+            (Some(32), Some(256)) => String::from("(uint32_t)_mm256_extract_epi32"),
+            (Some(64), Some(256)) => String::from("(uint64_t)_mm256_extract_epi64"),
+            (Some(8), Some(512)) => String::from("(uint8_t)_mm512_extract_intrinsic_test_epi8"),
+            (Some(16), Some(512)) => String::from("(uint16_t)_mm512_extract_intrinsic_test_epi16"),
+            (Some(32), Some(512)) => String::from("(uint32_t)_mm512_extract_intrinsic_test_epi32"),
+            (Some(64), Some(512)) => String::from("(uint64_t)_mm512_extract_intrinsic_test_epi64"),
+            (Some(8), Some(64)) => String::from("(uint8_t)_mm64_extract_intrinsic_test_epi8"),
+            (Some(16), Some(64)) => String::from("(uint16_t)_mm_extract_pi16"),
+            (Some(32), Some(64)) => String::from("(uint32_t)_mm64_extract_intrinsic_test_epi32"),
             _ => unreachable!(
                 "invalid length for vector argument: {:?}, {:?}",
                 self.bit_len, self.simd_len

From 52091b500845da14994d17efa0c7c31534c71729 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sat, 11 Oct 2025 15:17:06 +0530
Subject: [PATCH 65/73] feat: updated exclusion list with more intrinsics, that
 can be fixed immediately

---
 Cargo.lock                                  | 77 +++++++++++++++++++--
 ci/run.sh                                   |  1 +
 crates/intrinsic-test/Cargo.toml            |  1 +
 crates/intrinsic-test/missing_x86.txt       | 32 ++++++++-
 crates/intrinsic-test/src/common/cli.rs     |  6 ++
 crates/intrinsic-test/src/common/compare.rs |  1 -
 crates/intrinsic-test/src/x86/mod.rs        | 13 +++-
 7 files changed, 121 insertions(+), 10 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 70f09adf2c..e198e14ffe 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -282,6 +282,18 @@ dependencies = [
  "wasi",
 ]
 
+[[package]]
+name = "getrandom"
+version = "0.3.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "899def5c37c4fd7b2664648c28120ecec138e4d395b459e5ca34f9cce2dd77fd"
+dependencies = [
+ "cfg-if",
+ "libc",
+ "r-efi",
+ "wasip2",
+]
+
 [[package]]
 name = "hashbrown"
 version = "0.12.3"
@@ -348,6 +360,7 @@ dependencies = [
  "log",
  "pretty_env_logger",
  "quick-xml 0.37.5",
+ "rand 0.9.2",
  "rayon",
  "regex",
  "serde",
@@ -473,7 +486,7 @@ checksum = "588f6378e4dd99458b60ec275b4477add41ce4fa9f64dcba6f15adccb19b50d6"
 dependencies = [
  "env_logger 0.8.4",
  "log",
- "rand",
+ "rand 0.8.5",
 ]
 
 [[package]]
@@ -485,6 +498,12 @@ dependencies = [
  "proc-macro2",
 ]
 
+[[package]]
+name = "r-efi"
+version = "5.3.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f"
+
 [[package]]
 name = "rand"
 version = "0.8.5"
@@ -492,8 +511,18 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "34af8d1a0e25924bc5b7c43c079c942339d8f0a8b57c39049bef581b46327404"
 dependencies = [
  "libc",
- "rand_chacha",
- "rand_core",
+ "rand_chacha 0.3.1",
+ "rand_core 0.6.4",
+]
+
+[[package]]
+name = "rand"
+version = "0.9.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6db2770f06117d490610c7488547d543617b21bfa07796d7a12f6f1bd53850d1"
+dependencies = [
+ "rand_chacha 0.9.0",
+ "rand_core 0.9.3",
 ]
 
 [[package]]
@@ -503,7 +532,17 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e6c10a63a0fa32252be49d21e7709d4d4baf8d231c2dbce1eaa8141b9b127d88"
 dependencies = [
  "ppv-lite86",
- "rand_core",
+ "rand_core 0.6.4",
+]
+
+[[package]]
+name = "rand_chacha"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d3022b5f1df60f26e1ffddd6c66e8aa15de382ae63b3a0c1bfc0e4d3e3f325cb"
+dependencies = [
+ "ppv-lite86",
+ "rand_core 0.9.3",
 ]
 
 [[package]]
@@ -512,7 +551,16 @@ version = "0.6.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c"
 dependencies = [
- "getrandom",
+ "getrandom 0.2.16",
+]
+
+[[package]]
+name = "rand_core"
+version = "0.9.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "99d9a13982dcf210057a8a78572b2217b667c3beacbf3a0d8b454f6f82837d38"
+dependencies = [
+ "getrandom 0.3.4",
 ]
 
 [[package]]
@@ -703,7 +751,7 @@ dependencies = [
 name = "stdarch-gen-loongarch"
 version = "0.1.0"
 dependencies = [
- "rand",
+ "rand 0.8.5",
 ]
 
 [[package]]
@@ -736,7 +784,7 @@ version = "0.0.0"
 dependencies = [
  "core_arch",
  "quickcheck",
- "rand",
+ "rand 0.8.5",
 ]
 
 [[package]]
@@ -819,6 +867,15 @@ version = "0.11.1+wasi-snapshot-preview1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b"
 
+[[package]]
+name = "wasip2"
+version = "1.0.1+wasi-0.2.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "0562428422c63773dad2c345a1882263bbf4d65cf3f42e90921f787ef5ad58e7"
+dependencies = [
+ "wit-bindgen",
+]
+
 [[package]]
 name = "wasmparser"
 version = "0.235.0"
@@ -1003,6 +1060,12 @@ version = "0.53.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486"
 
+[[package]]
+name = "wit-bindgen"
+version = "0.46.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f17a85883d4e6d00e8a97c586de764dabcc06133f7f1d55dce5cdc070ad7fe59"
+
 [[package]]
 name = "xml-rs"
 version = "0.8.27"
diff --git a/ci/run.sh b/ci/run.sh
index a74769c56d..bd0e06687f 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -94,6 +94,7 @@ case ${TARGET} in
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
+        TEST_SAMPLE_INTRINSICS_PERCENTAGE=5
         export STDARCH_DISABLE_ASSERT_INSTR=1
         PATH="$PATH":"$(pwd)"/c_programs
         export PATH
diff --git a/crates/intrinsic-test/Cargo.toml b/crates/intrinsic-test/Cargo.toml
index 2c0f53897e..9fb70f32f8 100644
--- a/crates/intrinsic-test/Cargo.toml
+++ b/crates/intrinsic-test/Cargo.toml
@@ -22,3 +22,4 @@ itertools = "0.14.0"
 quick-xml = { version = "0.37.5", features = ["serialize", "overlapped-lists"] }
 serde-xml-rs = "0.8.0"
 regex = "1.11.1"
+rand = "0.9.2"
diff --git a/crates/intrinsic-test/missing_x86.txt b/crates/intrinsic-test/missing_x86.txt
index 824d36f605..e546799740 100644
--- a/crates/intrinsic-test/missing_x86.txt
+++ b/crates/intrinsic-test/missing_x86.txt
@@ -871,4 +871,34 @@ _m_pxor
 _m_to_int
 _m_to_int64
 _mm512_mask_floor_pd
-_mm512_mask_floor_ps
\ No newline at end of file
+_mm512_mask_floor_ps
+
+# SDE ERROR: Cannot execute XGETBV with ECX != 0
+_xgetbv
+
+# Miscellaneous issues that can be fixed first
+_kshiftli_mask16
+_kshiftli_mask32
+_kshiftli_mask64
+_kshiftli_mask8
+_kshiftri_mask16
+_kshiftri_mask32
+_kshiftri_mask64
+_kshiftri_mask8
+_mm256_castsi128_si256
+_mm256_extract_epi16
+_mm256_extract_epi8
+_mm512_castsi128_si512
+_mm512_castsi256_si512
+_mm512_conj_pch
+_mm512_mask_reduce_max_pd
+_mm512_mask_reduce_max_ps
+_mm512_mask_reduce_min_pd
+_mm512_mask_reduce_min_ps
+_mm_comineq_sh
+_mm_extract_epi16
+_mm_extract_epi8
+_mm_mask_cvtepi16_epi8
+_mm_mask_cvtpd_epi32
+_mm_mask_cvtpd_ps
+_mm_ucomineq_sh
\ No newline at end of file
diff --git a/crates/intrinsic-test/src/common/cli.rs b/crates/intrinsic-test/src/common/cli.rs
index beae6a4b04..461ab542ea 100644
--- a/crates/intrinsic-test/src/common/cli.rs
+++ b/crates/intrinsic-test/src/common/cli.rs
@@ -54,6 +54,9 @@ pub struct Cli {
     /// Set the sysroot for the C++ compiler
     #[arg(long)]
     pub cxx_toolchain_dir: Option<String>,
+
+    #[arg(long, default_value_t = 100u8)]
+    pub sample_percentage: u8,
 }
 
 pub struct ProcessedCli {
@@ -65,6 +68,7 @@ pub struct ProcessedCli {
     pub linker: Option<String>,
     pub cxx_toolchain_dir: Option<String>,
     pub skip: Vec<String>,
+    pub sample_percentage: u8,
 }
 
 impl ProcessedCli {
@@ -74,6 +78,7 @@ impl ProcessedCli {
         let target = cli_options.target;
         let linker = cli_options.linker;
         let cxx_toolchain_dir = cli_options.cxx_toolchain_dir;
+        let sample_percentage = cli_options.sample_percentage;
 
         let skip = if let Some(filename) = cli_options.skip {
             let data = std::fs::read_to_string(&filename).expect("Failed to open file");
@@ -108,6 +113,7 @@ impl ProcessedCli {
             cxx_toolchain_dir,
             skip,
             filename,
+            sample_percentage,
         }
     }
 }
diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index 1ad00839ef..89e5f965bc 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -14,7 +14,6 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
     let intrinsics = intrinsic_name_list
         .par_iter()
         .filter_map(|intrinsic_name| {
-
             let c = runner_command(runner)
                 .arg("intrinsic-test-programs")
                 .arg(intrinsic_name)
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index 1eac6fb5f9..ca5748e5fb 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -12,6 +12,8 @@ use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
 use intrinsic::X86IntrinsicType;
 use itertools::Itertools;
+use rand::rng;
+use rand::seq::IndexedRandom;
 use xml_parser::get_xml_intrinsics;
 
 pub struct X86ArchitectureTest {
@@ -47,7 +49,10 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
         let intrinsics =
             get_xml_intrinsics(&cli_options.filename).expect("Error parsing input file");
 
-        let mut intrinsics = intrinsics
+        let mut rng = rng();
+        let sample_percentage: usize = cli_options.sample_percentage as usize;
+
+        let intrinsics = intrinsics
             .into_iter()
             // Not sure how we would compare intrinsic that returns void.
             .filter(|i| i.results.kind() != TypeKind::Void)
@@ -62,6 +67,12 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             .unique_by(|i| i.name.clone())
             .collect::<Vec<_>>();
 
+        let sample_size = (intrinsics.len() * sample_percentage) / 100;
+        let mut intrinsics = intrinsics
+            .choose_multiple(&mut rng, sample_size)
+            .cloned()
+            .collect::<Vec<_>>();
+
         intrinsics.sort_by(|a, b| a.name.cmp(&b.name));
         Self {
             intrinsics: intrinsics,

From 7b80a1fd2fd0c87d362dff8cd45e9f1718cce3fb Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 15 Oct 2025 14:12:49 +0530
Subject: [PATCH 66/73] chore: remove x86-intel.xml from `stdarch-verify` crate

---
 crates/stdarch-verify/tests/x86-intel.rs |      2 +-
 crates/stdarch-verify/x86-intel.xml      | 158422 --------------------
 2 files changed, 1 insertion(+), 158423 deletions(-)
 delete mode 100644 crates/stdarch-verify/x86-intel.xml

diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs
index 02b6bdc768..5a98db980b 100644
--- a/crates/stdarch-verify/tests/x86-intel.rs
+++ b/crates/stdarch-verify/tests/x86-intel.rs
@@ -164,7 +164,7 @@ fn verify_all_signatures() {
     // Open up the network console and you'll see an xml file was downloaded
     // (currently called data-3.6.9.xml). That's the file we downloaded
     // here.
-    let xml = include_bytes!("../x86-intel.xml");
+    let xml = include_bytes!("../../../intrinsics_data/x86-intel.xml");
 
     let xml = &xml[..];
     let data: Data = quick_xml::de::from_reader(xml).expect("failed to deserialize xml");
diff --git a/crates/stdarch-verify/x86-intel.xml b/crates/stdarch-verify/x86-intel.xml
deleted file mode 100644
index 41f2119e68..0000000000
--- a/crates/stdarch-verify/x86-intel.xml
+++ /dev/null
@@ -1,158422 +0,0 @@
-<intrinsics_list version="3.6.9" date="07/12/2024">
-<intrinsic name="_addcarryx_u32" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="unsigned char" varname="c_in" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<parameter etype="UI32" memwidth="32" type="unsigned int *" varname="out" />
-	<description>Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
-	<operation>
-tmp[32:0] := a[31:0] + b[31:0] + (c_in &gt; 0 ? 1 : 0)
-MEM[out+31:out] := tmp[31:0]
-dst[0] := tmp[32]
-dst[7:1] := 0
-	</operation>
-	<instruction form="r32, r32" name="ADCX" xed="ADCX_GPR32d_GPR32d" />
-	<instruction form="r32, r32" name="ADOX" xed="ADOX_GPR32d_GPR32d" />
-	<CPUID>ADX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_addcarryx_u64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="unsigned char" varname="c_in" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<parameter etype="UI64" memwidth="64" type="unsigned __int64 *" varname="out" />
-	<description>Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
-	<operation>
-tmp[64:0] := a[63:0] + b[63:0] + (c_in &gt; 0 ? 1 : 0)
-MEM[out+63:out] := tmp[63:0]
-dst[0] := tmp[64]
-dst[7:1] := 0
-	</operation>
-	<instruction form="r64, r64" name="ADCX" xed="ADCX_GPR64q_GPR64q" />
-	<instruction form="r64, r64" name="ADOX" xed="ADOX_GPR64q_GPR64q" />
-	<CPUID>ADX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-<intrinsic name="_mm_aesenc_si128" vexEq="TRUE" tech="Other">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="RoundKey" />
-	<description>Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"."</description>
-	<operation>a[127:0] := ShiftRows(a[127:0])
-a[127:0] := SubBytes(a[127:0])
-a[127:0] := MixColumns(a[127:0])
-dst[127:0] := a[127:0] XOR RoundKey[127:0]
-	</operation>
-	<instruction form="xmm, xmm" name="AESENC" xed="AESENC_XMMdq_XMMdq" />
-	<CPUID>AES</CPUID>
-	<header>wmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesenclast_si128" vexEq="TRUE" tech="Other">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="RoundKey" />
-	<description>Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"."</description>
-	<operation>a[127:0] := ShiftRows(a[127:0])
-a[127:0] := SubBytes(a[127:0])
-dst[127:0] := a[127:0] XOR RoundKey[127:0]
-	</operation>
-	<instruction form="xmm, xmm" name="AESENCLAST" xed="AESENCLAST_XMMdq_XMMdq" />
-	<CPUID>AES</CPUID>
-	<header>wmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesdec_si128" vexEq="TRUE" tech="Other">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="RoundKey" />
-	<description>Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst".</description>
-	<operation>a[127:0] := InvShiftRows(a[127:0])
-a[127:0] := InvSubBytes(a[127:0])
-a[127:0] := InvMixColumns(a[127:0])
-dst[127:0] := a[127:0] XOR RoundKey[127:0]
-	</operation>
-	<instruction form="xmm, xmm" name="AESDEC" xed="AESDEC_XMMdq_XMMdq" />
-	<CPUID>AES</CPUID>
-	<header>wmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesdeclast_si128" vexEq="TRUE" tech="Other">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="RoundKey" />
-	<description>Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst".</description>
-	<operation>a[127:0] := InvShiftRows(a[127:0])
-a[127:0] := InvSubBytes(a[127:0])
-dst[127:0] := a[127:0] XOR RoundKey[127:0]
-	</operation>
-	<instruction form="xmm, xmm" name="AESDECLAST" xed="AESDECLAST_XMMdq_XMMdq" />
-	<CPUID>AES</CPUID>
-	<header>wmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesimc_si128" vexEq="TRUE" tech="Other">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Perform the InvMixColumns transformation on "a" and store the result in "dst".</description>
-	<operation>dst[127:0] := InvMixColumns(a[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="AESIMC" xed="AESIMC_XMMdq_XMMdq" />
-	<CPUID>AES</CPUID>
-	<header>wmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aeskeygenassist_si128" vexEq="TRUE" tech="Other">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from "a" and an 8-bit round constant specified in "imm8", and store the result in "dst"."</description>
-	<operation>X3[31:0] := a[127:96]
-X2[31:0] := a[95:64]
-X1[31:0] := a[63:32]
-X0[31:0] := a[31:0]
-RCON[31:0] := ZeroExtend32(imm8[7:0])
-dst[31:0] := SubWord(X1)
-dst[63:32] := RotWord(SubWord(X1)) XOR RCON
-dst[95:64] := SubWord(X3)
-dst[127:96] := RotWord(SubWord(X3)) XOR RCON
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="AESKEYGENASSIST" xed="AESKEYGENASSIST_XMMdq_XMMdq_IMMb" />
-	<CPUID>AES</CPUID>
-	<header>wmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_tile_dpbf16ps" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="dst" />
-	<parameter type="constexpr int" varname="a" />
-	<parameter type="constexpr int" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in tiles "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst".</description>
-	<operation>FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (a.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.fp32[n] += FP32(a.row[m].bf16[2*k+0]) * FP32(b.row[k].bf16[2*n+0])
-			tmp.fp32[n] += FP32(a.row[m].bf16[2*k+1]) * FP32(b.row[k].bf16[2*n+1])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, tmm, tmm" name="TDPBF16PS" xed="TDPBF16PS_TMMf32_TMMu32_TMMu32" />
-	<CPUID>AMX-BF16</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_dpbf16ps" tech="AMX">
-	<return type="void" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in tiles "src0" and "src1", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm, tmm, tmm" name="TDPBF16PS" xed="TDPBF16PS_TMMf32_TMMu32_TMMu32" />
-	<operation>FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (src0.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.fp32[n] += FP32(src0.row[m].bf16[2*k+0]) * FP32(src1.row[k].bf16[2*n+0])
-			tmp.fp32[n] += FP32(src0.row[m].bf16[2*k+1]) * FP32(src1.row[k].bf16[2*n+1])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="__tile1024i" varname="src0" />
-	<parameter type="__tile1024i" varname="src1" />
-	<CPUID>AMX-BF16</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	
-<intrinsic name="_tile_cmmimfp16ps" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" etype="FP32" varname="dst" />
-	<parameter type="constexpr int" etype="FP16" varname="a" />
-	<parameter type="constexpr int" etype="FP16" varname="b" />
-	<description>Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. Each dword element in input tiles "a" and "b" is interpreted as a complex number with FP16 real part and FP16 imaginary part. Calculates the imaginary part of the result. For each possible combination of (row of "a", column of "b"), it performs a set of multiplication and accumulations on all corresponding complex numbers (one from "a" and one from "b"). The imaginary part of the "a" element is multiplied with the real part of the corresponding "b" element, and the real part of the "a" element is multiplied with the imaginary part of the corresponding "b" elements. The two accumulated results are added, and then accumulated into the corresponding row and column of "dst".</description>
-	<operation>FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (a.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+1])
-			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+0])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, tmm, tmm" name="TCMMIMFP16PS" xed="TCMMIMFP16PS_TMMf32_TMMf16_TMMf16" />
-	<CPUID>AMX-COMPLEX</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_cmmrlfp16ps" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" etype="FP32" varname="dst" />
-	<parameter type="constexpr int" etype="FP16" varname="a" />
-	<parameter type="constexpr int" etype="FP16" varname="b" />
-	<description>Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. Each dword element in input tiles "a" and "b" is interpreted as a complex number with FP16 real part and FP16 imaginary part. Calculates the real part of the result. For each possible combination of (row of "a", column of "b"), it performs a set of multiplication and accumulations on all corresponding complex numbers (one from "a" and one from "b"). The real part of the "a" element is multiplied with the real part of the corresponding "b" element, and the negated imaginary part of the "a" element is multiplied with the imaginary part of the corresponding "b" elements. The two accumulated results are added, and then accumulated into the corresponding row and column of "dst".</description>
-	<operation>FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (a.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+0])
-			tmp.fp32[n] += FP32(-a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+1])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<instruction form="tmm, tmm, tmm" name="TCMMRLFP16PS" xed="TCMMRLFP16PS_TMMf32_TMMf16_TMMf16" />
-	<CPUID>AMX-COMPLEX</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_cmmimfp16ps" tech="AMX">
-	<return type="void" />
-	<description>Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. Each dword element in input tiles "src0" and "src1" is interpreted as a complex number with FP16 real part and FP16 imaginary part. This function calculates the imaginary part of the result.</description>
-	<instruction form="tmm, tmm, tmm" name="TCMMIMFP16PS" xed="TCMMIMFP16PS_TMMf32_TMMf16_TMMf16" />
-	<operation>FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (src0.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+0]) * FP32(src1.row[k].fp16[2*n+1])
-			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+1]) * FP32(src1.row[k].fp16[2*n+0])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="__tile1024i" varname="src0" />
-	<parameter type="__tile1024i" varname="src1" />
-	<CPUID>AMX-COMPLEX</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_cmmrlfp16ps" tech="AMX">
-	<return type="void" />
-	<description>Perform matrix multiplication of two tiles containing complex elements and accumulate the results into a packed single precision tile. Each dword element in input tiles src0 and src1 is interpreted as a complex number with FP16 real part and FP16 imaginary part. This function calculates the real part of the result.</description>
-	<instruction form="tmm, tmm, tmm" name="TCMMRLFP16PS" xed="TCMMRLFP16PS_TMMf32_TMMf16_TMMf16" />
-	<operation>FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (src0.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+0]) * FP32(src1.row[k].fp16[2*n+0])
-			tmp.fp32[n] += FP32(-src0.row[m].fp16[2*k+1]) * FP32(src1.row[k].fp16[2*n+1])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="__tile1024i" varname="src0" />
-	<parameter type="__tile1024i" varname="src1" />
-	<CPUID>AMX-COMPLEX</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	
-<intrinsic name="_tile_dpfp16ps" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" etype="FP32" varname="dst" />
-	<parameter type="constexpr int" etype="FP16" varname="a" />
-	<parameter type="constexpr int" etype="FP16" varname="b" />
-	<description>Compute dot-product of FP16 (16-bit) floating-point pairs in tiles "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst".</description>
-	<operation>FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (a.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+0]) * FP32(b.row[k].fp16[2*n+0])
-			tmp.fp32[n] += FP32(a.row[m].fp16[2*k+1]) * FP32(b.row[k].fp16[2*n+1])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, tmm, tmm" name="TDPFP16PS" xed="TDPFP16PS_TMMf32_TMM2f16_TMM2f16" />
-	<CPUID>AMX-FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_dpfp16ps" tech="AMX">
-	<return type="void" />
-	<description>Compute dot-product of FP16 (16-bit) floating-point pairs in tiles "src0" and "src1", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm, tmm, tmm" name="TDPBF16PS" xed="TDPBF16PS_TMMf32_TMMu32_TMMu32" />
-	<operation>FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (src0.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+0]) * FP32(src1.row[k].fp16[2*n+0])
-			tmp.fp32[n] += FP32(src0.row[m].fp16[2*k+1]) * FP32(src1.row[k].fp16[2*n+1])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="__tile1024i" varname="src0" />
-	<parameter type="__tile1024i" varname="src1" />
-	<CPUID>AMX-FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	
-<intrinsic name="_tile_dpbsud" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="dst" />
-	<parameter type="constexpr int" varname="a" />
-	<parameter type="constexpr int" varname="b" />
-	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "a" with corresponding unsigned 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst".</description>
-	<operation>DEFINE DPBD(c, x, y) {
-	tmp1 := SignExtend32(x.byte[0]) * ZeroExtend32(y.byte[0])
-	tmp2 := SignExtend32(x.byte[1]) * ZeroExtend32(y.byte[1])
-	tmp3 := SignExtend32(x.byte[2]) * ZeroExtend32(y.byte[2])
-	tmp4 := SignExtend32(x.byte[3]) * ZeroExtend32(y.byte[3])
-	
-	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
-}
-FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (a.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, tmm, tmm" name="TDPBSUD" xed="TDPBSUD_TMMi32_TMMu32_TMMu32" />
-	<CPUID>AMX-INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_dpbusd" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="dst" />
-	<parameter type="constexpr int" varname="a" />
-	<parameter type="constexpr int" varname="b" />
-	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst".</description>
-	<operation>DEFINE DPBD(c, x, y) {
-	tmp1 := ZeroExtend32(x.byte[0]) * SignExtend32(y.byte[0])
-	tmp2 := ZeroExtend32(x.byte[1]) * SignExtend32(y.byte[1])
-	tmp3 := ZeroExtend32(x.byte[2]) * SignExtend32(y.byte[2])
-	tmp4 := ZeroExtend32(x.byte[3]) * SignExtend32(y.byte[3])
-	
-	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
-}
-FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (a.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, tmm, tmm" name="TDPBUSD" xed="TDPBUSD_TMMi32_TMMu32_TMMu32" />
-	<CPUID>AMX-INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_dpbuud" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="dst" />
-	<parameter type="constexpr int" varname="a" />
-	<parameter type="constexpr int" varname="b" />
-	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding unsigned 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst".</description>
-	<operation>DEFINE DPBD(c, x, y) {
-	tmp1 := ZeroExtend32(x.byte[0]) * ZeroExtend32(y.byte[0])
-	tmp2 := ZeroExtend32(x.byte[1]) * ZeroExtend32(y.byte[1])
-	tmp3 := ZeroExtend32(x.byte[2]) * ZeroExtend32(y.byte[2])
-	tmp4 := ZeroExtend32(x.byte[3]) * ZeroExtend32(y.byte[3])
-	
-	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
-}
-FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (a.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, tmm, tmm" name="TDPBUUD" xed="TDPBUUD_TMMu32_TMMu32_TMMu32" />
-	<CPUID>AMX-INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_dpbssd" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="dst" />
-	<parameter type="constexpr int" varname="a" />
-	<parameter type="constexpr int" varname="b" />
-	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst".</description>
-	<operation>DEFINE DPBD(c, x, y) {
-	tmp1 := SignExtend32(x.byte[0]) * SignExtend32(y.byte[0])
-	tmp2 := SignExtend32(x.byte[1]) * SignExtend32(y.byte[1])
-	tmp3 := SignExtend32(x.byte[2]) * SignExtend32(y.byte[2])
-	tmp4 := SignExtend32(x.byte[3]) * SignExtend32(y.byte[3])
-	
-	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
-}
-FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (a.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, tmm, tmm" name="TDPBSSD" xed="TDPBSSD_TMMi32_TMMu32_TMMu32" />
-	<CPUID>AMX-INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_dpbssd" tech="AMX">
-	<return type="void" />
-	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "src0" with corresponding signed 8-bit integers in "src1", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm, tmm, tmm" name="TDPBSSD" xed="TDPBSSD_TMMi32_TMMu32_TMMu32" />
-	<operation>DEFINE DPBD(c, x, y) {
-	tmp1 := SignExtend32(x.byte[0]) * SignExtend32(y.byte[0])
-	tmp2 := SignExtend32(x.byte[1]) * SignExtend32(y.byte[1])
-	tmp3 := SignExtend32(x.byte[2]) * SignExtend32(y.byte[2])
-	tmp4 := SignExtend32(x.byte[3]) * SignExtend32(y.byte[3])
-	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
-}
-FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (src0.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.dword[n] := DPBD(tmp.dword[n], src0.row[m].dword[k], src1.row[k].dword[n])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="__tile1024i" varname="src0" />
-	<parameter type="__tile1024i" varname="src1" />
-	<CPUID>AMX-INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_dpbsud" tech="AMX">
-	<return type="void" />
-	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "src0" with corresponding unsigned 8-bit integers in "src1", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm, tmm, tmm" name="TDPBSUD" xed="TDPBSUD_TMMi32_TMMu32_TMMu32" />
-	<operation>DEFINE DPBD(c, x, y) {
-	tmp1 := SignExtend32(x.byte[0]) * ZeroExtend32(y.byte[0])
-	tmp2 := SignExtend32(x.byte[1]) * ZeroExtend32(y.byte[1])
-	tmp3 := SignExtend32(x.byte[2]) * ZeroExtend32(y.byte[2])
-	tmp4 := SignExtend32(x.byte[3]) * ZeroExtend32(y.byte[3])
-	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
-}
-FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (src0.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.dword[n] := DPBD(tmp.dword[n], src0.row[m].dword[k], src1.row[k].dword[n])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="__tile1024i" varname="src0" />
-	<parameter type="__tile1024i" varname="src1" />
-	<CPUID>AMX-INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_dpbusd" tech="AMX">
-	<return type="void" />
-	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "src0" with corresponding signed 8-bit integers in "src1", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm, tmm, tmm" name="TDPBUSD" xed="TDPBUSD_TMMi32_TMMu32_TMMu32" />
-	<operation>DEFINE DPBD(c, x, y) {
-	tmp1 := ZeroExtend32(x.byte[0]) * SignExtend32(y.byte[0])
-	tmp2 := ZeroExtend32(x.byte[1]) * SignExtend32(y.byte[1])
-	tmp3 := ZeroExtend32(x.byte[2]) * SignExtend32(y.byte[2])
-	tmp4 := ZeroExtend32(x.byte[3]) * SignExtend32(y.byte[3])
-	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
-}
-FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (src0.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.dword[n] := DPBD(tmp.dword[n], src0.row[m].dword[k], src1.row[k].dword[n])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="__tile1024i" varname="src0" />
-	<parameter type="__tile1024i" varname="src1" />
-	<CPUID>AMX-INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_dpbuud" tech="AMX">
-	<return type="void" />
-	<description>Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "src0" with corresponding unsigned 8-bit integers in "src1", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm, tmm, tmm" name="TDPBUUD" xed="TDPBUUD_TMMu32_TMMu32_TMMu32" />
-	<operation>DEFINE DPBD(c, x, y) {
-	tmp1 := ZeroExtend32(x.byte[0]) * ZeroExtend32(y.byte[0])
-	tmp2 := ZeroExtend32(x.byte[1]) * ZeroExtend32(y.byte[1])
-	tmp3 := ZeroExtend32(x.byte[2]) * ZeroExtend32(y.byte[2])
-	tmp4 := ZeroExtend32(x.byte[3]) * ZeroExtend32(y.byte[3])
-	RETURN c + tmp1 + tmp2 + tmp3 + tmp4
-}
-FOR m := 0 TO dst.rows - 1
-	tmp := dst.row[m]
-	FOR k := 0 TO (src0.colsb / 4) - 1
-		FOR n := 0 TO (dst.colsb / 4) - 1
-			tmp.dword[n] := DPBD(tmp.dword[n], src0.row[m].dword[k], src1.row[k].dword[n])
-		ENDFOR
-	ENDFOR
-	write_row_and_zero(dst, m, tmp, dst.colsb)
-ENDFOR
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="__tile1024i" varname="src0" />
-	<parameter type="__tile1024i" varname="src1" />
-	<CPUID>AMX-INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	
-<intrinsic name="_tile_loadconfig" tech="AMX">
-	<return type="void" />
-	<parameter memwidth="512" type="const void *" varname="mem_addr" />
-	<description>Load tile configuration from a 64-byte memory location specified by "mem_addr". The tile configuration format is specified below, and includes the tile type pallette, the number of bytes per row, and the number of rows. If the specified pallette_id is zero, that signifies the init state for both the tile config and the tile data, and the tiles are zeroed. Any invalid configurations will result in #GP fault.</description>
-	<operation>
-//	format of memory payload. each field is a byte.
-//		 0: palette
-//		 1: start_row
-//	 2-15: reserved, must be zero
-//	16-17: tile0.colsb
-//	18-19: tile1.colsb
-//	20-21: tile2.colsb
-//			...
-//	30-31: tile7.colsb
-//	32-47: reserved, must be zero
-//		48: tile0.rows
-//		49: tile1.rows
-//		50: tile2.rows
-//			 ...
-//		55: tile7.rows
-//	56-63: reserved, must be zero
-	</operation>
-	<instruction form="m512" name="LDTILECFG" xed="LDTILECFG_MEM" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_storeconfig" tech="AMX">
-	<return type="void" />
-	<parameter memwidth="512" type="void *" varname="mem_addr" />
-	<description>Stores the current tile configuration to a 64-byte memory location specified by "mem_addr". The tile configuration format is specified below, and includes the tile type pallette, the number of bytes per row, and the number of rows. If tiles are not configured, all zeroes will be stored to memory.</description>
-	<operation>
-//	format of memory payload. each field is a byte.
-//		 0: palette
-//		 1: start_row
-//	 2-15: reserved, must be zero
-//	16-17: tile0.colsb
-//	18-19: tile1.colsb
-//	20-21: tile2.colsb
-//			...
-//	30-31: tile7.colsb
-//	32-47: reserved, must be zero
-//		48: tile0.rows
-//		49: tile1.rows
-//		50: tile2.rows
-//			 ...
-//		55: tile7.rows
-//	56-63: reserved, must be zero
-	</operation>
-	<instruction form="m512" name="STTILECFG" xed="STTILECFG_MEM" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_loadd" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="dst" />
-	<parameter type="const void *" varname="base" />
-	<parameter etype="UI32" type="size_t" varname="stride" />
-	<description>Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst" using the tile configuration previously configured via "_tile_loadconfig".</description>
-	<operation>start := tileconfig.startRow
-IF start == 0 // not restarting, zero incoming state
-	tilezero(dst)
-FI
-nbytes := dst.colsb
-DO WHILE start &lt; dst.rows
-	memptr := base + start * stride
-	write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes)
-	start := start + 1
-OD
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, sibmem" name="TILELOADD" xed="TILELOADD_TMMu32_MEMu32" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_stream_loadd" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="dst" />
-	<parameter type="const void *" varname="base" />
-	<parameter etype="UI32" type="size_t" varname="stride" />
-	<description>Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst" using the tile configuration previously configured via "_tile_loadconfig". This intrinsic provides a hint to the implementation that the data will likely not be reused in the near future and the data caching can be optimized accordingly.</description>
-	<operation>start := tileconfig.startRow
-IF start == 0 // not restarting, zero incoming state
-	tilezero(dst)
-FI
-nbytes := dst.colsb
-DO WHILE start &lt; dst.rows
-	memptr := base + start * stride
-	write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes)
-	start := start + 1
-OD
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-	</operation>
-	<instruction form="tmm, sibmem" name="TILELOADDT1" xed="TILELOADDT1_TMMu32_MEMu32" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_release" tech="AMX">
-	<return type="void" />
-	<description>Release the tile configuration to return to the init state, which releases all storage it currently holds.</description>
-	<instruction name="TILERELEASE" xed="TILERELEASE" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_stored" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="src" />
-	<parameter type="void *" varname="base" />
-	<parameter etype="UI32" type="size_t" varname="stride" />
-	<description>Store the tile specified by "src" to memory specifieid by "base" address and "stride" using the tile configuration previously configured via "_tile_loadconfig".</description>
-	<operation>start := tileconfig.startRow
-DO WHILE start &lt; src.rows
-	memptr := base + start * stride
-	write_memory(memptr, src.colsb, src.row[start])
-	start := start + 1
-OD
-zero_tileconfig_start()
-	</operation>
-	<instruction form="sibmem, tmm" name="TILESTORED" xed="TILESTORED_MEMu32_TMMu32" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_tile_zero" tech="AMX">
-	<return type="void" />
-	<parameter type="constexpr int" varname="tdest" />
-	<description>Zero the tile specified by "tdest".</description>
-	<operation>nbytes := palette_table[tileconfig.palette_id].bytes_per_row
-FOR i := 0 TO palette_table[tileconfig.palette_id].max_rows-1
-	FOR j := 0 TO nbytes-1
-		tdest.row[i].byte[j] := 0
-	ENDFOR
-ENDFOR
-	</operation>
-	<instruction form="tmm" name="TILEZERO" xed="TILEZERO_TMMu32" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_loadd" tech="AMX">
-	<return type="void" />
-	<description>Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm, sibmem" name="TILELOADD" xed="TILELOADD_TMMu32_MEMu32" />
-	<operation>start := tileconfig.startRow
-IF start == 0 // not restarting, zero incoming state
-	tilezero(dst)
-FI
-nbytes := dst.colsb
-DO WHILE start &lt; dst.rows
-	memptr := base + start * stride
-	write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes)
-	start := start + 1
-OD
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="const void*" varname="base" />
-	<parameter type="size_t" varname="stride" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_stored" tech="AMX">
-	<return type="void" />
-	<description>Store the tile specified by "src" to memory specifieid by "base" address and "stride". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="sibmem, tmm" name="TILESTORED" xed="TILESTORED_MEMu32_TMMu32" />
-	<operation>start := tileconfig.startRow
-DO WHILE start &lt; src.rows
-	memptr := base + start * stride
-	write_memory(memptr, src.colsb, src.row[start])
-	start := start + 1
-OD
-zero_tileconfig_start()
-</operation>
-	<parameter type="void*" varname="base" />
-	<parameter type="size_t" varname="stride" />
-	<parameter type="__tile1024i" varname="src" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_stream_loadd" tech="AMX">
-	<return type="void" />
-	<description>Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst". This intrinsic provides a hint to the implementation that the data will likely not be reused in the near future and the data caching can be optimized accordingly. The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm, sibmem" name="TILELOADDT1" xed="TILELOADDT1_TMMu32_MEMu32" />
-	<operation>start := tileconfig.startRow
-IF start == 0 // not restarting, zero incoming state
-	tilezero(dst)
-FI
-nbytes := dst.colsb
-DO WHILE start &lt; dst.rows
-	memptr := base + start * stride
-	write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes)
-	start := start + 1
-OD
-zero_upper_rows(dst, dst.rows)
-zero_tileconfig_start()
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<parameter type="const void*" varname="base" />
-	<parameter type="size_t" varname="stride" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	<intrinsic name="__tile_zero" tech="AMX">
-	<return type="void" />
-	<description>Zero the tile specified by "dst". The shape of tile is specified in the struct of __tile1024i. The register of the tile is allocated by compiler.</description>
-	<instruction form="tmm" name="TILEZERO" xed="TILEZERO_TMMu32" />
-	<operation>nbytes := palette_table[tileconfig.palette_id].bytes_per_row
-FOR i := 0 TO palette_table[tileconfig.palette_id].max_rows-1
-	FOR j := 0 TO nbytes-1
-		tdest.row[i].byte[j] := 0
-	ENDFOR
-ENDFOR
-</operation>
-	<parameter type="__tile1024i*" varname="dst" />
-	<CPUID>AMX-TILE</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	
-<intrinsic name="_mm256_acos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ACOS(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_acos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ACOS(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_acosh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ACOSH(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_acosh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ACOSH(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_asin_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ASIN(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_asin_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ASIN(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_asinh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ASINH(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_asinh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ASINH(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_atan_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ATAN(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_atan_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ATAN(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_atan2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_atan2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_atanh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ATANH(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_atanh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ATANH(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := COS(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := COS(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cosd_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := COSD(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cosd_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := COSD(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cosh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := COSH(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cosh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := COSH(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hypot_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hypot_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sin_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SIN(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sin_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SIN(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sincos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" memwidth="256" type="__m256d *" varname="mem_addr" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SIN(a[i+63:i])
-	MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sincos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" memwidth="256" type="__m256 *" varname="mem_addr" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SIN(a[i+31:i])
-	MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sind_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SIND(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sind_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SIND(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sinh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SINH(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sinh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SINH(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_tan_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := TAN(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_tan_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := TAN(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_tand_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := TAND(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_tand_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := TAND(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_tanh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := TANH(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_tanh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := TANH(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cbrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := CubeRoot(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cbrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := CubeRoot(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cexp_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
-	<operation>
-DEFINE CEXP(a[31:0], b[31:0]) {
-	result[31:0]  := POW(FP32(e), a[31:0]) * COS(b[31:0])
-	result[63:32] := POW(FP32(e), a[31:0]) * SIN(b[31:0])
-	RETURN result
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := CEXP(a[i+31:i], a[i+63:i+32])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_clog_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the natural logarithm of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
-	<operation>
-DEFINE CLOG(a[31:0], b[31:0]) {
-	result[31:0]  := LOG(SQRT(POW(a, 2.0) + POW(b, 2.0)))
-	result[63:32] := ATAN2(b, a)
-	RETURN result
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := CLOG(a[i+31:i], a[i+63:i+32])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_csqrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the square root of packed complex snumbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
-	<operation>
-DEFINE CSQRT(a[31:0], b[31:0]) {
-	sign[31:0] := (b &lt; 0.0) ? -FP32(1.0) : FP32(1.0)
-	result[31:0]  := SQRT((a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
-	result[63:32] := sign * SQRT((-a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
-	RETURN result
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := CSQRT(a[i+31:i], a[i+63:i+32])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_exp_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := POW(e, a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_exp_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := POW(FP32(e), a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_exp10_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := POW(10.0, a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_exp10_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_exp2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := POW(2.0, a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_exp2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_expm1_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_expm1_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_invcbrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := InvCubeRoot(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_invcbrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := InvCubeRoot(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_invsqrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := InvSQRT(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_invsqrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := InvSQRT(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_log_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_log_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_log10_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_log10_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_log1p_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := LOG(1.0 + a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_log1p_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := LOG(1.0 + a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_log2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_log2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_logb_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_logb_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_pow_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_pow_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_svml_sqrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SQRT(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_svml_sqrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SQRT(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cdfnorm_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := CDFNormal(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cdfnorm_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := CDFNormal(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cdfnorminv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := InverseCDFNormal(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cdfnorminv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := InverseCDFNormal(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_erf_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ERF(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_erf_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ERF(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_erfc_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := 1.0 - ERF(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_erfc_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+63:i] := 1.0 - ERF(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_erfcinv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_erfcinv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_erfinv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := 1.0 / ERF(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_erfinv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+63:i] := 1.0 / ERF(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_epi8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 8*j
-	IF b[i+7:i] == 0
-		#DE
-	FI
-	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_epi16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	IF b[i+15:i] == 0
-		#DE
-	FI
-	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF b[i+31:i] == 0
-		#DE
-	FI
-	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_epi64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	IF b[i+63:i] == 0
-		#DE
-	FI
-	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_epu8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 8*j
-	IF b[i+7:i] == 0
-		#DE
-	FI
-	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_epu16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	IF b[i+15:i] == 0
-		#DE
-	FI
-	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_epu32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF b[i+31:i] == 0
-		#DE
-	FI
-	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_epu64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	IF b[i+63:i] == 0
-		#DE
-	FI
-	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_idiv_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_idivrem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" memwidth="256" type="__m256i *" varname="mem_addr" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr".</description>
-	<operation>FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
-	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_irem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rem_epi8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 31
-	i := 8*j
-	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rem_epi16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := 16*j
-	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rem_epi64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := 64*j
-	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rem_epu8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 31
-	i := 8*j
-	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rem_epu16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := 16*j
-	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rem_epu32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rem_epu64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := 64*j
-	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_udiv_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_udivrem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" memwidth="256" type="__m256i *" varname="mem_addr" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr".</description>
-	<operation>FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
-	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_urem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_svml_ceil_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := CEIL(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_svml_ceil_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := CEIL(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_svml_floor_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := FLOOR(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_svml_floor_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := FLOOR(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_svml_round_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ROUND(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_svml_round_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ROUND(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_trunc_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := TRUNCATE(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_trunc_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := TRUNCATE(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_add_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] + b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VADDPD" xed="VADDPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_add_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VADDPS" xed="VADDPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_addsub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF ((j &amp; 1) == 0)
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VADDSUBPD" xed="VADDSUBPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_addsub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF ((j &amp; 1) == 0)
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VADDSUBPS" xed="VADDSUBPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	dst[i+63:i] := a[i+63:i] / b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VDIVPD" xed="VDIVPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := a[i+31:i] / b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VDIVPS" xed="VDIVPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dp_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".</description>
-	<operation>
-DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
-	FOR j := 0 to 3
-		i := j*32
-		IF imm8[(4+j)%8]
-			temp[i+31:i] := a[i+31:i] * b[i+31:i]
-		ELSE
-			temp[i+31:i] := FP32(0.0)
-		FI
-	ENDFOR
-	
-	sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0])
-	
-	FOR j := 0 to 3
-		i := j*32
-		IF imm8[j%8]
-			tmpdst[i+31:i] := sum[31:0]
-		ELSE
-			tmpdst[i+31:i] := FP32(0.0)
-		FI
-	ENDFOR
-	RETURN tmpdst[127:0]
-}
-dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])
-dst[255:128] := DP(a[255:128], b[255:128], imm8[7:0])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VDPPS" xed="VDPPS_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hadd_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
-	<operation>
-dst[63:0] := a[127:64] + a[63:0]
-dst[127:64] := b[127:64] + b[63:0]
-dst[191:128] := a[255:192] + a[191:128]
-dst[255:192] := b[255:192] + b[191:128]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VHADDPD" xed="VHADDPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hadd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32] + a[31:0]
-dst[63:32] := a[127:96] + a[95:64]
-dst[95:64] := b[63:32] + b[31:0]
-dst[127:96] := b[127:96] + b[95:64]
-dst[159:128] := a[191:160] + a[159:128]
-dst[191:160] := a[255:224] + a[223:192]
-dst[223:192] := b[191:160] + b[159:128]
-dst[255:224] := b[255:224] + b[223:192]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VHADDPS" xed="VHADDPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hsub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
-	<operation>
-dst[63:0] := a[63:0] - a[127:64]
-dst[127:64] := b[63:0] - b[127:64]
-dst[191:128] := a[191:128] - a[255:192]
-dst[255:192] := b[191:128] - b[255:192]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VHSUBPD" xed="VHSUBPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hsub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Horizontally subtract adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] - a[63:32]
-dst[63:32] := a[95:64] - a[127:96]
-dst[95:64] := b[31:0] - b[63:32]
-dst[127:96] := b[95:64] - b[127:96]
-dst[159:128] := a[159:128] - a[191:160]
-dst[191:160] := a[223:192] - a[255:224]
-dst[223:192] := b[159:128] - b[191:160]
-dst[255:224] := b[223:192] - b[255:224]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VHSUBPS" xed="VHSUBPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mul_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] * b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMULPD" xed="VMULPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mul_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] * b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMULPS" xed="VMULPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] - b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VSUBPD" xed="VSUBPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VSUBPS" xed="VSUBPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_and_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VANDPD" xed="VANDPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_and_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VANDPS" xed="VANDPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_andnot_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VANDNPD" xed="VANDNPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_andnot_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VANDNPS" xed="VANDNPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_or_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VORPD" xed="VORPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_or_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VORPS" xed="VORPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_xor_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VXORPD" xed="VXORPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_xor_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VXORPS" xed="VXORPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testz_si256" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
-	<operation>
-IF ((a[255:0] AND b[255:0]) == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-IF (((NOT a[255:0]) AND b[255:0]) == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-RETURN ZF
-	</operation>
-	<instruction form="ymm, ymm" name="VPTEST" xed="VPTEST_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testc_si256" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
-	<operation>
-IF ((a[255:0] AND b[255:0]) == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-IF (((NOT a[255:0]) AND b[255:0]) == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-RETURN CF
-	</operation>
-	<instruction form="ymm, ymm" name="VPTEST" xed="VPTEST_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testnzc_si256" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
-	<operation>
-IF ((a[255:0] AND b[255:0]) == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-IF (((NOT a[255:0]) AND b[255:0]) == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-IF (ZF == 0 &amp;&amp; CF == 0)
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="ymm, ymm" name="VPTEST" xed="VPTEST_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testz_pd" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
-	<operation>
-tmp[255:0] := a[255:0] AND b[255:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[255:0] := (NOT a[255:0]) AND b[255:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := ZF
-	</operation>
-	<instruction form="ymm, ymm" name="VTESTPD" xed="VTESTPD_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testc_pd" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
-	<operation>
-tmp[255:0] := a[255:0] AND b[255:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[255:0] := (NOT a[255:0]) AND b[255:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := CF
-	</operation>
-	<instruction form="ymm, ymm" name="VTESTPD" xed="VTESTPD_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testnzc_pd" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
-	<operation>
-tmp[255:0] := a[255:0] AND b[255:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[255:0] := (NOT a[255:0]) AND b[255:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[255] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-IF (ZF == 0 &amp;&amp; CF == 0)
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="ymm, ymm" name="VTESTPD" xed="VTESTPD_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_testz_pd" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
-	<operation>
-tmp[127:0] := a[127:0] AND b[127:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[127:0] := (NOT a[127:0]) AND b[127:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := ZF
-	</operation>
-	<instruction form="xmm, xmm" name="VTESTPD" xed="VTESTPD_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_testc_pd" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
-	<operation>
-tmp[127:0] := a[127:0] AND b[127:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[127:0] := (NOT a[127:0]) AND b[127:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := CF
-	</operation>
-	<instruction form="xmm, xmm" name="VTESTPD" xed="VTESTPD_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_testnzc_pd" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
-	<operation>
-tmp[127:0] := a[127:0] AND b[127:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[127:0] := (NOT a[127:0]) AND b[127:0]
-IF (tmp[63] == 0 &amp;&amp; tmp[127] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-IF (ZF == 0 &amp;&amp; CF == 0)
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="xmm, xmm" name="VTESTPD" xed="VTESTPD_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testz_ps" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
-	<operation>
-tmp[255:0] := a[255:0] AND b[255:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
-    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[255:0] := (NOT a[255:0]) AND b[255:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
-    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := ZF
-	</operation>
-	<instruction form="ymm, ymm" name="VTESTPS" xed="VTESTPS_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testc_ps" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
-	<operation>
-tmp[255:0] := a[255:0] AND b[255:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
-    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[255:0] := (NOT a[255:0]) AND b[255:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
-    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := CF
-	</operation>
-	<instruction form="ymm, ymm" name="VTESTPS" xed="VTESTPS_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testnzc_ps" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
-	<operation>
-tmp[255:0] := a[255:0] AND b[255:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
-    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[255:0] := (NOT a[255:0]) AND b[255:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0 &amp;&amp; \
-    tmp[159] == 0 &amp;&amp; tmp[191] == 0 &amp;&amp; tmp[223] == 0 &amp;&amp; tmp[255] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-IF (ZF == 0 &amp;&amp; CF == 0)
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="ymm, ymm" name="VTESTPS" xed="VTESTPS_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_testz_ps" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
-	<operation>
-tmp[127:0] := a[127:0] AND b[127:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[127:0] := (NOT a[127:0]) AND b[127:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := ZF
-	</operation>
-	<instruction form="xmm, xmm" name="VTESTPS" xed="VTESTPS_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_testc_ps" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
-	<operation>
-tmp[127:0] := a[127:0] AND b[127:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[127:0] := (NOT a[127:0]) AND b[127:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := CF
-	</operation>
-	<instruction form="xmm, xmm" name="VTESTPS" xed="VTESTPS_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_testnzc_ps" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
-	<operation>
-tmp[127:0] := a[127:0] AND b[127:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-tmp[127:0] := (NOT a[127:0]) AND b[127:0]
-IF (tmp[31] == 0 &amp;&amp; tmp[63] == 0 &amp;&amp; tmp[95] == 0 &amp;&amp; tmp[127] == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-IF (ZF == 0 &amp;&amp; CF == 0)
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="xmm, xmm" name="VTESTPS" xed="VTESTPS_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_blend_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF imm8[j]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VBLENDPD" xed="VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_blend_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF imm8[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VBLENDPS" xed="VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_blendv_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="MASK" type="__m256d" varname="mask" />
-	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF mask[i+63]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, ymm" name="VBLENDVPD" xed="VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_blendv_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="MASK" type="__m256" varname="mask" />
-	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF mask[i+31]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, ymm" name="VBLENDVPS" xed="VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shuffle_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
-dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFPD" xed="VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shuffle_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-dst[223:192] := SELECT4(b[255:128], imm8[5:4])
-dst[255:224] := SELECT4(b[255:128], imm8[7:6])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFPS" xed="VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extractf128_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VEXTRACTF128" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extractf128_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VEXTRACTF128" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extractf128_si256" tech="AVX_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VEXTRACTF128" xed="VEXTRACTF128_XMMdq_YMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extract_epi32" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI32" type="__int32" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="3" type="const int" varname="index" />
-	<description>Extract a 32-bit integer from "a", selected with "index", and store the result in "dst".</description>
-	<operation>
-dst[31:0] := (a[255:0] &gt;&gt; (index[2:0] * 32))[31:0]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extract_epi64" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="index" />
-	<description>Extract a 64-bit integer from "a", selected with "index", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := (a[255:0] &gt;&gt; (index[1:0] * 64))[63:0]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutevar_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], b[1:0])
-dst[63:32] := SELECT4(a[127:0], b[33:32])
-dst[95:64] := SELECT4(a[127:0], b[65:64])
-dst[127:96] := SELECT4(a[127:0], b[97:96])
-dst[159:128] := SELECT4(a[255:128], b[129:128])
-dst[191:160] := SELECT4(a[255:128], b[161:160])
-dst[223:192] := SELECT4(a[255:128], b[193:192])
-dst[255:224] := SELECT4(a[255:128], b[225:224])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMILPS" xed="VPERMILPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutevar_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], b[1:0])
-dst[63:32] := SELECT4(a[127:0], b[33:32])
-dst[95:64] := SELECT4(a[127:0], b[65:64])
-dst[127:96] := SELECT4(a[127:0], b[97:96])
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMILPS" xed="VPERMILPS_XMMdq_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permute_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPERMILPS" xed="VPERMILPS_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_permute_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VPERMILPS" xed="VPERMILPS_XMMdq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutevar_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
-	<operation>
-IF (b[1] == 0) dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) dst[127:64] := a[127:64]; FI
-IF (b[129] == 0) dst[191:128] := a[191:128]; FI
-IF (b[129] == 1) dst[191:128] := a[255:192]; FI
-IF (b[193] == 0) dst[255:192] := a[191:128]; FI
-IF (b[193] == 1) dst[255:192] := a[255:192]; FI
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMILPD" xed="VPERMILPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutevar_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst".</description>
-	<operation>
-IF (b[1] == 0) dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) dst[127:64] := a[127:64]; FI
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMILPD" xed="VPERMILPD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permute_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
-IF (imm8[2] == 0) dst[191:128] := a[191:128]; FI
-IF (imm8[2] == 1) dst[191:128] := a[255:192]; FI
-IF (imm8[3] == 0) dst[255:192] := a[191:128]; FI
-IF (imm8[3] == 1) dst[255:192] := a[255:192]; FI
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPERMILPD" xed="VPERMILPD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_permute_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VPERMILPD" xed="VPERMILPD_XMMdq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permute2f128_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src1, src2, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src1[127:0]
-	1:	tmp[127:0] := src1[255:128]
-	2:	tmp[127:0] := src2[127:0]
-	3:	tmp[127:0] := src2[255:128]
-	ESAC
-	IF control[3]
-		tmp[127:0] := 0
-	FI
-	RETURN tmp[127:0]
-}
-dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
-dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPERM2F128" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permute2f128_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src1, src2, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src1[127:0]
-	1:	tmp[127:0] := src1[255:128]
-	2:	tmp[127:0] := src2[127:0]
-	3:	tmp[127:0] := src2[255:128]
-	ESAC
-	IF control[3]
-		tmp[127:0] := 0
-	FI
-	RETURN tmp[127:0]
-}
-dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
-dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPERM2F128" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permute2f128_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src1, src2, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src1[127:0]
-	1:	tmp[127:0] := src1[255:128]
-	2:	tmp[127:0] := src2[127:0]
-	3:	tmp[127:0] := src2[255:128]
-	ESAC
-	IF control[3]
-		tmp[127:0] := 0
-	FI
-	RETURN tmp[127:0]
-}
-dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
-dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPERM2F128" xed="VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insertf128_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insertf128_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[255:0] := a[255:0]
-CASE imm8[0] OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insertf128_si256" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insert_epi8" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__int8" varname="i" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="index" />
-	<description>Copy "a" to "dst", and insert the 8-bit integer "i" into "dst" at the location specified by "index".</description>
-	<operation>
-dst[255:0] := a[255:0]
-sel := index[4:0]*8
-dst[sel+7:sel] := i[7:0]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insert_epi16" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__int16" varname="i" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="index" />
-	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "index".</description>
-	<operation>
-dst[255:0] := a[255:0]
-sel := index[3:0]*16
-dst[sel+15:sel] := i[15:0]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insert_epi32" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__int32" varname="i" />
-	<parameter etype="IMM" immwidth="3" type="const int" varname="index" />
-	<description>Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "index".</description>
-	<operation>
-dst[255:0] := a[255:0]
-sel := index[2:0]*32
-dst[sel+31:sel] := i[31:0]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insert_epi64" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__int64" varname="i" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="index" />
-	<description>Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "index".</description>
-	<operation>
-dst[255:0] := a[255:0]
-sel := index[1:0]*64
-dst[sel+63:sel] := i[63:0]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpackhi_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VUNPCKHPD" xed="VUNPCKHPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpackhi_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VUNPCKHPS" xed="VUNPCKHPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpacklo_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VUNPCKLPD" xed="VUNPCKLPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpacklo_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VUNPCKLPS" xed="VUNPCKLPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMAXPD" xed="VMAXPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMAXPS" xed="VMAXPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMINPD" xed="VMINPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMINPS" xed="VMINPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_round_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ROUND(a[i+63:i], rounding)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VROUNDPD" xed="VROUNDPD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_round_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ROUND(a[i+31:i], rounding)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VROUNDPS" xed="VROUNDPS_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_floor_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := FLOOR(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VROUNDPS" xed="VROUNDPS_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_ceil_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := CEIL(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VROUNDPS" xed="VROUNDPS_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_floor_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := FLOOR(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VROUNDPD" xed="VROUNDPD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_ceil_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := CEIL(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VROUNDPD" xed="VROUNDPD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VCMPPD" xed="VCMPPD_XMMdq_XMMdq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VCMPPD" xed="VCMPPD_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VCMPPS" xed="VCMPPS_XMMdq_XMMdq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VCMPPS" xed="VCMPPS_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_sd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-dst[63:0] := ( a[63:0] OP b[63:0] ) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VCMPSD" xed="VCMPSD_XMMdq_XMMdq_XMMq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_ss" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-dst[31:0] := ( a[31:0] OP b[31:0] ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VCMPSS" xed="VCMPSS_XMMdq_XMMdq_XMMd_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi32_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_YMMqq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi32_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTDQ2PS" xed="VCVTDQ2PS_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtpd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMdq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtps_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTPS2DQ" xed="VCVTPS2DQ_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtps_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPS2PD" xed="VCVTPS2PD_YMMqq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttpd_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMdq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtpd_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMdq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttps_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtss_f32" vexEq="TRUE" tech="AVX_ALL">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-	</operation>
-	<instruction form="m32, xmm" name="VMOVSS" xed="VMOVSS_MEMd_XMMd" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsd_f64" vexEq="TRUE" tech="AVX_ALL">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="m64, xmm" name="VMOVSD" xed="VMOVSD_MEMq_XMMq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsi256_si32" vexEq="TRUE" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-	</operation>
-	<instruction form="r32, xmm" name="VMOVD" xed="VMOVD_GPR32d_XMMd" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_zeroall" tech="AVX_ALL">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Zero the contents of all XMM or YMM registers.</description>
-	<operation>YMM0[MAX:0] := 0
-YMM1[MAX:0] := 0
-YMM2[MAX:0] := 0
-YMM3[MAX:0] := 0
-YMM4[MAX:0] := 0
-YMM5[MAX:0] := 0
-YMM6[MAX:0] := 0
-YMM7[MAX:0] := 0
-IF _64_BIT_MODE
-	YMM8[MAX:0] := 0
-	YMM9[MAX:0] := 0
-	YMM10[MAX:0] := 0
-	YMM11[MAX:0] := 0
-	YMM12[MAX:0] := 0
-	YMM13[MAX:0] := 0
-	YMM14[MAX:0] := 0
-	YMM15[MAX:0] := 0
-FI
-	</operation>
-	<instruction name="VZEROALL" xed="VZEROALL" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm256_zeroupper" tech="AVX_ALL">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Zero the upper 128 bits of all YMM registers; the lower 128-bits of the registers are unmodified.</description>
-	<operation>YMM0[MAX:128] := 0
-YMM1[MAX:128] := 0
-YMM2[MAX:128] := 0
-YMM3[MAX:128] := 0
-YMM4[MAX:128] := 0
-YMM5[MAX:128] := 0
-YMM6[MAX:128] := 0
-YMM7[MAX:128] := 0
-IF _64_BIT_MODE
-	YMM8[MAX:128] := 0
-	YMM9[MAX:128] := 0
-	YMM10[MAX:128] := 0
-	YMM11[MAX:128] := 0
-	YMM12[MAX:128] := 0
-	YMM13[MAX:128] := 0
-	YMM14[MAX:128] := 0
-	YMM15[MAX:128] := 0
-FI
-	</operation>
-	<instruction name="VZEROUPPER" xed="VZEROUPPER" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm256_undefined_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m256 with undefined elements.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm256_undefined_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m256d with undefined elements.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm256_undefined_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m256i with undefined elements.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_ss" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" memwidth="32" type="float const *" varname="mem_addr" />
-	<description>Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst".</description>
-	<operation>
-tmp[31:0] := MEM[mem_addr+31:mem_addr]
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := tmp[31:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m32" name="VBROADCASTSS" xed="VBROADCASTSS_YMMqq_MEMd" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcast_ss" tech="AVX_ALL">
-	<category>Swizzle</category>
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="32" type="float const *" varname="mem_addr" />
-	<description>Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst".</description>
-	<operation>
-tmp[31:0] := MEM[mem_addr+31:mem_addr]
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := tmp[31:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m32" name="VBROADCASTSS" xed="VBROADCASTSS_XMMdq_MEMd" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_sd" tech="AVX_ALL">
-	<category>Swizzle</category>
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" memwidth="64" type="double const *" varname="mem_addr" />
-	<description>Broadcast a double-precision (64-bit) floating-point element from memory to all elements of "dst".</description>
-	<operation>
-tmp[63:0] := MEM[mem_addr+63:mem_addr]
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := tmp[63:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m64" name="VBROADCASTSD" xed="VBROADCASTSD_YMMqq_MEMq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_ps" tech="AVX_ALL">
-	<category>Swizzle</category>
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" memwidth="128" type="__m128 const *" varname="mem_addr" />
-	<description>Broadcast 128 bits from memory (composed of 4 packed single-precision (32-bit) floating-point elements) to all elements of "dst".</description>
-	<operation>
-tmp[127:0] := MEM[mem_addr+127:mem_addr]
-dst[127:0] := tmp[127:0]
-dst[255:128] := tmp[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m128" name="VBROADCASTF128" xed="VBROADCASTF128_YMMqq_MEMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_pd" tech="AVX_ALL">
-	<category>Swizzle</category>
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" memwidth="128" type="__m128d const *" varname="mem_addr" />
-	<description>Broadcast 128 bits from memory (composed of 2 packed double-precision (64-bit) floating-point elements) to all elements of "dst".</description>
-	<operation>
-tmp[127:0] := MEM[mem_addr+127:mem_addr]
-dst[127:0] := tmp[127:0]
-dst[255:128] := tmp[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m128" name="VBROADCASTF128" xed="VBROADCASTF128_YMMqq_MEMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_load_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" memwidth="256" type="double const *" varname="mem_addr" />
-	<description>Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst".
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVAPD" xed="VMOVAPD_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_load_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" memwidth="256" type="float const *" varname="mem_addr" />
-	<description>Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst".
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVAPS" xed="VMOVAPS_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" memwidth="256" type="double const *" varname="mem_addr" />
-	<description>Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVUPD" xed="VMOVUPD_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" memwidth="256" type="float const *" varname="mem_addr" />
-	<description>Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVUPS" xed="VMOVUPS_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_load_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" memwidth="256" type="__m256i const *" varname="mem_addr" />
-	<description>Load 256-bits of integer data from memory into "dst".
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVDQA" xed="VMOVDQA_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" memwidth="256" type="__m256i const *" varname="mem_addr" />
-	<description>Load 256-bits of integer data from memory into "dst".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVDQU" xed="VMOVDQU_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskload_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" memwidth="256" type="double const *" varname="mem_addr" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF mask[i+63]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, m256" name="VMASKMOVPD" xed="VMASKMOVPD_YMMqq_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskload_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="128" type="double const *" varname="mem_addr" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF mask[i+63]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, m128" name="VMASKMOVPD" xed="VMASKMOVPD_XMMdq_XMMdq_MEMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskload_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" memwidth="256" type="float const *" varname="mem_addr" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF mask[i+31]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, m256" name="VMASKMOVPS" xed="VMASKMOVPS_YMMqq_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskload_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="128" type="float const *" varname="mem_addr" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF mask[i+31]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, m128" name="VMASKMOVPS" xed="VMASKMOVPS_XMMdq_XMMdq_MEMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_lddqu_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" memwidth="256" type="__m256i const *" varname="mem_addr" />
-	<description>Load 256-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm256_loadu_si256" when the data crosses a cache line boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VLDDQU" xed="VLDDQU_YMMqq_MEMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu2_m128" sequence="TRUE" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" memwidth="128" type="float const*" varname="hiaddr" />
-	<parameter etype="FP32" memwidth="128" type="float const*" varname="loaddr" />
-	<description>Load two 128-bit values (composed of 4 packed single-precision (32-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst".
-	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[loaddr+127:loaddr]
-dst[255:128] := MEM[hiaddr+127:hiaddr]
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu2_m128d" sequence="TRUE" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" memwidth="128" type="double const*" varname="hiaddr" />
-	<parameter etype="FP64" memwidth="128" type="double const*" varname="loaddr" />
-	<description>Load two 128-bit values (composed of 2 packed double-precision (64-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst".
-	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[loaddr+127:loaddr]
-dst[255:128] := MEM[hiaddr+127:hiaddr]
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu2_m128i" sequence="TRUE" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="hiaddr" />
-	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="loaddr" />
-	<description>Load two 128-bit values (composed of integer data) from memory, and combine them into a 256-bit value in "dst".
-	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[loaddr+127:loaddr]
-dst[255:128] := MEM[hiaddr+127:hiaddr]
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_store_pd" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="256" type="double *" varname="mem_addr" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory.
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVAPD" xed="VMOVAPD_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_store_ps" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="256" type="float *" varname="mem_addr" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory.
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVAPS" xed="VMOVAPS_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu_pd" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="256" type="double *" varname="mem_addr" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory.
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVUPD" xed="VMOVUPD_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu_ps" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="256" type="float *" varname="mem_addr" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory.
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVUPS" xed="VMOVUPS_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_store_si256" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="M256" memwidth="256" type="__m256i *" varname="mem_addr" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<description>Store 256-bits of integer data from "a" into memory.
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVDQA" xed="VMOVDQA_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu_si256" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="M256" memwidth="256" type="__m256i *" varname="mem_addr" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<description>Store 256-bits of integer data from "a" into memory.
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVDQU" xed="VMOVDQU_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskstore_pd" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="256" type="double *" varname="mem_addr" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF mask[i+63]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256, ymm, ymm" name="VMASKMOVPD" xed="VMASKMOVPD_MEMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskstore_pd" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="double *" varname="mem_addr" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF mask[i+63]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128, xmm, xmm" name="VMASKMOVPD" xed="VMASKMOVPD_MEMdq_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskstore_ps" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="256" type="float *" varname="mem_addr" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF mask[i+31]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256, ymm, ymm" name="VMASKMOVPS" xed="VMASKMOVPS_MEMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskstore_ps" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="float *" varname="mem_addr" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF mask[i+31]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128, xmm, xmm" name="VMASKMOVPS" xed="VMASKMOVPS_MEMdq_XMMdq_XMMdq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_stream_si256" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="M256" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<description>Store 256-bits of integer data from "a" into memory using a non-temporal memory hint.
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVNTDQ" xed="VMOVNTDQ_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_stream_pd" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVNTPD" xed="VMOVNTPD_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_stream_ps" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVNTPS" xed="VMOVNTPS_MEMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu2_m128" sequence="TRUE" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="float*" varname="hiaddr" />
-	<parameter etype="FP32" memwidth="128" type="float*" varname="loaddr" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Store the high and low 128-bit halves (each composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory two different 128-bit locations.
-	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[loaddr+127:loaddr] := a[127:0]
-MEM[hiaddr+127:hiaddr] := a[255:128]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu2_m128d" sequence="TRUE" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="double*" varname="hiaddr" />
-	<parameter etype="FP64" memwidth="128" type="double*" varname="loaddr" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Store the high and low 128-bit halves (each composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory two different 128-bit locations.
-	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[loaddr+127:loaddr] := a[127:0]
-MEM[hiaddr+127:hiaddr] := a[255:128]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu2_m128i" sequence="TRUE" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="M128" memwidth="128" type="__m128i*" varname="hiaddr" />
-	<parameter etype="M128" memwidth="128" type="__m128i*" varname="loaddr" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<description>Store the high and low 128-bit halves (each composed of integer data) from "a" into memory two different 128-bit locations.
-	"hiaddr" and "loaddr" do not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[loaddr+127:loaddr] := a[127:0]
-MEM[hiaddr+127:hiaddr] := a[255:128]
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movehdup_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32] 
-dst[63:32] := a[63:32] 
-dst[95:64] := a[127:96] 
-dst[127:96] := a[127:96]
-dst[159:128] := a[191:160] 
-dst[191:160] := a[191:160] 
-dst[223:192] := a[255:224] 
-dst[255:224] := a[255:224]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VMOVSHDUP" xed="VMOVSHDUP_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_moveldup_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] 
-dst[63:32] := a[31:0] 
-dst[95:64] := a[95:64] 
-dst[127:96] := a[95:64]
-dst[159:128] := a[159:128] 
-dst[191:160] := a[159:128] 
-dst[223:192] := a[223:192] 
-dst[255:224] := a[223:192]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VMOVSLDUP" xed="VMOVSLDUP_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movedup_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := a[63:0]
-dst[191:128] := a[191:128]
-dst[255:192] := a[191:128]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VMOVDDUP" xed="VMOVDDUP_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rcp_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := 1.0 / a[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VRCPPS" xed="VRCPPS_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rsqrt_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VRSQRTPS" xed="VRSQRTPS_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sqrt_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SQRT(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VSQRTPD" xed="VSQRTPD_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sqrt_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SQRT(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VSQRTPS" xed="VSQRTPS_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movemask_pd" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF a[i+63]
-		dst[j] := 1
-	ELSE
-		dst[j] := 0
-	FI
-ENDFOR
-dst[MAX:4] := 0
-	</operation>
-	<instruction form="r32, ymm" name="VMOVMSKPD" xed="VMOVMSKPD_GPR32d_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movemask_ps" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF a[i+31]
-		dst[j] := 1
-	ELSE
-		dst[j] := 0
-	FI
-ENDFOR
-dst[MAX:8] := 0
-	</operation>
-	<instruction form="r32, ymm" name="VMOVMSKPS" xed="VMOVMSKPS_GPR32d_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setzero_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m256d with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VXORPD" xed="VXORPD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setzero_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m256 with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VXORPS" xed="VXORPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setzero_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m256i with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPXOR" xed="VPXOR_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_pd" sequence="TRUE" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="e3" />
-	<parameter etype="FP64" type="double" varname="e2" />
-	<parameter etype="FP64" type="double" varname="e1" />
-	<parameter etype="FP64" type="double" varname="e0" />
-	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst[63:0] := e0
-dst[127:64] := e1
-dst[191:128] := e2
-dst[255:192] := e3
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_ps" sequence="TRUE" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="float" varname="e7" />
-	<parameter etype="FP32" type="float" varname="e6" />
-	<parameter etype="FP32" type="float" varname="e5" />
-	<parameter etype="FP32" type="float" varname="e4" />
-	<parameter etype="FP32" type="float" varname="e3" />
-	<parameter etype="FP32" type="float" varname="e2" />
-	<parameter etype="FP32" type="float" varname="e1" />
-	<parameter etype="FP32" type="float" varname="e0" />
-	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst[31:0] := e0
-dst[63:32] := e1
-dst[95:64] := e2
-dst[127:96] := e3
-dst[159:128] := e4
-dst[191:160] := e5
-dst[223:192] := e6
-dst[255:224] := e7
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_epi8" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="char" varname="e31" />
-	<parameter etype="UI8" type="char" varname="e30" />
-	<parameter etype="UI8" type="char" varname="e29" />
-	<parameter etype="UI8" type="char" varname="e28" />
-	<parameter etype="UI8" type="char" varname="e27" />
-	<parameter etype="UI8" type="char" varname="e26" />
-	<parameter etype="UI8" type="char" varname="e25" />
-	<parameter etype="UI8" type="char" varname="e24" />
-	<parameter etype="UI8" type="char" varname="e23" />
-	<parameter etype="UI8" type="char" varname="e22" />
-	<parameter etype="UI8" type="char" varname="e21" />
-	<parameter etype="UI8" type="char" varname="e20" />
-	<parameter etype="UI8" type="char" varname="e19" />
-	<parameter etype="UI8" type="char" varname="e18" />
-	<parameter etype="UI8" type="char" varname="e17" />
-	<parameter etype="UI8" type="char" varname="e16" />
-	<parameter etype="UI8" type="char" varname="e15" />
-	<parameter etype="UI8" type="char" varname="e14" />
-	<parameter etype="UI8" type="char" varname="e13" />
-	<parameter etype="UI8" type="char" varname="e12" />
-	<parameter etype="UI8" type="char" varname="e11" />
-	<parameter etype="UI8" type="char" varname="e10" />
-	<parameter etype="UI8" type="char" varname="e9" />
-	<parameter etype="UI8" type="char" varname="e8" />
-	<parameter etype="UI8" type="char" varname="e7" />
-	<parameter etype="UI8" type="char" varname="e6" />
-	<parameter etype="UI8" type="char" varname="e5" />
-	<parameter etype="UI8" type="char" varname="e4" />
-	<parameter etype="UI8" type="char" varname="e3" />
-	<parameter etype="UI8" type="char" varname="e2" />
-	<parameter etype="UI8" type="char" varname="e1" />
-	<parameter etype="UI8" type="char" varname="e0" />
-	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[7:0] := e0
-dst[15:8] := e1
-dst[23:16] := e2
-dst[31:24] := e3
-dst[39:32] := e4
-dst[47:40] := e5
-dst[55:48] := e6
-dst[63:56] := e7
-dst[71:64] := e8
-dst[79:72] := e9
-dst[87:80] := e10
-dst[95:88] := e11
-dst[103:96] := e12
-dst[111:104] := e13
-dst[119:112] := e14
-dst[127:120] := e15
-dst[135:128] := e16
-dst[143:136] := e17
-dst[151:144] := e18
-dst[159:152] := e19
-dst[167:160] := e20
-dst[175:168] := e21
-dst[183:176] := e22
-dst[191:184] := e23
-dst[199:192] := e24
-dst[207:200] := e25
-dst[215:208] := e26
-dst[223:216] := e27
-dst[231:224] := e28
-dst[239:232] := e29
-dst[247:240] := e30
-dst[255:248] := e31
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_epi16" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="e15" />
-	<parameter etype="UI16" type="short" varname="e14" />
-	<parameter etype="UI16" type="short" varname="e13" />
-	<parameter etype="UI16" type="short" varname="e12" />
-	<parameter etype="UI16" type="short" varname="e11" />
-	<parameter etype="UI16" type="short" varname="e10" />
-	<parameter etype="UI16" type="short" varname="e9" />
-	<parameter etype="UI16" type="short" varname="e8" />
-	<parameter etype="UI16" type="short" varname="e7" />
-	<parameter etype="UI16" type="short" varname="e6" />
-	<parameter etype="UI16" type="short" varname="e5" />
-	<parameter etype="UI16" type="short" varname="e4" />
-	<parameter etype="UI16" type="short" varname="e3" />
-	<parameter etype="UI16" type="short" varname="e2" />
-	<parameter etype="UI16" type="short" varname="e1" />
-	<parameter etype="UI16" type="short" varname="e0" />
-	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[15:0] := e0
-dst[31:16] := e1
-dst[47:32] := e2
-dst[63:48] := e3
-dst[79:64] := e4
-dst[95:80] := e5
-dst[111:96] := e6
-dst[127:112] := e7
-dst[143:128] := e8
-dst[159:144] := e9
-dst[175:160] := e10
-dst[191:176] := e11
-dst[207:192] := e12
-dst[223:208] := e13
-dst[239:224] := e14
-dst[255:240] := e15
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_epi32" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="e7" />
-	<parameter etype="UI32" type="int" varname="e6" />
-	<parameter etype="UI32" type="int" varname="e5" />
-	<parameter etype="UI32" type="int" varname="e4" />
-	<parameter etype="UI32" type="int" varname="e3" />
-	<parameter etype="UI32" type="int" varname="e2" />
-	<parameter etype="UI32" type="int" varname="e1" />
-	<parameter etype="UI32" type="int" varname="e0" />
-	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[31:0] := e0
-dst[63:32] := e1
-dst[95:64] := e2
-dst[127:96] := e3
-dst[159:128] := e4
-dst[191:160] := e5
-dst[223:192] := e6
-dst[255:224] := e7
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_epi64x" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="e3" />
-	<parameter etype="UI64" type="__int64" varname="e2" />
-	<parameter etype="UI64" type="__int64" varname="e1" />
-	<parameter etype="UI64" type="__int64" varname="e0" />
-	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[63:0] := e0
-dst[127:64] := e1
-dst[191:128] := e2
-dst[255:192] := e3
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_pd" sequence="TRUE" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="e3" />
-	<parameter etype="FP64" type="double" varname="e2" />
-	<parameter etype="FP64" type="double" varname="e1" />
-	<parameter etype="FP64" type="double" varname="e0" />
-	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[63:0] := e3
-dst[127:64] := e2
-dst[191:128] := e1
-dst[255:192] := e0
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_ps" sequence="TRUE" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="float" varname="e7" />
-	<parameter etype="FP32" type="float" varname="e6" />
-	<parameter etype="FP32" type="float" varname="e5" />
-	<parameter etype="FP32" type="float" varname="e4" />
-	<parameter etype="FP32" type="float" varname="e3" />
-	<parameter etype="FP32" type="float" varname="e2" />
-	<parameter etype="FP32" type="float" varname="e1" />
-	<parameter etype="FP32" type="float" varname="e0" />
-	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[31:0] := e7
-dst[63:32] := e6
-dst[95:64] := e5
-dst[127:96] := e4
-dst[159:128] := e3
-dst[191:160] := e2
-dst[223:192] := e1
-dst[255:224] := e0
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_epi8" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="char" varname="e31" />
-	<parameter etype="UI8" type="char" varname="e30" />
-	<parameter etype="UI8" type="char" varname="e29" />
-	<parameter etype="UI8" type="char" varname="e28" />
-	<parameter etype="UI8" type="char" varname="e27" />
-	<parameter etype="UI8" type="char" varname="e26" />
-	<parameter etype="UI8" type="char" varname="e25" />
-	<parameter etype="UI8" type="char" varname="e24" />
-	<parameter etype="UI8" type="char" varname="e23" />
-	<parameter etype="UI8" type="char" varname="e22" />
-	<parameter etype="UI8" type="char" varname="e21" />
-	<parameter etype="UI8" type="char" varname="e20" />
-	<parameter etype="UI8" type="char" varname="e19" />
-	<parameter etype="UI8" type="char" varname="e18" />
-	<parameter etype="UI8" type="char" varname="e17" />
-	<parameter etype="UI8" type="char" varname="e16" />
-	<parameter etype="UI8" type="char" varname="e15" />
-	<parameter etype="UI8" type="char" varname="e14" />
-	<parameter etype="UI8" type="char" varname="e13" />
-	<parameter etype="UI8" type="char" varname="e12" />
-	<parameter etype="UI8" type="char" varname="e11" />
-	<parameter etype="UI8" type="char" varname="e10" />
-	<parameter etype="UI8" type="char" varname="e9" />
-	<parameter etype="UI8" type="char" varname="e8" />
-	<parameter etype="UI8" type="char" varname="e7" />
-	<parameter etype="UI8" type="char" varname="e6" />
-	<parameter etype="UI8" type="char" varname="e5" />
-	<parameter etype="UI8" type="char" varname="e4" />
-	<parameter etype="UI8" type="char" varname="e3" />
-	<parameter etype="UI8" type="char" varname="e2" />
-	<parameter etype="UI8" type="char" varname="e1" />
-	<parameter etype="UI8" type="char" varname="e0" />
-	<description>Set packed 8-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[7:0] := e31
-dst[15:8] := e30
-dst[23:16] := e29
-dst[31:24] := e28
-dst[39:32] := e27
-dst[47:40] := e26
-dst[55:48] := e25
-dst[63:56] := e24
-dst[71:64] := e23
-dst[79:72] := e22
-dst[87:80] := e21
-dst[95:88] := e20
-dst[103:96] := e19
-dst[111:104] := e18
-dst[119:112] := e17
-dst[127:120] := e16
-dst[135:128] := e15
-dst[143:136] := e14
-dst[151:144] := e13
-dst[159:152] := e12
-dst[167:160] := e11
-dst[175:168] := e10
-dst[183:176] := e9
-dst[191:184] := e8
-dst[199:192] := e7
-dst[207:200] := e6
-dst[215:208] := e5
-dst[223:216] := e4
-dst[231:224] := e3
-dst[239:232] := e2
-dst[247:240] := e1
-dst[255:248] := e0
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_epi16" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="e15" />
-	<parameter etype="UI16" type="short" varname="e14" />
-	<parameter etype="UI16" type="short" varname="e13" />
-	<parameter etype="UI16" type="short" varname="e12" />
-	<parameter etype="UI16" type="short" varname="e11" />
-	<parameter etype="UI16" type="short" varname="e10" />
-	<parameter etype="UI16" type="short" varname="e9" />
-	<parameter etype="UI16" type="short" varname="e8" />
-	<parameter etype="UI16" type="short" varname="e7" />
-	<parameter etype="UI16" type="short" varname="e6" />
-	<parameter etype="UI16" type="short" varname="e5" />
-	<parameter etype="UI16" type="short" varname="e4" />
-	<parameter etype="UI16" type="short" varname="e3" />
-	<parameter etype="UI16" type="short" varname="e2" />
-	<parameter etype="UI16" type="short" varname="e1" />
-	<parameter etype="UI16" type="short" varname="e0" />
-	<description>Set packed 16-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[15:0] := e15
-dst[31:16] := e14
-dst[47:32] := e13
-dst[63:48] := e12
-dst[79:64] := e11
-dst[95:80] := e10
-dst[111:96] := e9
-dst[127:112] := e8
-dst[143:128] := e7
-dst[159:144] := e6
-dst[175:160] := e5
-dst[191:176] := e4
-dst[207:192] := e3
-dst[223:208] := e2
-dst[239:224] := e1
-dst[255:240] := e0
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_epi32" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="e7" />
-	<parameter etype="UI32" type="int" varname="e6" />
-	<parameter etype="UI32" type="int" varname="e5" />
-	<parameter etype="UI32" type="int" varname="e4" />
-	<parameter etype="UI32" type="int" varname="e3" />
-	<parameter etype="UI32" type="int" varname="e2" />
-	<parameter etype="UI32" type="int" varname="e1" />
-	<parameter etype="UI32" type="int" varname="e0" />
-	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[31:0] := e7
-dst[63:32] := e6
-dst[95:64] := e5
-dst[127:96] := e4
-dst[159:128] := e3
-dst[191:160] := e2
-dst[223:192] := e1
-dst[255:224] := e0
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_epi64x" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="e3" />
-	<parameter etype="UI64" type="__int64" varname="e2" />
-	<parameter etype="UI64" type="__int64" varname="e1" />
-	<parameter etype="UI64" type="__int64" varname="e0" />
-	<description>Set packed 64-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[63:0] := e3
-dst[127:64] := e2
-dst[191:128] := e1
-dst[255:192] := e0
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set1_pd" sequence="TRUE" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="a" />
-	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set1_ps" sequence="TRUE" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set1_epi8" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastb".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := a[7:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set1_epi16" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate the "vpbroadcastw".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := a[15:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set1_epi32" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastd".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set1_epi64x" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="long long" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_m128" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="hi" />
-	<parameter etype="FP32" type="__m128" varname="lo" />
-	<description>Set packed __m256 vector "dst" with the supplied values.</description>
-	<operation>
-dst[127:0] := lo[127:0]
-dst[255:128] := hi[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_m128d" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="hi" />
-	<parameter etype="FP64" type="__m128d" varname="lo" />
-	<description>Set packed __m256d vector "dst" with the supplied values.</description>
-	<operation>
-dst[127:0] := lo[127:0]
-dst[255:128] := hi[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_m128i" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="hi" />
-	<parameter etype="M128" type="__m128i" varname="lo" />
-	<description>Set packed __m256i vector "dst" with the supplied values.</description>
-	<operation>
-dst[127:0] := lo[127:0]
-dst[255:128] := hi[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_m128" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="lo" />
-	<parameter etype="FP32" type="__m128" varname="hi" />
-	<description>Set packed __m256 vector "dst" with the supplied values.</description>
-	<operation>
-dst[127:0] := lo[127:0]
-dst[255:128] := hi[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_m128d" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="lo" />
-	<parameter etype="FP64" type="__m128d" varname="hi" />
-	<description>Set packed __m256d vector "dst" with the supplied values.</description>
-	<operation>
-dst[127:0] := lo[127:0]
-dst[255:128] := hi[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_m128i" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="lo" />
-	<parameter etype="M128" type="__m128i" varname="hi" />
-	<description>Set packed __m256i vector "dst" with the supplied values.</description>
-	<operation>
-dst[127:0] := lo[127:0]
-dst[255:128] := hi[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF128" xed="VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castpd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Cast vector of type __m256d to type __m256.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castps_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Cast vector of type __m256 to type __m256d.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castps_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Cast vector of type __m256 to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castpd_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Cast vector of type __m256d to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castsi256_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Cast vector of type __m256i to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castsi256_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Cast vector of type __m256i to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castps256_ps128" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Cast vector of type __m256 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castpd256_pd128" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Cast vector of type __m256d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castsi256_si128" tech="AVX_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<description>Cast vector of type __m256i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castps128_ps256" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Cast vector of type __m128 to type __m256; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castpd128_pd256" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Cast vector of type __m128d to type __m256d; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castsi128_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m128i" varname="a" />
-	<description>Cast vector of type __m128i to type __m256i; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_zextps128_ps256" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Cast vector of type __m128 to type __m256; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_zextpd128_pd256" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Cast vector of type __m128d to type __m256d; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_zextsi128_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m128i" varname="a" />
-	<description>Cast vector of type __m128i to type __m256i; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_extract_epi8" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI8" type="int" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="index" />
-	<description>Extract an 8-bit integer from "a", selected with "index", and store the result in "dst".</description>
-	<operation>
-dst[7:0] := (a[255:0] &gt;&gt; (index[4:0] * 8))[7:0]
-	</operation>
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extract_epi16" sequence="TRUE" tech="AVX_ALL">
-	<return etype="UI16" type="int" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="index" />
-	<description>Extract a 16-bit integer from "a", selected with "index", and store the result in "dst".</description>
-	<operation>
-dst[15:0] := (a[255:0] &gt;&gt; (index[3:0] * 16))[15:0]
-	</operation>
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_blend_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Blend packed 16-bit integers from "a" and "b" within 128-bit lanes using control mask "imm8", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF imm8[j%8]
-		dst[i+15:i] := b[i+15:i]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPBLENDW" xed="VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_blend_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF imm8[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPBLENDD" xed="VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_blend_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF imm8[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPBLENDD" xed="VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_blendv_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<description>Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF mask[i+7]
-		dst[i+7:i] := b[i+7:i]
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, ymm" name="VPBLENDVB" xed="VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastb_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := a[7:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_XMMdq_XMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcastb_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := a[7:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_YMMqq_XMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastd_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_XMMdq_XMMd" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcastd_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_YMMqq_XMMd" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastq_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMdq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcastq_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastsd_pd" vexEq="TRUE" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="MOVDDUP" xed="MOVDDUP_XMMdq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcastsd_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_YMMqq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastsi128_si256" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst".</description>
-	<operation>
-dst[127:0] := a[127:0]
-dst[255:128] := a[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m128" name="VBROADCASTI128" xed="VBROADCASTI128_YMMqq_MEMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcastsi128_si256" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst".</description>
-	<operation>
-dst[127:0] := a[127:0]
-dst[255:128] := a[127:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m128" name="VBROADCASTI128" xed="VBROADCASTI128_YMMqq_MEMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastss_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_XMMdq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcastss_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_YMMqq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastw_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := a[15:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_XMMdq_XMMw" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcastw_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := a[15:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_YMMqq_XMMw" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extracti128_si256" tech="AVX_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VEXTRACTI128" xed="VEXTRACTI128_XMMdq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_inserti128_si256" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of integer data) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTI128" xed="VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permute2x128_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src1, src2, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src1[127:0]
-	1:	tmp[127:0] := src1[255:128]
-	2:	tmp[127:0] := src2[127:0]
-	3:	tmp[127:0] := src2[255:128]
-	ESAC
-	IF control[3]
-		tmp[127:0] := 0
-	FI
-	RETURN tmp[127:0]
-}
-dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0])
-dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPERM2I128" xed="VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permute4x64_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPERMQ" xed="VPERMQ_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permute4x64_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPERMPD" xed="VPERMPD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutevar8x32_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	id := idx[i+2:i]*32
-	dst[i+31:i] := a[id+31:id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMD" xed="VPERMD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutevar8x32_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	id := idx[i+2:i]*32
-	dst[i+31:i] := a[id+31:id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMPS" xed="VPERMPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shuffle_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSHUFD" xed="VPSHUFD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shuffle_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF b[i+7] == 1
-		dst[i+7:i] := 0
-	ELSE
-		index[3:0] := b[i+3:i]
-		dst[i+7:i] := a[index*8+7:index*8]
-	FI
-	IF b[128+i+7] == 1
-		dst[128+i+7:128+i] := 0
-	ELSE
-		index[3:0] := b[128+i+3:128+i]
-		dst[128+i+7:128+i] := a[128+index*8+7:128+index*8]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSHUFB" xed="VPSHUFB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shufflehi_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-dst[191:128] := a[191:128]
-dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
-dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
-dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
-dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSHUFHW" xed="VPSHUFHW_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shufflelo_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
-	<operation>
-dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-dst[127:64] := a[127:64]
-dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
-dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
-dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
-dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
-dst[255:192] := a[255:192]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSHUFLW" xed="VPSHUFLW_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpackhi_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPUNPCKHBW" xed="VPUNPCKHBW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpackhi_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPUNPCKHWD" xed="VPUNPCKHWD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpackhi_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpackhi_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpacklo_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPUNPCKLBW" xed="VPUNPCKLBW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpacklo_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPUNPCKLWD" xed="VPUNPCKLWD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpacklo_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_unpacklo_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_abs_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := ABS(a[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPABSB" xed="VPABSB_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_abs_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ABS(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPABSW" xed="VPABSW_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_abs_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ABS(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPABSD" xed="VPABSD_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMAXSB" xed="VPMAXSB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMAXSW" xed="VPMAXSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMAXSD" xed="VPMAXSD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_epu8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMAXUB" xed="VPMAXUB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_epu16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMAXUW" xed="VPMAXUW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_epu32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMAXUD" xed="VPMAXUD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMINSB" xed="VPMINSB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMINSW" xed="VPMINSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMINSD" xed="VPMINSD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_epu8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMINUB" xed="VPMINUB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_epu16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMINUW" xed="VPMINUW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_epu32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMINUD" xed="VPMINUD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_add_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := a[i+7:i] + b[i+7:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPADDB" xed="VPADDB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_add_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := a[i+15:i] + b[i+15:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPADDW" xed="VPADDW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_add_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPADDD" xed="VPADDD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_add_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] + b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPADDQ" xed="VPADDQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_adds_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPADDSB" xed="VPADDSB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_adds_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPADDSW" xed="VPADDSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_adds_epu8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPADDUSB" xed="VPADDUSB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_adds_epu16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPADDUSW" xed="VPADDUSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hadd_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := a[31:16] + a[15:0]
-dst[31:16] := a[63:48] + a[47:32]
-dst[47:32] := a[95:80] + a[79:64]
-dst[63:48] := a[127:112] + a[111:96]
-dst[79:64] := b[31:16] + b[15:0]
-dst[95:80] := b[63:48] + b[47:32]
-dst[111:96] := b[95:80] + b[79:64]
-dst[127:112] := b[127:112] + b[111:96]
-dst[143:128] := a[159:144] + a[143:128]
-dst[159:144] := a[191:176] + a[175:160]
-dst[175:160] := a[223:208] + a[207:192]
-dst[191:176] := a[255:240] + a[239:224]
-dst[207:192] := b[159:144] + b[143:128]
-dst[223:208] := b[191:176] + b[175:160]
-dst[239:224] := b[223:208] + b[207:192]
-dst[255:240] := b[255:240] + b[239:224]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPHADDW" xed="VPHADDW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hadd_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32] + a[31:0]
-dst[63:32] := a[127:96] + a[95:64]
-dst[95:64] := b[63:32] + b[31:0]
-dst[127:96] := b[127:96] + b[95:64]
-dst[159:128] := a[191:160] + a[159:128]
-dst[191:160] := a[255:224] + a[223:192]
-dst[223:192] := b[191:160] + b[159:128]
-dst[255:224] := b[255:224] + b[223:192]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPHADDD" xed="VPHADDD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hadds_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[31:16] + a[15:0])
-dst[31:16] := Saturate16(a[63:48] + a[47:32])
-dst[47:32] := Saturate16(a[95:80] + a[79:64])
-dst[63:48] := Saturate16(a[127:112] + a[111:96])
-dst[79:64] := Saturate16(b[31:16] + b[15:0])
-dst[95:80] := Saturate16(b[63:48] + b[47:32])
-dst[111:96] := Saturate16(b[95:80] + b[79:64])
-dst[127:112] := Saturate16(b[127:112] + b[111:96])
-dst[143:128] := Saturate16(a[159:144] + a[143:128])
-dst[159:144] := Saturate16(a[191:176] + a[175:160])
-dst[175:160] := Saturate16(a[223:208] + a[207:192])
-dst[191:176] := Saturate16(a[255:240] + a[239:224])
-dst[207:192] := Saturate16(b[159:144] + b[143:128])
-dst[223:208] := Saturate16(b[191:176] + b[175:160])
-dst[239:224] := Saturate16(b[223:208] + b[207:192])
-dst[255:240] := Saturate16(b[255:240] + b[239:224])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPHADDSW" xed="VPHADDSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hsub_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := a[15:0] - a[31:16]
-dst[31:16] := a[47:32] - a[63:48]
-dst[47:32] := a[79:64] - a[95:80]
-dst[63:48] := a[111:96] - a[127:112]
-dst[79:64] := b[15:0] - b[31:16]
-dst[95:80] := b[47:32] - b[63:48]
-dst[111:96] := b[79:64] - b[95:80]
-dst[127:112] := b[111:96] - b[127:112]
-dst[143:128] := a[143:128] - a[159:144]
-dst[159:144] := a[175:160] - a[191:176]
-dst[175:160] := a[207:192] - a[223:208]
-dst[191:176] := a[239:224] - a[255:240]
-dst[207:192] := b[143:128] - b[159:144]
-dst[223:208] := b[175:160] - b[191:176]
-dst[239:224] := b[207:192] - b[223:208]
-dst[255:240] := b[239:224] - b[255:240]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPHSUBW" xed="VPHSUBW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hsub_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] - a[63:32]
-dst[63:32] := a[95:64] - a[127:96]
-dst[95:64] := b[31:0] - b[63:32]
-dst[127:96] := b[95:64] - b[127:96]
-dst[159:128] := a[159:128] - a[191:160]
-dst[191:160] := a[223:192] - a[255:224]
-dst[223:192] := b[159:128] - b[191:160]
-dst[255:224] := b[223:192] - b[255:224]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPHSUBD" xed="VPHSUBD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_hsubs_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[15:0] - a[31:16])
-dst[31:16] := Saturate16(a[47:32] - a[63:48])
-dst[47:32] := Saturate16(a[79:64] - a[95:80])
-dst[63:48] := Saturate16(a[111:96] - a[127:112])
-dst[79:64] := Saturate16(b[15:0] - b[31:16])
-dst[95:80] := Saturate16(b[47:32] - b[63:48])
-dst[111:96] := Saturate16(b[79:64] - b[95:80])
-dst[127:112] := Saturate16(b[111:96] - b[127:112])
-dst[143:128] := Saturate16(a[143:128] - a[159:144])
-dst[159:144] := Saturate16(a[175:160] - a[191:176])
-dst[175:160] := Saturate16(a[207:192] - a[223:208])
-dst[191:176] := Saturate16(a[239:224] - a[255:240])
-dst[207:192] := Saturate16(b[143:128] - b[159:144])
-dst[223:208] := Saturate16(b[175:160] - b[191:176])
-dst[239:224] := Saturate16(b[207:192] - b[223:208])
-dst[255:240] := Saturate16(b[239:224] - b[255:240])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPHSUBSW" xed="VPHSUBSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_madd_epi16" tech="AVX_ALL">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMADDWD" xed="VPMADDWD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maddubs_epi16" tech="AVX_ALL">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMADDUBSW" xed="VPMADDUBSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mul_epi32" tech="AVX_ALL">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULDQ" xed="VPMULDQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mul_epu32" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+31:i] * b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULUDQ" xed="VPMULUDQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mulhi_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULHW" xed="VPMULHW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mulhi_epu16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	tmp[31:0] := a[i+15:i] * b[i+15:i]
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULHUW" xed="VPMULHUW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mulhrs_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-	dst[i+15:i] := tmp[16:1]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULHRSW" xed="VPMULHRSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mullo_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-	dst[i+15:i] := tmp[15:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULLW" xed="VPMULLW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mullo_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Multiply the packed signed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	tmp[63:0] := a[i+31:i] * b[i+31:i]
-	dst[i+31:i] := tmp[31:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULLD" xed="VPMULLD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sad_epu8" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
-ENDFOR
-FOR j := 0 to 3
-	i := j*64
-	dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
-	               tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
-	dst[i+63:i+16] := 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSADBW" xed="VPSADBW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sign_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Negate packed signed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF b[i+7:i] &lt; 0
-		dst[i+7:i] := -(a[i+7:i])
-	ELSE IF b[i+7:i] == 0
-		dst[i+7:i] := 0
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSIGNB" xed="VPSIGNB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sign_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Negate packed signed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF b[i+15:i] &lt; 0
-		dst[i+15:i] := -(a[i+15:i])
-	ELSE IF b[i+15:i] == 0
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSIGNW" xed="VPSIGNW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sign_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Negate packed signed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF b[i+31:i] &lt; 0
-		dst[i+31:i] := -(a[i+31:i])
-	ELSE IF b[i+31:i] == 0
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSIGND" xed="VPSIGND_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sub_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := a[i+7:i] - b[i+7:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSUBB" xed="VPSUBB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sub_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := a[i+15:i] - b[i+15:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSUBW" xed="VPSUBW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sub_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSUBD" xed="VPSUBD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sub_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] - b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSUBQ" xed="VPSUBQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_subs_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSUBSB" xed="VPSUBSB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_subs_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSUBSW" xed="VPSUBSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_subs_epu8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSUBUSB" xed="VPSUBUSB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_subs_epu16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSUBUSW" xed="VPSUBUSW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_alignr_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*128
-	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
-	dst[i+127:i] := tmp[127:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPALIGNR" xed="VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movemask_epi8" tech="AVX_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[j] := a[i+7]
-ENDFOR
-	</operation>
-	<instruction form="r32, ymm" name="VPMOVMSKB" xed="VPMOVMSKB_GPR32d_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mpsadbw_epu8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
-	Eight SADs are performed for each 128-bit lane using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8".</description>
-	<operation>
-DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) {
-	a_offset := imm8[2]*32
-	b_offset := imm8[1:0]*32
-	FOR j := 0 to 7
-		i := j*8
-		k := a_offset+i
-		l := b_offset
-		tmp[i*2+15:i*2] := ABS(Signed(a[k+7:k] - b[l+7:l])) + ABS(Signed(a[k+15:k+8] - b[l+15:l+8])) + \
-		                   ABS(Signed(a[k+23:k+16] - b[l+23:l+16])) + ABS(Signed(a[k+31:k+24] - b[l+31:l+24]))
-	ENDFOR
-	RETURN tmp[127:0]
-}
-dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0])
-dst[255:128] := MPSADBW(a[255:128], b[255:128], imm8[5:3])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VMPSADBW" xed="VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_packs_epi16" tech="AVX_ALL">
-	<return etype="SI8" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := Saturate8(a[15:0])
-dst[15:8] := Saturate8(a[31:16])
-dst[23:16] := Saturate8(a[47:32])
-dst[31:24] := Saturate8(a[63:48])
-dst[39:32] := Saturate8(a[79:64])
-dst[47:40] := Saturate8(a[95:80])
-dst[55:48] := Saturate8(a[111:96])
-dst[63:56] := Saturate8(a[127:112])
-dst[71:64] := Saturate8(b[15:0])
-dst[79:72] := Saturate8(b[31:16])
-dst[87:80] := Saturate8(b[47:32])
-dst[95:88] := Saturate8(b[63:48])
-dst[103:96] := Saturate8(b[79:64])
-dst[111:104] := Saturate8(b[95:80])
-dst[119:112] := Saturate8(b[111:96])
-dst[127:120] := Saturate8(b[127:112])
-dst[135:128] := Saturate8(a[143:128])
-dst[143:136] := Saturate8(a[159:144])
-dst[151:144] := Saturate8(a[175:160])
-dst[159:152] := Saturate8(a[191:176])
-dst[167:160] := Saturate8(a[207:192])
-dst[175:168] := Saturate8(a[223:208])
-dst[183:176] := Saturate8(a[239:224])
-dst[191:184] := Saturate8(a[255:240])
-dst[199:192] := Saturate8(b[143:128])
-dst[207:200] := Saturate8(b[159:144])
-dst[215:208] := Saturate8(b[175:160])
-dst[223:216] := Saturate8(b[191:176])
-dst[231:224] := Saturate8(b[207:192])
-dst[239:232] := Saturate8(b[223:208])
-dst[247:240] := Saturate8(b[239:224])
-dst[255:248] := Saturate8(b[255:240])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPACKSSWB" xed="VPACKSSWB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_packs_epi32" tech="AVX_ALL">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[31:0])
-dst[31:16] := Saturate16(a[63:32])
-dst[47:32] := Saturate16(a[95:64])
-dst[63:48] := Saturate16(a[127:96])
-dst[79:64] := Saturate16(b[31:0])
-dst[95:80] := Saturate16(b[63:32])
-dst[111:96] := Saturate16(b[95:64])
-dst[127:112] := Saturate16(b[127:96])
-dst[143:128] := Saturate16(a[159:128])
-dst[159:144] := Saturate16(a[191:160])
-dst[175:160] := Saturate16(a[223:192])
-dst[191:176] := Saturate16(a[255:224])
-dst[207:192] := Saturate16(b[159:128])
-dst[223:208] := Saturate16(b[191:160])
-dst[239:224] := Saturate16(b[223:192])
-dst[255:240] := Saturate16(b[255:224])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPACKSSDW" xed="VPACKSSDW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_packus_epi16" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := SaturateU8(a[15:0])
-dst[15:8] := SaturateU8(a[31:16])
-dst[23:16] := SaturateU8(a[47:32])
-dst[31:24] := SaturateU8(a[63:48])
-dst[39:32] := SaturateU8(a[79:64])
-dst[47:40] := SaturateU8(a[95:80])
-dst[55:48] := SaturateU8(a[111:96])
-dst[63:56] := SaturateU8(a[127:112])
-dst[71:64] := SaturateU8(b[15:0])
-dst[79:72] := SaturateU8(b[31:16])
-dst[87:80] := SaturateU8(b[47:32])
-dst[95:88] := SaturateU8(b[63:48])
-dst[103:96] := SaturateU8(b[79:64])
-dst[111:104] := SaturateU8(b[95:80])
-dst[119:112] := SaturateU8(b[111:96])
-dst[127:120] := SaturateU8(b[127:112])
-dst[135:128] := SaturateU8(a[143:128])
-dst[143:136] := SaturateU8(a[159:144])
-dst[151:144] := SaturateU8(a[175:160])
-dst[159:152] := SaturateU8(a[191:176])
-dst[167:160] := SaturateU8(a[207:192])
-dst[175:168] := SaturateU8(a[223:208])
-dst[183:176] := SaturateU8(a[239:224])
-dst[191:184] := SaturateU8(a[255:240])
-dst[199:192] := SaturateU8(b[143:128])
-dst[207:200] := SaturateU8(b[159:144])
-dst[215:208] := SaturateU8(b[175:160])
-dst[223:216] := SaturateU8(b[191:176])
-dst[231:224] := SaturateU8(b[207:192])
-dst[239:232] := SaturateU8(b[223:208])
-dst[247:240] := SaturateU8(b[239:224])
-dst[255:248] := SaturateU8(b[255:240])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPACKUSWB" xed="VPACKUSWB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_packus_epi32" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".</description>
-	<operation>
-dst[15:0] := SaturateU16(a[31:0])
-dst[31:16] := SaturateU16(a[63:32])
-dst[47:32] := SaturateU16(a[95:64])
-dst[63:48] := SaturateU16(a[127:96])
-dst[79:64] := SaturateU16(b[31:0])
-dst[95:80] := SaturateU16(b[63:32])
-dst[111:96] := SaturateU16(b[95:64])
-dst[127:112] := SaturateU16(b[127:96])
-dst[143:128] := SaturateU16(a[159:128])
-dst[159:144] := SaturateU16(a[191:160])
-dst[175:160] := SaturateU16(a[223:192])
-dst[191:176] := SaturateU16(a[255:224])
-dst[207:192] := SaturateU16(b[159:128])
-dst[223:208] := SaturateU16(b[191:160])
-dst[239:224] := SaturateU16(b[223:192])
-dst[255:240] := SaturateU16(b[255:224])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPACKUSDW" xed="VPACKUSDW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_and_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[255:0] := (a[255:0] AND b[255:0])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPAND" xed="VPAND_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_andnot_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<description>Compute the bitwise NOT of 256 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
-	<operation>
-dst[255:0] := ((NOT a[255:0]) AND b[255:0])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPANDN" xed="VPANDN_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_or_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<description>Compute the bitwise OR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[255:0] := (a[255:0] OR b[255:0])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPOR" xed="VPOR_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_xor_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m256i" varname="a" />
-	<parameter etype="M256" type="__m256i" varname="b" />
-	<description>Compute the bitwise XOR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[255:0] := (a[255:0] XOR b[255:0])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPXOR" xed="VPXOR_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_avg_epu8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPAVGB" xed="VPAVGB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_avg_epu16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPAVGW" xed="VPAVGW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPCMPEQB" xed="VPCMPEQB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPCMPEQW" xed="VPCMPEQW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPCMPEQD" xed="VPCMPEQD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPCMPEQQ" xed="VPCMPEQQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epi8" tech="AVX_ALL">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPCMPGTB" xed="VPCMPGTB_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPCMPGTW" xed="VPCMPGTW_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPCMPGTD" xed="VPCMPGTD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ( a[i+63:i] &gt; b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPCMPGTQ" xed="VPCMPGTQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi16_epi32" tech="AVX_ALL">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j:= 0 to 7
-	i := 32*j
-	k := 16*j
-	dst[i+31:i] := SignExtend32(a[k+15:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_YMMqq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi16_epi64" tech="AVX_ALL">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j:= 0 to 3
-	i := 64*j
-	k := 16*j
-	dst[i+63:i] := SignExtend64(a[k+15:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi32_epi64" tech="AVX_ALL">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j:= 0 to 3
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := SignExtend64(a[k+31:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_YMMqq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi8_epi16" tech="AVX_ALL">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	l := j*16
-	dst[l+15:l] := SignExtend16(a[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_YMMqq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi8_epi32" tech="AVX_ALL">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 8*j
-	dst[i+31:i] := SignExtend32(a[k+7:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi8_epi64" tech="AVX_ALL">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 8*j
-	dst[i+63:i] := SignExtend64(a[k+7:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_YMMqq_XMMd" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu16_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 16*j
-	dst[i+31:i] := ZeroExtend32(a[k+15:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_YMMqq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu16_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j:= 0 to 3
-	i := 64*j
-	k := 16*j
-	dst[i+63:i] := ZeroExtend64(a[k+15:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu32_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j:= 0 to 3
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := ZeroExtend64(a[k+31:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_YMMqq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu8_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	l := j*16
-	dst[l+15:l] := ZeroExtend16(a[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_YMMqq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu8_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 8*j
-	dst[i+31:i] := ZeroExtend32(a[k+7:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu8_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 8*j
-	dst[i+63:i] := ZeroExtend64(a[k+7:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_YMMqq_XMMd" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_i32gather_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="double const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm32x, xmm" name="VGATHERDPD" xed="VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i32gather_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="double const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm32x, ymm" name="VGATHERDPD" xed="VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_i32gather_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="float const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm32x, xmm" name="VGATHERDPS" xed="VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i32gather_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="float const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm32x, ymm" name="VGATHERDPS" xed="VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_i32gather_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="int const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm32x, xmm" name="VPGATHERDD" xed="VPGATHERDD_XMMu32_MEMd_XMMi32_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i32gather_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="int const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm32x, ymm" name="VPGATHERDD" xed="VPGATHERDD_YMMu32_MEMd_YMMi32_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_i32gather_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm32x, xmm" name="VPGATHERDQ" xed="VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i32gather_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm32x, ymm" name="VPGATHERDQ" xed="VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_i64gather_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="double const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm64x, xmm" name="VGATHERQPD" xed="VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i64gather_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="double const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm64x, ymm" name="VGATHERQPD" xed="VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_i64gather_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="float const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, vm64x, xmm" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i64gather_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="float const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm64y, xmm" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_i64gather_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="int const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, vm64x, xmm" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i64gather_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="int const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm64y, xmm" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_i64gather_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm64x, xmm" name="VPGATHERQQ" xed="VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i64gather_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm64x, ymm" name="VPGATHERQQ" xed="VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i32gather_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="FP64" type="double const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m128d" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	IF mask[i+63]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-mask[MAX:128] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm32x, xmm" name="VGATHERDPD" xed="VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i32gather_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="FP64" type="double const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m256d" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	IF mask[i+63]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-mask[MAX:256] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm32x, ymm" name="VGATHERDPD" xed="VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i32gather_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="FP32" type="float const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m128" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	IF mask[i+31]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-mask[MAX:128] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm32x, xmm" name="VGATHERDPS" xed="VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i32gather_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="FP32" type="float const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="MASK" type="__m256" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	IF mask[i+31]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-mask[MAX:256] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm32x, ymm" name="VGATHERDPS" xed="VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i32gather_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="UI32" type="int const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	IF mask[i+31]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-mask[MAX:128] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm32x, xmm" name="VPGATHERDD" xed="VPGATHERDD_XMMu32_MEMd_XMMi32_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i32gather_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="UI32" type="int const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	IF mask[i+31]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-mask[MAX:256] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm32x, ymm" name="VPGATHERDD" xed="VPGATHERDD_YMMu32_MEMd_YMMi32_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i32gather_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	IF mask[i+63]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-mask[MAX:128] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm32x, xmm" name="VPGATHERDQ" xed="VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i32gather_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	IF mask[i+63]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-mask[MAX:256] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm32x, ymm" name="VPGATHERDQ" xed="VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i64gather_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="FP64" type="double const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m128d" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	IF mask[i+63]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-mask[MAX:128] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm64x, xmm" name="VGATHERQPD" xed="VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i64gather_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="FP64" type="double const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="MASK" type="__m256d" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	IF mask[i+63]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-mask[MAX:256] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm64x, ymm" name="VGATHERQPD" xed="VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i64gather_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="FP32" type="float const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m128" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	IF mask[i+31]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-mask[MAX:64] := 0
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, vm64x, xmm" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i64gather_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="FP32" type="float const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="MASK" type="__m128" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	IF mask[i+31]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-mask[MAX:128] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm64y, xmm" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i64gather_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="UI32" type="int const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	IF mask[i+31]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-mask[MAX:64] := 0
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, vm64x, xmm" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i64gather_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="UI32" type="int const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	IF mask[i+31]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-mask[MAX:128] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm64y, xmm" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MEMd_XMMi32_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i64gather_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	IF mask[i+63]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-mask[MAX:128] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, vm64x, xmm" name="VPGATHERQQ" xed="VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i64gather_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="UI64" type="__int64 const*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	IF mask[i+63]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-mask[MAX:256] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm64x, ymm" name="VPGATHERQQ" xed="VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskload_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" memwidth="128" type="int const*" varname="mem_addr" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<description>Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF mask[i+31]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, m128" name="VPMASKMOVD" xed="VPMASKMOVD_XMMdq_XMMdq_MEMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskload_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" memwidth="256" type="int const*" varname="mem_addr" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<description>Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF mask[i+31]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, m256" name="VPMASKMOVD" xed="VPMASKMOVD_YMMqq_YMMqq_MEMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskload_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" memwidth="128" type="__int64 const*" varname="mem_addr" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<description>Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF mask[i+63]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, m128" name="VPMASKMOVQ" xed="VPMASKMOVQ_XMMdq_XMMdq_MEMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskload_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" memwidth="256" type="__int64 const*" varname="mem_addr" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<description>Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF mask[i+63]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, m256" name="VPMASKMOVQ" xed="VPMASKMOVQ_YMMqq_YMMqq_MEMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_stream_load_si256" tech="AVX_ALL">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits of integer data from memory into "dst" using a non-temporal memory hint.
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVNTDQA" xed="VMOVNTDQA_YMMqq_MEMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskstore_epi32" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="128" type="int*" varname="mem_addr" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF mask[i+31]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128, xmm, xmm" name="VPMASKMOVD" xed="VPMASKMOVD_MEMdq_XMMdq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskstore_epi32" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="256" type="int*" varname="mem_addr" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF mask[i+31]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256, ymm, ymm" name="VPMASKMOVD" xed="VPMASKMOVD_MEMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskstore_epi64" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="128" type="__int64*" varname="mem_addr" />
-	<parameter etype="MASK" type="__m128i" varname="mask" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF mask[i+63]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128, xmm, xmm" name="VPMASKMOVQ" xed="VPMASKMOVQ_MEMdq_XMMdq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskstore_epi64" tech="AVX_ALL">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="256" type="__int64*" varname="mem_addr" />
-	<parameter etype="MASK" type="__m256i" varname="mask" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF mask[i+63]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256, ymm, ymm" name="VPMASKMOVQ" xed="VPMASKMOVQ_MEMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_slli_si256" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
-dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSLLDQ" xed="VPSLLDQ_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_bslli_epi128" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
-dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSLLDQ" xed="VPSLLDQ_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sll_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSLLW" xed="VPSLLW_YMMqq_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_slli_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSLLW" xed="VPSLLW_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sll_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSLLD" xed="VPSLLD_YMMqq_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_slli_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSLLD" xed="VPSLLD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sll_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSLLQ" xed="VPSLLQ_YMMqq_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_slli_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSLLQ" xed="VPSLLQ_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sllv_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSLLVD" xed="VPSLLVD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sllv_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSLLVD" xed="VPSLLVD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sllv_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSLLVQ" xed="VPSLLVQ_XMMdq_XMMdq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sllv_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSLLVQ" xed="VPSLLVQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sra_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSRAW" xed="VPSRAW_YMMqq_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srai_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSRAW" xed="VPSRAW_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sra_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSRAD" xed="VPSRAD_YMMqq_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srai_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSRAD" xed="VPSRAD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srav_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSRAVD" xed="VPSRAVD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srav_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSRAVD" xed="VPSRAVD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srli_si256" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
-dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSRLDQ" xed="VPSRLDQ_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_bsrli_epi128" tech="AVX_ALL">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
-dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSRLDQ" xed="VPSRLDQ_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srl_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSRLW" xed="VPSRLW_YMMqq_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srli_epi16" tech="AVX_ALL">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSRLW" xed="VPSRLW_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srl_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSRLD" xed="VPSRLD_YMMqq_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srli_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSRLD" xed="VPSRLD_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srl_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSRLQ" xed="VPSRLQ_YMMqq_YMMqq_XMMq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srli_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSRLQ" xed="VPSRLQ_YMMqq_YMMqq_IMMb" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srlv_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSRLVD" xed="VPSRLVD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srlv_epi32" tech="AVX_ALL">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSRLVD" xed="VPSRLVD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srlv_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSRLVQ" xed="VPSRLVQ_XMMdq_XMMdq_XMMdq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srlv_epi64" tech="AVX_ALL">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSRLVQ" xed="VPSRLVQ_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-FOR i := 0 to 1
-	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
-	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
-	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
-	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
-ENDFOR
-FOR j := 0 to 3
-	i := j*64
-	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VDBPSADBW" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-FOR i := 0 to 1
-	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
-	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
-	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
-	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
-ENDFOR
-FOR j := 0 to 3
-	i := j*64
-	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VDBPSADBW" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-FOR i := 0 to 1
-	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
-	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
-	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
-	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
-ENDFOR
-FOR j := 0 to 3
-	i := j*64
-	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VDBPSADBW" xed="VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-tmp.dword[0] := b.dword[ imm8[1:0] ]
-tmp.dword[1] := b.dword[ imm8[3:2] ]
-tmp.dword[2] := b.dword[ imm8[5:4] ]
-tmp.dword[3] := b.dword[ imm8[7:6] ]
-FOR j := 0 to 1
-	i := j*64
-	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-tmp.dword[0] := b.dword[ imm8[1:0] ]
-tmp.dword[1] := b.dword[ imm8[3:2] ]
-tmp.dword[2] := b.dword[ imm8[5:4] ]
-tmp.dword[3] := b.dword[ imm8[7:6] ]
-FOR j := 0 to 1
-	i := j*64
-	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-tmp.dword[0] := b.dword[ imm8[1:0] ]
-tmp.dword[1] := b.dword[ imm8[3:2] ]
-tmp.dword[2] := b.dword[ imm8[5:4] ]
-tmp.dword[3] := b.dword[ imm8[7:6] ]
-FOR j := 0 to 1
-	i := j*64
-	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_alignr_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*128
-	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
-	tmp_dst[i+127:i] := tmp[127:0]
-ENDFOR
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPALIGNR" xed="VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_alignr_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*128
-	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
-	tmp_dst[i+127:i] := tmp[127:0]
-ENDFOR
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPALIGNR" xed="VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_alignr_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[255:0] := ((a[127:0] &lt;&lt; 128)[255:0] OR b[127:0]) &gt;&gt; (imm8*8)
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPALIGNR" xed="VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_alignr_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[255:0] := ((a[127:0] &lt;&lt; 128)[255:0] OR b[127:0]) &gt;&gt; (imm8*8)
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPALIGNR" xed="VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_blend_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := b[i+7:i]
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMB" xed="VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_blend_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := b[i+7:i]
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMB" xed="VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_blend_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := b[i+15:i]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMW" xed="VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_blend_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := b[i+15:i]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMW" xed="VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcastb_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcastb_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_broadcastb_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_broadcastb_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcastw_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcastw_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_broadcastw_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_broadcastw_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask2_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+3:i]
-		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := idx[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2W" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+3:i]
-		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2W" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+3:i]
-		dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2W" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2W" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	off := 16*idx[i+3:i]
-	dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMI2W" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VPERMT2W" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask2_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+2:i]
-		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := idx[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2W" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+2:i]
-		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2W" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+2:i]
-		dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2W" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2W" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	off := 16*idx[i+2:i]
-	dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMI2W" xed="VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VPERMT2W" xed="VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	id := idx[i+3:i]*16
-	IF k[j]
-		dst[i+15:i] := a[id+15:id]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMW" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	id := idx[i+3:i]*16
-	IF k[j]
-		dst[i+15:i] := a[id+15:id]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMW" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	id := idx[i+3:i]*16
-	dst[i+15:i] := a[id+15:id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMW" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	id := idx[i+2:i]*16
-	IF k[j]
-		dst[i+15:i] := a[id+15:id]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMW" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	id := idx[i+2:i]*16
-	IF k[j]
-		dst[i+15:i] := a[id+15:id]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMW" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	id := idx[i+2:i]*16
-	dst[i+15:i] := a[id+15:id]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMW" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movepi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF a[i+7]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm" name="VPMOVB2M" xed="VPMOVB2M_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movepi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF a[i+7]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm" name="VPMOVB2M" xed="VPMOVB2M_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movm_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := 0xFF
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm" name="VPMOVM2B" xed="VPMOVM2B_YMMu8_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movm_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := 0xFF
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm" name="VPMOVM2B" xed="VPMOVM2B_XMMu8_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movm_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := 0xFFFF
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm" name="VPMOVM2W" xed="VPMOVM2W_YMMu16_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movm_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := 0xFFFF
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm" name="VPMOVM2W" xed="VPMOVM2W_XMMu16_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movepi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF a[i+15]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm" name="VPMOVW2M" xed="VPMOVW2M_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movepi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF a[i+15]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm" name="VPMOVW2M" xed="VPMOVW2M_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shuffle_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		IF b[i+7] == 1
-			dst[i+7:i] := 0
-		ELSE
-			index[4:0] := b[i+3:i] + (j &amp; 0x10)
-			dst[i+7:i] := a[index*8+7:index*8]
-		FI
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSHUFB" xed="VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shuffle_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		IF b[i+7] == 1
-			dst[i+7:i] := 0
-		ELSE
-			index[4:0] := b[i+3:i] + (j &amp; 0x10)
-			dst[i+7:i] := a[index*8+7:index*8]
-		FI
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSHUFB" xed="VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shuffle_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		IF b[i+7] == 1
-			dst[i+7:i] := 0
-		ELSE
-			index[3:0] := b[i+3:i]
-			dst[i+7:i] := a[index*8+7:index*8]
-		FI
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSHUFB" xed="VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shuffle_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		IF b[i+7] == 1
-			dst[i+7:i] := 0
-		ELSE
-			index[3:0] := b[i+3:i]
-			dst[i+7:i] := a[index*8+7:index*8]
-		FI
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSHUFB" xed="VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shufflehi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := a[63:0]
-tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-tmp_dst[191:128] := a[191:128]
-tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
-tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
-tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
-tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSHUFHW" xed="VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shufflehi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := a[63:0]
-tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-tmp_dst[191:128] := a[191:128]
-tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
-tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
-tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
-tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSHUFHW" xed="VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shufflehi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := a[63:0]
-tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shufflehi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := a[63:0]
-tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shufflelo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-tmp_dst[127:64] := a[127:64]
-tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
-tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
-tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
-tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
-tmp_dst[255:192] := a[255:192]
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSHUFLW" xed="VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shufflelo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-tmp_dst[127:64] := a[127:64]
-tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
-tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
-tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
-tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
-tmp_dst[255:192] := a[255:192]
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSHUFLW" xed="VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shufflelo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-tmp_dst[127:64] := a[127:64]
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shufflelo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-tmp_dst[127:64] := a[127:64]
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpackhi_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKHBW" xed="VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpackhi_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKHBW" xed="VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpackhi_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpackhi_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpackhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKHWD" xed="VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpackhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKHWD" xed="VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpackhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpackhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpacklo_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKLBW" xed="VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpacklo_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKLBW" xed="VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpacklo_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpacklo_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpacklo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKLWD" xed="VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpacklo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKLWD" xed="VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpacklo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpacklo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m256" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m256" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m128" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m128" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m256" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m256" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m128" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m128" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits (composed of 16 packed 16-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits (composed of 32 packed 8-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 8 packed 16-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m128" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 16 packed 8-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m128" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mov_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mov_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVDQU16" xed="VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mov_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mov_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVDQU16" xed="VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mov_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mov_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVDQU8" xed="VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mov_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mov_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVDQU8" xed="VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_storeu_epi16" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI16" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_storeu_epi16" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI16" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_storeu_epi8" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI8" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_storeu_epi8" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI8" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu_epi16" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI16" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Store 256-bits (composed of 16 packed 16-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu_epi8" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI8" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Store 256-bits (composed of 32 packed 8-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_epi16" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI16" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Store 128-bits (composed of 8 packed 16-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_epi8" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI8" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Store 128-bits (composed of 16 packed 8-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_abs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := ABS(a[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPABSB" xed="VPABSB_YMMi8_MASKmskw_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_abs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := ABS(a[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPABSB" xed="VPABSB_YMMi8_MASKmskw_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_abs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := ABS(a[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPABSB" xed="VPABSB_XMMi8_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_abs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := ABS(a[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPABSB" xed="VPABSB_XMMi8_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_abs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ABS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPABSW" xed="VPABSW_YMMi16_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_abs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ABS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPABSW" xed="VPABSW_YMMi16_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_abs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ABS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPABSW" xed="VPABSW_XMMi16_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_abs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ABS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPABSW" xed="VPABSW_XMMi16_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_add_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] + b[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPADDB" xed="VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_add_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] + b[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPADDB" xed="VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] + b[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPADDB" xed="VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] + b[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPADDB" xed="VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_adds_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPADDSB" xed="VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_adds_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPADDSB" xed="VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_adds_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPADDSB" xed="VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_adds_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPADDSB" xed="VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_adds_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPADDSW" xed="VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_adds_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPADDSW" xed="VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_adds_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPADDSW" xed="VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_adds_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPADDSW" xed="VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_adds_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPADDUSB" xed="VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_adds_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPADDUSB" xed="VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_adds_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPADDUSB" xed="VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_adds_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPADDUSB" xed="VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_adds_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPADDUSW" xed="VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_adds_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPADDUSW" xed="VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_adds_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPADDUSW" xed="VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_adds_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPADDUSW" xed="VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_add_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] + b[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPADDW" xed="VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_add_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] + b[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPADDW" xed="VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] + b[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPADDW" xed="VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] + b[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPADDW" xed="VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_avg_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPAVGB" xed="VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_avg_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPAVGB" xed="VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_avg_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPAVGB" xed="VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_avg_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPAVGB" xed="VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_avg_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPAVGW" xed="VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_avg_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPAVGW" xed="VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_avg_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPAVGW" xed="VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_avg_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPAVGW" xed="VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_maddubs_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMADDUBSW" xed="VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_maddubs_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMADDUBSW" xed="VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_maddubs_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMADDUBSW" xed="VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_maddubs_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMADDUBSW" xed="VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_madd_epi16" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMADDWD" xed="VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_madd_epi16" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMADDWD" xed="VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_madd_epi16" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMADDWD" xed="VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_madd_epi16" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMADDWD" xed="VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMAXSB" xed="VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMAXSB" xed="VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMAXSB" xed="VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMAXSB" xed="VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMAXSW" xed="VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMAXSW" xed="VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMAXSW" xed="VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMAXSW" xed="VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMAXUB" xed="VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMAXUB" xed="VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMAXUB" xed="VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMAXUB" xed="VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMAXUW" xed="VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMAXUW" xed="VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMAXUW" xed="VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMAXUW" xed="VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMINSB" xed="VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMINSB" xed="VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMINSB" xed="VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMINSB" xed="VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMINSW" xed="VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMINSW" xed="VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMINSW" xed="VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMINSW" xed="VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMINUB" xed="VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMINUB" xed="VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMINUB" xed="VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMINUB" xed="VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMINUW" xed="VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMINUW" xed="VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMINUW" xed="VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMINUW" xed="VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mulhrs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-		dst[i+15:i] := tmp[16:1]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULHRSW" xed="VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mulhrs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-		dst[i+15:i] := tmp[16:1]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULHRSW" xed="VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mulhrs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-		dst[i+15:i] := tmp[16:1]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULHRSW" xed="VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mulhrs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-		dst[i+15:i] := tmp[16:1]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULHRSW" xed="VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mulhi_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := a[i+15:i] * b[i+15:i]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULHUW" xed="VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mulhi_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := a[i+15:i] * b[i+15:i]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULHUW" xed="VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mulhi_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := a[i+15:i] * b[i+15:i]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULHUW" xed="VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mulhi_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := a[i+15:i] * b[i+15:i]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULHUW" xed="VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mulhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULHW" xed="VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mulhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULHW" xed="VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mulhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULHW" xed="VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mulhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULHW" xed="VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mullo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULLW" xed="VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mullo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULLW" xed="VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mullo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULLW" xed="VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mullo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULLW" xed="VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sub_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] - b[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSUBB" xed="VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sub_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] - b[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSUBB" xed="VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] - b[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSUBB" xed="VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] - b[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSUBB" xed="VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_subs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSUBSB" xed="VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_subs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSUBSB" xed="VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_subs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSUBSB" xed="VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_subs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSUBSB" xed="VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_subs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSUBSW" xed="VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_subs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSUBSW" xed="VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_subs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSUBSW" xed="VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_subs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSUBSW" xed="VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_subs_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSUBUSB" xed="VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_subs_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSUBUSB" xed="VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_subs_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSUBUSB" xed="VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_subs_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSUBUSB" xed="VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_subs_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSUBUSW" xed="VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_subs_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSUBUSW" xed="VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_subs_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSUBUSW" xed="VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_subs_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSUBUSW" xed="VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sub_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] - b[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSUBW" xed="VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sub_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] - b[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSUBW" xed="VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] - b[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSUBW" xed="VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] - b[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSUBW" xed="VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_packs_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := Saturate16(a[31:0])
-tmp_dst[31:16] := Saturate16(a[63:32])
-tmp_dst[47:32] := Saturate16(a[95:64])
-tmp_dst[63:48] := Saturate16(a[127:96])
-tmp_dst[79:64] := Saturate16(b[31:0])
-tmp_dst[95:80] := Saturate16(b[63:32])
-tmp_dst[111:96] := Saturate16(b[95:64])
-tmp_dst[127:112] := Saturate16(b[127:96])
-tmp_dst[143:128] := Saturate16(a[159:128])
-tmp_dst[159:144] := Saturate16(a[191:160])
-tmp_dst[175:160] := Saturate16(a[223:192])
-tmp_dst[191:176] := Saturate16(a[255:224])
-tmp_dst[207:192] := Saturate16(b[159:128])
-tmp_dst[223:208] := Saturate16(b[191:160])
-tmp_dst[239:224] := Saturate16(b[223:192])
-tmp_dst[255:240] := Saturate16(b[255:224])
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPACKSSDW" xed="VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_packs_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := Saturate16(a[31:0])
-tmp_dst[31:16] := Saturate16(a[63:32])
-tmp_dst[47:32] := Saturate16(a[95:64])
-tmp_dst[63:48] := Saturate16(a[127:96])
-tmp_dst[79:64] := Saturate16(b[31:0])
-tmp_dst[95:80] := Saturate16(b[63:32])
-tmp_dst[111:96] := Saturate16(b[95:64])
-tmp_dst[127:112] := Saturate16(b[127:96])
-tmp_dst[143:128] := Saturate16(a[159:128])
-tmp_dst[159:144] := Saturate16(a[191:160])
-tmp_dst[175:160] := Saturate16(a[223:192])
-tmp_dst[191:176] := Saturate16(a[255:224])
-tmp_dst[207:192] := Saturate16(b[159:128])
-tmp_dst[223:208] := Saturate16(b[191:160])
-tmp_dst[239:224] := Saturate16(b[223:192])
-tmp_dst[255:240] := Saturate16(b[255:224])
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPACKSSDW" xed="VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_packs_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := Saturate16(a[31:0])
-tmp_dst[31:16] := Saturate16(a[63:32])
-tmp_dst[47:32] := Saturate16(a[95:64])
-tmp_dst[63:48] := Saturate16(a[127:96])
-tmp_dst[79:64] := Saturate16(b[31:0])
-tmp_dst[95:80] := Saturate16(b[63:32])
-tmp_dst[111:96] := Saturate16(b[95:64])
-tmp_dst[127:112] := Saturate16(b[127:96])
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPACKSSDW" xed="VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_packs_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := Saturate16(a[31:0])
-tmp_dst[31:16] := Saturate16(a[63:32])
-tmp_dst[47:32] := Saturate16(a[95:64])
-tmp_dst[63:48] := Saturate16(a[127:96])
-tmp_dst[79:64] := Saturate16(b[31:0])
-tmp_dst[95:80] := Saturate16(b[63:32])
-tmp_dst[111:96] := Saturate16(b[95:64])
-tmp_dst[127:112] := Saturate16(b[127:96])
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPACKSSDW" xed="VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_packs_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := Saturate8(a[15:0])
-tmp_dst[15:8] := Saturate8(a[31:16])
-tmp_dst[23:16] := Saturate8(a[47:32])
-tmp_dst[31:24] := Saturate8(a[63:48])
-tmp_dst[39:32] := Saturate8(a[79:64])
-tmp_dst[47:40] := Saturate8(a[95:80])
-tmp_dst[55:48] := Saturate8(a[111:96])
-tmp_dst[63:56] := Saturate8(a[127:112])
-tmp_dst[71:64] := Saturate8(b[15:0])
-tmp_dst[79:72] := Saturate8(b[31:16])
-tmp_dst[87:80] := Saturate8(b[47:32])
-tmp_dst[95:88] := Saturate8(b[63:48])
-tmp_dst[103:96] := Saturate8(b[79:64])
-tmp_dst[111:104] := Saturate8(b[95:80])
-tmp_dst[119:112] := Saturate8(b[111:96])
-tmp_dst[127:120] := Saturate8(b[127:112])
-tmp_dst[135:128] := Saturate8(a[143:128])
-tmp_dst[143:136] := Saturate8(a[159:144])
-tmp_dst[151:144] := Saturate8(a[175:160])
-tmp_dst[159:152] := Saturate8(a[191:176])
-tmp_dst[167:160] := Saturate8(a[207:192])
-tmp_dst[175:168] := Saturate8(a[223:208])
-tmp_dst[183:176] := Saturate8(a[239:224])
-tmp_dst[191:184] := Saturate8(a[255:240])
-tmp_dst[199:192] := Saturate8(b[143:128])
-tmp_dst[207:200] := Saturate8(b[159:144])
-tmp_dst[215:208] := Saturate8(b[175:160])
-tmp_dst[223:216] := Saturate8(b[191:176])
-tmp_dst[231:224] := Saturate8(b[207:192])
-tmp_dst[239:232] := Saturate8(b[223:208])
-tmp_dst[247:240] := Saturate8(b[239:224])
-tmp_dst[255:248] := Saturate8(b[255:240])
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPACKSSWB" xed="VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_packs_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := Saturate8(a[15:0])
-tmp_dst[15:8] := Saturate8(a[31:16])
-tmp_dst[23:16] := Saturate8(a[47:32])
-tmp_dst[31:24] := Saturate8(a[63:48])
-tmp_dst[39:32] := Saturate8(a[79:64])
-tmp_dst[47:40] := Saturate8(a[95:80])
-tmp_dst[55:48] := Saturate8(a[111:96])
-tmp_dst[63:56] := Saturate8(a[127:112])
-tmp_dst[71:64] := Saturate8(b[15:0])
-tmp_dst[79:72] := Saturate8(b[31:16])
-tmp_dst[87:80] := Saturate8(b[47:32])
-tmp_dst[95:88] := Saturate8(b[63:48])
-tmp_dst[103:96] := Saturate8(b[79:64])
-tmp_dst[111:104] := Saturate8(b[95:80])
-tmp_dst[119:112] := Saturate8(b[111:96])
-tmp_dst[127:120] := Saturate8(b[127:112])
-tmp_dst[135:128] := Saturate8(a[143:128])
-tmp_dst[143:136] := Saturate8(a[159:144])
-tmp_dst[151:144] := Saturate8(a[175:160])
-tmp_dst[159:152] := Saturate8(a[191:176])
-tmp_dst[167:160] := Saturate8(a[207:192])
-tmp_dst[175:168] := Saturate8(a[223:208])
-tmp_dst[183:176] := Saturate8(a[239:224])
-tmp_dst[191:184] := Saturate8(a[255:240])
-tmp_dst[199:192] := Saturate8(b[143:128])
-tmp_dst[207:200] := Saturate8(b[159:144])
-tmp_dst[215:208] := Saturate8(b[175:160])
-tmp_dst[223:216] := Saturate8(b[191:176])
-tmp_dst[231:224] := Saturate8(b[207:192])
-tmp_dst[239:232] := Saturate8(b[223:208])
-tmp_dst[247:240] := Saturate8(b[239:224])
-tmp_dst[255:248] := Saturate8(b[255:240])
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPACKSSWB" xed="VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_packs_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := Saturate8(a[15:0])
-tmp_dst[15:8] := Saturate8(a[31:16])
-tmp_dst[23:16] := Saturate8(a[47:32])
-tmp_dst[31:24] := Saturate8(a[63:48])
-tmp_dst[39:32] := Saturate8(a[79:64])
-tmp_dst[47:40] := Saturate8(a[95:80])
-tmp_dst[55:48] := Saturate8(a[111:96])
-tmp_dst[63:56] := Saturate8(a[127:112])
-tmp_dst[71:64] := Saturate8(b[15:0])
-tmp_dst[79:72] := Saturate8(b[31:16])
-tmp_dst[87:80] := Saturate8(b[47:32])
-tmp_dst[95:88] := Saturate8(b[63:48])
-tmp_dst[103:96] := Saturate8(b[79:64])
-tmp_dst[111:104] := Saturate8(b[95:80])
-tmp_dst[119:112] := Saturate8(b[111:96])
-tmp_dst[127:120] := Saturate8(b[127:112])
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPACKSSWB" xed="VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_packs_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := Saturate8(a[15:0])
-tmp_dst[15:8] := Saturate8(a[31:16])
-tmp_dst[23:16] := Saturate8(a[47:32])
-tmp_dst[31:24] := Saturate8(a[63:48])
-tmp_dst[39:32] := Saturate8(a[79:64])
-tmp_dst[47:40] := Saturate8(a[95:80])
-tmp_dst[55:48] := Saturate8(a[111:96])
-tmp_dst[63:56] := Saturate8(a[127:112])
-tmp_dst[71:64] := Saturate8(b[15:0])
-tmp_dst[79:72] := Saturate8(b[31:16])
-tmp_dst[87:80] := Saturate8(b[47:32])
-tmp_dst[95:88] := Saturate8(b[63:48])
-tmp_dst[103:96] := Saturate8(b[79:64])
-tmp_dst[111:104] := Saturate8(b[95:80])
-tmp_dst[119:112] := Saturate8(b[111:96])
-tmp_dst[127:120] := Saturate8(b[127:112])
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPACKSSWB" xed="VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_packus_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := SaturateU16(a[31:0])
-tmp_dst[31:16] := SaturateU16(a[63:32])
-tmp_dst[47:32] := SaturateU16(a[95:64])
-tmp_dst[63:48] := SaturateU16(a[127:96])
-tmp_dst[79:64] := SaturateU16(b[31:0])
-tmp_dst[95:80] := SaturateU16(b[63:32])
-tmp_dst[111:96] := SaturateU16(b[95:64])
-tmp_dst[127:112] := SaturateU16(b[127:96])
-tmp_dst[143:128] := SaturateU16(a[159:128])
-tmp_dst[159:144] := SaturateU16(a[191:160])
-tmp_dst[175:160] := SaturateU16(a[223:192])
-tmp_dst[191:176] := SaturateU16(a[255:224])
-tmp_dst[207:192] := SaturateU16(b[159:128])
-tmp_dst[223:208] := SaturateU16(b[191:160])
-tmp_dst[239:224] := SaturateU16(b[223:192])
-tmp_dst[255:240] := SaturateU16(b[255:224])
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPACKUSDW" xed="VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_packus_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := SaturateU16(a[31:0])
-tmp_dst[31:16] := SaturateU16(a[63:32])
-tmp_dst[47:32] := SaturateU16(a[95:64])
-tmp_dst[63:48] := SaturateU16(a[127:96])
-tmp_dst[79:64] := SaturateU16(b[31:0])
-tmp_dst[95:80] := SaturateU16(b[63:32])
-tmp_dst[111:96] := SaturateU16(b[95:64])
-tmp_dst[127:112] := SaturateU16(b[127:96])
-tmp_dst[143:128] := SaturateU16(a[159:128])
-tmp_dst[159:144] := SaturateU16(a[191:160])
-tmp_dst[175:160] := SaturateU16(a[223:192])
-tmp_dst[191:176] := SaturateU16(a[255:224])
-tmp_dst[207:192] := SaturateU16(b[159:128])
-tmp_dst[223:208] := SaturateU16(b[191:160])
-tmp_dst[239:224] := SaturateU16(b[223:192])
-tmp_dst[255:240] := SaturateU16(b[255:224])
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPACKUSDW" xed="VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_packus_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := SaturateU16(a[31:0])
-tmp_dst[31:16] := SaturateU16(a[63:32])
-tmp_dst[47:32] := SaturateU16(a[95:64])
-tmp_dst[63:48] := SaturateU16(a[127:96])
-tmp_dst[79:64] := SaturateU16(b[31:0])
-tmp_dst[95:80] := SaturateU16(b[63:32])
-tmp_dst[111:96] := SaturateU16(b[95:64])
-tmp_dst[127:112] := SaturateU16(b[127:96])
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPACKUSDW" xed="VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_packus_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := SaturateU16(a[31:0])
-tmp_dst[31:16] := SaturateU16(a[63:32])
-tmp_dst[47:32] := SaturateU16(a[95:64])
-tmp_dst[63:48] := SaturateU16(a[127:96])
-tmp_dst[79:64] := SaturateU16(b[31:0])
-tmp_dst[95:80] := SaturateU16(b[63:32])
-tmp_dst[111:96] := SaturateU16(b[95:64])
-tmp_dst[127:112] := SaturateU16(b[127:96])
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPACKUSDW" xed="VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_packus_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := SaturateU8(a[15:0])
-tmp_dst[15:8] := SaturateU8(a[31:16])
-tmp_dst[23:16] := SaturateU8(a[47:32])
-tmp_dst[31:24] := SaturateU8(a[63:48])
-tmp_dst[39:32] := SaturateU8(a[79:64])
-tmp_dst[47:40] := SaturateU8(a[95:80])
-tmp_dst[55:48] := SaturateU8(a[111:96])
-tmp_dst[63:56] := SaturateU8(a[127:112])
-tmp_dst[71:64] := SaturateU8(b[15:0])
-tmp_dst[79:72] := SaturateU8(b[31:16])
-tmp_dst[87:80] := SaturateU8(b[47:32])
-tmp_dst[95:88] := SaturateU8(b[63:48])
-tmp_dst[103:96] := SaturateU8(b[79:64])
-tmp_dst[111:104] := SaturateU8(b[95:80])
-tmp_dst[119:112] := SaturateU8(b[111:96])
-tmp_dst[127:120] := SaturateU8(b[127:112])
-tmp_dst[135:128] := SaturateU8(a[143:128])
-tmp_dst[143:136] := SaturateU8(a[159:144])
-tmp_dst[151:144] := SaturateU8(a[175:160])
-tmp_dst[159:152] := SaturateU8(a[191:176])
-tmp_dst[167:160] := SaturateU8(a[207:192])
-tmp_dst[175:168] := SaturateU8(a[223:208])
-tmp_dst[183:176] := SaturateU8(a[239:224])
-tmp_dst[191:184] := SaturateU8(a[255:240])
-tmp_dst[199:192] := SaturateU8(b[143:128])
-tmp_dst[207:200] := SaturateU8(b[159:144])
-tmp_dst[215:208] := SaturateU8(b[175:160])
-tmp_dst[223:216] := SaturateU8(b[191:176])
-tmp_dst[231:224] := SaturateU8(b[207:192])
-tmp_dst[239:232] := SaturateU8(b[223:208])
-tmp_dst[247:240] := SaturateU8(b[239:224])
-tmp_dst[255:248] := SaturateU8(b[255:240])
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPACKUSWB" xed="VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_packus_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := SaturateU8(a[15:0])
-tmp_dst[15:8] := SaturateU8(a[31:16])
-tmp_dst[23:16] := SaturateU8(a[47:32])
-tmp_dst[31:24] := SaturateU8(a[63:48])
-tmp_dst[39:32] := SaturateU8(a[79:64])
-tmp_dst[47:40] := SaturateU8(a[95:80])
-tmp_dst[55:48] := SaturateU8(a[111:96])
-tmp_dst[63:56] := SaturateU8(a[127:112])
-tmp_dst[71:64] := SaturateU8(b[15:0])
-tmp_dst[79:72] := SaturateU8(b[31:16])
-tmp_dst[87:80] := SaturateU8(b[47:32])
-tmp_dst[95:88] := SaturateU8(b[63:48])
-tmp_dst[103:96] := SaturateU8(b[79:64])
-tmp_dst[111:104] := SaturateU8(b[95:80])
-tmp_dst[119:112] := SaturateU8(b[111:96])
-tmp_dst[127:120] := SaturateU8(b[127:112])
-tmp_dst[135:128] := SaturateU8(a[143:128])
-tmp_dst[143:136] := SaturateU8(a[159:144])
-tmp_dst[151:144] := SaturateU8(a[175:160])
-tmp_dst[159:152] := SaturateU8(a[191:176])
-tmp_dst[167:160] := SaturateU8(a[207:192])
-tmp_dst[175:168] := SaturateU8(a[223:208])
-tmp_dst[183:176] := SaturateU8(a[239:224])
-tmp_dst[191:184] := SaturateU8(a[255:240])
-tmp_dst[199:192] := SaturateU8(b[143:128])
-tmp_dst[207:200] := SaturateU8(b[159:144])
-tmp_dst[215:208] := SaturateU8(b[175:160])
-tmp_dst[223:216] := SaturateU8(b[191:176])
-tmp_dst[231:224] := SaturateU8(b[207:192])
-tmp_dst[239:232] := SaturateU8(b[223:208])
-tmp_dst[247:240] := SaturateU8(b[239:224])
-tmp_dst[255:248] := SaturateU8(b[255:240])
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPACKUSWB" xed="VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_packus_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := SaturateU8(a[15:0])
-tmp_dst[15:8] := SaturateU8(a[31:16])
-tmp_dst[23:16] := SaturateU8(a[47:32])
-tmp_dst[31:24] := SaturateU8(a[63:48])
-tmp_dst[39:32] := SaturateU8(a[79:64])
-tmp_dst[47:40] := SaturateU8(a[95:80])
-tmp_dst[55:48] := SaturateU8(a[111:96])
-tmp_dst[63:56] := SaturateU8(a[127:112])
-tmp_dst[71:64] := SaturateU8(b[15:0])
-tmp_dst[79:72] := SaturateU8(b[31:16])
-tmp_dst[87:80] := SaturateU8(b[47:32])
-tmp_dst[95:88] := SaturateU8(b[63:48])
-tmp_dst[103:96] := SaturateU8(b[79:64])
-tmp_dst[111:104] := SaturateU8(b[95:80])
-tmp_dst[119:112] := SaturateU8(b[111:96])
-tmp_dst[127:120] := SaturateU8(b[127:112])
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPACKUSWB" xed="VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_packus_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := SaturateU8(a[15:0])
-tmp_dst[15:8] := SaturateU8(a[31:16])
-tmp_dst[23:16] := SaturateU8(a[47:32])
-tmp_dst[31:24] := SaturateU8(a[63:48])
-tmp_dst[39:32] := SaturateU8(a[79:64])
-tmp_dst[47:40] := SaturateU8(a[95:80])
-tmp_dst[55:48] := SaturateU8(a[111:96])
-tmp_dst[63:56] := SaturateU8(a[127:112])
-tmp_dst[71:64] := SaturateU8(b[15:0])
-tmp_dst[79:72] := SaturateU8(b[31:16])
-tmp_dst[87:80] := SaturateU8(b[47:32])
-tmp_dst[95:88] := SaturateU8(b[63:48])
-tmp_dst[103:96] := SaturateU8(b[79:64])
-tmp_dst[111:104] := SaturateU8(b[95:80])
-tmp_dst[119:112] := SaturateU8(b[111:96])
-tmp_dst[127:120] := SaturateU8(b[127:112])
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPACKUSWB" xed="VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := Saturate8(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVSWB" xed="VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := Saturate8(a[i+15:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVSWB" xed="VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSWB" xed="VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi8_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := SignExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi8_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := SignExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi8_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := SignExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi8_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := SignExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSXBW" xed="VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := SaturateU8(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVUSWB" xed="VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := SaturateU8(a[i+15:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVUSWB" xed="VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVUSWB" xed="VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := Truncate8(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVWB" xed="VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := Truncate8(a[i+15:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVWB" xed="VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVWB" xed="VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu8_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := ZeroExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu8_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := ZeroExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu8_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := ZeroExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu8_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := ZeroExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVZXBW" xed="VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_set1_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_set1_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_set1_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_set1_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_set1_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_set1_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast 16-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_set1_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_set1_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpge_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmple_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmplt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpneq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpeq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpge_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpgt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmple_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmplt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpneq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpeq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpge_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpgt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmple_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmplt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpneq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpge_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmple_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmplt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpneq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpeq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpge_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpgt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmple_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmplt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpneq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpeq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpge_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpgt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmple_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmplt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpneq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpge_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmple_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmplt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpneq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpeq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpge_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpgt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmple_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmplt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpneq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpeq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpge_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpgt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmple_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmplt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpneq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpge_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmple_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmplt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpneq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpeq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpge_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpgt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmple_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmplt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpneq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpeq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpge_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpgt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmple_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmplt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpneq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_test_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_test_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_test_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_test_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_test_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_test_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_test_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_test_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_testn_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k1[j]
-		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testn_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_testn_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k1[j]
-		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_testn_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_testn_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k1[j]
-		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testn_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_testn_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k1[j]
-		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_testn_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSLLVW" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSLLVW" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSLLVW" xed="VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSLLVW" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSLLVW" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSLLVW" xed="VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sll_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSLLW" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_slli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSLLW" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sll_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSLLW" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_slli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSLLW" xed="VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sll_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSLLW" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_slli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSLLW" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sll_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSLLW" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_slli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSLLW" xed="VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSRAVW" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSRAVW" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSRAVW" xed="VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRAVW" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRAVW" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSRAVW" xed="VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sra_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSRAW" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srai_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSRAW" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sra_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSRAW" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srai_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSRAW" xed="VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sra_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRAW" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srai_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSRAW" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sra_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRAW" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srai_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSRAW" xed="VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSRLVW" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSRLVW" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSRLVW" xed="VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRLVW" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRLVW" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSRLVW" xed="VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srl_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSRLW" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSRLW" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srl_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSRLW" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSRLW" xed="VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srl_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRLW" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSRLW" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srl_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRLW" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSRLW" xed="VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_add_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[15:0] + src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] + src[i+16*len+31:i+16*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_ADD(a, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_add_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[15:0] + src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] + src[i+16*len+15:i+16*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0
-	FI
-ENDFOR
-dst[15:0] := REDUCE_ADD(tmp, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_add_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[15:0] + src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] + src[i+16*len+31:i+16*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_ADD(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_add_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[15:0] + src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] + src[i+16*len+15:i+16*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0
-	FI
-ENDFOR
-dst[15:0] := REDUCE_ADD(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_add_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[7:0] + src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] + src[i+8*len+15:i+8*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_ADD(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_add_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[7:0] + src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] + src[i+8*len+7:i+8*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0
-	FI
-ENDFOR
-dst[7:0] := REDUCE_ADD(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_add_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[7:0] + src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] + src[i+8*len+15:i+8*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_ADD(a, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_add_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[7:0] + src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] + src[i+8*len+7:i+8*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0
-	FI
-ENDFOR
-dst[7:0] := REDUCE_ADD(tmp, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_mul_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[15:0] * src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] * src[i+16*len+31:i+16*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MUL(a, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_mul_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[15:0] * src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] * src[i+16*len+15:i+16*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 1
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MUL(tmp, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_mul_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[15:0] * src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] * src[i+16*len+31:i+16*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MUL(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_mul_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[15:0] * src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] * src[i+16*len+15:i+16*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 1
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MUL(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_mul_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[7:0] * src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] * src[i+8*len+15:i+8*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MUL(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_mul_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[7:0] * src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] * src[i+8*len+7:i+8*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 1
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MUL(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_mul_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[7:0] * src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] * src[i+8*len+15:i+8*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MUL(a, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_mul_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[7:0] * src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] * src[i+8*len+7:i+8*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 1
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MUL(tmp, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_or_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[15:0] OR src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] OR src[i+16*len+31:i+16*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_OR(a, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_or_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[15:0] OR src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] OR src[i+16*len+15:i+16*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0
-	FI
-ENDFOR
-dst[15:0] := REDUCE_OR(tmp, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_or_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[15:0] OR src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] OR src[i+16*len+31:i+16*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_OR(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_or_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[15:0] OR src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] OR src[i+16*len+15:i+16*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0
-	FI
-ENDFOR
-dst[15:0] := REDUCE_OR(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_or_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[7:0] OR src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] OR src[i+8*len+15:i+8*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_OR(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_or_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[7:0] OR src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] OR src[i+8*len+7:i+8*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0
-	FI
-ENDFOR
-dst[7:0] := REDUCE_OR(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_or_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[7:0] OR src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] OR src[i+8*len+15:i+8*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_OR(a, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_or_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[7:0] OR src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] OR src[i+8*len+7:i+8*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0
-	FI
-ENDFOR
-dst[7:0] := REDUCE_OR(tmp, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_and_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[15:0] AND src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] AND src[i+16*len+31:i+16*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_AND(a, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_and_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[15:0] AND src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] AND src[i+16*len+15:i+16*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0xFFFF
-	FI
-ENDFOR
-dst[15:0] := REDUCE_AND(tmp, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_and_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[15:0] AND src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] AND src[i+16*len+31:i+16*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_AND(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_and_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed 16-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[15:0] AND src[31:16]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := src[i+15:i] AND src[i+16*len+15:i+16*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0xFFFF
-	FI
-ENDFOR
-dst[15:0] := REDUCE_AND(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_and_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[7:0] AND src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] AND src[i+8*len+15:i+8*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_AND(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_and_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[7:0] AND src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] AND src[i+8*len+7:i+8*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0xFF
-	FI
-ENDFOR
-dst[7:0] := REDUCE_AND(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_and_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[7:0] AND src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] AND src[i+8*len+15:i+8*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_AND(a, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_and_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed 8-bit integers in "a" by multiplication using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[7:0] AND src[15:8]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := src[i+7:i] AND src[i+8*len+7:i+8*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0xFF
-	FI
-ENDFOR
-dst[7:0] := REDUCE_AND(tmp, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_max_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed signed 16-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MAX(a, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_max_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed signed 16-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := Int16(-0x8000)
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MAX(tmp, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_max_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed signed 16-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MAX(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_max_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed signed 16-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := Int16(-0x8000)
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MAX(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_max_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed signed 8-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MAX(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_max_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed signed 8-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := Int8(-0x80)
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MAX(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_max_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed signed 8-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MAX(a, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_max_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed signed 8-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := Int8(-0x80)
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MAX(tmp, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_max_epu16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Reduce the packed unsigned 16-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MAX(a, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_max_epu16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Reduce the packed unsigned 16-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MAX(tmp, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_max_epu16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Reduce the packed unsigned 16-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MAX(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_max_epu16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Reduce the packed unsigned 16-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &gt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &gt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MAX(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_max_epu8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Reduce the packed unsigned 8-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MAX(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_max_epu8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Reduce the packed unsigned 8-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MAX(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_max_epu8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Reduce the packed unsigned 8-bit integers in "a" by maximum. Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MAX(a, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_max_epu8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Reduce the packed unsigned 8-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &gt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &gt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MAX(tmp, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_min_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed signed 16-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MIN(a, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_min_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Reduce the packed signed 16-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := Int16(0x7FFF)
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MIN(tmp, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_min_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed signed 16-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MIN(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_min_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="SI16" type="short" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Reduce the packed signed 16-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := Int16(0x7FFF)
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MIN(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_min_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed signed 8-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MIN(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_min_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Reduce the packed signed 8-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := Int8(0x7F)
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MIN(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_min_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed signed 8-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MIN(a, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_min_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="SI8" type="char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Reduce the packed signed 8-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := Int8(0x7F)
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MIN(tmp, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_min_epu16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Reduce the packed unsigned 16-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MIN(a, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_min_epu16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Reduce the packed unsigned 16-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0xFFFF
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MIN(tmp, 8)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_min_epu16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Reduce the packed unsigned 16-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[16*len-1:0], len)
-}
-dst[15:0] := REDUCE_MIN(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_min_epu16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Reduce the packed unsigned 16-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[15:0] &lt; src[31:16] ? src[15:0] : src[31:16])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*16
-		src[i+15:i] := (src[i+15:i] &lt; src[i+16*len+15:i+16*len] ? src[i+15:i] : src[i+16*len+15:i+16*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[16*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[i+15:i] := a[i+15:i]
-	ELSE
-		tmp[i+15:i] := 0xFFFF
-	FI
-ENDFOR
-dst[15:0] := REDUCE_MIN(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_min_epu8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Reduce the packed unsigned 8-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MIN(a, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_min_epu8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Reduce the packed unsigned 8-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0xFF
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MIN(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_min_epu8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Reduce the packed unsigned 8-bit integers in "a" by minimum. Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[8*len-1:0], len)
-}
-dst[7:0] := REDUCE_MIN(a, 32)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_min_epu8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Reduce the packed unsigned 8-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[7:0] &lt; src[15:8] ? src[7:0] : src[15:8])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*8
-		src[i+7:i] := (src[i+7:i] &lt; src[i+8*len+7:i+8*len] ? src[i+7:i] : src[i+8*len+7:i+8*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[8*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		tmp[i+7:i] := a[i+7:i]
-	ELSE
-		tmp[i+7:i] := 0xFF
-	FI
-ENDFOR
-dst[7:0] := REDUCE_MIN(tmp, 16)
-	</operation>
-	<CPUID>AVX512BW</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	
-<intrinsic name="_mm512_kunpackd" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Unpack and interleave 32 bits from masks "a" and "b", and store the 64-bit result in "dst".</description>
-	<operation>
-dst[31:0] := b[31:0]
-dst[63:32] := a[31:0]
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="k, k, k" name="KUNPCKDQ" xed="KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kunpackw" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Unpack and interleave 16 bits from masks "a" and "b", and store the 32-bit result in "dst".</description>
-	<operation>
-dst[15:0] := b[15:0]
-dst[31:16] := a[15:0]
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="k, k, k" name="KUNPCKWD" xed="KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-FOR i := 0 to 3
-	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
-	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
-	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
-	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
-ENDFOR
-FOR j := 0 to 7
-	i := j*64
-	dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	               ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                  ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                  ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                  ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-FOR i := 0 to 3
-	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
-	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
-	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
-	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
-ENDFOR
-FOR j := 0 to 7
-	i := j*64
-	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_dbsad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.</description>
-	<operation>
-FOR i := 0 to 3
-	tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ]
-	tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ]
-	tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ]
-	tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ]
-ENDFOR
-FOR j := 0 to 7
-	i := j*64
-	tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\
-	                   ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24])
-	
-	tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\
-	                      ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32])
-	
-	tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40])
-	
-	tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\
-	                      ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48])
-ENDFOR
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VDBPSADBW" xed="VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_alignr_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*128
-	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
-	dst[i+127:i] := tmp[127:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPALIGNR" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_alignr_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*128
-	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
-	tmp_dst[i+127:i] := tmp[127:0]
-ENDFOR
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPALIGNR" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_alignr_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*128
-	tmp[255:0] := ((a[i+127:i] &lt;&lt; 128)[255:0] OR b[i+127:i]) &gt;&gt; (imm8*8)
-	tmp_dst[i+127:i] := tmp[127:0]
-ENDFOR
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPALIGNR" xed="VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_blend_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := b[i+7:i]
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMB" xed="VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_blend_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := b[i+15:i]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMW" xed="VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcastb_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := a[7:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcastb_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcastb_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcastw_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := a[15:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcastw_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcastw_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask2_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+4:i]
-		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := idx[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2W" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+4:i]
-		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2W" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		off := 16*idx[i+4:i]
-		dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2W" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2W" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex2var_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	off := 16*idx[i+4:i]
-	dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMI2W" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VPERMT2W" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	id := idx[i+4:i]*16
-	IF k[j]
-		dst[i+15:i] := a[id+15:id]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMW" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	id := idx[i+4:i]*16
-	IF k[j]
-		dst[i+15:i] := a[id+15:id]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMW" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutexvar_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	id := idx[i+4:i]*16
-	dst[i+15:i] := a[id+15:id]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMW" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movepi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF a[i+7]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm" name="VPMOVB2M" xed="VPMOVB2M_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movm_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<description>Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := 0xFF
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm" name="VPMOVM2B" xed="VPMOVM2B_ZMMu8_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movm_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<description>Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := 0xFFFF
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm" name="VPMOVM2W" xed="VPMOVM2W_ZMMu16_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movepi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF a[i+15]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm" name="VPMOVW2M" xed="VPMOVW2M_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sad_epu8" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce eight unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
-ENDFOR
-FOR j := 0 to 7
-	i := j*64
-	dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
-	               tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
-	dst[i+63:i+16] := 0
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSADBW" xed="VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shuffle_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" within 128-bit lanes using the control in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		IF b[i+7] == 1
-			dst[i+7:i] := 0
-		ELSE
-			index[5:0] := b[i+3:i] + (j &amp; 0x30)
-			dst[i+7:i] := a[index*8+7:index*8]
-		FI
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSHUFB" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shuffle_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		IF b[i+7] == 1
-			dst[i+7:i] := 0
-		ELSE
-			index[5:0] := b[i+3:i] + (j &amp; 0x30)
-			dst[i+7:i] := a[index*8+7:index*8]
-		FI
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSHUFB" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shuffle_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF b[i+7] == 1
-		dst[i+7:i] := 0
-	ELSE
-		index[5:0] := b[i+3:i] + (j &amp; 0x30)
-		dst[i+7:i] := a[index*8+7:index*8]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSHUFB" xed="VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shufflehi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := a[63:0]
-tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-tmp_dst[191:128] := a[191:128]
-tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
-tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
-tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
-tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
-tmp_dst[319:256] := a[319:256]
-tmp_dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
-tmp_dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
-tmp_dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
-tmp_dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
-tmp_dst[447:384] := a[447:384]
-tmp_dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
-tmp_dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
-tmp_dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
-tmp_dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shufflehi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := a[63:0]
-tmp_dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-tmp_dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-tmp_dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-tmp_dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-tmp_dst[191:128] := a[191:128]
-tmp_dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
-tmp_dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
-tmp_dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
-tmp_dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
-tmp_dst[319:256] := a[319:256]
-tmp_dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
-tmp_dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
-tmp_dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
-tmp_dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
-tmp_dst[447:384] := a[447:384]
-tmp_dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
-tmp_dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
-tmp_dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
-tmp_dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shufflehi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-dst[191:128] := a[191:128]
-dst[207:192] := (a &gt;&gt; (imm8[1:0] * 16))[207:192]
-dst[223:208] := (a &gt;&gt; (imm8[3:2] * 16))[207:192]
-dst[239:224] := (a &gt;&gt; (imm8[5:4] * 16))[207:192]
-dst[255:240] := (a &gt;&gt; (imm8[7:6] * 16))[207:192]
-dst[319:256] := a[319:256]
-dst[335:320] := (a &gt;&gt; (imm8[1:0] * 16))[335:320]
-dst[351:336] := (a &gt;&gt; (imm8[3:2] * 16))[335:320]
-dst[367:352] := (a &gt;&gt; (imm8[5:4] * 16))[335:320]
-dst[383:368] := (a &gt;&gt; (imm8[7:6] * 16))[335:320]
-dst[447:384] := a[447:384]
-dst[463:448] := (a &gt;&gt; (imm8[1:0] * 16))[463:448]
-dst[479:464] := (a &gt;&gt; (imm8[3:2] * 16))[463:448]
-dst[495:480] := (a &gt;&gt; (imm8[5:4] * 16))[463:448]
-dst[511:496] := (a &gt;&gt; (imm8[7:6] * 16))[463:448]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSHUFHW" xed="VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shufflelo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-tmp_dst[127:64] := a[127:64]
-tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
-tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
-tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
-tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
-tmp_dst[255:192] := a[255:192]
-tmp_dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
-tmp_dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
-tmp_dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
-tmp_dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
-tmp_dst[383:320] := a[383:320]
-tmp_dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
-tmp_dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
-tmp_dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
-tmp_dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
-tmp_dst[511:448] := a[511:448]
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shufflelo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-tmp_dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-tmp_dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-tmp_dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-tmp_dst[127:64] := a[127:64]
-tmp_dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
-tmp_dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
-tmp_dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
-tmp_dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
-tmp_dst[255:192] := a[255:192]
-tmp_dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
-tmp_dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
-tmp_dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
-tmp_dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
-tmp_dst[383:320] := a[383:320]
-tmp_dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
-tmp_dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
-tmp_dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
-tmp_dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
-tmp_dst[511:448] := a[511:448]
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shufflelo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst".</description>
-	<operation>
-dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-dst[127:64] := a[127:64]
-dst[143:128] := (a &gt;&gt; (imm8[1:0] * 16))[143:128]
-dst[159:144] := (a &gt;&gt; (imm8[3:2] * 16))[143:128]
-dst[175:160] := (a &gt;&gt; (imm8[5:4] * 16))[143:128]
-dst[191:176] := (a &gt;&gt; (imm8[7:6] * 16))[143:128]
-dst[255:192] := a[255:192]
-dst[271:256] := (a &gt;&gt; (imm8[1:0] * 16))[271:256]
-dst[287:272] := (a &gt;&gt; (imm8[3:2] * 16))[271:256]
-dst[303:288] := (a &gt;&gt; (imm8[5:4] * 16))[271:256]
-dst[319:304] := (a &gt;&gt; (imm8[7:6] * 16))[271:256]
-dst[383:320] := a[383:320]
-dst[399:384] := (a &gt;&gt; (imm8[1:0] * 16))[399:384]
-dst[415:400] := (a &gt;&gt; (imm8[3:2] * 16))[399:384]
-dst[431:416] := (a &gt;&gt; (imm8[5:4] * 16))[399:384]
-dst[447:432] := (a &gt;&gt; (imm8[7:6] * 16))[399:384]
-dst[511:448] := a[511:448]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSHUFLW" xed="VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpackhi_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpackhi_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpackhi_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPUNPCKHBW" xed="VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpackhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpackhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpackhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPUNPCKHWD" xed="VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpacklo_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpacklo_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpacklo_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPUNPCKLBW" xed="VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpacklo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpacklo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpacklo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPUNPCKLWD" xed="VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_loadu_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 32 packed 16-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_loadu_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 64 packed 8-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_load_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" memwidth="32" type="__mmask32*" varname="mem_addr" />
-	<description>Load 32-bit mask from memory into "k".</description>
-	<operation>
-k[31:0] := MEM[mem_addr+31:mem_addr]
-	</operation>
-	<instruction form="k, m32" name="KMOVD" xed="KMOVD_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_load_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" memwidth="64" type="__mmask64*" varname="mem_addr" />
-	<description>Load 64-bit mask from memory into "k".</description>
-	<operation>
-k[63:0] := MEM[mem_addr+63:mem_addr]
-	</operation>
-	<instruction form="k, m64" name="KMOVQ" xed="KMOVQ_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mov_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mov_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVDQU16" xed="VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mov_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mov_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVDQU8" xed="VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_storeu_epi16" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI16" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Store packed 16-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_storeu_epi8" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI8" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Store packed 8-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_storeu_epi16" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI16" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Store 512-bits (composed of 32 packed 16-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVDQU16" xed="VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_storeu_epi8" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI8" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Store 512-bits (composed of 64 packed 8-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVDQU8" xed="VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_store_mask32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="MASK" memwidth="32" type="__mmask32*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<description>Store 32-bit mask from "a" into memory.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[31:0]
-	</operation>
-	<instruction form="m32, k" name="KMOVD" xed="KMOVD_MEMu32_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_store_mask64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="MASK" memwidth="64" type="__mmask64*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<description>Store 64-bit mask from "a" into memory.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-	</operation>
-	<instruction form="m64, k" name="KMOVQ" xed="KMOVQ_MEMu64_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_abs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := ABS(a[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPABSB" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_abs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := ABS(a[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPABSB" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_abs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := ABS(a[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPABSB" xed="VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_abs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ABS(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPABSW" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_abs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ABS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPABSW" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_abs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ABS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPABSW" xed="VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := a[i+7:i] + b[i+7:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPADDB" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] + b[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPADDB" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] + b[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPADDB" xed="VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_adds_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPADDSB" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_adds_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPADDSB" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_adds_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPADDSB" xed="VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_adds_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPADDSW" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_adds_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPADDSW" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_adds_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPADDSW" xed="VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_adds_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPADDUSB" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_adds_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPADDUSB" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_adds_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPADDUSB" xed="VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_adds_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPADDUSW" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_adds_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPADDUSW" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_adds_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPADDUSW" xed="VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := a[i+15:i] + b[i+15:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPADDW" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] + b[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPADDW" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] + b[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPADDW" xed="VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_avg_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPAVGB" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_avg_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPAVGB" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_avg_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPAVGB" xed="VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_avg_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPAVGW" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_avg_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPAVGW" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_avg_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPAVGW" xed="VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maddubs_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMADDUBSW" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_maddubs_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMADDUBSW" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_maddubs_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMADDUBSW" xed="VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_madd_epi16" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMADDWD" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_madd_epi16" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMADDWD" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_madd_epi16" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMADDWD" xed="VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMAXSB" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMAXSB" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMAXSB" xed="VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMAXSW" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMAXSW" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMAXSW" xed="VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMAXUB" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMAXUB" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMAXUB" xed="VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMAXUW" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMAXUW" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMAXUW" xed="VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMINSB" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMINSB" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMINSB" xed="VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMINSW" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMINSW" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMINSW" xed="VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMINUB" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMINUB" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMINUB" xed="VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMINUW" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMINUW" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMINUW" xed="VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mulhrs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-		dst[i+15:i] := tmp[16:1]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULHRSW" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mulhrs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-		dst[i+15:i] := tmp[16:1]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULHRSW" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mulhrs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-	dst[i+15:i] := tmp[16:1]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULHRSW" xed="VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mulhi_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := a[i+15:i] * b[i+15:i]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULHUW" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mulhi_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := a[i+15:i] * b[i+15:i]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULHUW" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mulhi_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	tmp[31:0] := a[i+15:i] * b[i+15:i]
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULHUW" xed="VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mulhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULHW" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mulhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULHW" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mulhi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULHW" xed="VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mullo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULLW" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mullo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-		dst[i+15:i] := tmp[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULLW" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mullo_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-	dst[i+15:i] := tmp[15:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULLW" xed="VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] - b[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSUBB" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[i+7:i] - b[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSUBB" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := a[i+7:i] - b[i+7:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSUBB" xed="VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_subs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSUBSB" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_subs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSUBSB" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_subs_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSUBSB" xed="VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_subs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSUBSW" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_subs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSUBSW" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_subs_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSUBSW" xed="VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_subs_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSUBUSB" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_subs_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSUBUSB" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_subs_epu8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSUBUSB" xed="VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_subs_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSUBUSW" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_subs_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSUBUSW" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_subs_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSUBUSW" xed="VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] - b[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSUBW" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[i+15:i] - b[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSUBW" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := a[i+15:i] - b[i+15:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSUBW" xed="VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_packs_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := Saturate16(a[31:0])
-tmp_dst[31:16] := Saturate16(a[63:32])
-tmp_dst[47:32] := Saturate16(a[95:64])
-tmp_dst[63:48] := Saturate16(a[127:96])
-tmp_dst[79:64] := Saturate16(b[31:0])
-tmp_dst[95:80] := Saturate16(b[63:32])
-tmp_dst[111:96] := Saturate16(b[95:64])
-tmp_dst[127:112] := Saturate16(b[127:96])
-tmp_dst[143:128] := Saturate16(a[159:128])
-tmp_dst[159:144] := Saturate16(a[191:160])
-tmp_dst[175:160] := Saturate16(a[223:192])
-tmp_dst[191:176] := Saturate16(a[255:224])
-tmp_dst[207:192] := Saturate16(b[159:128])
-tmp_dst[223:208] := Saturate16(b[191:160])
-tmp_dst[239:224] := Saturate16(b[223:192])
-tmp_dst[255:240] := Saturate16(b[255:224])
-tmp_dst[271:256] := Saturate16(a[287:256])
-tmp_dst[287:272] := Saturate16(a[319:288])
-tmp_dst[303:288] := Saturate16(a[351:320])
-tmp_dst[319:304] := Saturate16(a[383:352])
-tmp_dst[335:320] := Saturate16(b[287:256])
-tmp_dst[351:336] := Saturate16(b[319:288])
-tmp_dst[367:352] := Saturate16(b[351:320])
-tmp_dst[383:368] := Saturate16(b[383:352])
-tmp_dst[399:384] := Saturate16(a[415:384])
-tmp_dst[415:400] := Saturate16(a[447:416])
-tmp_dst[431:416] := Saturate16(a[479:448])
-tmp_dst[447:432] := Saturate16(a[511:480])
-tmp_dst[463:448] := Saturate16(b[415:384])
-tmp_dst[479:464] := Saturate16(b[447:416])
-tmp_dst[495:480] := Saturate16(b[479:448])
-tmp_dst[511:496] := Saturate16(b[511:480])
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPACKSSDW" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_packs_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := Saturate16(a[31:0])
-tmp_dst[31:16] := Saturate16(a[63:32])
-tmp_dst[47:32] := Saturate16(a[95:64])
-tmp_dst[63:48] := Saturate16(a[127:96])
-tmp_dst[79:64] := Saturate16(b[31:0])
-tmp_dst[95:80] := Saturate16(b[63:32])
-tmp_dst[111:96] := Saturate16(b[95:64])
-tmp_dst[127:112] := Saturate16(b[127:96])
-tmp_dst[143:128] := Saturate16(a[159:128])
-tmp_dst[159:144] := Saturate16(a[191:160])
-tmp_dst[175:160] := Saturate16(a[223:192])
-tmp_dst[191:176] := Saturate16(a[255:224])
-tmp_dst[207:192] := Saturate16(b[159:128])
-tmp_dst[223:208] := Saturate16(b[191:160])
-tmp_dst[239:224] := Saturate16(b[223:192])
-tmp_dst[255:240] := Saturate16(b[255:224])
-tmp_dst[271:256] := Saturate16(a[287:256])
-tmp_dst[287:272] := Saturate16(a[319:288])
-tmp_dst[303:288] := Saturate16(a[351:320])
-tmp_dst[319:304] := Saturate16(a[383:352])
-tmp_dst[335:320] := Saturate16(b[287:256])
-tmp_dst[351:336] := Saturate16(b[319:288])
-tmp_dst[367:352] := Saturate16(b[351:320])
-tmp_dst[383:368] := Saturate16(b[383:352])
-tmp_dst[399:384] := Saturate16(a[415:384])
-tmp_dst[415:400] := Saturate16(a[447:416])
-tmp_dst[431:416] := Saturate16(a[479:448])
-tmp_dst[447:432] := Saturate16(a[511:480])
-tmp_dst[463:448] := Saturate16(b[415:384])
-tmp_dst[479:464] := Saturate16(b[447:416])
-tmp_dst[495:480] := Saturate16(b[479:448])
-tmp_dst[511:496] := Saturate16(b[511:480])
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPACKSSDW" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_packs_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[31:0])
-dst[31:16] := Saturate16(a[63:32])
-dst[47:32] := Saturate16(a[95:64])
-dst[63:48] := Saturate16(a[127:96])
-dst[79:64] := Saturate16(b[31:0])
-dst[95:80] := Saturate16(b[63:32])
-dst[111:96] := Saturate16(b[95:64])
-dst[127:112] := Saturate16(b[127:96])
-dst[143:128] := Saturate16(a[159:128])
-dst[159:144] := Saturate16(a[191:160])
-dst[175:160] := Saturate16(a[223:192])
-dst[191:176] := Saturate16(a[255:224])
-dst[207:192] := Saturate16(b[159:128])
-dst[223:208] := Saturate16(b[191:160])
-dst[239:224] := Saturate16(b[223:192])
-dst[255:240] := Saturate16(b[255:224])
-dst[271:256] := Saturate16(a[287:256])
-dst[287:272] := Saturate16(a[319:288])
-dst[303:288] := Saturate16(a[351:320])
-dst[319:304] := Saturate16(a[383:352])
-dst[335:320] := Saturate16(b[287:256])
-dst[351:336] := Saturate16(b[319:288])
-dst[367:352] := Saturate16(b[351:320])
-dst[383:368] := Saturate16(b[383:352])
-dst[399:384] := Saturate16(a[415:384])
-dst[415:400] := Saturate16(a[447:416])
-dst[431:416] := Saturate16(a[479:448])
-dst[447:432] := Saturate16(a[511:480])
-dst[463:448] := Saturate16(b[415:384])
-dst[479:464] := Saturate16(b[447:416])
-dst[495:480] := Saturate16(b[479:448])
-dst[511:496] := Saturate16(b[511:480])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPACKSSDW" xed="VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_packs_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI8" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := Saturate8(a[15:0])
-tmp_dst[15:8] := Saturate8(a[31:16])
-tmp_dst[23:16] := Saturate8(a[47:32])
-tmp_dst[31:24] := Saturate8(a[63:48])
-tmp_dst[39:32] := Saturate8(a[79:64])
-tmp_dst[47:40] := Saturate8(a[95:80])
-tmp_dst[55:48] := Saturate8(a[111:96])
-tmp_dst[63:56] := Saturate8(a[127:112])
-tmp_dst[71:64] := Saturate8(b[15:0])
-tmp_dst[79:72] := Saturate8(b[31:16])
-tmp_dst[87:80] := Saturate8(b[47:32])
-tmp_dst[95:88] := Saturate8(b[63:48])
-tmp_dst[103:96] := Saturate8(b[79:64])
-tmp_dst[111:104] := Saturate8(b[95:80])
-tmp_dst[119:112] := Saturate8(b[111:96])
-tmp_dst[127:120] := Saturate8(b[127:112])
-tmp_dst[135:128] := Saturate8(a[143:128])
-tmp_dst[143:136] := Saturate8(a[159:144])
-tmp_dst[151:144] := Saturate8(a[175:160])
-tmp_dst[159:152] := Saturate8(a[191:176])
-tmp_dst[167:160] := Saturate8(a[207:192])
-tmp_dst[175:168] := Saturate8(a[223:208])
-tmp_dst[183:176] := Saturate8(a[239:224])
-tmp_dst[191:184] := Saturate8(a[255:240])
-tmp_dst[199:192] := Saturate8(b[143:128])
-tmp_dst[207:200] := Saturate8(b[159:144])
-tmp_dst[215:208] := Saturate8(b[175:160])
-tmp_dst[223:216] := Saturate8(b[191:176])
-tmp_dst[231:224] := Saturate8(b[207:192])
-tmp_dst[239:232] := Saturate8(b[223:208])
-tmp_dst[247:240] := Saturate8(b[239:224])
-tmp_dst[255:248] := Saturate8(b[255:240])
-tmp_dst[263:256] := Saturate8(a[271:256])
-tmp_dst[271:264] := Saturate8(a[287:272])
-tmp_dst[279:272] := Saturate8(a[303:288])
-tmp_dst[287:280] := Saturate8(a[319:304])
-tmp_dst[295:288] := Saturate8(a[335:320])
-tmp_dst[303:296] := Saturate8(a[351:336])
-tmp_dst[311:304] := Saturate8(a[367:352])
-tmp_dst[319:312] := Saturate8(a[383:368])
-tmp_dst[327:320] := Saturate8(b[271:256])
-tmp_dst[335:328] := Saturate8(b[287:272])
-tmp_dst[343:336] := Saturate8(b[303:288])
-tmp_dst[351:344] := Saturate8(b[319:304])
-tmp_dst[359:352] := Saturate8(b[335:320])
-tmp_dst[367:360] := Saturate8(b[351:336])
-tmp_dst[375:368] := Saturate8(b[367:352])
-tmp_dst[383:376] := Saturate8(b[383:368])
-tmp_dst[391:384] := Saturate8(a[399:384])
-tmp_dst[399:392] := Saturate8(a[415:400])
-tmp_dst[407:400] := Saturate8(a[431:416])
-tmp_dst[415:408] := Saturate8(a[447:432])
-tmp_dst[423:416] := Saturate8(a[463:448])
-tmp_dst[431:424] := Saturate8(a[479:464])
-tmp_dst[439:432] := Saturate8(a[495:480])
-tmp_dst[447:440] := Saturate8(a[511:496])
-tmp_dst[455:448] := Saturate8(b[399:384])
-tmp_dst[463:456] := Saturate8(b[415:400])
-tmp_dst[471:464] := Saturate8(b[431:416])
-tmp_dst[479:472] := Saturate8(b[447:432])
-tmp_dst[487:480] := Saturate8(b[463:448])
-tmp_dst[495:488] := Saturate8(b[479:464])
-tmp_dst[503:496] := Saturate8(b[495:480])
-tmp_dst[511:504] := Saturate8(b[511:496])
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPACKSSWB" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_packs_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := Saturate8(a[15:0])
-tmp_dst[15:8] := Saturate8(a[31:16])
-tmp_dst[23:16] := Saturate8(a[47:32])
-tmp_dst[31:24] := Saturate8(a[63:48])
-tmp_dst[39:32] := Saturate8(a[79:64])
-tmp_dst[47:40] := Saturate8(a[95:80])
-tmp_dst[55:48] := Saturate8(a[111:96])
-tmp_dst[63:56] := Saturate8(a[127:112])
-tmp_dst[71:64] := Saturate8(b[15:0])
-tmp_dst[79:72] := Saturate8(b[31:16])
-tmp_dst[87:80] := Saturate8(b[47:32])
-tmp_dst[95:88] := Saturate8(b[63:48])
-tmp_dst[103:96] := Saturate8(b[79:64])
-tmp_dst[111:104] := Saturate8(b[95:80])
-tmp_dst[119:112] := Saturate8(b[111:96])
-tmp_dst[127:120] := Saturate8(b[127:112])
-tmp_dst[135:128] := Saturate8(a[143:128])
-tmp_dst[143:136] := Saturate8(a[159:144])
-tmp_dst[151:144] := Saturate8(a[175:160])
-tmp_dst[159:152] := Saturate8(a[191:176])
-tmp_dst[167:160] := Saturate8(a[207:192])
-tmp_dst[175:168] := Saturate8(a[223:208])
-tmp_dst[183:176] := Saturate8(a[239:224])
-tmp_dst[191:184] := Saturate8(a[255:240])
-tmp_dst[199:192] := Saturate8(b[143:128])
-tmp_dst[207:200] := Saturate8(b[159:144])
-tmp_dst[215:208] := Saturate8(b[175:160])
-tmp_dst[223:216] := Saturate8(b[191:176])
-tmp_dst[231:224] := Saturate8(b[207:192])
-tmp_dst[239:232] := Saturate8(b[223:208])
-tmp_dst[247:240] := Saturate8(b[239:224])
-tmp_dst[255:248] := Saturate8(b[255:240])
-tmp_dst[263:256] := Saturate8(a[271:256])
-tmp_dst[271:264] := Saturate8(a[287:272])
-tmp_dst[279:272] := Saturate8(a[303:288])
-tmp_dst[287:280] := Saturate8(a[319:304])
-tmp_dst[295:288] := Saturate8(a[335:320])
-tmp_dst[303:296] := Saturate8(a[351:336])
-tmp_dst[311:304] := Saturate8(a[367:352])
-tmp_dst[319:312] := Saturate8(a[383:368])
-tmp_dst[327:320] := Saturate8(b[271:256])
-tmp_dst[335:328] := Saturate8(b[287:272])
-tmp_dst[343:336] := Saturate8(b[303:288])
-tmp_dst[351:344] := Saturate8(b[319:304])
-tmp_dst[359:352] := Saturate8(b[335:320])
-tmp_dst[367:360] := Saturate8(b[351:336])
-tmp_dst[375:368] := Saturate8(b[367:352])
-tmp_dst[383:376] := Saturate8(b[383:368])
-tmp_dst[391:384] := Saturate8(a[399:384])
-tmp_dst[399:392] := Saturate8(a[415:400])
-tmp_dst[407:400] := Saturate8(a[431:416])
-tmp_dst[415:408] := Saturate8(a[447:432])
-tmp_dst[423:416] := Saturate8(a[463:448])
-tmp_dst[431:424] := Saturate8(a[479:464])
-tmp_dst[439:432] := Saturate8(a[495:480])
-tmp_dst[447:440] := Saturate8(a[511:496])
-tmp_dst[455:448] := Saturate8(b[399:384])
-tmp_dst[463:456] := Saturate8(b[415:400])
-tmp_dst[471:464] := Saturate8(b[431:416])
-tmp_dst[479:472] := Saturate8(b[447:432])
-tmp_dst[487:480] := Saturate8(b[463:448])
-tmp_dst[495:488] := Saturate8(b[479:464])
-tmp_dst[503:496] := Saturate8(b[495:480])
-tmp_dst[511:504] := Saturate8(b[511:496])
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPACKSSWB" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_packs_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="SI8" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := Saturate8(a[15:0])
-dst[15:8] := Saturate8(a[31:16])
-dst[23:16] := Saturate8(a[47:32])
-dst[31:24] := Saturate8(a[63:48])
-dst[39:32] := Saturate8(a[79:64])
-dst[47:40] := Saturate8(a[95:80])
-dst[55:48] := Saturate8(a[111:96])
-dst[63:56] := Saturate8(a[127:112])
-dst[71:64] := Saturate8(b[15:0])
-dst[79:72] := Saturate8(b[31:16])
-dst[87:80] := Saturate8(b[47:32])
-dst[95:88] := Saturate8(b[63:48])
-dst[103:96] := Saturate8(b[79:64])
-dst[111:104] := Saturate8(b[95:80])
-dst[119:112] := Saturate8(b[111:96])
-dst[127:120] := Saturate8(b[127:112])
-dst[135:128] := Saturate8(a[143:128])
-dst[143:136] := Saturate8(a[159:144])
-dst[151:144] := Saturate8(a[175:160])
-dst[159:152] := Saturate8(a[191:176])
-dst[167:160] := Saturate8(a[207:192])
-dst[175:168] := Saturate8(a[223:208])
-dst[183:176] := Saturate8(a[239:224])
-dst[191:184] := Saturate8(a[255:240])
-dst[199:192] := Saturate8(b[143:128])
-dst[207:200] := Saturate8(b[159:144])
-dst[215:208] := Saturate8(b[175:160])
-dst[223:216] := Saturate8(b[191:176])
-dst[231:224] := Saturate8(b[207:192])
-dst[239:232] := Saturate8(b[223:208])
-dst[247:240] := Saturate8(b[239:224])
-dst[255:248] := Saturate8(b[255:240])
-dst[263:256] := Saturate8(a[271:256])
-dst[271:264] := Saturate8(a[287:272])
-dst[279:272] := Saturate8(a[303:288])
-dst[287:280] := Saturate8(a[319:304])
-dst[295:288] := Saturate8(a[335:320])
-dst[303:296] := Saturate8(a[351:336])
-dst[311:304] := Saturate8(a[367:352])
-dst[319:312] := Saturate8(a[383:368])
-dst[327:320] := Saturate8(b[271:256])
-dst[335:328] := Saturate8(b[287:272])
-dst[343:336] := Saturate8(b[303:288])
-dst[351:344] := Saturate8(b[319:304])
-dst[359:352] := Saturate8(b[335:320])
-dst[367:360] := Saturate8(b[351:336])
-dst[375:368] := Saturate8(b[367:352])
-dst[383:376] := Saturate8(b[383:368])
-dst[391:384] := Saturate8(a[399:384])
-dst[399:392] := Saturate8(a[415:400])
-dst[407:400] := Saturate8(a[431:416])
-dst[415:408] := Saturate8(a[447:432])
-dst[423:416] := Saturate8(a[463:448])
-dst[431:424] := Saturate8(a[479:464])
-dst[439:432] := Saturate8(a[495:480])
-dst[447:440] := Saturate8(a[511:496])
-dst[455:448] := Saturate8(b[399:384])
-dst[463:456] := Saturate8(b[415:400])
-dst[471:464] := Saturate8(b[431:416])
-dst[479:472] := Saturate8(b[447:432])
-dst[487:480] := Saturate8(b[463:448])
-dst[495:488] := Saturate8(b[479:464])
-dst[503:496] := Saturate8(b[495:480])
-dst[511:504] := Saturate8(b[511:496])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPACKSSWB" xed="VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_packus_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := SaturateU16(a[31:0])
-tmp_dst[31:16] := SaturateU16(a[63:32])
-tmp_dst[47:32] := SaturateU16(a[95:64])
-tmp_dst[63:48] := SaturateU16(a[127:96])
-tmp_dst[79:64] := SaturateU16(b[31:0])
-tmp_dst[95:80] := SaturateU16(b[63:32])
-tmp_dst[111:96] := SaturateU16(b[95:64])
-tmp_dst[127:112] := SaturateU16(b[127:96])
-tmp_dst[143:128] := SaturateU16(a[159:128])
-tmp_dst[159:144] := SaturateU16(a[191:160])
-tmp_dst[175:160] := SaturateU16(a[223:192])
-tmp_dst[191:176] := SaturateU16(a[255:224])
-tmp_dst[207:192] := SaturateU16(b[159:128])
-tmp_dst[223:208] := SaturateU16(b[191:160])
-tmp_dst[239:224] := SaturateU16(b[223:192])
-tmp_dst[255:240] := SaturateU16(b[255:224])
-tmp_dst[271:256] := SaturateU16(a[287:256])
-tmp_dst[287:272] := SaturateU16(a[319:288])
-tmp_dst[303:288] := SaturateU16(a[351:320])
-tmp_dst[319:304] := SaturateU16(a[383:352])
-tmp_dst[335:320] := SaturateU16(b[287:256])
-tmp_dst[351:336] := SaturateU16(b[319:288])
-tmp_dst[367:352] := SaturateU16(b[351:320])
-tmp_dst[383:368] := SaturateU16(b[383:352])
-tmp_dst[399:384] := SaturateU16(a[415:384])
-tmp_dst[415:400] := SaturateU16(a[447:416])
-tmp_dst[431:416] := SaturateU16(a[479:448])
-tmp_dst[447:432] := SaturateU16(a[511:480])
-tmp_dst[463:448] := SaturateU16(b[415:384])
-tmp_dst[479:464] := SaturateU16(b[447:416])
-tmp_dst[495:480] := SaturateU16(b[479:448])
-tmp_dst[511:496] := SaturateU16(b[511:480])
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPACKUSDW" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_packus_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[15:0] := SaturateU16(a[31:0])
-tmp_dst[31:16] := SaturateU16(a[63:32])
-tmp_dst[47:32] := SaturateU16(a[95:64])
-tmp_dst[63:48] := SaturateU16(a[127:96])
-tmp_dst[79:64] := SaturateU16(b[31:0])
-tmp_dst[95:80] := SaturateU16(b[63:32])
-tmp_dst[111:96] := SaturateU16(b[95:64])
-tmp_dst[127:112] := SaturateU16(b[127:96])
-tmp_dst[143:128] := SaturateU16(a[159:128])
-tmp_dst[159:144] := SaturateU16(a[191:160])
-tmp_dst[175:160] := SaturateU16(a[223:192])
-tmp_dst[191:176] := SaturateU16(a[255:224])
-tmp_dst[207:192] := SaturateU16(b[159:128])
-tmp_dst[223:208] := SaturateU16(b[191:160])
-tmp_dst[239:224] := SaturateU16(b[223:192])
-tmp_dst[255:240] := SaturateU16(b[255:224])
-tmp_dst[271:256] := SaturateU16(a[287:256])
-tmp_dst[287:272] := SaturateU16(a[319:288])
-tmp_dst[303:288] := SaturateU16(a[351:320])
-tmp_dst[319:304] := SaturateU16(a[383:352])
-tmp_dst[335:320] := SaturateU16(b[287:256])
-tmp_dst[351:336] := SaturateU16(b[319:288])
-tmp_dst[367:352] := SaturateU16(b[351:320])
-tmp_dst[383:368] := SaturateU16(b[383:352])
-tmp_dst[399:384] := SaturateU16(a[415:384])
-tmp_dst[415:400] := SaturateU16(a[447:416])
-tmp_dst[431:416] := SaturateU16(a[479:448])
-tmp_dst[447:432] := SaturateU16(a[511:480])
-tmp_dst[463:448] := SaturateU16(b[415:384])
-tmp_dst[479:464] := SaturateU16(b[447:416])
-tmp_dst[495:480] := SaturateU16(b[479:448])
-tmp_dst[511:496] := SaturateU16(b[511:480])
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := tmp_dst[i+15:i]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPACKUSDW" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_packus_epi32" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".</description>
-	<operation>
-dst[15:0] := SaturateU16(a[31:0])
-dst[31:16] := SaturateU16(a[63:32])
-dst[47:32] := SaturateU16(a[95:64])
-dst[63:48] := SaturateU16(a[127:96])
-dst[79:64] := SaturateU16(b[31:0])
-dst[95:80] := SaturateU16(b[63:32])
-dst[111:96] := SaturateU16(b[95:64])
-dst[127:112] := SaturateU16(b[127:96])
-dst[143:128] := SaturateU16(a[159:128])
-dst[159:144] := SaturateU16(a[191:160])
-dst[175:160] := SaturateU16(a[223:192])
-dst[191:176] := SaturateU16(a[255:224])
-dst[207:192] := SaturateU16(b[159:128])
-dst[223:208] := SaturateU16(b[191:160])
-dst[239:224] := SaturateU16(b[223:192])
-dst[255:240] := SaturateU16(b[255:224])
-dst[271:256] := SaturateU16(a[287:256])
-dst[287:272] := SaturateU16(a[319:288])
-dst[303:288] := SaturateU16(a[351:320])
-dst[319:304] := SaturateU16(a[383:352])
-dst[335:320] := SaturateU16(b[287:256])
-dst[351:336] := SaturateU16(b[319:288])
-dst[367:352] := SaturateU16(b[351:320])
-dst[383:368] := SaturateU16(b[383:352])
-dst[399:384] := SaturateU16(a[415:384])
-dst[415:400] := SaturateU16(a[447:416])
-dst[431:416] := SaturateU16(a[479:448])
-dst[447:432] := SaturateU16(a[511:480])
-dst[463:448] := SaturateU16(b[415:384])
-dst[479:464] := SaturateU16(b[447:416])
-dst[495:480] := SaturateU16(b[479:448])
-dst[511:496] := SaturateU16(b[511:480])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPACKUSDW" xed="VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_packus_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := SaturateU8(a[15:0])
-tmp_dst[15:8] := SaturateU8(a[31:16])
-tmp_dst[23:16] := SaturateU8(a[47:32])
-tmp_dst[31:24] := SaturateU8(a[63:48])
-tmp_dst[39:32] := SaturateU8(a[79:64])
-tmp_dst[47:40] := SaturateU8(a[95:80])
-tmp_dst[55:48] := SaturateU8(a[111:96])
-tmp_dst[63:56] := SaturateU8(a[127:112])
-tmp_dst[71:64] := SaturateU8(b[15:0])
-tmp_dst[79:72] := SaturateU8(b[31:16])
-tmp_dst[87:80] := SaturateU8(b[47:32])
-tmp_dst[95:88] := SaturateU8(b[63:48])
-tmp_dst[103:96] := SaturateU8(b[79:64])
-tmp_dst[111:104] := SaturateU8(b[95:80])
-tmp_dst[119:112] := SaturateU8(b[111:96])
-tmp_dst[127:120] := SaturateU8(b[127:112])
-tmp_dst[135:128] := SaturateU8(a[143:128])
-tmp_dst[143:136] := SaturateU8(a[159:144])
-tmp_dst[151:144] := SaturateU8(a[175:160])
-tmp_dst[159:152] := SaturateU8(a[191:176])
-tmp_dst[167:160] := SaturateU8(a[207:192])
-tmp_dst[175:168] := SaturateU8(a[223:208])
-tmp_dst[183:176] := SaturateU8(a[239:224])
-tmp_dst[191:184] := SaturateU8(a[255:240])
-tmp_dst[199:192] := SaturateU8(b[143:128])
-tmp_dst[207:200] := SaturateU8(b[159:144])
-tmp_dst[215:208] := SaturateU8(b[175:160])
-tmp_dst[223:216] := SaturateU8(b[191:176])
-tmp_dst[231:224] := SaturateU8(b[207:192])
-tmp_dst[239:232] := SaturateU8(b[223:208])
-tmp_dst[247:240] := SaturateU8(b[239:224])
-tmp_dst[255:248] := SaturateU8(b[255:240])
-tmp_dst[263:256] := SaturateU8(a[271:256])
-tmp_dst[271:264] := SaturateU8(a[287:272])
-tmp_dst[279:272] := SaturateU8(a[303:288])
-tmp_dst[287:280] := SaturateU8(a[319:304])
-tmp_dst[295:288] := SaturateU8(a[335:320])
-tmp_dst[303:296] := SaturateU8(a[351:336])
-tmp_dst[311:304] := SaturateU8(a[367:352])
-tmp_dst[319:312] := SaturateU8(a[383:368])
-tmp_dst[327:320] := SaturateU8(b[271:256])
-tmp_dst[335:328] := SaturateU8(b[287:272])
-tmp_dst[343:336] := SaturateU8(b[303:288])
-tmp_dst[351:344] := SaturateU8(b[319:304])
-tmp_dst[359:352] := SaturateU8(b[335:320])
-tmp_dst[367:360] := SaturateU8(b[351:336])
-tmp_dst[375:368] := SaturateU8(b[367:352])
-tmp_dst[383:376] := SaturateU8(b[383:368])
-tmp_dst[391:384] := SaturateU8(a[399:384])
-tmp_dst[399:392] := SaturateU8(a[415:400])
-tmp_dst[407:400] := SaturateU8(a[431:416])
-tmp_dst[415:408] := SaturateU8(a[447:432])
-tmp_dst[423:416] := SaturateU8(a[463:448])
-tmp_dst[431:424] := SaturateU8(a[479:464])
-tmp_dst[439:432] := SaturateU8(a[495:480])
-tmp_dst[447:440] := SaturateU8(a[511:496])
-tmp_dst[455:448] := SaturateU8(b[399:384])
-tmp_dst[463:456] := SaturateU8(b[415:400])
-tmp_dst[471:464] := SaturateU8(b[431:416])
-tmp_dst[479:472] := SaturateU8(b[447:432])
-tmp_dst[487:480] := SaturateU8(b[463:448])
-tmp_dst[495:488] := SaturateU8(b[479:464])
-tmp_dst[503:496] := SaturateU8(b[495:480])
-tmp_dst[511:504] := SaturateU8(b[511:496])
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPACKUSWB" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_packus_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[7:0] := SaturateU8(a[15:0])
-tmp_dst[15:8] := SaturateU8(a[31:16])
-tmp_dst[23:16] := SaturateU8(a[47:32])
-tmp_dst[31:24] := SaturateU8(a[63:48])
-tmp_dst[39:32] := SaturateU8(a[79:64])
-tmp_dst[47:40] := SaturateU8(a[95:80])
-tmp_dst[55:48] := SaturateU8(a[111:96])
-tmp_dst[63:56] := SaturateU8(a[127:112])
-tmp_dst[71:64] := SaturateU8(b[15:0])
-tmp_dst[79:72] := SaturateU8(b[31:16])
-tmp_dst[87:80] := SaturateU8(b[47:32])
-tmp_dst[95:88] := SaturateU8(b[63:48])
-tmp_dst[103:96] := SaturateU8(b[79:64])
-tmp_dst[111:104] := SaturateU8(b[95:80])
-tmp_dst[119:112] := SaturateU8(b[111:96])
-tmp_dst[127:120] := SaturateU8(b[127:112])
-tmp_dst[135:128] := SaturateU8(a[143:128])
-tmp_dst[143:136] := SaturateU8(a[159:144])
-tmp_dst[151:144] := SaturateU8(a[175:160])
-tmp_dst[159:152] := SaturateU8(a[191:176])
-tmp_dst[167:160] := SaturateU8(a[207:192])
-tmp_dst[175:168] := SaturateU8(a[223:208])
-tmp_dst[183:176] := SaturateU8(a[239:224])
-tmp_dst[191:184] := SaturateU8(a[255:240])
-tmp_dst[199:192] := SaturateU8(b[143:128])
-tmp_dst[207:200] := SaturateU8(b[159:144])
-tmp_dst[215:208] := SaturateU8(b[175:160])
-tmp_dst[223:216] := SaturateU8(b[191:176])
-tmp_dst[231:224] := SaturateU8(b[207:192])
-tmp_dst[239:232] := SaturateU8(b[223:208])
-tmp_dst[247:240] := SaturateU8(b[239:224])
-tmp_dst[255:248] := SaturateU8(b[255:240])
-tmp_dst[263:256] := SaturateU8(a[271:256])
-tmp_dst[271:264] := SaturateU8(a[287:272])
-tmp_dst[279:272] := SaturateU8(a[303:288])
-tmp_dst[287:280] := SaturateU8(a[319:304])
-tmp_dst[295:288] := SaturateU8(a[335:320])
-tmp_dst[303:296] := SaturateU8(a[351:336])
-tmp_dst[311:304] := SaturateU8(a[367:352])
-tmp_dst[319:312] := SaturateU8(a[383:368])
-tmp_dst[327:320] := SaturateU8(b[271:256])
-tmp_dst[335:328] := SaturateU8(b[287:272])
-tmp_dst[343:336] := SaturateU8(b[303:288])
-tmp_dst[351:344] := SaturateU8(b[319:304])
-tmp_dst[359:352] := SaturateU8(b[335:320])
-tmp_dst[367:360] := SaturateU8(b[351:336])
-tmp_dst[375:368] := SaturateU8(b[367:352])
-tmp_dst[383:376] := SaturateU8(b[383:368])
-tmp_dst[391:384] := SaturateU8(a[399:384])
-tmp_dst[399:392] := SaturateU8(a[415:400])
-tmp_dst[407:400] := SaturateU8(a[431:416])
-tmp_dst[415:408] := SaturateU8(a[447:432])
-tmp_dst[423:416] := SaturateU8(a[463:448])
-tmp_dst[431:424] := SaturateU8(a[479:464])
-tmp_dst[439:432] := SaturateU8(a[495:480])
-tmp_dst[447:440] := SaturateU8(a[511:496])
-tmp_dst[455:448] := SaturateU8(b[399:384])
-tmp_dst[463:456] := SaturateU8(b[415:400])
-tmp_dst[471:464] := SaturateU8(b[431:416])
-tmp_dst[479:472] := SaturateU8(b[447:432])
-tmp_dst[487:480] := SaturateU8(b[463:448])
-tmp_dst[495:488] := SaturateU8(b[479:464])
-tmp_dst[503:496] := SaturateU8(b[495:480])
-tmp_dst[511:504] := SaturateU8(b[511:496])
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := tmp_dst[i+7:i]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPACKUSWB" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_packus_epi16" tech="AVX-512">
-	<category>Miscellaneous</category>
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := SaturateU8(a[15:0])
-dst[15:8] := SaturateU8(a[31:16])
-dst[23:16] := SaturateU8(a[47:32])
-dst[31:24] := SaturateU8(a[63:48])
-dst[39:32] := SaturateU8(a[79:64])
-dst[47:40] := SaturateU8(a[95:80])
-dst[55:48] := SaturateU8(a[111:96])
-dst[63:56] := SaturateU8(a[127:112])
-dst[71:64] := SaturateU8(b[15:0])
-dst[79:72] := SaturateU8(b[31:16])
-dst[87:80] := SaturateU8(b[47:32])
-dst[95:88] := SaturateU8(b[63:48])
-dst[103:96] := SaturateU8(b[79:64])
-dst[111:104] := SaturateU8(b[95:80])
-dst[119:112] := SaturateU8(b[111:96])
-dst[127:120] := SaturateU8(b[127:112])
-dst[135:128] := SaturateU8(a[143:128])
-dst[143:136] := SaturateU8(a[159:144])
-dst[151:144] := SaturateU8(a[175:160])
-dst[159:152] := SaturateU8(a[191:176])
-dst[167:160] := SaturateU8(a[207:192])
-dst[175:168] := SaturateU8(a[223:208])
-dst[183:176] := SaturateU8(a[239:224])
-dst[191:184] := SaturateU8(a[255:240])
-dst[199:192] := SaturateU8(b[143:128])
-dst[207:200] := SaturateU8(b[159:144])
-dst[215:208] := SaturateU8(b[175:160])
-dst[223:216] := SaturateU8(b[191:176])
-dst[231:224] := SaturateU8(b[207:192])
-dst[239:232] := SaturateU8(b[223:208])
-dst[247:240] := SaturateU8(b[239:224])
-dst[255:248] := SaturateU8(b[255:240])
-dst[263:256] := SaturateU8(a[271:256])
-dst[271:264] := SaturateU8(a[287:272])
-dst[279:272] := SaturateU8(a[303:288])
-dst[287:280] := SaturateU8(a[319:304])
-dst[295:288] := SaturateU8(a[335:320])
-dst[303:296] := SaturateU8(a[351:336])
-dst[311:304] := SaturateU8(a[367:352])
-dst[319:312] := SaturateU8(a[383:368])
-dst[327:320] := SaturateU8(b[271:256])
-dst[335:328] := SaturateU8(b[287:272])
-dst[343:336] := SaturateU8(b[303:288])
-dst[351:344] := SaturateU8(b[319:304])
-dst[359:352] := SaturateU8(b[335:320])
-dst[367:360] := SaturateU8(b[351:336])
-dst[375:368] := SaturateU8(b[367:352])
-dst[383:376] := SaturateU8(b[383:368])
-dst[391:384] := SaturateU8(a[399:384])
-dst[399:392] := SaturateU8(a[415:400])
-dst[407:400] := SaturateU8(a[431:416])
-dst[415:408] := SaturateU8(a[447:432])
-dst[423:416] := SaturateU8(a[463:448])
-dst[431:424] := SaturateU8(a[479:464])
-dst[439:432] := SaturateU8(a[495:480])
-dst[447:440] := SaturateU8(a[511:496])
-dst[455:448] := SaturateU8(b[399:384])
-dst[463:456] := SaturateU8(b[415:400])
-dst[471:464] := SaturateU8(b[431:416])
-dst[479:472] := SaturateU8(b[447:432])
-dst[487:480] := SaturateU8(b[463:448])
-dst[495:488] := SaturateU8(b[479:464])
-dst[503:496] := SaturateU8(b[495:480])
-dst[511:504] := SaturateU8(b[511:496])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPACKUSWB" xed="VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := Saturate8(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVSWB" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m256i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVSWB" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVSWB" xed="VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtsepi16_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVSWB" xed="VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi8_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	l := j*16
-	dst[l+15:l] := SignExtend16(a[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VPMOVSXBW" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi8_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := SignExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VPMOVSXBW" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi8_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI8" type="__m256i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := SignExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VPMOVSXBW" xed="VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := SaturateU8(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVUSWB" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVUSWB" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVUSWB" xed="VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtusepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVUSWB" xed="VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	dst[l+7:l] := Truncate8(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVWB" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVWB" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi16_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVWB" xed="VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi16_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+15:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVWB" xed="VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu8_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	l := j*16
-	dst[l+15:l] := ZeroExtend16(a[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VPMOVZXBW" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu8_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := ZeroExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VPMOVZXBW" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu8_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	l := j*16
-	IF k[j]
-		dst[l+15:l] := ZeroExtend16(a[i+7:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VPMOVZXBW" xed="VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_set1_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_set1_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[7:0]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, r8" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_set1_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast 16-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_set1_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[15:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, r16" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpge_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpgt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpge_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpgt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPB" xed="VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpge_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpgt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpge_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpgt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &gt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt;= b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] &lt; b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_epu8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUB" xed="VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpge_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpgt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpge_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpgt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_epu16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPUW" xed="VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpge_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpgt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="const int" varname="imm8" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpge_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpgt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &gt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt;= b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] &lt; b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPW" xed="VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_test_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_test_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPTESTMB" xed="VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_test_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_test_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPTESTMW" xed="VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_testn_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="k1" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k1[j]
-		k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_testn_epi8_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPTESTNMB" xed="VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_testn_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k1[j]
-		k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_testn_epi16_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPTESTNMW" xed="VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_bslli_epi128" tech="AVX-512">
-	<return etype="M128" type="__m512i" varname="dst" />
-	<parameter etype="M128" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
-dst[255:128] := a[255:128] &lt;&lt; (tmp*8)
-dst[383:256] := a[383:256] &lt;&lt; (tmp*8)
-dst[511:384] := a[511:384] &lt;&lt; (tmp*8)
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSLLDQ" xed="VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSLLVW" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSLLVW" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sllv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSLLVW" xed="VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sll_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_slli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sll_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_slli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sll_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_slli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSLLW" xed="VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSRAVW" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSRAVW" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srav_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0)
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSRAVW" xed="VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sra_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srai_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sra_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srai_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-		ELSE
-			dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sra_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srai_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSRAW" xed="VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_bsrli_epi128" tech="AVX-512">
-	<return etype="M128" type="__m512i" varname="dst" />
-	<parameter etype="M128" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
-dst[255:128] := a[255:128] &gt;&gt; (tmp*8)
-dst[383:256] := a[383:256] &gt;&gt; (tmp*8)
-dst[511:384] := a[511:384] &gt;&gt; (tmp*8)
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSRLDQ" xed="VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSRLVW" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[i+15:i] &lt; 16
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-		ELSE
-			dst[i+15:i] := 0
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSRLVW" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srlv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF count[i+15:i] &lt; 16
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSRLVW" xed="VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srl_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srl_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF count[63:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		IF imm8[7:0] &gt; 15
-			dst[i+15:i] := 0
-		ELSE
-			dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srl_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srli_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSRLW" xed="VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_kadd_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Add 32-bit masks in "a" and "b", and store the result in "k".</description>
-	<operation>
-k[31:0] := a[31:0] + b[31:0]
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, k, k" name="KADDD" xed="KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kadd_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Add 64-bit masks in "a" and "b", and store the result in "k".</description>
-	<operation>
-k[63:0] := a[63:0] + b[63:0]
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, k, k" name="KADDQ" xed="KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kand_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[31:0] := a[31:0] AND b[31:0]
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDD" xed="KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kand_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[63:0] := a[63:0] AND b[63:0]
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDQ" xed="KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kandn_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise NOT of 32-bit masks "a" and then AND with "b", and store the result in "k".</description>
-	<operation>
-k[31:0] := (NOT a[31:0]) AND b[31:0]
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDND" xed="KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kandn_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise NOT of 64-bit masks "a" and then AND with "b", and store the result in "k".</description>
-	<operation>
-k[63:0] := (NOT a[63:0]) AND b[63:0]
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDNQ" xed="KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_knot_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<description>Compute the bitwise NOT of 32-bit mask "a", and store the result in "k".</description>
-	<operation>
-k[31:0] := NOT a[31:0]
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, k" name="KNOTD" xed="KNOTD_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_knot_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<description>Compute the bitwise NOT of 64-bit mask "a", and store the result in "k".</description>
-	<operation>
-k[63:0] := NOT a[63:0]
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, k" name="KNOTQ" xed="KNOTQ_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kor_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise OR of 32-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[31:0] := a[31:0] OR b[31:0]
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, k, k" name="KORD" xed="KORD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kor_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise OR of 64-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[63:0] := a[63:0] OR b[63:0]
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, k, k" name="KORQ" xed="KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kxnor_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise XNOR of 32-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[31:0] := NOT (a[31:0] XOR b[31:0])
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXNORD" xed="KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kxnor_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise XNOR of 64-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[63:0] := NOT (a[63:0] XOR b[63:0])
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXNORQ" xed="KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kxor_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise XOR of 32-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[31:0] := a[31:0] XOR b[31:0]
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXORD" xed="KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kxor_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise XOR of 64-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[63:0] := a[63:0] XOR b[63:0]
-k[MAX:64] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXORQ" xed="KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kshiftli_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
-	<description>Shift the bits of 32-bit mask "a" left by "count" while shifting in zeros, and store the least significant 32 bits of the result in "k".</description>
-	<operation>
-k[MAX:0] := 0
-IF count[7:0] &lt;= 31
-	k[31:0] := a[31:0] &lt;&lt; count[7:0]
-FI
-	</operation>
-	<instruction form="k, k, imm8" name="KSHIFTLD" xed="KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kshiftli_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
-	<description>Shift the bits of 64-bit mask "a" left by "count" while shifting in zeros, and store the least significant 64 bits of the result in "k".</description>
-	<operation>
-k[MAX:0] := 0
-IF count[7:0] &lt;= 63
-	k[63:0] := a[63:0] &lt;&lt; count[7:0]
-FI
-	</operation>
-	<instruction form="k, k, imm8" name="KSHIFTLQ" xed="KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kshiftri_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
-	<description>Shift the bits of 32-bit mask "a" right by "count" while shifting in zeros, and store the least significant 32 bits of the result in "k".</description>
-	<operation>
-k[MAX:0] := 0
-IF count[7:0] &lt;= 31
-	k[31:0] := a[31:0] &gt;&gt; count[7:0]
-FI
-	</operation>
-	<instruction form="k, k, imm8" name="KSHIFTRD" xed="KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kshiftri_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
-	<description>Shift the bits of 64-bit mask "a" right by "count" while shifting in zeros, and store the least significant 64 bits of the result in "k".</description>
-	<operation>
-k[MAX:0] := 0
-IF count[7:0] &lt;= 63
-	k[63:0] := a[63:0] &gt;&gt; count[7:0]
-FI
-	</operation>
-	<instruction form="k, k, imm8" name="KSHIFTRQ" xed="KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortest_mask32_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="all_ones" />
-	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
-	<operation>
-tmp[31:0] := a[31:0] OR b[31:0]
-IF tmp[31:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-IF tmp[31:0] == 0xFFFFFFFF
-	MEM[all_ones+7:all_ones] := 1
-ELSE
-	MEM[all_ones+7:all_ones] := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTD" xed="KORTESTD_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortestz_mask32_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[31:0] := a[31:0] OR b[31:0]
-IF tmp[31:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTD" xed="KORTESTD_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortestc_mask32_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[31:0] := a[31:0] OR b[31:0]
-IF tmp[31:0] == 0xFFFFFFFF
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTD" xed="KORTESTD_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortest_mask64_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="all_ones" />
-	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
-	<operation>
-tmp[63:0] := a[63:0] OR b[63:0]
-IF tmp[63:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-IF tmp[7:0] == 0xFFFFFFFFFFFFFFFF
-	MEM[all_ones+7:all_ones] := 1
-ELSE
-	MEM[all_ones+7:all_ones] := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTQ" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortestz_mask64_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[63:0] := a[63:0] OR b[63:0]
-IF tmp[63:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTQ" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortestc_mask64_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[63:0] := a[63:0] OR b[63:0]
-IF tmp[63:0] == 0xFFFFFFFFFFFFFFFF
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTQ" xed="KORTESTQ_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktest_mask32_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="and_not" />
-	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
-	<operation>
-tmp1[31:0] := a[31:0] AND b[31:0]
-IF tmp1[31:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-tmp2[31:0] := (NOT a[31:0]) AND b[31:0]
-IF tmp2[31:0] == 0x0
-	MEM[and_not+7:and_not] := 1
-ELSE
-	MEM[and_not+7:and_not] := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTD" xed="KTESTD_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktestz_mask32_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise AND of 32-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[31:0] := a[31:0] AND b[31:0]
-IF tmp[31:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTD" xed="KTESTD_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktestc_mask32_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="b" />
-	<description>Compute the bitwise NOT of 32-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[31:0] := (NOT a[31:0]) AND b[31:0]
-IF tmp[31:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTD" xed="KTESTD_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktest_mask64_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="and_not" />
-	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
-	<operation>
-tmp1[63:0] := a[63:0] AND b[63:0]
-IF tmp1[63:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-tmp2[63:0] := (NOT a[63:0]) AND b[63:0]
-IF tmp2[63:0] == 0x0
-	MEM[and_not+7:and_not] := 1
-ELSE
-	MEM[and_not+7:and_not] := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTQ" xed="KTESTQ_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktestz_mask64_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise AND of 64-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[63:0] := a[63:0] AND b[63:0]
-IF tmp[63:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTQ" xed="KTESTQ_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktestc_mask64_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="b" />
-	<description>Compute the bitwise NOT of 64-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[63:0] := (NOT a[63:0]) AND b[63:0]
-IF tmp[63:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTQ" xed="KTESTQ_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_cvtmask32_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="a" />
-	<description>Convert 32-bit mask "a" into an integer value, and store the result in "dst".</description>
-	<operation>
-dst := ZeroExtend32(a[31:0])
-	</operation>
-	<instruction form="r32, k" name="KMOVD" xed="KMOVD_GPR32u32_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_cvtmask64_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="a" />
-	<description>Convert 64-bit mask "a" into an integer value, and store the result in "dst".</description>
-	<operation>
-dst := ZeroExtend64(a[63:0])
-	</operation>
-	<instruction form="r64, k" name="KMOVQ" xed="KMOVQ_GPR64u64_MASKmskw_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_cvtu32_mask32" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Convert integer value "a" into an 32-bit mask, and store the result in "k".</description>
-	<operation>
-k := ZeroExtend32(a[31:0])
-	</operation>
-	<instruction form="k, r32" name="KMOVD" xed="KMOVD_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_cvtu64_mask64" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Convert integer value "a" into an 64-bit mask, and store the result in "k".</description>
-	<operation>
-k := ZeroExtend64(a[63:0])
-	</operation>
-	<instruction form="k, r64" name="KMOVQ" xed="KMOVQ_MASKmskw_GPR64u64_AVX512" />
-	<CPUID>AVX512BW</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_broadcastmb_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ZeroExtend64(k[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm" name="VPBROADCASTMB2Q" xed="VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastmb_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ZeroExtend64(k[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm" name="VPBROADCASTMB2Q" xed="VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcastmw_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ZeroExtend32(k[15:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm" name="VPBROADCASTMW2D" xed="VPBROADCASTMW2D_YMMu32_MASKu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcastmw_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ZeroExtend32(k[15:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm" name="VPBROADCASTMW2D" xed="VPBROADCASTMW2D_XMMu32_MASKu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	FOR k := 0 to j-1
-		m := k*32
-		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-	ENDFOR
-	dst[i+31:i+j] := 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPCONFLICTD" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*32
-			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-		ENDFOR
-		dst[i+31:i+j] := 0
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPCONFLICTD" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*32
-			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-		ENDFOR
-		dst[i+31:i+j] := 0
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPCONFLICTD" xed="VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	FOR k := 0 to j-1
-		m := k*32
-		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-	ENDFOR
-	dst[i+31:i+j] := 0
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPCONFLICTD" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*32
-			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-		ENDFOR
-		dst[i+31:i+j] := 0
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPCONFLICTD" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*32
-			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-		ENDFOR
-		dst[i+31:i+j] := 0
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPCONFLICTD" xed="VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	FOR k := 0 to j-1
-		m := k*64
-		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-	ENDFOR
-	dst[i+63:i+j] := 0
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPCONFLICTQ" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*64
-			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-		ENDFOR
-		dst[i+63:i+j] := 0
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPCONFLICTQ" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*64
-			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-		ENDFOR
-		dst[i+63:i+j] := 0
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPCONFLICTQ" xed="VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	FOR k := 0 to j-1
-		m := k*64
-		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-	ENDFOR
-	dst[i+63:i+j] := 0
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*64
-			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-		ENDFOR
-		dst[i+63:i+j] := 0
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*64
-			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-		ENDFOR
-		dst[i+63:i+j] := 0
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	tmp := 31
-	dst[i+31:i] := 0
-	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-		tmp := tmp - 1
-		dst[i+31:i] := dst[i+31:i] + 1
-	OD
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPLZCNTD" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		tmp := 31
-		dst[i+31:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+31:i] := dst[i+31:i] + 1
-		OD
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPLZCNTD" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		tmp := 31
-		dst[i+31:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+31:i] := dst[i+31:i] + 1
-		OD
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPLZCNTD" xed="VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	tmp := 31
-	dst[i+31:i] := 0
-	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-		tmp := tmp - 1
-		dst[i+31:i] := dst[i+31:i] + 1
-	OD
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPLZCNTD" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		tmp := 31
-		dst[i+31:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+31:i] := dst[i+31:i] + 1
-		OD
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPLZCNTD" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		tmp := 31
-		dst[i+31:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+31:i] := dst[i+31:i] + 1
-		OD
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPLZCNTD" xed="VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp := 63
-	dst[i+63:i] := 0
-	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-		tmp := tmp - 1
-		dst[i+63:i] := dst[i+63:i] + 1
-	OD
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPLZCNTQ" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp := 63
-		dst[i+63:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+63:i] := dst[i+63:i] + 1
-		OD
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPLZCNTQ" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp := 63
-		dst[i+63:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+63:i] := dst[i+63:i] + 1
-		OD
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPLZCNTQ" xed="VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp := 63
-	dst[i+63:i] := 0
-	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-		tmp := tmp - 1
-		dst[i+63:i] := dst[i+63:i] + 1
-	OD
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPLZCNTQ" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp := 63
-		dst[i+63:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+63:i] := dst[i+63:i] + 1
-		OD
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPLZCNTQ" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp := 63
-		dst[i+63:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+63:i] := dst[i+63:i] + 1
-		OD
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPLZCNTQ" xed="VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512CD</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_broadcastmb_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ZeroExtend64(k[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm" name="VPBROADCASTMB2Q" xed="VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcastmw_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ZeroExtend32(k[15:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm" name="VPBROADCASTMW2D" xed="VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	FOR k := 0 to j-1
-		m := k*32
-		dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-	ENDFOR
-	dst[i+31:i+j] := 0
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPCONFLICTD" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*32
-			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-		ENDFOR
-		dst[i+31:i+j] := 0
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPCONFLICTD" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_conflict_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*32
-			dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0
-		ENDFOR
-		dst[i+31:i+j] := 0
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPCONFLICTD" xed="VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	FOR k := 0 to j-1
-		m := k*64
-		dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-	ENDFOR
-	dst[i+63:i+j] := 0
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*64
-			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-		ENDFOR
-		dst[i+63:i+j] := 0
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_conflict_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		FOR l := 0 to j-1
-			m := l*64
-			dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0
-		ENDFOR
-		dst[i+63:i+j] := 0
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPCONFLICTQ" xed="VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	tmp := 31
-	dst[i+31:i] := 0
-	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-		tmp := tmp - 1
-		dst[i+31:i] := dst[i+31:i] + 1
-	OD
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPLZCNTD" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp := 31
-		dst[i+31:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+31:i] := dst[i+31:i] + 1
-		OD
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPLZCNTD" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_lzcnt_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp := 31
-		dst[i+31:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+31:i] := dst[i+31:i] + 1
-		OD
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPLZCNTD" xed="VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	tmp := 63
-	dst[i+63:i] := 0
-	DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-		tmp := tmp - 1
-		dst[i+63:i] := dst[i+63:i] + 1
-	OD
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPLZCNTQ" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp := 63
-		dst[i+63:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+63:i] := dst[i+63:i] + 1
-		OD
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPLZCNTQ" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_lzcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp := 63
-		dst[i+63:i] := 0
-		DO WHILE (tmp &gt;= 0 AND a[i+tmp] == 0)
-			tmp := tmp - 1
-			dst[i+63:i] := dst[i+63:i] + 1
-		OD
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPLZCNTQ" xed="VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD" />
-	<CPUID>AVX512CD</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_mask_andnot_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VANDNPD" xed="VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_andnot_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VANDNPD" xed="VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_andnot_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VANDNPD" xed="VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_andnot_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VANDNPD" xed="VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_andnot_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VANDNPS" xed="VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_andnot_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VANDNPS" xed="VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_andnot_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VANDNPS" xed="VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_andnot_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VANDNPS" xed="VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_and_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VANDPD" xed="VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_and_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0 
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VANDPD" xed="VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_and_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VANDPD" xed="VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_and_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VANDPD" xed="VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_and_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VANDPS" xed="VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_and_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VANDPS" xed="VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_and_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VANDPS" xed="VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_and_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VANDPS" xed="VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_or_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VORPD" xed="VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_or_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VORPD" xed="VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_or_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VORPD" xed="VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_or_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VORPD" xed="VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_or_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VORPS" xed="VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_or_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VORPS" xed="VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_or_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VORPS" xed="VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_or_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VORPS" xed="VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_xor_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VXORPD" xed="VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_xor_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VXORPD" xed="VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_xor_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VXORPD" xed="VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_xor_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VXORPD" xed="VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_xor_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VXORPS" xed="VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_xor_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VXORPS" xed="VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_xor_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VXORPS" xed="VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_xor_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VXORPS" xed="VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_f32x2" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 2)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcast_f32x2" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcast_f32x2" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	n := (j % 2)*64
-	dst[i+63:i] := a[n+63:n]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	n := (j % 2)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	n := (j % 2)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 2)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	n := (j % 2)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	n := (j % 2)*64
-	dst[i+63:i] := a[n+63:n]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	n := (j % 2)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	n := (j % 2)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extractf64x2_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_extractf64x2_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_extractf64x2_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extracti64x2_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_extracti64x2_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_extracti64x2_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fpclass_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fpclass_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fpclass_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fpclass_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fpclass_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fpclass_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fpclass_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fpclass_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insertf64x2" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[255:0] := a[255:0]
-CASE imm8[0] OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_insertf64x2" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_insertf64x2" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_inserti64x2" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[255:0] := a[255:0]
-CASE imm8[0] OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_inserti64x2" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_inserti64x2" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movepi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF a[i+31]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm" name="VPMOVD2M" xed="VPMOVD2M_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movepi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF a[i+31]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm" name="VPMOVD2M" xed="VPMOVD2M_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movm_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := 0xFFFFFFFF
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm" name="VPMOVM2D" xed="VPMOVM2D_YMMu32_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movm_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := 0xFFFFFFFF
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm" name="VPMOVM2D" xed="VPMOVM2D_XMMu32_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movm_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm" name="VPMOVM2Q" xed="VPMOVM2Q_YMMu64_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movm_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm" name="VPMOVM2Q" xed="VPMOVM2Q_XMMu64_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_movepi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF a[i+63]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm" name="VPMOVQ2M" xed="VPMOVQ2M_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movepi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF a[i+63]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm" name="VPMOVQ2M" xed="VPMOVQ2M_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VRANGEPD" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VRANGEPD" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VRANGEPD" xed="VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRANGEPD" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRANGEPD" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VRANGEPD" xed="VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VRANGEPS" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VRANGEPS" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VRANGEPS" xed="VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRANGEPS" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRANGEPS" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VRANGEPS" xed="VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VREDUCEPD" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VREDUCEPD" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VREDUCEPD" xed="VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VREDUCEPS" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VREDUCEPS" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	RETURN tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VREDUCEPS" xed="VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTPD2QQ" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTPD2QQ" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTPD2QQ" xed="VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPS2QQ" xed="VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTQQ2PD" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTQQ2PD" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTQQ2PD" xed="VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := a[i+63:i] * b[i+63:i]
-		dst[i+63:i] := tmp[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULLQ" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := a[i+63:i] * b[i+63:i]
-		dst[i+63:i] := tmp[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULLQ" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := a[i+63:i] * b[i+63:i]
-	dst[i+63:i] := tmp[63:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULLQ" xed="VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := a[i+63:i] * b[i+63:i]
-		dst[i+63:i] := tmp[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULLQ" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := a[i+63:i] * b[i+63:i]
-		dst[i+63:i] := tmp[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULLQ" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := a[i+63:i] * b[i+63:i]
-	dst[i+63:i] := tmp[63:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPMULLQ" xed="VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_andnot_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VANDNPD" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_andnot_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VANDNPD" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_andnot_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VANDNPD" xed="VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_andnot_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VANDNPS" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_andnot_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VANDNPS" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_andnot_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VANDNPS" xed="VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_and_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VANDPD" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_and_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VANDPD" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_and_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VANDPD" xed="VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_and_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VANDPS" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_and_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VANDPS" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_and_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VANDPS" xed="VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_or_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VORPD" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_or_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VORPD" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_or_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VORPD" xed="VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_or_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VORPS" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_or_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VORPS" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_or_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VORPS" xed="VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_xor_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VXORPD" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_xor_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VXORPD" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_xor_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VXORPD" xed="VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_xor_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VXORPS" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_xor_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VXORPS" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_xor_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VXORPS" xed="VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_f32x2" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 2)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_f32x2" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_f32x2" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VBROADCASTF32X2" xed="VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_f32x8" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 8)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m256" name="VBROADCASTF32X8" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_f32x8" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 8)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m256" name="VBROADCASTF32X8" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_f32x8" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 8)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m256" name="VBROADCASTF32X8" xed="VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 2)*64
-	dst[i+63:i] := a[n+63:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 2)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_f64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 2)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m128" name="VBROADCASTF64X2" xed="VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 2)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_i32x2" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 2)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VBROADCASTI32X2" xed="VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_i32x8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 8)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m256" name="VBROADCASTI32X8" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_i32x8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 8)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m256" name="VBROADCASTI32X8" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_i32x8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 8)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m256" name="VBROADCASTI32X8" xed="VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 2)*64
-	dst[i+63:i] := a[n+63:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 2)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_i64x2" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 2)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m128" name="VBROADCASTI64X2" xed="VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_extractf32x8_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[255:0] := a[255:0]
-1: dst[255:0] := a[511:256]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm, imm8" name="VEXTRACTF32X8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_extractf32x8_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[255:0] := a[255:0]
-1: tmp[255:0] := a[511:256]
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm, imm8" name="VEXTRACTF32X8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_extractf32x8_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[255:0] := a[255:0]
-1: tmp[255:0] := a[511:256]
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm, imm8" name="VEXTRACTF32X8" xed="VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_extractf64x2_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[1:0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-2: dst[127:0] := a[383:256]
-3: dst[127:0] := a[511:384]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_extractf64x2_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[1:0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-2: tmp[127:0] := a[383:256]
-3: tmp[127:0] := a[511:384]
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_extractf64x2_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[1:0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-2: tmp[127:0] := a[383:256]
-3: tmp[127:0] := a[511:384]
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm, imm8" name="VEXTRACTF64X2" xed="VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_extracti32x8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[255:0] := a[255:0]
-1: dst[255:0] := a[511:256]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm, imm8" name="VEXTRACTI32X8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_extracti32x8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[255:0] := a[255:0]
-1: tmp[255:0] := a[511:256]
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm, imm8" name="VEXTRACTI32X8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_extracti32x8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[255:0] := a[255:0]
-1: tmp[255:0] := a[511:256]
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm, imm8" name="VEXTRACTI32X8" xed="VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_extracti64x2_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[1:0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-2: dst[127:0] := a[383:256]
-3: dst[127:0] := a[511:384]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_extracti64x2_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[1:0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-2: tmp[127:0] := a[383:256]
-3: tmp[127:0] := a[511:384]
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_extracti64x2_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[1:0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-2: tmp[127:0] := a[383:256]
-3: tmp[127:0] := a[511:384]
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm, imm8" name="VEXTRACTI64X2" xed="VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fpclass_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fpclass_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0])
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, imm8" name="VFPCLASSPD" xed="VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fpclass_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fpclass_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-	[fpclass_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0])
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, imm8" name="VFPCLASSPS" xed="VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fpclass_sd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test the lower double-precision (64-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k".
-	[fpclass_note]</description>
-	<operation>k[0] := CheckFPClass_FP64(a[63:0], imm8[7:0])
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, imm8" name="VFPCLASSSD" xed="VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fpclass_sd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test the lower double-precision (64-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).
-	[fpclass_note]</description>
-	<operation>IF k1[0]
-	k[0] := CheckFPClass_FP64(a[63:0], imm8[7:0])
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, imm8" name="VFPCLASSSD" xed="VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fpclass_ss_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test the lower single-precision (32-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k.
-	[fpclass_note]</description>
-	<operation>k[0] := CheckFPClass_FP32(a[31:0], imm8[7:0])
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, imm8" name="VFPCLASSSS" xed="VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fpclass_ss_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test the lower single-precision (32-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).
-	[fpclass_note]</description>
-	<operation>IF k1[0]
-	k[0] := CheckFPClass_FP32(a[31:0], imm8[7:0])
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, imm8" name="VFPCLASSSS" xed="VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_insertf32x8" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: dst[255:0] := b[255:0]
-1: dst[511:256] := b[255:0]
-ESAC
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, ymm, imm8" name="VINSERTF32X8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_insertf32x8" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: tmp[255:0] := b[255:0]
-1: tmp[511:256] := b[255:0]
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, ymm, imm8" name="VINSERTF32X8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_insertf32x8" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: tmp[255:0] := b[255:0]
-1: tmp[511:256] := b[255:0]
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, ymm, imm8" name="VINSERTF32X8" xed="VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_insertf64x2" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[511:0] := a[511:0]
-CASE imm8[1:0] OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-2: dst[383:256] := b[127:0]
-3: dst[511:384] := b[127:0]
-ESAC
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_insertf64x2" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-2: tmp[383:256] := b[127:0]
-3: tmp[511:384] := b[127:0]
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_insertf64x2" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-2: tmp[383:256] := b[127:0]
-3: tmp[511:384] := b[127:0]
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm, imm8" name="VINSERTF64X2" xed="VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_inserti32x8" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[511:0] := a[511:0]
-CASE imm8[0] OF
-0: dst[255:0] := b[255:0]
-1: dst[511:256] := b[255:0]
-ESAC
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, ymm, imm8" name="VINSERTI32X8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_inserti32x8" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: tmp[255:0] := b[255:0]
-1: tmp[511:256] := b[255:0]
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, ymm, imm8" name="VINSERTI32X8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_inserti32x8" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: tmp[255:0] := b[255:0]
-1: tmp[511:256] := b[255:0]
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, ymm, imm8" name="VINSERTI32X8" xed="VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_inserti64x2" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[511:0] := a[511:0]
-CASE imm8[1:0] OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-2: dst[383:256] := b[127:0]
-3: dst[511:384] := b[127:0]
-ESAC
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_inserti64x2" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-2: tmp[383:256] := b[127:0]
-3: tmp[511:384] := b[127:0]
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_inserti64x2" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-2: tmp[383:256] := b[127:0]
-3: tmp[511:384] := b[127:0]
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm, imm8" name="VINSERTI64X2" xed="VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movepi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF a[i+31]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm" name="VPMOVD2M" xed="VPMOVD2M_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movm_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := 0xFFFFFFFF
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm" name="VPMOVM2D" xed="VPMOVM2D_ZMMu32_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movm_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := 0xFFFFFFFFFFFFFFFF
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm" name="VPMOVM2Q" xed="VPMOVM2Q_ZMMu64_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movepi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF a[i+63]
-		k[j] := 1
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm" name="VPMOVQ2M" xed="VPMOVQ2M_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_range_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {sae}, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_range_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {sae}, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_range_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_range_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {sae}, imm8" name="VRANGEPD" xed="VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_range_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {sae}, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_range_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {sae}, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_range_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_range_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[63:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {sae}, imm8" name="VRANGEPS" xed="VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_range_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-IF k[0]
-	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_range_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-IF k[0]
-	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_range_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-IF k[0]
-	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_range_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-IF k[0]
-	dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_range_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src1[63:0] : src2[63:0]
-	1: tmp[63:0] := (src1[63:0] &lt;= src2[63:0]) ? src2[63:0] : src1[63:0]
-	2: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src1[63:0] : src2[63:0]
-	3: tmp[63:0] := (ABS(src1[63:0]) &lt;= ABS(src2[63:0])) ? src2[63:0] : src1[63:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[63:0] := (src1[63] &lt;&lt; 63) OR (tmp[62:0])
-	1: dst[63:0] := tmp[63:0]
-	2: dst[63:0] := (0 &lt;&lt; 63) OR (tmp[62:0])
-	3: dst[63:0] := (1 &lt;&lt; 63) OR (tmp[62:0])
-	ESAC
-	
-	RETURN dst
-}
-dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VRANGESD" xed="VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_range_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[31:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-IF k[0]
-	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_range_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[31:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-IF k[0]
-	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_range_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[31:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-IF k[0]
-	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_range_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit.</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[31:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-IF k[0]
-	dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_range_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute min, 11 = absolute max.
-	imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note]</description>
-	<operation>
-DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) {
-	CASE opCtl[1:0] OF
-	0: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src1[31:0] : src2[31:0]
-	1: tmp[31:0] := (src1[31:0] &lt;= src2[31:0]) ? src2[31:0] : src1[31:0]
-	2: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src1[31:0] : src2[31:0]
-	3: tmp[31:0] := (ABS(src1[31:0]) &lt;= ABS(src2[31:0])) ? src2[31:0] : src1[31:0]
-	ESAC
-	
-	CASE signSelCtl[1:0] OF
-	0: dst[31:0] := (src1[31] &lt;&lt; 31) OR (tmp[30:0])
-	1: dst[31:0] := tmp[31:0]
-	2: dst[31:0] := (0 &lt;&lt; 31) OR (tmp[30:0])
-	3: dst[31:0] := (1 &lt;&lt; 31) OR (tmp[30:0])
-	ESAC
-	
-	RETURN dst
-}
-dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VRANGESS" xed="VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_reduce_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}, imm8" name="VREDUCEPD" xed="VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_reduce_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}, imm8" name="VREDUCEPS" xed="VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-IF k[0]
-	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-IF k[0]
-	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-IF k[0]
-	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-IF k[0]
-	dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	tmp[63:0] := src1[63:0] - tmp[63:0]
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := FP64(0.0)
-	FI
-	RETURN tmp[63:0]
-}
-dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VREDUCESD" xed="VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-IF k[0]
-	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-IF k[0]
-	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-IF k[0]
-	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-IF k[0]
-	dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	tmp[31:0] := src1[31:0] - tmp[31:0]
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := FP32(0.0)
-	FI
-	RETURN tmp[31:0]
-}
-dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VREDUCESS" xed="VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTPD2QQ" xed="VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTPD2UQQ" xed="VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {er}" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	 [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {er}" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {er}" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTPS2QQ" xed="VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {er}" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {er}" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {er}" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTPS2UQQ" xed="VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTQQ2PD" xed="VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {er}" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {er}" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {er}" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTQQ2PS" xed="VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttpd_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTTPD2QQ" xed="VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttpd_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTTPD2UQQ" xed="VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {sae}" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {sae}" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {sae}" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttps_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTTPS2QQ" xed="VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {sae}" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {sae}" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {sae}" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttps_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTTPS2UQQ" xed="VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu64_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTUQQ2PD" xed="VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {er}" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {er}" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {er}" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu64_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTUQQ2PS" xed="VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := a[i+63:i] * b[i+63:i]
-		dst[i+63:i] := tmp[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULLQ" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := a[i+63:i] * b[i+63:i]
-		dst[i+63:i] := tmp[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULLQ" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mullo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	tmp[127:0] := a[i+63:i] * b[i+63:i]
-	dst[i+63:i] := tmp[63:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULLQ" xed="VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_kadd_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Add 8-bit masks in "a" and "b", and store the result in "k".</description>
-	<operation>
-k[7:0] := a[7:0] + b[7:0]
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, k, k" name="KADDB" xed="KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kadd_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Add 16-bit masks in "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := a[15:0] + b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KADDW" xed="KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kand_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[7:0] := a[7:0] AND b[7:0]
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDB" xed="KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kandn_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise NOT of 8-bit masks "a" and then AND with "b", and store the result in "k".</description>
-	<operation>
-k[7:0] := (NOT a[7:0]) AND b[7:0]
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDNB" xed="KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_knot_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<description>Compute the bitwise NOT of 8-bit mask "a", and store the result in "k".</description>
-	<operation>
-k[7:0] := NOT a[7:0]
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, k" name="KNOTB" xed="KNOTB_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kor_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise OR of 8-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[7:0] := a[7:0] OR b[7:0]
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, k, k" name="KORB" xed="KORB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kxnor_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise XNOR of 8-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[7:0] := NOT (a[7:0] XOR b[7:0])
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXNORB" xed="KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kxor_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise XOR of 8-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[7:0] := a[7:0] XOR b[7:0]
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXORB" xed="KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kshiftli_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
-	<description>Shift the bits of 8-bit mask "a" left by "count" while shifting in zeros, and store the least significant 8 bits of the result in "k".</description>
-	<operation>
-k[MAX:0] := 0
-IF count[7:0] &lt;= 7
-	k[7:0] := a[7:0] &lt;&lt; count[7:0]
-FI
-	</operation>
-	<instruction form="k, k, imm8" name="KSHIFTLB" xed="KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kshiftri_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
-	<description>Shift the bits of 8-bit mask "a" right by "count" while shifting in zeros, and store the least significant 8 bits of the result in "k".</description>
-	<operation>
-k[MAX:0] := 0
-IF count[7:0] &lt;= 7
-	k[7:0] := a[7:0] &gt;&gt; count[7:0]
-FI
-	</operation>
-	<instruction form="k, k, imm8" name="KSHIFTRB" xed="KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortest_mask8_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="all_ones" />
-	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
-	<operation>
-tmp[7:0] := a[7:0] OR b[7:0]
-IF tmp[7:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-IF tmp[7:0] == 0xFF
-	MEM[all_ones+7:all_ones] := 1
-ELSE
-	MEM[all_ones+7:all_ones] := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTB" xed="KORTESTB_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortestz_mask8_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[7:0] := a[7:0] OR b[7:0]
-IF tmp[7:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTB" xed="KORTESTB_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortestc_mask8_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[7:0] := a[7:0] OR b[7:0]
-IF tmp[7:0] == 0xFF
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTB" xed="KORTESTB_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktest_mask8_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="and_not" />
-	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
-	<operation>
-tmp1[7:0] := a[7:0] AND b[7:0]
-IF tmp1[7:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-tmp2[7:0] := (NOT a[7:0]) AND b[7:0]
-IF tmp2[7:0] == 0x0
-	MEM[and_not+7:and_not] := 1
-ELSE
-	MEM[and_not+7:and_not] := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTB" xed="KTESTB_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktestz_mask8_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise AND of 8-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[7:0] := a[7:0] AND b[7:0]
-IF tmp[7:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTB" xed="KTESTB_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktestc_mask8_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="b" />
-	<description>Compute the bitwise NOT of 8-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[7:0] := (NOT a[7:0]) AND b[7:0]
-IF tmp[7:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTB" xed="KTESTB_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktest_mask16_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="and_not" />
-	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not".</description>
-	<operation>
-tmp1[15:0] := a[15:0] AND b[15:0]
-IF tmp1[15:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-tmp2[15:0] := (NOT a[15:0]) AND b[15:0]
-IF tmp2[15:0] == 0x0
-	MEM[and_not+7:and_not] := 1
-ELSE
-	MEM[and_not+7:and_not] := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTW" xed="KTESTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktestz_mask16_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[15:0] := a[15:0] AND b[15:0]
-IF tmp[15:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTW" xed="KTESTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_ktestc_mask16_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise NOT of 16-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[15:0] := (NOT a[15:0]) AND b[15:0]
-IF tmp[15:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KTESTW" xed="KTESTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_cvtmask8_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<description>Convert 8-bit mask "a" into an integer value, and store the result in "dst".</description>
-	<operation>
-dst := ZeroExtend32(a[7:0])
-	</operation>
-	<instruction form="r32, k" name="KMOVB" xed="KMOVB_GPR32u32_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_cvtu32_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="unsigned int" varname="a" />
-	<description>Convert integer value "a" into an 8-bit mask, and store the result in "k".</description>
-	<operation>
-k := a[7:0]
-	</operation>
-	<instruction form="k, r32" name="KMOVB" xed="KMOVB_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_load_mask8" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="mem_addr" />
-	<description>Load 8-bit mask from memory into "k".</description>
-	<operation>
-k[7:0] := MEM[mem_addr+7:mem_addr]
-	</operation>
-	<instruction form="k, m8" name="KMOVB" xed="KMOVB_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_store_mask8" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="a" />
-	<description>Store 8-bit mask from "a" into memory.</description>
-	<operation>
-MEM[mem_addr+7:mem_addr] := a[7:0]
-	</operation>
-	<instruction form="m8, k" name="KMOVB" xed="KMOVB_MEMu8_MASKmskw_AVX512" />
-	<CPUID>AVX512DQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_acos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ACOS(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_acos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ACOS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_acos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ACOS(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_acos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ACOS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_acosh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ACOSH(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_acosh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ACOSH(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_acosh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ACOSH(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_acosh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ACOSH(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_asin_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ASIN(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_asin_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ASIN(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_asin_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ASIN(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_asin_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ASIN(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_asinh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ASINH(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_asinh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ASINH(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_asinh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ASINH(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_asinh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ASINH(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_atan2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_atan2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_atan2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_atan2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_atan_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ATAN(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_atan_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ATAN(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_atan_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ATAN(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_atan_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ATAN(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_atanh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ATANH(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_atanh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ATANH(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_atanh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse hyperblic tangent of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ATANH(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_atanh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ATANH(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := COS(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := COS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := COS(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := COS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cosd_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := COSD(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cosd_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := COSD(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cosd_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := COSD(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cosd_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := COSD(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cosh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := COSH(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cosh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := COSH(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cosh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := COSH(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cosh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := COSH(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sin_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SIN(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sin_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SIN(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sin_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SIN(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sin_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SIN(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sinh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SINH(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sinh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SINH(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sinh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SINH(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sinh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SINH(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sind_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SIND(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sind_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SIND(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sind_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SIND(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sind_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SIND(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_tan_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := TAN(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_tan_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := TAN(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_tan_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := TAN(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_tan_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := TAN(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_tand_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := TAND(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_tand_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := TAND(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_tand_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := TAND(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_tand_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := TAND(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_tanh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := TANH(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_tanh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := TANH(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_tanh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := TANH(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_tanh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := TANH(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sincos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" memwidth="512" type="__m512d *" varname="mem_addr" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SIN(a[i+63:i])
-	MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-cos_res[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sincos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" memwidth="512" type="__m512d *" varname="mem_addr" />
-	<parameter etype="FP64" type="__m512d" varname="sin_src" />
-	<parameter etype="FP64" type="__m512d" varname="cos_src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", store the cosine into memory at "mem_addr". Elements are written to their respective locations using writemask "k" (elements are copied from "sin_src" or "cos_src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SIN(a[i+63:i])
-		MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := sin_src[i+63:i]
-		MEM[mem_addr+i+63:mem_addr+i] := cos_src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-cos_res[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sincos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" memwidth="512" type="__m512 *" varname="mem_addr" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SIN(a[i+31:i])
-	MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-cos_res[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sincos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" memwidth="512" type="__m512 *" varname="mem_addr" />
-	<parameter etype="FP32" type="__m512" varname="sin_src" />
-	<parameter etype="FP32" type="__m512" varname="cos_src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", store the cosine into memory at "mem_addr". Elements are written to their respective locations using writemask "k" (elements are copied from "sin_src" or "cos_src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SIN(a[i+31:i])
-		MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := sin_src[i+31:i]
-		MEM[mem_addr+i+31:mem_addr+i] := cos_src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-cos_res[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cbrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := CubeRoot(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cbrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := CubeRoot(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cbrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := CubeRoot(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cbrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := CubeRoot(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_exp10_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := POW(10.0, a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_exp10_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POW(10.0, a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_exp10_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_exp10_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_exp2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := POW(2.0, a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_exp2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POW(2.0, a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_exp2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_exp2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_exp_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := POW(e, a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_exp_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POW(e, a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_exp_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := POW(FP32(e), a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_exp_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POW(FP32(e), a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_expm1_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expm1_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_expm1_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expm1_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_hypot_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_hypot_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_hypot_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_hypot_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_invsqrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := InvSQRT(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_invsqrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := InvSQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_invsqrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := InvSQRT(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_invsqrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := InvSQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_log10_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_log10_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_log10_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_log10_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_log1p_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := LOG(1.0 + a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_log1p_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LOG(1.0 + a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_log1p_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := LOG(1.0 + a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_log1p_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LOG(1.0 + a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_log2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_log2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_log_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_log_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LOG(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_log_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_log_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LOG(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_logb_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_logb_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_logb_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_logb_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_pow_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_pow_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_pow_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_pow_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_recip_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Computes the reciprocal of packed double-precision (64-bit) floating-point elements in "a", storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := (1.0 / a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_recip_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Computes the reciprocal of packed double-precision (64-bit) floating-point elements in "a", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_recip_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Computes the reciprocal of packed single-precision (32-bit) floating-point elements in "a", storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (1.0 / a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_recip_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Computes the reciprocal of packed single-precision (32-bit) floating-point elements in "a", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cdfnorm_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := CDFNormal(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cdfnorm_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := CDFNormal(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cdfnorm_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := CDFNormal(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cdfnorm_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := CDFNormal(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cdfnorminv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := InverseCDFNormal(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cdfnorminv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := InverseCDFNormal(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cdfnorminv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := InverseCDFNormal(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cdfnorminv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := InverseCDFNormal(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_erf_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ERF(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_erf_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ERF(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_erfc_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := 1.0 - ERF(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_erfc_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := 1.0 - ERF(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_erf_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ERF(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_erf_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ERF(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_erfc_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+63:i] := 1.0 - ERF(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_erfc_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+63:i] := 1.0 - ERF(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_erfinv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := 1.0 / ERF(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_erfinv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := 1.0 / ERF(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_erfinv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+63:i] := 1.0 / ERF(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_erfinv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+63:i] := 1.0 / ERF(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_erfcinv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_erfcinv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_erfcinv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_erfcinv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm512_ceil_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := CEIL(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_ceil_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := CEIL(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_ceil_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := CEIL(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_ceil_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := CEIL(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_floor_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := FLOOR(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_floor_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FLOOR(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_floor_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := FLOOR(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_floor_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FLOOR(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_nearbyint_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Rounds each packed double-precision (64-bit) floating-point element in "a" to the nearest integer value and stores the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := NearbyInt(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_nearbyint_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Rounds each packed double-precision (64-bit) floating-point element in "a" to the nearest integer value and stores the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := NearbyInt(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_nearbyint_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Rounds each packed single-precision (32-bit) floating-point element in "a" to the nearest integer value and stores the results as packed single-precision floating-point elements in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := NearbyInt(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_nearbyint_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Rounds each packed single-precision (32-bit) floating-point element in "a" to the nearest integer value and stores the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := NearbyInt(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rint_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Rounds the packed double-precision (64-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := RoundToNearestEven(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rint_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Rounds the packed double-precision (64-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundToNearestEven(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rint_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Rounds the packed single-precision (32-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := RoundToNearestEven(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rint_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Rounds the packed single-precision (32-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundToNearestEven(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_svml_round_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ROUND(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_svml_round_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ROUND(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i] 
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_trunc_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := TRUNCATE(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_trunc_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := TRUNCATE(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_trunc_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := TRUNCATE(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_trunc_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := TRUNCATE(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF b[i+31:i] == 0
-		#DE
-	FI
-	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_div_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		IF b[i+31:i] == 0
-			#DE
-		FI
-		dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_epi8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := 8*j
-	IF b[i+7:i] == 0
-		#DE
-	FI
-	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_epi16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	IF b[i+15:i] == 0
-		#DE
-	FI
-	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_epi64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	IF b[i+63:i] == 0
-		#DE
-	FI
-	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rem_epi8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 63
-	i := 8*j
-	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rem_epi16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 31
-	i := 16*j
-	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rem_epi64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 64*j
-	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_epu32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF b[i+31:i] == 0
-		#DE
-	FI
-	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_div_epu32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		IF b[i+31:i] == 0
-			#DE
-		FI
-		dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_epu8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := 8*j
-	IF b[i+7:i] == 0
-		#DE
-	FI
-	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_epu16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := 16*j
-	IF b[i+15:i] == 0
-		#DE
-	FI
-	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_epu64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	IF b[i+63:i] == 0
-		#DE
-	FI
-	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rem_epu32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rem_epu32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rem_epu8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 63
-	i := 8*j
-	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rem_epu16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 31
-	i := 16*j
-	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rem_epu64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 64*j
-	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_log2_ps" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VLOG2PS" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_log2_ps" tech="SVML">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VLOG2PS" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_mask_add_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VADDPD" xed="VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_add_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VADDPD" xed="VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VADDPD" xed="VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VADDPD" xed="VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_add_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VADDPS" xed="VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_add_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VADDPS" xed="VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VADDPS" xed="VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VADDPS" xed="VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_div_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] / b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VDIVPD" xed="VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_div_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] / b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VDIVPD" xed="VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] / b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VDIVPD" xed="VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] / b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VDIVPD" xed="VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_div_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] / b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VDIVPS" xed="VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_div_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] / b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VDIVPS" xed="VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] / b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VDIVPS" xed="VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] / b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VDIVPS" xed="VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PD" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PD" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PD" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PD" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PD" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PD" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD132PD" xed="VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD213PD" xed="VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD231PD" xed="VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PD" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PD" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PD" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PD" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PD" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PD" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132PD" xed="VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213PD" xed="VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231PD" xed="VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PS" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PS" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PS" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PS" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PS" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PS" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD132PS" xed="VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD213PS" xed="VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD231PS" xed="VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PS" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PS" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PS" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PS" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PS" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PS" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132PS" xed="VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213PS" xed="VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231PS" xed="VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PD" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PD" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PD" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PD" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PD" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PD" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB132PD" xed="VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB213PD" xed="VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB231PD" xed="VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PD" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PD" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PD" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PD" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PD" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PD" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132PD" xed="VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213PD" xed="VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231PD" xed="VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PS" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PS" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PS" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PS" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PS" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PS" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB132PS" xed="VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB213PS" xed="VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB231PS" xed="VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PS" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PS" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PS" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PS" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PS" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PS" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132PS" xed="VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213PS" xed="VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231PS" xed="VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1 
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0) 
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PD" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PD" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PD" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PD" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PD" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PD" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD132PD" xed="VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD213PD" xed="VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD231PD" xed="VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PD" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PD" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PD" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PD" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PD" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PD" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132PD" xed="VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213PD" xed="VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231PD" xed="VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PS" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PS" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PS" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PS" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PS" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PS" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD132PS" xed="VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD213PS" xed="VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD231PS" xed="VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PS" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PS" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PS" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PS" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PS" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PS" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132PS" xed="VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213PS" xed="VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231PS" xed="VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PD" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PD" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PD" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PD" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PD" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PD" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB132PD" xed="VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB213PD" xed="VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB231PD" xed="VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PS" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PS" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PS" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PS" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PS" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PS" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB132PS" xed="VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB213PS" xed="VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB231PS" xed="VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMAXPD" xed="VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMAXPD" xed="VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMAXPD" xed="VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMAXPD" xed="VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMAXPS" xed="VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMAXPS" xed="VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMAXPS" xed="VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMAXPS" xed="VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMINPD" xed="VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMINPD" xed="VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMINPD" xed="VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMINPD" xed="VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMINPS" xed="VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMINPS" xed="VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMINPS" xed="VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMINPS" xed="VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mul_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMULPD" xed="VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mul_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMULPD" xed="VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMULPD" xed="VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMULPD" xed="VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mul_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  RM.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMULPS" xed="VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mul_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMULPS" xed="VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMULPS" xed="VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMULPS" xed="VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_abs_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ABS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPABSD" xed="VPABSD_YMMi32_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_abs_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ABS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPABSD" xed="VPABSD_YMMi32_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_abs_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ABS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPABSD" xed="VPABSD_XMMi32_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_abs_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ABS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPABSD" xed="VPABSD_XMMi32_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ABS(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPABSQ" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ABS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPABSQ" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ABS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPABSQ" xed="VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ABS(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPABSQ" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ABS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPABSQ" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ABS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPABSQ" xed="VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_add_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPADDD" xed="VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_add_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPADDD" xed="VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPADDD" xed="VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPADDD" xed="VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_add_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPADDQ" xed="VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_add_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] :=0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPADDQ" xed="VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPADDQ" xed="VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPADDQ" xed="VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMAXSD" xed="VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMAXSD" xed="VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMAXSD" xed="VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMAXSD" xed="VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMAXSQ" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMAXSQ" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMAXSQ" xed="VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMAXSQ" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMAXSQ" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPMAXSQ" xed="VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMAXUD" xed="VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMAXUD" xed="VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMAXUD" xed="VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMAXUD" xed="VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMAXUQ" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMAXUQ" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMAXUQ" xed="VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMAXUQ" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMAXUQ" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPMAXUQ" xed="VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMINSD" xed="VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMINSD" xed="VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMINSD" xed="VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMINSD" xed="VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMINSQ" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMINSQ" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMINSQ" xed="VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMINSQ" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMINSQ" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPMINSQ" xed="VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMINUD" xed="VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMINUD" xed="VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMINUD" xed="VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMINUD" xed="VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMINUQ" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMINUQ" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMINUQ" xed="VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMINUQ" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMINUQ" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPMINUQ" xed="VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mul_epi32" tech="AVX-512">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULDQ" xed="VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mul_epi32" tech="AVX-512">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULDQ" xed="VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_epi32" tech="AVX-512">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULDQ" xed="VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_epi32" tech="AVX-512">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULDQ" xed="VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mullo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		tmp[63:0] := a[i+31:i] * b[i+31:i]
-		dst[i+31:i] := tmp[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULLD" xed="VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mullo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		tmp[63:0] := a[i+31:i] * b[i+31:i]
-		dst[i+31:i] := tmp[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULLD" xed="VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mullo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		tmp[63:0] := a[i+31:i] * b[i+31:i]
-		dst[i+31:i] := tmp[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULLD" xed="VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mullo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		tmp[63:0] := a[i+31:i] * b[i+31:i]
-		dst[i+31:i] := tmp[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULLD" xed="VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mul_epu32" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULUDQ" xed="VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mul_epu32" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULUDQ" xed="VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_epu32" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULUDQ" xed="VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_epu32" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULUDQ" xed="VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sub_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSUBD" xed="VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sub_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSUBD" xed="VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSUBD" xed="VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSUBD" xed="VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sub_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSUBQ" xed="VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sub_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSUBQ" xed="VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSUBQ" xed="VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSUBQ" xed="VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VRCP14PD" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VRCP14PD" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := (1.0 / a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VRCP14PD" xed="VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VRCP14PD" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VRCP14PD" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (1.0 / a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VRCP14PD" xed="VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VRCP14PS" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VRCP14PS" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := (1.0 / a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VRCP14PS" xed="VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VRCP14PS" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VRCP14PS" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (1.0 / a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VRCP14PS" xed="VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VRSQRT14PD" xed="VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VRSQRT14PD" xed="VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VRSQRT14PD" xed="VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VRSQRT14PD" xed="VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VRSQRT14PD" xed="VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VRSQRT14PD" xed="VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VRSQRT14PS" xed="VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VRSQRT14PS" xed="VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VRSQRT14PS" xed="VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VRSQRT14PS" xed="VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VRSQRT14PS" xed="VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VRSQRT14PS" xed="VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VSUBPD" xed="VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VSUBPD" xed="VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSUBPD" xed="VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSUBPD" xed="VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VSUBPS" xed="VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VSUBPS" xed="VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSUBPS" xed="VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSUBPS" xed="VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst".</description>
-	<operation>
-temp[511:256] := a[255:0]
-temp[255:0] := b[255:0]
-temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
-dst[255:0] := temp[255:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VALIGND" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-temp[511:256] := a[255:0]
-temp[255:0] := b[255:0]
-temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := temp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VALIGND" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-temp[511:256] := a[255:0]
-temp[255:0] := b[255:0]
-temp[511:0] := temp[511:0] &gt;&gt; (32*imm8[2:0])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := temp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VALIGND" xed="VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst".</description>
-	<operation>
-temp[255:128] := a[127:0]
-temp[127:0] := b[127:0]
-temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
-dst[127:0] := temp[127:0]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VALIGND" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-temp[255:128] := a[127:0]
-temp[127:0] := b[127:0]
-temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := temp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VALIGND" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-temp[255:128] := a[127:0]
-temp[127:0] := b[127:0]
-temp[255:0] := temp[255:0] &gt;&gt; (32*imm8[1:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := temp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VALIGND" xed="VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst".</description>
-	<operation>
-temp[511:256] := a[255:0]
-temp[255:0] := b[255:0]
-temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
-dst[255:0] := temp[255:0]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VALIGNQ" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-temp[511:256] := a[255:0]
-temp[255:0] := b[255:0]
-temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := temp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VALIGNQ" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-temp[511:256] := a[255:0]
-temp[255:0] := b[255:0]
-temp[511:0] := temp[511:0] &gt;&gt; (64*imm8[1:0])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := temp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VALIGNQ" xed="VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst".</description>
-	<operation>
-temp[255:128] := a[127:0]
-temp[127:0] := b[127:0]
-temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
-dst[127:0] := temp[127:0]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VALIGNQ" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-temp[255:128] := a[127:0]
-temp[127:0] := b[127:0]
-temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := temp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VALIGNQ" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-temp[255:128] := a[127:0]
-temp[127:0] := b[127:0]
-temp[255:0] := temp[255:0] &gt;&gt; (64*imm8[0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := temp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VALIGNQ" xed="VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_blend_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VBLENDMPD" xed="VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_blend_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VBLENDMPD" xed="VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_blend_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VBLENDMPS" xed="VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_blend_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VBLENDMPS" xed="VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_f32x4" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 4)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcast_f32x4" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 4)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcast_f32x4" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 4)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_broadcast_i32x4" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 4)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcast_i32x4" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 4)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcast_i32x4" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := (j % 4)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcastsd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcastsd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcastss_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcastss_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_broadcastss_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_broadcastss_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compress_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := src[255:m]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCOMPRESSPD" xed="VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_compress_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCOMPRESSPD" xed="VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compress_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := src[127:m]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_compress_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compress_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := src[255:m]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCOMPRESSPS" xed="VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_compress_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCOMPRESSPS" xed="VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compress_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := src[127:m]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_compress_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expand_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VEXPANDPD" xed="VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expand_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VEXPANDPD" xed="VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expand_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VEXPANDPD" xed="VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expand_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm " name="VEXPANDPD" xed="VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expand_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VEXPANDPS" xed="VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expand_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VEXPANDPS" xed="VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expand_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VEXPANDPS" xed="VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expand_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VEXPANDPS" xed="VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extractf32x4_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_extractf32x4_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_extractf32x4_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_extracti32x4_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_extracti32x4_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_extracti32x4_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN: j := 0
-	SNAN_TOKEN: j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VGETEXPPD" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VGETEXPPD" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VGETEXPPD" xed="VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VGETEXPPD" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VGETEXPPD" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VGETEXPPD" xed="VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VGETEXPPS" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VGETEXPPS" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VGETEXPPS" xed="VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VGETEXPPS" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VGETEXPPS" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VGETEXPPS" xed="VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VGETMANTPD" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VGETMANTPD" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VGETMANTPD" xed="VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VGETMANTPS" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VGETMANTPS" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VGETMANTPS" xed="VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_insertf32x4" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_insertf32x4" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_insertf32x4" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_inserti32x4" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_inserti32x4" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_inserti32x4" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[255:0] := a[255:0]
-CASE (imm8[0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_blend_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMD" xed="VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_blend_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMD" xed="VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_blend_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMQ" xed="VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_blend_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMQ" xed="VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcastd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcastd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_broadcastd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_broadcastd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_broadcastq_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_broadcastq_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_broadcastq_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_broadcastq_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compress_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := src[255:m]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPCOMPRESSD" xed="VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_compress_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPCOMPRESSD" xed="VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compress_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := src[127:m]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_compress_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compress_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := src[255:m]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_compress_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compress_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := src[127:m]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_compress_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutexvar_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	id := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMD" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutexvar_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	id := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMD" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutexvar_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	id := idx[i+2:i]*32
-	dst[i+31:i] := a[id+31:id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMD" xed="VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask2_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	off := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := idx[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2D" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	off := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2D" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	off := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := (idx[i+3]) ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2D" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2D" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	off := idx[i+2:i]*32
-	dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMI2D" xed="VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VPERMT2D" xed="VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask2_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	off := idx[i+1:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := idx[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2D" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="idx" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	off := idx[i+1:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2D" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="idx" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	off := idx[i+1:i]*32
-	IF k[j]
-		dst[i+31:i] := (idx[i+2]) ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2D" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2D" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="idx" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	off := idx[i+1:i]*32
-	dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMI2D" xed="VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VPERMT2D" xed="VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask2_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	off := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := idx[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2PD" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	off := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2PD" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	off := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := (idx[i+2]) ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2PD" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2PD" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	off := idx[i+1:i]*64
-	dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMI2PD" xed="VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VPERMT2PD" xed="VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask2_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set)</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	off := idx[i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := idx[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2PD" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="idx" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	off := idx[i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2PD" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="idx" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	off := idx[i]*64
-	IF k[j]
-		dst[i+63:i] := (idx[i+1]) ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2PD" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2PD" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="idx" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	off := idx[i]*64
-	dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMI2PD" xed="VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VPERMT2PD" xed="VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask2_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	off := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := idx[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2PS" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	off := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2PS" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	off := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := (idx[i+3]) ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2PS" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2PS" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	off := idx[i+2:i]*32
-	dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMI2PS" xed="VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VPERMT2PS" xed="VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask2_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	off := idx[i+1:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := idx[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2PS" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="idx" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	off := idx[i+1:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2PS" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="idx" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	off := idx[i+1:i]*32
-	IF k[j]
-		dst[i+31:i] := (idx[i+2]) ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2PS" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2PS" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="idx" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	off := idx[i+1:i]*32
-	dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMI2PS" xed="VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VPERMT2PS" xed="VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask2_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	off := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := idx[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2Q" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	off := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2Q" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	off := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := (idx[i+2]) ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2Q" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2Q" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	off := idx[i+1:i]*64
-	dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMI2Q" xed="VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VPERMT2Q" xed="VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask2_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	off := idx[i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := idx[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2Q" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="idx" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	off := idx[i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2Q" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="idx" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	off := idx[i]*64
-	IF k[j]
-		dst[i+63:i] := (idx[i+1]) ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2Q" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2Q" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="idx" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	off := idx[i]*64
-	dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMI2Q" xed="VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VPERMT2Q" xed="VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permute_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
-IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
-IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
-IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
-IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPERMILPD" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutevar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
-IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
-IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
-IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
-IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMILPD" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permute_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
-IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
-IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
-IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
-IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPERMILPD" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutevar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
-IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
-IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
-IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
-IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMILPD" xed="VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permute_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPERMILPD" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutevar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMILPD" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permute_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPERMILPD" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutevar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMILPD" xed="VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permute_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPERMILPS" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutevar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
-tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
-tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
-tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
-tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
-tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
-tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMILPS" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permute_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPERMILPS" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutevar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
-tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
-tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
-tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
-tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
-tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
-tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMILPS" xed="VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permute_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPERMILPS" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutevar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
-tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
-tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMILPS" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permute_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPERMILPS" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutevar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
-tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
-tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMILPS" xed="VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutex_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutexvar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	id := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := a[id+63:id]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutex_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutexvar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	id := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := a[id+63:id]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutexvar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	id := idx[i+1:i]*64
-	dst[i+63:i] := a[id+63:id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMPD" xed="VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutexvar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	id := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMPS" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutexvar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	id := idx[i+2:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMPS" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutexvar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="idx" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	id := idx[i+2:i]*32
-	dst[i+31:i] := a[id+31:id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMPS" xed="VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutex_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 64-bit integers in "a" across lanes lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutexvar_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	id := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := a[id+63:id]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutex_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutexvar_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	id := idx[i+1:i]*64
-	IF k[j]
-		dst[i+63:i] := a[id+63:id]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutexvar_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="idx" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	id := idx[i+1:i]*64
-	dst[i+63:i] := a[id+63:id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMQ" xed="VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expand_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPEXPANDD" xed="VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expand_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPEXPANDD" xed="VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expand_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPEXPANDD" xed="VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expand_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPEXPANDD" xed="VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expand_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPEXPANDQ" xed="VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expand_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPEXPANDQ" xed="VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expand_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPEXPANDQ" xed="VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expand_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPEXPANDQ" xed="VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shuffle_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSHUFD" xed="VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shuffle_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSHUFD" xed="VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shuffle_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSHUFD" xed="VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shuffle_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSHUFD" xed="VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpackhi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpackhi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpackhi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpackhi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpackhi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpackhi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpackhi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpackhi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpacklo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpacklo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpacklo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpacklo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpacklo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpacklo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpacklo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpacklo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VSCALEFPD" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VSCALEFPD" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VSCALEFPD" xed="VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFPD" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFPD" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSCALEFPD" xed="VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VSCALEFPS" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VSCALEFPS" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VSCALEFPS" xed="VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFPS" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFPS" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSCALEFPS" xed="VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shuffle_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst.m128[0] := a.m128[imm8[0]]
-tmp_dst.m128[1] := b.m128[imm8[1]]
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shuffle_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst.m128[0] := a.m128[imm8[0]]
-tmp_dst.m128[1] := b.m128[imm8[1]]
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shuffle_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst.m128[0] := a.m128[imm8[0]]
-dst.m128[1] := b.m128[imm8[1]]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shuffle_f64x2" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst.m128[0] := a.m128[imm8[0]]
-tmp_dst.m128[1] := b.m128[imm8[1]]
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shuffle_f64x2" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst.m128[0] := a.m128[imm8[0]]
-tmp_dst.m128[1] := b.m128[imm8[1]]
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shuffle_f64x2" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst.m128[0] := a.m128[imm8[0]]
-dst.m128[1] := b.m128[imm8[1]]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shuffle_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst.m128[0] := a.m128[imm8[0]]
-tmp_dst.m128[1] := b.m128[imm8[1]]
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shuffle_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst.m128[0] := a.m128[imm8[0]]
-tmp_dst.m128[1] := b.m128[imm8[1]]
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shuffle_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst.m128[0] := a.m128[imm8[0]]
-dst.m128[1] := b.m128[imm8[1]]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shuffle_i64x2" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst.m128[0] := a.m128[imm8[0]]
-tmp_dst.m128[1] := b.m128[imm8[1]]
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shuffle_i64x2" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst.m128[0] := a.m128[imm8[0]]
-tmp_dst.m128[1] := b.m128[imm8[1]]
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shuffle_i64x2" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst.m128[0] := a.m128[imm8[0]]
-dst.m128[1] := b.m128[imm8[1]]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shuffle_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
-tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFPD" xed="VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shuffle_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
-tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFPD" xed="VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shuffle_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VSHUFPD" xed="VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shuffle_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VSHUFPD" xed="VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shuffle_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VSHUFPS" xed="VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shuffle_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VSHUFPS" xed="VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shuffle_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VSHUFPS" xed="VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shuffle_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VSHUFPS" xed="VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpackhi_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VUNPCKHPD" xed="VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpackhi_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VUNPCKHPD" xed="VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpackhi_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VUNPCKHPD" xed="VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpackhi_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VUNPCKHPD" xed="VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpackhi_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VUNPCKHPS" xed="VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpackhi_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VUNPCKHPS" xed="VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpackhi_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VUNPCKHPS" xed="VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpackhi_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VUNPCKHPS" xed="VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpacklo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VUNPCKLPD" xed="VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpacklo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VUNPCKLPD" xed="VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpacklo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VUNPCKLPD" xed="VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpacklo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VUNPCKLPD" xed="VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_unpacklo_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VUNPCKLPS" xed="VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_unpacklo_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VUNPCKLPS" xed="VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_unpacklo_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VUNPCKLPS" xed="VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_unpacklo_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VUNPCKLPS" xed="VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpge_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmple_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmplt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpneq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpeq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpge_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpgt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmple_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmplt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpneq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="SI32" type="__m256i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpeq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpge_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpgt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmple_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmplt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpneq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpge_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmple_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmplt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpneq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpeq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpge_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpgt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmple_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmplt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpneq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="SI64" type="__m256i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpeq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpge_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpgt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmple_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmplt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpneq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpge_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmple_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmplt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpneq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpeq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpge_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpgt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmple_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmplt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpneq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpeq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpge_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpgt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmple_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmplt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpneq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpeq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpge_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpgt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmple_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmplt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmpneq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpeq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpge_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpgt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmple_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmplt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmpneq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpeq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpge_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpgt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmple_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmplt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmpneq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_test_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_test_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_test_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_test_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_test_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_test_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_test_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_test_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_testn_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k1[j]
-		k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testn_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_testn_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k1[j]
-		k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_testn_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_testn_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k1[j]
-		k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_testn_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:4] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_testn_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k1[j]
-		k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_testn_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:2] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compressstoreu_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 64
-m := base_addr
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		MEM[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VCOMPRESSPD" xed="VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compressstoreu_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 64
-m := base_addr
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		MEM[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compressstoreu_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 32
-m := base_addr
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		MEM[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VCOMPRESSPS" xed="VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compressstoreu_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 32
-m := base_addr
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		MEM[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_store_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVAPD" xed="VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_store_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVAPD" xed="VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_store_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_store_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_store_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_store_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_store_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_store_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_storeu_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_storeu_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_storeu_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_storeu_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_storeu_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVUPD" xed="VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_storeu_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVUPD" xed="VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_storeu_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_storeu_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compressstoreu_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 32
-m := base_addr
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		MEM[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VPCOMPRESSD" xed="VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compressstoreu_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 32
-m := base_addr
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		MEM[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compressstoreu_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 64
-m := base_addr
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		MEM[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compressstoreu_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 64
-m := base_addr
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		MEM[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i32scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32y, ymm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i32scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32y {k}, ymm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_i32scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32x, xmm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i32scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32x {k}, xmm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i32scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32x, ymm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i32scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32x {k}, ymm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_i32scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32x, xmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i32scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32x {k}, xmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i64scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64y, xmm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i64scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64y {k}, xmm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_i64scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64x, xmm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i64scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64x {k}, xmm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i64scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64y, ymm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i64scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64y {k}, ymm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_i64scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64x, xmm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i64scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64x {k}, xmm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i32scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32x, ymm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i32scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32x {k}, ymm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_i32scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32x, xmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i32scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32x {k}, xmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i32scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32y, ymm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i32scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32y {k}, ymm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_i32scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32x, xmm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i32scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32x {k}, xmm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i64scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64y, ymm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i64scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64y {k}, ymm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_i64scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64x, xmm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i64scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64x {k}, xmm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_i64scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64y, xmm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_i64scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64y {k}, xmm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_i64scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64x, xmm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_i64scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64x {k}, xmm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Store 256-bits (composed of 4 packed 64-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Store 256-bits (composed of 8 packed 32-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Store 128-bits (composed of 2 packed 64-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Store 128-bits (composed of 4 packed 32-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_store_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Store 256-bits (composed of 4 packed 64-bit integers) from "a" into memory.
-		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_store_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="256" type="void*" varname="mem_addr" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Store 256-bits (composed of 8 packed 32-bit integers) from "a" into memory.
-		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Store 128-bits (composed of 2 packed 64-bit integers) from "a" into memory.
-		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Store 128-bits (composed of 4 packed 32-bit integers) from "a" into memory.
-		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	IF k[j]
-		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-	ELSE
-		dst[m+63:m] := src[m+63:m]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	IF k[j]
-		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-	ELSE
-		dst[m+63:m] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	IF k[j]
-		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-	ELSE
-		dst[m+63:m] := src[m+63:m]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	IF k[j]
-		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-	ELSE
-		dst[m+63:m] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTDQ2PD" xed="VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTDQ2PS" xed="VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTDQ2PS" xed="VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPD2PS" xed="VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTPS2DQ" xed="VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTPS2DQ" xed="VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvt_roundps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvt_roundps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvt_roundps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvt_roundps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_Int32_To_FP64(a[l+31:l])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_Int32_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := Truncate8(a[i+31:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, ymm" name="VPMOVDB" xed="VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := Truncate8(a[i+31:i])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVDB" xed="VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := Truncate16(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVDW" xed="VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := Truncate16(a[i+31:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVDW" xed="VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVDW" xed="VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := Truncate8(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, ymm" name="VPMOVQB" xed="VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := Truncate8(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="16" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m16 {k}, xmm" name="VPMOVQB" xed="VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := Truncate32(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Truncate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI32" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVQD" xed="VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Truncate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := Truncate32(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Truncate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI32" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVQD" xed="VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Truncate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVQD" xed="VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := Truncate16(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, ymm" name="VPMOVQW" xed="VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := Truncate16(a[i+63:i])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, xmm" name="VPMOVQW" xed="VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := Saturate8(a[i+31:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, ymm" name="VPMOVSDB" xed="VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := Saturate8(a[i+31:i])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, xmm" name="VPMOVSDB" xed="VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := Saturate16(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI16" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVSDW" xed="VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := Saturate16(a[i+31:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI16" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVSDW" xed="VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSDW" xed="VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := Saturate8(a[i+63:i])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, ymm" name="VPMOVSQB" xed="VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := Saturate8(a[i+63:i])
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="16" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m16 {k}, xmm" name="VPMOVSQB" xed="VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := Saturate32(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Saturate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI32" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVSQD" xed="VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Saturate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := Saturate32(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Saturate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI32" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVSQD" xed="VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Saturate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSQD" xed="VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := Saturate16(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtsepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI16" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, ymm" name="VPMOVSQW" xed="VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := Saturate16(a[i+63:i])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI16" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, xmm" name="VPMOVSQW" xed="VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi8_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi8_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi8_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi8_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi8_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi8_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi8_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi8_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi32_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi32_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi32_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi32_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSXDQ" xed="VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi16_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*16
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi16_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi16_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	l := j*16
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi16_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSXWD" xed="VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi16_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi16_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi16_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi16_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := SaturateU8(a[i+31:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, ymm" name="VPMOVUSDB" xed="VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := SaturateU8(a[i+31:i])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, xmm" name="VPMOVUSDB" xed="VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := SaturateU16(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVUSDW" xed="VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := SaturateU16(a[i+31:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVUSDW" xed="VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVUSDW" xed="VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := SaturateU8(a[i+63:i])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, ymm" name="VPMOVUSQB" xed="VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := SaturateU8(a[i+63:i])
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="16" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m16 {k}, xmm" name="VPMOVUSQB" xed="VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := SaturateU32(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := SaturateU32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI32" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, ymm" name="VPMOVUSQD" xed="VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := SaturateU32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := SaturateU32(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := SaturateU32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI32" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VPMOVUSQD" xed="VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := SaturateU32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVUSQD" xed="VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := SaturateU16(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtusepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, ymm" name="VPMOVUSQW" xed="VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := SaturateU16(a[i+63:i])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtusepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, xmm" name="VPMOVUSQW" xed="VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in th elow 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu8_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu8_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu8_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu8_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu32_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu32_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+31:l])
-	ELSE 
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu32_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu32_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+31:l])
-	ELSE 
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVZXDQ" xed="VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu16_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu16_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu16_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu16_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVZXWD" xed="VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu16_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu16_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu16_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu16_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expandloadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m256" name="VEXPANDPD" xed="VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expandloadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m256" name="VEXPANDPD" xed="VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expandloadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m128" name="VEXPANDPD" xed="VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expandloadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m128" name="VEXPANDPD" xed="VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expandloadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m256" name="VEXPANDPS" xed="VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expandloadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m256" name="VEXPANDPS" xed="VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expandloadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m128" name="VEXPANDPS" xed="VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expandloadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m128" name="VEXPANDPS" xed="VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mmask_i32gather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, vm32x" name="VGATHERDPD" xed="VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mmask_i32gather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, vm32x" name="VGATHERDPD" xed="VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mmask_i32gather_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="FP32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, vm32y" name="VGATHERDPS" xed="VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mmask_i32gather_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="FP32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, vm32x" name="VGATHERDPS" xed="VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mmask_i64gather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, vm64y" name="VGATHERQPD" xed="VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mmask_i64gather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, vm64x" name="VGATHERQPD" xed="VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mmask_i64gather_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="FP32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="ymm {k}, vm64y" name="VGATHERQPS" xed="VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mmask_i64gather_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="FP32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, vm64x" name="VGATHERQPS" xed="VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_load_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VMOVAPD" xed="VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_load_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m256" name="VMOVAPD" xed="VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_load_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m128" name="VMOVAPD" xed="VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_load_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m128" name="VMOVAPD" xed="VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_load_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m256" name="VMOVAPS" xed="VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_load_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m256" name="VMOVAPS" xed="VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_load_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m128" name="VMOVAPS" xed="VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_load_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m128" name="VMOVAPS" xed="VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m64" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m64" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VMOVDQU32" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m64" name="VMOVDQU32" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VMOVDQU32" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VMOVDQU32" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VMOVDQU64" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m64" name="VMOVDQU64" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VMOVDQU64" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VMOVDQU64" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_loadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VMOVUPD" xed="VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_loadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m64" name="VMOVUPD" xed="VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_loadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VMOVUPD" xed="VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_loadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VMOVUPD" xed="VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_loadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VMOVUPS" xed="VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_loadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m64" name="VMOVUPS" xed="VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_loadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VMOVUPS" xed="VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_loadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VMOVUPS" xed="VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expandloadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VPEXPANDD" xed="VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expandloadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m64" name="VPEXPANDD" xed="VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expandloadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VPEXPANDD" xed="VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expandloadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VPEXPANDD" xed="VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expandloadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expandloadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expandloadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expandloadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mmask_i32gather_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, vm32y" name="VPGATHERDD" xed="VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mmask_i32gather_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, vm32x" name="VPGATHERDD" xed="VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mmask_i32gather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, vm32x" name="VPGATHERDQ" xed="VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mmask_i32gather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, vm32x" name="VPGATHERDQ" xed="VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mmask_i64gather_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, vm64y" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mmask_i64gather_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, vm64x" name="VPGATHERQD" xed="VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mmask_i64gather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, vm64y" name="VPGATHERQQ" xed="VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mmask_i64gather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="const int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, vm64x" name="VPGATHERQQ" xed="VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits (composed of 4 packed 64-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVDQU64" xed="VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits (composed of 8 packed 32-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVDQU32" xed="VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 2 packed 64-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m128" name="VMOVDQU64" xed="VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 4 packed 32-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m128" name="VMOVDQU32" xed="VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits (composed of 4 packed 64-bit integers) from memory into "dst".
-		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits (composed of 8 packed 32-bit integers) from memory into "dst".
-		"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 2 packed 64-bit integers) from memory into "dst".
-		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m128" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 4 packed 32-bit integers) from memory into "dst".
-		"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m128" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mov_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVAPD" xed="VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mov_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVAPD" xed="VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mov_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVAPD" xed="VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mov_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVAPD" xed="VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mov_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVAPS" xed="VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mov_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVAPS" xed="VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mov_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVAPS" xed="VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mov_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVAPS" xed="VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_movedup_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[63:0] := a[63:0]
-tmp[127:64] := a[63:0]
-tmp[191:128] := a[191:128]
-tmp[255:192] := a[191:128]
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVDDUP" xed="VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_movedup_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[63:0] := a[63:0]
-tmp[127:64] := a[63:0]
-tmp[191:128] := a[191:128]
-tmp[255:192] := a[191:128]
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVDDUP" xed="VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_movedup_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[63:0] := a[63:0]
-tmp[127:64] := a[63:0]
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVDDUP" xed="VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_movedup_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[63:0] := a[63:0]
-tmp[127:64] := a[63:0]
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVDDUP" xed="VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mov_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mov_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVDQA32" xed="VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mov_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mov_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVDQA32" xed="VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mov_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mov_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVDQA64" xed="VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mov_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mov_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVDQA64" xed="VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_movehdup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[63:32] 
-tmp[63:32] := a[63:32] 
-tmp[95:64] := a[127:96] 
-tmp[127:96] := a[127:96]
-tmp[159:128] := a[191:160] 
-tmp[191:160] := a[191:160] 
-tmp[223:192] := a[255:224] 
-tmp[255:224] := a[255:224]
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVSHDUP" xed="VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_movehdup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[63:32] 
-tmp[63:32] := a[63:32] 
-tmp[95:64] := a[127:96] 
-tmp[127:96] := a[127:96]
-tmp[159:128] := a[191:160] 
-tmp[191:160] := a[191:160] 
-tmp[223:192] := a[255:224] 
-tmp[255:224] := a[255:224]
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVSHDUP" xed="VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_movehdup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[63:32] 
-tmp[63:32] := a[63:32] 
-tmp[95:64] := a[127:96] 
-tmp[127:96] := a[127:96]
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVSHDUP" xed="VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_movehdup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[63:32] 
-tmp[63:32] := a[63:32] 
-tmp[95:64] := a[127:96] 
-tmp[127:96] := a[127:96]
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVSHDUP" xed="VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_moveldup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[31:0] 
-tmp[63:32] := a[31:0] 
-tmp[95:64] := a[95:64] 
-tmp[127:96] := a[95:64]
-tmp[159:128] := a[159:128] 
-tmp[191:160] := a[159:128] 
-tmp[223:192] := a[223:192] 
-tmp[255:224] := a[223:192]
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VMOVSLDUP" xed="VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_moveldup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[31:0] 
-tmp[63:32] := a[31:0] 
-tmp[95:64] := a[95:64] 
-tmp[127:96] := a[95:64]
-tmp[159:128] := a[159:128] 
-tmp[191:160] := a[159:128] 
-tmp[223:192] := a[223:192] 
-tmp[255:224] := a[223:192]
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VMOVSLDUP" xed="VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_moveldup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[31:0] 
-tmp[63:32] := a[31:0] 
-tmp[95:64] := a[95:64] 
-tmp[127:96] := a[95:64]
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VMOVSLDUP" xed="VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_moveldup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[31:0] 
-tmp[63:32] := a[31:0] 
-tmp[95:64] := a[95:64] 
-tmp[127:96] := a[95:64]
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VMOVSLDUP" xed="VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_and_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPANDD" xed="VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_and_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPANDD" xed="VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_and_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPANDD" xed="VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_and_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPANDD" xed="VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_andnot_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPANDND" xed="VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_andnot_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPANDND" xed="VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_andnot_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPANDND" xed="VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_andnot_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPANDND" xed="VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_andnot_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPANDNQ" xed="VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_andnot_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPANDNQ" xed="VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_andnot_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPANDNQ" xed="VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_andnot_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPANDNQ" xed="VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_and_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPANDQ" xed="VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_and_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPANDQ" xed="VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_and_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPANDQ" xed="VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_and_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPANDQ" xed="VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPORD" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPORD" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPORD" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPORD" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPORQ" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPORQ" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPORQ" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPORQ" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		FOR h := 0 to 31
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		FOR h := 0 to 31
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 7
-	i := j*32
-	FOR h := 0 to 31
-		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		FOR h := 0 to 31
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		FOR h := 0 to 31
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 3
-	i := j*32
-	FOR h := 0 to 31
-		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		FOR h := 0 to 63
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		FOR h := 0 to 63
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 3
-	i := j*64
-	FOR h := 0 to 63
-		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		FOR h := 0 to 63
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		FOR h := 0 to 63
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 1
-	i := j*64
-	FOR h := 0 to 63
-		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPXORD" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPXORD" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPXORD" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPXORD" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPXORQ" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPXORQ" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPXORQ" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPXORQ" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPXORQ" xed="VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPXORD" xed="VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPXORQ" xed="VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPXORD" xed="VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPORQ" xed="VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPORD" xed="VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPORQ" xed="VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPORD" xed="VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_set1_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_set1_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_set1_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_set1_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_set1_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_set1_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_set1_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_set1_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPROLD" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPROLD" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPROLD" xed="VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPROLD" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPROLD" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VPROLD" xed="VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPROLQ" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPROLQ" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPROLQ" xed="VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPROLQ" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPROLQ" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VPROLQ" xed="VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPROLVD" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPROLVD" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPROLVD" xed="VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPROLVD" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPROLVD" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPROLVD" xed="VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPROLVQ" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPROLVQ" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPROLVQ" xed="VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPROLVQ" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPROLVQ" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPROLVQ" xed="VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPRORD" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPRORD" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPRORD" xed="VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPRORD" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPRORD" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VPRORD" xed="VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPRORQ" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPRORQ" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPRORQ" xed="VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPRORQ" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPRORQ" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VPRORQ" xed="VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPRORVD" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPRORVD" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPRORVD" xed="VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPRORVD" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPRORVD" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPRORVD" xed="VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPRORVQ" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPRORVQ" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPRORVQ" xed="VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPRORVQ" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPRORVQ" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPRORVQ" xed="VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sll_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSLLD" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_slli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSLLD" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sll_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSLLD" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_slli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSLLD" xed="VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sll_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSLLD" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_slli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSLLD" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sll_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSLLD" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_slli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSLLD" xed="VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sll_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSLLQ" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_slli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSLLQ" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sll_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSLLQ" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_slli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSLLQ" xed="VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sll_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSLLQ" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_slli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSLLQ" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sll_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSLLQ" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_slli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSLLQ" xed="VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sllv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSLLVD" xed="VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sllv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSLLVD" xed="VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sllv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSLLVD" xed="VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sllv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSLLVD" xed="VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sllv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSLLVQ" xed="VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sllv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSLLVQ" xed="VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sllv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSLLVQ" xed="VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sllv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSLLVQ" xed="VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sra_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSRAD" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srai_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSRAD" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sra_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSRAD" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srai_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSRAD" xed="VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sra_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRAD" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srai_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSRAD" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sra_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRAD" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srai_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="6" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSRAD" xed="VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-	ELSE
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, xmm" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-	ELSE
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VPSRAQ" xed="VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="7" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-	ELSE
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="7" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-	ELSE
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VPSRAQ" xed="VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srav_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSRAVD" xed="VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srav_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSRAVD" xed="VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srav_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRAVD" xed="VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srav_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRAVD" xed="VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSRAVQ" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSRAVQ" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSRAVQ" xed="VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRAVQ" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRAVQ" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSRAVQ" xed="VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srl_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSRLD" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSRLD" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srl_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSRLD" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSRLD" xed="VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srl_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRLD" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSRLD" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srl_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRLD" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSRLD" xed="VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srl_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, xmm" name="VPSRLQ" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VPSRLQ" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srl_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, xmm" name="VPSRLQ" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VPSRLQ" xed="VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srl_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRLQ" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VPSRLQ" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srl_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRLQ" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VPSRLQ" xed="VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srlv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSRLVD" xed="VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srlv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSRLVD" xed="VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srlv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRLVD" xed="VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srlv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRLVD" xed="VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_srlv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSRLVQ" xed="VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_srlv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSRLVQ" xed="VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_srlv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSRLVQ" xed="VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_srlv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSRLVQ" xed="VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sqrt_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VSQRTPD" xed="VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sqrt_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VSQRTPD" xed="VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VSQRTPD" xed="VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VSQRTPD" xed="VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sqrt_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VSQRTPS" xed="VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sqrt_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VSQRTPS" xed="VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VSQRTPS" xed="VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VSQRTPS" xed="VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_aesenclast_epi128" tech="Other">
-	<return etype="M128" type="__m512i" varname="dst" />
-	<parameter etype="M128" type="__m512i" varname="a" />
-	<parameter etype="M128" type="__m512i" varname="RoundKey" />
-	<description>Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
-	<operation>FOR j := 0 to 3
-	i := j*128
-	a[i+127:i] := ShiftRows(a[i+127:i])
-	a[i+127:i] := SubBytes(a[i+127:i])
-	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VAESENCLAST" xed="VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>VAES</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm512_aesenc_epi128" tech="Other">
-	<return etype="M128" type="__m512i" varname="dst" />
-	<parameter etype="M128" type="__m512i" varname="a" />
-	<parameter etype="M128" type="__m512i" varname="RoundKey" />
-	<description>Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
-	<operation>FOR j := 0 to 3
-	i := j*128
-	a[i+127:i] := ShiftRows(a[i+127:i])
-	a[i+127:i] := SubBytes(a[i+127:i])
-	a[i+127:i] := MixColumns(a[i+127:i])
-	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VAESENC" xed="VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>VAES</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm512_aesdeclast_epi128" tech="Other">
-	<return etype="M128" type="__m512i" varname="dst" />
-	<parameter etype="M128" type="__m512i" varname="a" />
-	<parameter etype="M128" type="__m512i" varname="RoundKey" />
-	<description>Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*128
-	a[i+127:i] := InvShiftRows(a[i+127:i])
-	a[i+127:i] := InvSubBytes(a[i+127:i])
-	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VAESDECLAST" xed="VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>VAES</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm512_aesdec_epi128" tech="Other">
-	<return etype="M128" type="__m512i" varname="dst" />
-	<parameter etype="M128" type="__m512i" varname="a" />
-	<parameter etype="M128" type="__m512i" varname="RoundKey" />
-	<description>Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*128
-	a[i+127:i] := InvShiftRows(a[i+127:i])
-	a[i+127:i] := InvSubBytes(a[i+127:i])
-	a[i+127:i] := InvMixColumns(a[i+127:i])
-	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VAESDEC" xed="VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<CPUID>VAES</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_maskz_mullo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp[63:0] := a[i+31:i] * b[i+31:i]
-		dst[i+31:i] := tmp[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULLD" xed="VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := a[63:0] + b[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] + b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] + b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] + b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] + b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VADDSD" xed="VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-dst[31:0] := a[31:0] + b[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] + b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] + b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] + b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] + b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VADDSS" xed="VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	dst[i+63:i] := a[i+63:i] / b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", =and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	dst[i+63:i] := a[i+63:i] / b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_div_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] / b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_div_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] / b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_div_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] / b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_div_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] / b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VDIVPD" xed="VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := a[i+31:i] / b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := a[i+31:i] / b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_div_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] / b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_div_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] / b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_div_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] / b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_div_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] / b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VDIVPS" xed="VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-		[round_note]</description>
-	<operation>
-dst[63:0] := a[63:0] / b[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". 
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] / b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] / b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] / b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] / b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VDIVSD" xed="VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-dst[31:0] := a[31:0] / b[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] / b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] / b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] / b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] / b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VDIVSS" xed="VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "a" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := c[63:0]
-FI
-dst[127:64] := c[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := c[63:0]
-FI
-dst[127:64] := c[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132SD" xed="VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213SD" xed="VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231SD" xed="VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := c[31:0]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := c[31:0]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132SS" xed="VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213SS" xed="VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231SS" xed="VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF ((j &amp; 1) == 0)
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmaddsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF ((j &amp; 1) == 0)
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmaddsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE 
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmaddsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmaddsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmaddsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF ((j &amp; 1) == 0)
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmaddsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF ((j &amp; 1) == 0)
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmaddsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmaddsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmaddsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmaddsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := c[63:0]
-FI
-dst[127:64] := c[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := c[63:0]
-FI
-dst[127:64] := c[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". 
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132SD" xed="VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213SD" xed="VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231SD" xed="VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := c[31:0]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := c[31:0]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132SS" xed="VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213SS" xed="VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231SS" xed="VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF ((j &amp; 1) == 0)
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsubadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF ((j &amp; 1) == 0)
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsubadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsubadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsubadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsubadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-		ELSE
-			dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF ((j &amp; 1) == 0)
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsubadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF ((j &amp; 1) == 0)
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsubadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsubadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsubadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsubadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-		ELSE
-			dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := c[63:0]
-FI
-dst[127:64] := c[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := c[63:0]
-FI
-dst[127:64] := c[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213SD" xed="VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231SD" xed="VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132SD" xed="VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := c[31:0]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := c[31:0]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132SS" xed="VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213SS" xed="VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231SS" xed="VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := c[63:0]
-FI
-dst[127:64] := c[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := c[63:0]
-FI
-dst[127:64] := c[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", subtract the lower element in "c" from the negated intermediate result, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := c[31:0]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := c[31:0]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] * b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] * b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] * b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] * b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-		[round_note]</description>
-	<operation>
-dst[63:0] := a[63:0] * b[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VMULSD" xed="VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] * b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] * b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] * b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] * b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-dst[31:0] := a[31:0] * b[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VMULSS" xed="VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPADDD" xed="VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] + b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPADDQ" xed="VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPADDQ" xed="VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPADDQ" xed="VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_epi32" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULDQ" xed="VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_epi32" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULDQ" xed="VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_epi32" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULDQ" xed="VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_epu32" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULUDQ" xed="VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_epu32" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULUDQ" xed="VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_epu32" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+31:i] * b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULUDQ" xed="VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSUBD" xed="VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSUBQ" xed="VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSUBQ" xed="VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] - b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSUBQ" xed="VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] - b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] - b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] - b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := a[63:0] - b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := a[63:0] - b[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSUBSD" xed="VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] - b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] - b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] - b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := a[31:0] - b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := a[31:0] - b[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSUBSS" xed="VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_storeu_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Store 512-bits (composed of 8 packed 64-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_storeu_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Store 512-bits (composed of 16 packed 32-bit integers) from "a" into memory.
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_store_mask16" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="MASK" memwidth="16" type="__mmask16*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<description>Store 16-bit mask from "a" into memory.</description>
-	<operation>
-MEM[mem_addr+15:mem_addr] := a[15:0]
-	</operation>
-	<instruction form="m16, k" name="KMOVW" xed="KMOVW_MEMu16_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compressstoreu_pd" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="FP64" memwidth="512" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 64
-m := base_addr
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		MEM[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compressstoreu_ps" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="FP32" memwidth="512" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 32
-m := base_addr
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		MEM[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_storeu_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_storeu_si512" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="M512" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="M512" type="__m512i" varname="a" />
-	<description>Store 512-bits of integer data from "a" into memory.
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVDQU32" xed="VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_storeu_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVDQU64" xed="VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_stream_si512" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="M512" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="M512" type="__m512i" varname="a" />
-	<description>Store 512-bits of integer data from "a" into memory using a non-temporal memory hint. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVNTDQ" xed="VMOVNTDQ_MEMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_stream_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVNTPD" xed="VMOVNTPD_MEMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_stream_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVNTPS" xed="VMOVNTPS_MEMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_store_sd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store the lower double-precision (64-bit) floating-point element from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-IF k[0]
-	MEM[mem_addr+63:mem_addr] := a[63:0]
-FI
-	</operation>
-	<instruction form="m64 {k}, xmm" name="VMOVSD" xed="VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_store_ss" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="32" type="float*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store the lower single-precision (32-bit) floating-point element from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-IF k[0]
-	MEM[mem_addr+31:mem_addr] := a[31:0]
-FI
-	</operation>
-	<instruction form="m32 {k}, xmm" name="VMOVSS" xed="VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_storeu_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVUPD" xed="VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_storeu_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVUPD" xed="VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_storeu_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_storeu_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compressstoreu_epi32" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="UI32" memwidth="512" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 32
-m := base_addr
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		MEM[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m32 {k}, zmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compressstoreu_epi64" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="UI64" memwidth="512" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 64
-m := base_addr
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		MEM[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, zmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32y, zmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32y {k}, zmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i64scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64z, ymm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i64scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64z {k}, ymm" name="VPSCATTERQD" xed="VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i64scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm64z, zmm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i64scatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm64z {k}, zmm" name="VPSCATTERQQ" xed="VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32y, zmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32y {k}, zmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i64scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32z, zmm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i64scatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32z {k}, zmm" name="VSCATTERQPD" xed="VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i64scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32z, ymm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i64scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32z {k}, ymm" name="VSCATTERQPS" xed="VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mullox_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Multiplies elements in packed 64-bit integer vectors "a" and "b" together, storing the lower 64 bits of the result in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] * b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mullox_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Multiplies elements in packed 64-bit integer vectors "a" and "b" together, storing the lower 64 bits of the result in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 8 packed 64-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVDQU64" xed="VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 16 packed 32-bit integers) from memory into "dst".
-		"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVDQU32" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_load_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" memwidth="16" type="__mmask16*" varname="mem_addr" />
-	<description>Load 16-bit mask from memory into "k".</description>
-	<operation>
-k[15:0] := MEM[mem_addr+15:mem_addr]
-	</operation>
-	<instruction form="k, m16" name="KMOVW" xed="KMOVW_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expandloadu_pd" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VEXPANDPD" xed="VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expandloadu_pd" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VEXPANDPD" xed="VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expandloadu_ps" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VEXPANDPS" xed="VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expandloadu_ps" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VEXPANDPS" xed="VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32gather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, vm32y" name="VGATHERDPD" xed="VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32gather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, vm32y" name="VGATHERDPD" xed="VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i64gather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, vm32z" name="VGATHERQPD" xed="VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i64gather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, vm32z" name="VGATHERQPD" xed="VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i64gather_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm64z" name="VGATHERQPS" xed="VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i64gather_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, vm64z" name="VGATHERQPS" xed="VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_load_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_load_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_loadu_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits of integer data from memory into "dst".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVDQU32" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVDQU32" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_loadu_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVDQU32" xed="VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVDQU64" xed="VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_loadu_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVDQU64" xed="VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_stream_load_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits of integer data from memory into "dst" using a non-temporal memory hint. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVNTDQA" xed="VMOVNTDQA_ZMMu32_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_load_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="64" type="const double*" varname="mem_addr" />
-	<description>Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and set the upper element of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MEM[mem_addr+63:mem_addr]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VMOVSD" xed="VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_load_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="64" type="const double*" varname="mem_addr" />
-	<description>Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and set the upper element of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MEM[mem_addr+63:mem_addr]
-ELSE
-	dst[63:0] := 0
-FI
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VMOVSD" xed="VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_load_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="32" type="const float*" varname="mem_addr" />
-	<description>Load a single-precision (32-bit) floating-point element from memory into the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and set the upper elements of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MEM[mem_addr+31:mem_addr]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, m32" name="VMOVSS" xed="VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_load_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" memwidth="32" type="const float*" varname="mem_addr" />
-	<description>Load a single-precision (32-bit) floating-point element from memory into the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and set the upper elements of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MEM[mem_addr+31:mem_addr]
-ELSE
-	dst[31:0] := 0
-FI
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, m32" name="VMOVSS" xed="VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_loadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVUPD" xed="VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_loadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVUPD" xed="VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_loadu_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVUPD" xed="VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_loadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVUPS" xed="VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_loadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVUPS" xed="VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_loadu_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VMOVUPS" xed="VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expandloadu_epi32" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m32" name="VPEXPANDD" xed="VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expandloadu_epi32" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m32" name="VPEXPANDD" xed="VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expandloadu_epi64" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expandloadu_epi64" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m64" name="VPEXPANDQ" xed="VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32gather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, vm32y" name="VPGATHERDQ" xed="VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32gather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, vm32y" name="VPGATHERDQ" xed="VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i64gather_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, vm64z" name="VPGATHERQD" xed="VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i64gather_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, vm64z" name="VPGATHERQD" xed="VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i64gather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*64
-	addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, vm64z" name="VPGATHERQQ" xed="VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i64gather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*64
-	IF k[j]
-		addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, vm64z" name="VPGATHERQQ" xed="VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_kand_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := a[15:0] AND b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDW" xed="KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kandn_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise NOT of 16-bit masks "a" and then AND with "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := (NOT a[15:0]) AND b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDNW" xed="KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_knot_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<description>Compute the bitwise NOT of 16-bit mask "a", and store the result in "k".</description>
-	<operation>
-k[15:0] := NOT a[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k" name="KNOTW" xed="KNOTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kor_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise OR of 16-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := a[15:0] OR b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KORW" xed="KORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kxnor_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise XNOR of 16-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := NOT (a[15:0] XOR b[15:0])
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXNORW" xed="KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kxor_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise XOR of 16-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := a[15:0] XOR b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXORW" xed="KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kshiftli_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
-	<description>Shift the bits of 16-bit mask "a" left by "count" while shifting in zeros, and store the least significant 16 bits of the result in "k".</description>
-	<operation>
-k[MAX:0] := 0
-IF count[7:0] &lt;= 15
-	k[15:0] := a[15:0] &lt;&lt; count[7:0]
-FI
-	</operation>
-	<instruction form="k, k, imm8" name="KSHIFTLW" xed="KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kshiftri_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="count" />
-	<description>Shift the bits of 16-bit mask "a" right by "count" while shifting in zeros, and store the least significant 16 bits of the result in "k".</description>
-	<operation>
-k[MAX:0] := 0
-IF count[7:0] &lt;= 15
-	k[15:0] := a[15:0] &gt;&gt; count[7:0]
-FI
-	</operation>
-	<instruction form="k, k, imm8" name="KSHIFTRW" xed="KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortest_mask16_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<parameter etype="UI8" memwidth="8" type="unsigned char*" varname="all_ones" />
-	<description>Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones".</description>
-	<operation>
-tmp[15:0] := a[15:0] OR b[15:0]
-IF tmp[15:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-IF tmp[15:0] == 0xFFFF
-	MEM[all_ones+7:all_ones] := 1
-ELSE
-	MEM[all_ones+7:all_ones] := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortestz_mask16_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[15:0] := a[15:0] OR b[15:0]
-IF tmp[15:0] == 0x0
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_kortestc_mask16_u8" tech="AVX-512">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst".</description>
-	<operation>
-tmp[15:0] := a[15:0] OR b[15:0]
-IF tmp[15:0] == 0xFFFF
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_cvtmask16_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<description>Convert 16-bit mask "a" into an integer value, and store the result in "dst".</description>
-	<operation>
-dst := ZeroExtend32(a[15:0])
-	</operation>
-	<instruction form="r32, k" name="KMOVW" xed="KMOVW_GPR32u32_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_cvtu32_mask16" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="unsigned int" varname="a" />
-	<description>Convert integer value "a" into an 16-bit mask, and store the result in "k".</description>
-	<operation>
-k := ZeroExtend16(a[15:0])
-	</operation>
-	<instruction form="k, r32" name="KMOVW" xed="KMOVW_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kandn" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise NOT of 16-bit masks "a" and then AND with "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := (NOT a[15:0]) AND b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDNW" xed="KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kand" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise AND of 16-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := a[15:0] AND b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KANDW" xed="KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kmov" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<description>Copy 16-bit mask "a" to "k".</description>
-	<operation>
-k[15:0] := a[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k" name="KMOVW" xed="KMOVW_MASKmskw_MASKu16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_knot" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<description>Compute the bitwise NOT of 16-bit mask "a", and store the result in "k".</description>
-	<operation>
-k[15:0] := NOT a[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k" name="KNOTW" xed="KNOTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kor" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise OR of 16-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := a[15:0] OR b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KORW" xed="KORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kunpackb" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Unpack and interleave 8 bits from masks "a" and "b", and store the 16-bit result in "k".</description>
-	<operation>
-k[7:0] := b[7:0]
-k[15:8] := a[7:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KUNPCKBW" xed="KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kxnor" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise XNOR of 16-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := NOT (a[15:0] XOR b[15:0])
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXNORW" xed="KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kxor" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="b" />
-	<description>Compute the bitwise XOR of 16-bit masks "a" and "b", and store the result in "k".</description>
-	<operation>
-k[15:0] := a[15:0] XOR b[15:0]
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, k, k" name="KXORW" xed="KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kortestz" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="MASK" type="__mmask16" varname="k2" />
-	<description>Performs bitwise OR between "k1" and "k2", storing the result in "dst". ZF flag is set if "dst" is 0.</description>
-	<operation>dst[15:0] := k1[15:0] | k2[15:0]
-IF dst == 0
-	SetZF()
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_kortestc" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="MASK" type="__mmask16" varname="k2" />
-	<description>Performs bitwise OR between "k1" and "k2", storing the result in "dst". CF flag is set if "dst" consists of all 1's.</description>
-	<operation>dst[15:0] := k1[15:0] | k2[15:0]
-IF PopCount(dst[15:0]) == 16
-	SetCF()
-FI
-	</operation>
-	<instruction form="k, k" name="KORTESTW" xed="KORTESTW_MASKmskw_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask2int" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<description>Converts bit mask "k1" into an integer value, storing the results in "dst".</description>
-	<operation>
-dst := ZeroExtend32(k1)
-	</operation>
-	<instruction form="r32, k" name="KMOVW" xed="KMOVW_GPR32u32_MASKmskw_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_int2mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="dst" />
-	<parameter etype="UI16" type="int" varname="mask" />
-	<description>Converts integer "mask" into bitmask, storing the result in "dst".</description>
-	<operation>
-dst := mask[15:0]
-	</operation>
-	<instruction form="k, r32" name="KMOVW" xed="KMOVW_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and stores the low 64 bytes (16 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-temp[1023:512] := a[511:0]
-temp[511:0] := b[511:0]
-temp[1023:0] := temp[1023:0] &gt;&gt; (32*imm8[3:0])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := temp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VALIGND" xed="VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 64 bytes (8 elements) in "dst".</description>
-	<operation>
-temp[1023:512] := a[511:0]
-temp[511:0] := b[511:0]
-temp[1023:0] := temp[1023:0] &gt;&gt; (64*imm8[2:0])
-dst[511:0] := temp[511:0]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VALIGNQ" xed="VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 64 bytes (8 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-temp[1023:512] := a[511:0]
-temp[511:0] := b[511:0]
-temp[1023:0] := temp[1023:0] &gt;&gt; (64*imm8[2:0])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := temp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VALIGNQ" xed="VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_alignr_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="3" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and stores the low 64 bytes (8 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-temp[1023:512] := a[511:0]
-temp[511:0] := b[511:0]
-temp[1023:0] := temp[1023:0] &gt;&gt; (64*imm8[2:0])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := temp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VALIGNQ" xed="VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fixupimm_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fixupimm_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fixupimm_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fixupimm_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPD" xed="VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fixupimm_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fixupimm_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fixupimm_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fixupimm_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8 {sae}" name="VFIXUPIMMPS" xed="VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fixupimm_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst", and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
-dst[127:64] := b[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fixupimm_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst", and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
-dst[127:64] := b[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fixupimm_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-IF k[0]
-	dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := b[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fixupimm_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-IF k[0]
-	dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := a[63:0]
-FI
-dst[127:64] := b[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fixupimm_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-IF k[0]
-	dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := b[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fixupimm_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "b" to the upper element of "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) {
-	tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0]
-	CASE(tsrc[63:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[63:0] := src1[63:0]
-	1 : dest[63:0] := tsrc[63:0]
-	2 : dest[63:0] := QNaN(tsrc[63:0])
-	3 : dest[63:0] := QNAN_Indefinite
-	4 : dest[63:0] := -INF
-	5 : dest[63:0] := +INF
-	6 : dest[63:0] := tsrc.sign? -INF : +INF
-	7 : dest[63:0] := -0
-	8 : dest[63:0] := +0
-	9 : dest[63:0] := -1
-	10: dest[63:0] := +1
-	11: dest[63:0] := 1/2
-	12: dest[63:0] := 90.0
-	13: dest[63:0] := PI/2
-	14: dest[63:0] := MAX_FLOAT
-	15: dest[63:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[63:0]
-}
-IF k[0]
-	dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := b[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VFIXUPIMMSD" xed="VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fixupimm_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst", and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
-dst[127:32] := b[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fixupimm_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst", and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
-dst[127:32] := b[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fixupimm_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-IF k[0]
-	dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := b[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fixupimm_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-IF k[0]
-	dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := a[31:0]
-FI
-dst[127:32] := b[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fixupimm_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.
-	[sae_note]</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-IF k[0]
-	dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := b[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fixupimm_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "b" to the upper elements of "dst". "imm8" is used to set the required flags reporting.</description>
-	<operation>enum TOKEN_TYPE {
-	QNAN_TOKEN := 0, \
-	SNAN_TOKEN := 1, \
-	ZERO_VALUE_TOKEN := 2, \
-	ONE_VALUE_TOKEN := 3, \
-	NEG_INF_TOKEN := 4, \
-	POS_INF_TOKEN := 5, \
-	NEG_VALUE_TOKEN := 6, \
-	POS_VALUE_TOKEN := 7
-}
-DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) {
-	tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0]
-	CASE(tsrc[31:0]) OF
-	QNAN_TOKEN:j := 0
-	SNAN_TOKEN:j := 1
-	ZERO_VALUE_TOKEN: j := 2
-	ONE_VALUE_TOKEN: j := 3
-	NEG_INF_TOKEN: j := 4
-	POS_INF_TOKEN: j := 5
-	NEG_VALUE_TOKEN: j := 6
-	POS_VALUE_TOKEN: j := 7
-	ESAC
-	
-	token_response[3:0] := src3[3+4*j:4*j]
-	
-	CASE(token_response[3:0]) OF
-	0 : dest[31:0] := src1[31:0]
-	1 : dest[31:0] := tsrc[31:0]
-	2 : dest[31:0] := QNaN(tsrc[31:0])
-	3 : dest[31:0] := QNAN_Indefinite
-	4 : dest[31:0] := -INF
-	5 : dest[31:0] := +INF
-	6 : dest[31:0] := tsrc.sign? -INF : +INF
-	7 : dest[31:0] := -0
-	8 : dest[31:0] := +0
-	9 : dest[31:0] := -1
-	10: dest[31:0] := +1
-	11: dest[31:0] := 1/2
-	12: dest[31:0] := 90.0
-	13: dest[31:0] := PI/2
-	14: dest[31:0] := MAX_FLOAT
-	15: dest[31:0] := -MAX_FLOAT
-	ESAC
-	
-	CASE(tsrc[31:0]) OF
-	ZERO_VALUE_TOKEN:
-		IF (imm8[0]) #ZE; FI
-	ZERO_VALUE_TOKEN:
-		IF (imm8[1]) #IE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[2]) #ZE; FI
-	ONE_VALUE_TOKEN:
-		IF (imm8[3]) #IE; FI
-	SNAN_TOKEN:
-		IF (imm8[4]) #IE; FI
-	NEG_INF_TOKEN:
-		IF (imm8[5]) #IE; FI
-	NEG_VALUE_TOKEN:
-		IF (imm8[6]) #IE; FI
-	POS_INF_TOKEN:
-		IF (imm8[7]) #IE; FI
-	ESAC
-	RETURN dest[31:0]
-}
-IF k[0]
-	dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := b[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VFIXUPIMMSS" xed="VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getexp_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.
-	[sae_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getexp_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.
-	[sae_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
-	[sae_note]</description>
-	<operation>dst[63:0] := ConvertExpFP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>dst[63:0] := ConvertExpFP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
-	[sae_note]</description>
-	<operation>IF k[0]
-	dst[63:0] := ConvertExpFP64(b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>IF k[0]
-	dst[63:0] := ConvertExpFP64(b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
-	[sae_note]</description>
-	<operation>IF k[0]
-	dst[63:0] := ConvertExpFP64(b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>IF k[0]
-	dst[63:0] := ConvertExpFP64(b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VGETEXPSD" xed="VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
-	[sae_note]</description>
-	<operation>dst[31:0] := ConvertExpFP32(b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>dst[31:0] := ConvertExpFP32(b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
-	[sae_note]</description>
-	<operation>IF k[0]
-	dst[31:0] := ConvertExpFP32(b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>IF k[0]
-	dst[31:0] := ConvertExpFP32(b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.
-	[sae_note]</description>
-	<operation>IF k[0]
-	dst[31:0] := ConvertExpFP32(b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>IF k[0]
-	dst[31:0] := ConvertExpFP32(b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VGETEXPSS" xed="VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getmant_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8 {sae}" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getmant_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8 {sae}" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>IF k[0]
-	dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>IF k[0]
-	dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>IF k[0]
-	dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>IF k[0]
-	dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv)
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGETMANTSD" xed="VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>IF k[0]
-	dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>IF k[0]
-	dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>IF k[0]
-	dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>IF k[0]
-	dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv)
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGETMANTSS" xed="VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPRORVD" xed="VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_roundscale_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8 {sae}" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_roundscale_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8 {sae}" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_roundscale_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_roundscale_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8 {sae}" name="VRNDSCALEPD" xed="VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_roundscale_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8 {sae}" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_roundscale_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8 {sae}" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_roundscale_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_roundscale_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8 {sae}" name="VRNDSCALEPS" xed="VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-IF k[0]
-	dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-IF k[0]
-	dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-IF k[0]
-	dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-IF k[0]
-	dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) {
-	m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0])
-	IF IsInf(tmp[63:0])
-		tmp[63:0] := src1[63:0]
-	FI
-	RETURN tmp[63:0]
-}
-dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VRNDSCALESD" xed="VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-IF k[0]
-	dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8 {sae}" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-IF k[0]
-	dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-IF k[0]
-	dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8 {sae}" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-IF k[0]
-	dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8 {sae}" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="const int" varname="imm8" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) {
-	m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0])
-	IF IsInf(tmp[31:0])
-		tmp[31:0] := src1[31:0]
-	FI
-	RETURN tmp[31:0]
-}
-dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VRNDSCALESS" xed="VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_scalef_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_scalef_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_scalef_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_scalef_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst".
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VSCALEFPD" xed="VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_scalef_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_scalef_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_scalef_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_scalef_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst".
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[31:0]
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VSCALEFPS" xed="VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-IF k[0]
-	dst[63:0] := SCALE(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-IF k[0]
-	dst[63:0] := SCALE(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-IF k[0]
-	dst[63:0] := SCALE(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-IF k[0]
-	dst[63:0] := SCALE(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-dst[63:0] := SCALE(a[63:0], b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0]))
-	RETURN dst[63:0]
-}
-dst[63:0] := SCALE(a[63:0], b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSCALEFSD" xed="VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[63:0]
-}
-IF k[0]
-	dst[31:0] := SCALE(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[63:0]
-}
-IF k[0]
-	dst[31:0] := SCALE(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[63:0]
-}
-IF k[0]
-	dst[31:0] := SCALE(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[63:0]
-}
-IF k[0]
-	dst[31:0] := SCALE(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[63:0]
-}
-dst[31:0] := SCALE(a[31:0], b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>DEFINE SCALE(src1, src2) {
-	IF (src2 == NaN)
-		IF (src2 == SNaN)
-			RETURN QNAN(src2)
-		FI
-	ELSE IF (src1 == NaN)
-		IF (src1 == SNaN)
-			RETURN QNAN(src1)
-		FI
-		IF (src2 != INF)
-			RETURN QNAN(src1)
-		FI
-	ELSE
-		tmp_src2 := src2
-		tmp_src1 := src1
-		IF (IS_DENORMAL(src2) AND MXCSR.DAZ)
-			tmp_src2 := 0
-		FI
-		IF (IS_DENORMAL(src1) AND MXCSR.DAZ)
-			tmp_src1 := 0
-		FI
-	FI
-	dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0]))
-	RETURN dst[63:0]
-}
-dst[31:0] := SCALE(a[31:0], b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSCALEFSS" xed="VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 4)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 4)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 4)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m128" name="VBROADCASTF32X4" xed="VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_f64x4" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 4)*64
-	dst[i+63:i] := a[n+63:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m256" name="VBROADCASTF64X4" xed="VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_f64x4" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 4)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m256" name="VBROADCASTF64X4" xed="VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_f64x4" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 4)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m256" name="VBROADCASTF64X4" xed="VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 4)*32
-	dst[i+31:i] := a[n+31:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 4)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	n := (j % 4)*32
-	IF k[j]
-		dst[i+31:i] := a[n+31:n]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m128" name="VBROADCASTI32X4" xed="VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcast_i64x4" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 4)*64
-	dst[i+63:i] := a[n+63:n]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m256" name="VBROADCASTI64X4" xed="VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcast_i64x4" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 4)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m256" name="VBROADCASTI64X4" xed="VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcast_i64x4" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	n := (j % 4)*64
-	IF k[j]
-		dst[i+63:i] := a[n+63:n]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m256" name="VBROADCASTI64X4" xed="VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcastsd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcastsd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcastsd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VBROADCASTSD" xed="VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcastss_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcastss_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcastss_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VBROADCASTSS" xed="VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compress_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := src[511:m]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_compress_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := 0
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCOMPRESSPD" xed="VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compress_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := src[511:m]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_compress_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := 0
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCOMPRESSPS" xed="VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expand_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VEXPANDPD" xed="VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expand_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VEXPANDPD" xed="VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expand_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VEXPANDPS" xed="VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expand_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VEXPANDPS" xed="VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_extractf32x4_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[1:0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-2: dst[127:0] := a[383:256]
-3: dst[127:0] := a[511:384]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_extractf32x4_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[1:0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-2: tmp[127:0] := a[383:256]
-3: tmp[127:0] := a[511:384]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_extractf32x4_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[1:0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-2: tmp[127:0] := a[383:256]
-3: tmp[127:0] := a[511:384]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm, imm8" name="VEXTRACTF32X4" xed="VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_extractf64x4_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[255:0] := a[255:0]
-1: dst[255:0] := a[511:256]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm, imm8" name="VEXTRACTF64X4" xed="VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_extractf64x4_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[255:0] := a[255:0]
-1: tmp[255:0] := a[511:256]
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm, imm8" name="VEXTRACTF64X4" xed="VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_extractf64x4_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[255:0] := a[255:0]
-1: tmp[255:0] := a[511:256]
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm, imm8" name="VEXTRACTF64X4" xed="VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_extracti32x4_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[1:0] OF
-0: dst[127:0] := a[127:0]
-1: dst[127:0] := a[255:128]
-2: dst[127:0] := a[383:256]
-3: dst[127:0] := a[511:384]
-ESAC
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_extracti32x4_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[1:0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-2: tmp[127:0] := a[383:256]
-3: tmp[127:0] := a[511:384]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_extracti32x4_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[1:0] OF
-0: tmp[127:0] := a[127:0]
-1: tmp[127:0] := a[255:128]
-2: tmp[127:0] := a[383:256]
-3: tmp[127:0] := a[511:384]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm, imm8" name="VEXTRACTI32X4" xed="VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_extracti64x4_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-CASE imm8[0] OF
-0: dst[255:0] := a[255:0]
-1: dst[255:0] := a[511:256]
-ESAC
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm, imm8" name="VEXTRACTI64X4" xed="VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_extracti64x4_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[255:0] := a[255:0]
-1: tmp[255:0] := a[511:256]
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm, imm8" name="VEXTRACTI64X4" xed="VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_extracti64x4_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-CASE imm8[0] OF
-0: tmp[255:0] := a[255:0]
-1: tmp[255:0] := a[511:256]
-ESAC
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm, imm8" name="VEXTRACTI64X4" xed="VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_insertf32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-2: dst[383:256] := b[127:0]
-3: dst[511:384] := b[127:0]
-ESAC
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_insertf32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-2: tmp[383:256] := b[127:0]
-3: tmp[511:384] := b[127:0]
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_insertf32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-2: tmp[383:256] := b[127:0]
-3: tmp[511:384] := b[127:0]
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm, imm8" name="VINSERTF32X4" xed="VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_insertf64x4" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: dst[255:0] := b[255:0]
-1: dst[511:256] := b[255:0]
-ESAC
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, ymm, imm8" name="VINSERTF64X4" xed="VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_insertf64x4" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: tmp[255:0] := b[255:0]
-1: tmp[511:256] := b[255:0]
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, ymm, imm8" name="VINSERTF64X4" xed="VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_insertf64x4" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: tmp[255:0] := b[255:0]
-1: tmp[511:256] := b[255:0]
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, ymm, imm8" name="VINSERTF64X4" xed="VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_inserti32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: dst[127:0] := b[127:0]
-1: dst[255:128] := b[127:0]
-2: dst[383:256] := b[127:0]
-3: dst[511:384] := b[127:0]
-ESAC
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_inserti32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-2: tmp[383:256] := b[127:0]
-3: tmp[511:384] := b[127:0]
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_inserti32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[1:0]) OF
-0: tmp[127:0] := b[127:0]
-1: tmp[255:128] := b[127:0]
-2: tmp[383:256] := b[127:0]
-3: tmp[511:384] := b[127:0]
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm, imm8" name="VINSERTI32X4" xed="VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_inserti64x4" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: dst[255:0] := b[255:0]
-1: dst[511:256] := b[255:0]
-ESAC
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, ymm, imm8" name="VINSERTI64X4" xed="VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_inserti64x4" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: tmp[255:0] := b[255:0]
-1: tmp[511:256] := b[255:0]
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, ymm, imm8" name="VINSERTI64X4" xed="VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_inserti64x4" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8".  Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[511:0] := a[511:0]
-CASE (imm8[0]) OF
-0: tmp[255:0] := b[255:0]
-1: tmp[511:256] := b[255:0]
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, ymm, imm8" name="VINSERTI64X4" xed="VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcastd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcastd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcastd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_broadcastq_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_broadcastq_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_broadcastq_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compress_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := src[511:m]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_compress_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 32
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[m+size-1:m] := a[i+31:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := 0
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPCOMPRESSD" xed="VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compress_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := src[511:m]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_compress_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 64
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[m+size-1:m] := a[i+63:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := 0
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPCOMPRESSQ" xed="VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutexvar_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	id := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutexvar_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	id := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutexvar_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	id := idx[i+3:i]*32
-	dst[i+31:i] := a[id+31:id]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask2_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	off := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := idx[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2D" xed="VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	off := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2D" xed="VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	off := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := (idx[i+4]) ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2D" xed="VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2D" xed="VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex2var_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	off := idx[i+3:i]*32
-	dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMI2D" xed="VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VPERMT2D" xed="VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask2_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set)</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	off := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := idx[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2PD" xed="VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	off := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2PD" xed="VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	off := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := (idx[i+3]) ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2PD" xed="VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2PD" xed="VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex2var_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	off := idx[i+2:i]*64
-	dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMI2PD" xed="VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VPERMT2PD" xed="VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask2_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	off := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := idx[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2PS" xed="VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	off := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2PS" xed="VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	off := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := (idx[i+4]) ? b[off+31:off] : a[off+31:off]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2PS" xed="VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2PS" xed="VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex2var_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	off := idx[i+3:i]*32
-	dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMI2PS" xed="VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VPERMT2PS" xed="VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask2_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	off := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := idx[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2Q" xed="VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	off := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2Q" xed="VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	off := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := (idx[i+3]) ? b[off+63:off] : a[off+63:off]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2Q" xed="VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2Q" xed="VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex2var_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	off := idx[i+2:i]*64
-	dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMI2Q" xed="VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VPERMT2Q" xed="VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permute_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
-IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
-IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
-IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
-IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
-IF (imm8[4] == 0) tmp_dst[319:256] := a[319:256]; FI
-IF (imm8[4] == 1) tmp_dst[319:256] := a[383:320]; FI
-IF (imm8[5] == 0) tmp_dst[383:320] := a[319:256]; FI
-IF (imm8[5] == 1) tmp_dst[383:320] := a[383:320]; FI
-IF (imm8[6] == 0) tmp_dst[447:384] := a[447:384]; FI
-IF (imm8[6] == 1) tmp_dst[447:384] := a[511:448]; FI
-IF (imm8[7] == 0) tmp_dst[511:448] := a[447:384]; FI
-IF (imm8[7] == 1) tmp_dst[511:448] := a[511:448]; FI
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutevar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
-IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
-IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
-IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
-IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
-IF (b[257] == 0) tmp_dst[319:256] := a[319:256]; FI
-IF (b[257] == 1) tmp_dst[319:256] := a[383:320]; FI
-IF (b[321] == 0) tmp_dst[383:320] := a[319:256]; FI
-IF (b[321] == 1) tmp_dst[383:320] := a[383:320]; FI
-IF (b[385] == 0) tmp_dst[447:384] := a[447:384]; FI
-IF (b[385] == 1) tmp_dst[447:384] := a[511:448]; FI
-IF (b[449] == 0) tmp_dst[511:448] := a[447:384]; FI
-IF (b[449] == 1) tmp_dst[511:448] := a[511:448]; FI
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permute_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI
-IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI
-IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI
-IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI
-IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI
-IF (imm8[4] == 0) tmp_dst[319:256] := a[319:256]; FI
-IF (imm8[4] == 1) tmp_dst[319:256] := a[383:320]; FI
-IF (imm8[5] == 0) tmp_dst[383:320] := a[319:256]; FI
-IF (imm8[5] == 1) tmp_dst[383:320] := a[383:320]; FI
-IF (imm8[6] == 0) tmp_dst[447:384] := a[447:384]; FI
-IF (imm8[6] == 1) tmp_dst[447:384] := a[511:448]; FI
-IF (imm8[7] == 0) tmp_dst[511:448] := a[447:384]; FI
-IF (imm8[7] == 1) tmp_dst[511:448] := a[511:448]; FI
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutevar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI
-IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI
-IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI
-IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI
-IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI
-IF (b[257] == 0) tmp_dst[319:256] := a[319:256]; FI
-IF (b[257] == 1) tmp_dst[319:256] := a[383:320]; FI
-IF (b[321] == 0) tmp_dst[383:320] := a[319:256]; FI
-IF (b[321] == 1) tmp_dst[383:320] := a[383:320]; FI
-IF (b[385] == 0) tmp_dst[447:384] := a[447:384]; FI
-IF (b[385] == 1) tmp_dst[447:384] := a[511:448]; FI
-IF (b[449] == 0) tmp_dst[511:448] := a[447:384]; FI
-IF (b[449] == 1) tmp_dst[511:448] := a[511:448]; FI
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permute_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI
-IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI
-IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI
-IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI
-IF (imm8[2] == 0) dst[191:128] := a[191:128]; FI
-IF (imm8[2] == 1) dst[191:128] := a[255:192]; FI
-IF (imm8[3] == 0) dst[255:192] := a[191:128]; FI
-IF (imm8[3] == 1) dst[255:192] := a[255:192]; FI
-IF (imm8[4] == 0) dst[319:256] := a[319:256]; FI
-IF (imm8[4] == 1) dst[319:256] := a[383:320]; FI
-IF (imm8[5] == 0) dst[383:320] := a[319:256]; FI
-IF (imm8[5] == 1) dst[383:320] := a[383:320]; FI
-IF (imm8[6] == 0) dst[447:384] := a[447:384]; FI
-IF (imm8[6] == 1) dst[447:384] := a[511:448]; FI
-IF (imm8[7] == 0) dst[511:448] := a[447:384]; FI
-IF (imm8[7] == 1) dst[511:448] := a[511:448]; FI
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutevar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
-	<operation>
-IF (b[1] == 0) dst[63:0] := a[63:0]; FI
-IF (b[1] == 1) dst[63:0] := a[127:64]; FI
-IF (b[65] == 0) dst[127:64] := a[63:0]; FI
-IF (b[65] == 1) dst[127:64] := a[127:64]; FI
-IF (b[129] == 0) dst[191:128] := a[191:128]; FI
-IF (b[129] == 1) dst[191:128] := a[255:192]; FI
-IF (b[193] == 0) dst[255:192] := a[191:128]; FI
-IF (b[193] == 1) dst[255:192] := a[255:192]; FI
-IF (b[257] == 0) dst[319:256] := a[319:256]; FI
-IF (b[257] == 1) dst[319:256] := a[383:320]; FI
-IF (b[321] == 0) dst[383:320] := a[319:256]; FI
-IF (b[321] == 1) dst[383:320] := a[383:320]; FI
-IF (b[385] == 0) dst[447:384] := a[447:384]; FI
-IF (b[385] == 1) dst[447:384] := a[511:448]; FI
-IF (b[449] == 0) dst[511:448] := a[447:384]; FI
-IF (b[449] == 1) dst[511:448] := a[511:448]; FI
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMILPD" xed="VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permute_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4])
-tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6])
-tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4])
-tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutevar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
-tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
-tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
-tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
-tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
-tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
-tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
-tmp_dst[287:256] := SELECT4(a[383:256], b[257:256])
-tmp_dst[319:288] := SELECT4(a[383:256], b[289:288])
-tmp_dst[351:320] := SELECT4(a[383:256], b[321:320])
-tmp_dst[383:352] := SELECT4(a[383:256], b[353:352])
-tmp_dst[415:384] := SELECT4(a[511:384], b[385:384])
-tmp_dst[447:416] := SELECT4(a[511:384], b[417:416])
-tmp_dst[479:448] := SELECT4(a[511:384], b[449:448])
-tmp_dst[511:480] := SELECT4(a[511:384], b[481:480])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permute_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4])
-tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6])
-tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4])
-tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutevar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], b[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], b[33:32])
-tmp_dst[95:64] := SELECT4(a[127:0], b[65:64])
-tmp_dst[127:96] := SELECT4(a[127:0], b[97:96])
-tmp_dst[159:128] := SELECT4(a[255:128], b[129:128])
-tmp_dst[191:160] := SELECT4(a[255:128], b[161:160])
-tmp_dst[223:192] := SELECT4(a[255:128], b[193:192])
-tmp_dst[255:224] := SELECT4(a[255:128], b[225:224])
-tmp_dst[287:256] := SELECT4(a[383:256], b[257:256])
-tmp_dst[319:288] := SELECT4(a[383:256], b[289:288])
-tmp_dst[351:320] := SELECT4(a[383:256], b[321:320])
-tmp_dst[383:352] := SELECT4(a[383:256], b[353:352])
-tmp_dst[415:384] := SELECT4(a[511:384], b[385:384])
-tmp_dst[447:416] := SELECT4(a[511:384], b[417:416])
-tmp_dst[479:448] := SELECT4(a[511:384], b[449:448])
-tmp_dst[511:480] := SELECT4(a[511:384], b[481:480])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permute_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-dst[351:320] := SELECT4(a[383:256], imm8[5:4])
-dst[383:352] := SELECT4(a[383:256], imm8[7:6])
-dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-dst[479:448] := SELECT4(a[511:384], imm8[5:4])
-dst[511:480] := SELECT4(a[511:384], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutevar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], b[1:0])
-dst[63:32] := SELECT4(a[127:0], b[33:32])
-dst[95:64] := SELECT4(a[127:0], b[65:64])
-dst[127:96] := SELECT4(a[127:0], b[97:96])
-dst[159:128] := SELECT4(a[255:128], b[129:128])
-dst[191:160] := SELECT4(a[255:128], b[161:160])
-dst[223:192] := SELECT4(a[255:128], b[193:192])
-dst[255:224] := SELECT4(a[255:128], b[225:224])
-dst[287:256] := SELECT4(a[383:256], b[257:256])
-dst[319:288] := SELECT4(a[383:256], b[289:288])
-dst[351:320] := SELECT4(a[383:256], b[321:320])
-dst[383:352] := SELECT4(a[383:256], b[353:352])
-dst[415:384] := SELECT4(a[511:384], b[385:384])
-dst[447:416] := SELECT4(a[511:384], b[417:416])
-dst[479:448] := SELECT4(a[511:384], b[449:448])
-dst[511:480] := SELECT4(a[511:384], b[481:480])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMILPS" xed="VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutex_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0])
-tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2])
-tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4])
-tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutexvar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	id := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := a[id+63:id]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutex_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0])
-tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2])
-tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4])
-tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutexvar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	id := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := a[id+63:id]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-dst[319:256] := SELECT4(a[511:256], imm8[1:0])
-dst[383:320] := SELECT4(a[511:256], imm8[3:2])
-dst[447:384] := SELECT4(a[511:256], imm8[5:4])
-dst[511:448] := SELECT4(a[511:256], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutexvar_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	id := idx[i+2:i]*64
-	dst[i+63:i] := a[id+63:id]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMPD" xed="VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutexvar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	id := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMPS" xed="VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutexvar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	id := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMPS" xed="VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutexvar_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	id := idx[i+3:i]*32
-	dst[i+31:i] := a[id+31:id]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMPS" xed="VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutex_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0])
-tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2])
-tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4])
-tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutexvar_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	id := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := a[id+63:id]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutex_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0])
-tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2])
-tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4])
-tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutexvar_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	id := idx[i+2:i]*64
-	IF k[j]
-		dst[i+63:i] := a[id+63:id]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[63:0] := src[63:0]
-	1:	tmp[63:0] := src[127:64]
-	2:	tmp[63:0] := src[191:128]
-	3:	tmp[63:0] := src[255:192]
-	ESAC
-	RETURN tmp[63:0]
-}
-dst[63:0] := SELECT4(a[255:0], imm8[1:0])
-dst[127:64] := SELECT4(a[255:0], imm8[3:2])
-dst[191:128] := SELECT4(a[255:0], imm8[5:4])
-dst[255:192] := SELECT4(a[255:0], imm8[7:6])
-dst[319:256] := SELECT4(a[511:256], imm8[1:0])
-dst[383:320] := SELECT4(a[511:256], imm8[3:2])
-dst[447:384] := SELECT4(a[511:256], imm8[5:4])
-dst[511:448] := SELECT4(a[511:256], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutexvar_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="idx" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	id := idx[i+2:i]*64
-	dst[i+63:i] := a[id+63:id]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMQ" xed="VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expand_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPEXPANDD" xed="VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expand_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[m+31:m]
-		m := m + 32
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPEXPANDD" xed="VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expand_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPEXPANDQ" xed="VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expand_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[m+63:m]
-		m := m + 64
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPEXPANDQ" xed="VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shuffle_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4])
-tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6])
-tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4])
-tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSHUFD" xed="VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpackhi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpackhi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpackhi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPUNPCKHDQ" xed="VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpackhi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpackhi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpackhi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPUNPCKHQDQ" xed="VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpacklo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpacklo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpacklo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPUNPCKLDQ" xed="VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpacklo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpacklo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpacklo_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPUNPCKLQDQ" xed="VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shuffle_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shuffle_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shuffle_f32x4" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFF32X4" xed="VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shuffle_f64x2" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shuffle_f64x2" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shuffle_f64x2" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFF64X2" xed="VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shuffle_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shuffle_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shuffle_i32x4" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFI32X4" xed="VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shuffle_i64x2" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shuffle_i64x2" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shuffle_i64x2" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[127:0] := src[127:0]
-	1:	tmp[127:0] := src[255:128]
-	2:	tmp[127:0] := src[383:256]
-	3:	tmp[127:0] := src[511:384]
-	ESAC
-	RETURN tmp[127:0]
-}
-dst[127:0] := SELECT4(a[511:0], imm8[1:0])
-dst[255:128] := SELECT4(a[511:0], imm8[3:2])
-dst[383:256] := SELECT4(b[511:0], imm8[5:4])
-dst[511:384] := SELECT4(b[511:0], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFI64X2" xed="VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shuffle_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
-tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
-tmp_dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320]
-tmp_dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320]
-tmp_dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448]
-tmp_dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448]
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFPD" xed="VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shuffle_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
-tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
-tmp_dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320]
-tmp_dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320]
-tmp_dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448]
-tmp_dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448]
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFPD" xed="VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shuffle_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192]
-dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192]
-dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320]
-dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320]
-dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448]
-dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFPD" xed="VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shuffle_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
-tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-tmp_dst[351:320] := SELECT4(b[383:256], imm8[5:4])
-tmp_dst[383:352] := SELECT4(b[383:256], imm8[7:6])
-tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-tmp_dst[479:448] := SELECT4(b[511:384], imm8[5:4])
-tmp_dst[511:480] := SELECT4(b[511:384], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VSHUFPS" xed="VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shuffle_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6])
-tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-tmp_dst[351:320] := SELECT4(b[383:256], imm8[5:4])
-tmp_dst[383:352] := SELECT4(b[383:256], imm8[7:6])
-tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-tmp_dst[479:448] := SELECT4(b[511:384], imm8[5:4])
-tmp_dst[511:480] := SELECT4(b[511:384], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VSHUFPS" xed="VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shuffle_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-dst[223:192] := SELECT4(b[255:128], imm8[5:4])
-dst[255:224] := SELECT4(b[255:128], imm8[7:6])
-dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-dst[351:320] := SELECT4(b[383:256], imm8[5:4])
-dst[383:352] := SELECT4(b[383:256], imm8[7:6])
-dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-dst[479:448] := SELECT4(b[511:384], imm8[5:4])
-dst[511:480] := SELECT4(b[511:384], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VSHUFPS" xed="VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpackhi_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VUNPCKHPD" xed="VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpackhi_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VUNPCKHPD" xed="VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpackhi_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VUNPCKHPD" xed="VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpackhi_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VUNPCKHPS" xed="VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpackhi_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VUNPCKHPS" xed="VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpackhi_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VUNPCKHPS" xed="VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpacklo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VUNPCKLPD" xed="VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpacklo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp_dst[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VUNPCKLPD" xed="VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpacklo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VUNPCKLPD" xed="VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_unpacklo_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VUNPCKLPS" xed="VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_unpacklo_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
-tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VUNPCKLPS" xed="VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_unpacklo_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128])
-dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256])
-dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VUNPCKLPS" xed="VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_round_sd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k". [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, xmm {sae}, imm8" name="VCMPSD" xed="VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_sd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VCMPSD" xed="VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_round_sd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-IF k1[0]
-	k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm {sae}, imm8" name="VCMPSD" xed="VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_sd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-IF k1[0]
-	k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPSD" xed="VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_round_ss_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k". [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, xmm {sae}, imm8" name="VCMPSS" xed="VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_ss_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VCMPSS" xed="VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_round_ss_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-IF k1[0]
-	k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm {sae}, imm8" name="VCMPSS" xed="VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_ss_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-IF k1[0]
-	k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPSS" xed="VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comi_round_sd" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1). [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-RETURN ( a[63:0] OP b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm {sae}" name="VCOMISD" xed="VCOMISD_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comi_round_ss" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1). [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-RETURN ( a[31:0] OP b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm {sae}" name="VCOMISS" xed="VCOMISS_XMMf32_XMMf32_AVX512" />
-	<instruction form="xmm, xmm {sae}" name="VUCOMISS" xed="VUCOMISS_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPEQQ" xed="VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpge_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpgt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPGTQ" xed="VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPEQQ" xed="VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpge_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpgt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPGTQ" xed="VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPQ" xed="VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpge_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpgt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpge_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpgt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &gt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt;= b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] &lt; b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_epu64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUQ" xed="VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTDQ2PD" xed="VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	IF k[j]
-		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-	ELSE
-		dst[m+63:m] := src[m+63:m]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTDQ2PD" xed="VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*64
-	IF k[j]
-		dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-	ELSE
-		dst[m+63:m] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTDQ2PD" xed="VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTDQ2PS" xed="VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {er}" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {er}" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {er}" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTPD2DQ" xed="VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {er}" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {er}" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {er}" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTPD2PS" xed="VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {er}" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {er}" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {er}" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTPD2UDQ" xed="VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP16" type="__m256i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {sae}" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP16" type="__m256i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {sae}" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {sae}" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTPH2PS" xed="VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTPS2DQ" xed="VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundps_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {sae}" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtps_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundps_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {sae}" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtps_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundps_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {sae}" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtps_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTPS2PD" xed="VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". [round2_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 32*j
-	dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". [round2_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 32*j
-	dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round2_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round2_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round2_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtps_ph" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round2_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 16*j
-	l := 32*j
-	IF k[j]
-		dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {sae}, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTPS2UDQ" xed="VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsd_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_Int32(a[63:0])
-	</operation>
-	<instruction form="r32, xmm {er}" name="VCVTSD2SI" xed="VCVTSD2SI_GPR32i32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsd_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64(a[63:0])
-	</operation>
-	<instruction form="r64, xmm {er}" name="VCVTSD2SI" xed="VCVTSD2SI_GPR64i64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsd_si32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_Int32(a[63:0])
-	</operation>
-	<instruction form="r32, xmm {er}" name="VCVTSD2SI" xed="VCVTSD2SI_GPR32i32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsd_si64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64(a[63:0])
-	</operation>
-	<instruction form="r64, xmm {er}" name="VCVTSD2SI" xed="VCVTSD2SI_GPR64i64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_Int32(a[63:0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTSD2SI" xed="VCVTSD2SI_GPR32i32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64(a[63:0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTSD2SI" xed="VCVTSD2SI_GPR64i64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_FP32(b[63:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvt_roundsd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := Convert_FP64_To_FP32(b[63:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := Convert_FP64_To_FP32(b[63:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvt_roundsd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := Convert_FP64_To_FP32(b[63:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsd_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := Convert_FP64_To_FP32(b[63:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VCVTSD2SS" xed="VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsd_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_UInt32(a[63:0])
-	</operation>
-	<instruction form="r32, xmm {er}" name="VCVTSD2USI" xed="VCVTSD2USI_GPR32u32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsd_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_UInt64(a[63:0])
-	</operation>
-	<instruction form="r64, xmm {er}" name="VCVTSD2USI" xed="VCVTSD2USI_GPR64u64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_UInt32(a[63:0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTSD2USI" xed="VCVTSD2USI_GPR32u32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_UInt64(a[63:0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTSD2USI" xed="VCVTSD2USI_GPR64u64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundi64_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_Int64_To_FP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SD" xed="VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsi64_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". 
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_Int64_To_FP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SD" xed="VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvti32_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<description>Convert the signed 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := Convert_Int32_To_FP64(b[31:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32" name="VCVTSI2SD" xed="VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvti64_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := Convert_Int64_To_FP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64" name="VCVTSI2SD" xed="VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundi32_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32 {er}" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundi64_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_Int64_To_FP32(b[63:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsi32_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32 {er}" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsi64_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_Int64_To_FP32(b[63:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvti32_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvti64_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<description>Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int64_To_FP32(b[63:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64" name="VCVTSI2SS" xed="VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundss_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". 
-	[sae_note]</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_FP64(b[31:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvt_roundss_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[sae_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := Convert_FP32_To_FP64(b[31:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtss_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := Convert_FP32_To_FP64(b[31:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvt_roundss_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". 
-	[sae_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := Convert_FP32_To_FP64(b[31:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtss_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := Convert_FP32_To_FP64(b[31:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VCVTSS2SD" xed="VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundss_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32(a[31:0])
-	</operation>
-	<instruction form="r32, xmm {er}" name="VCVTSS2SI" xed="VCVTSS2SI_GPR32i32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundss_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_Int64(a[31:0])
-	</operation>
-	<instruction form="r64, xmm {er}" name="VCVTSS2SI" xed="VCVTSS2SI_GPR64i64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundss_si32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32(a[31:0])
-	</operation>
-	<instruction form="r32, xmm {er}" name="VCVTSS2SI" xed="VCVTSS2SI_GPR32i32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundss_si64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_Int64(a[31:0])
-	</operation>
-	<instruction form="r64, xmm {er}" name="VCVTSS2SI" xed="VCVTSS2SI_GPR64i64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32(a[31:0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTSS2SI" xed="VCVTSS2SI_GPR32i32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_Int64(a[31:0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTSS2SI" xed="VCVTSS2SI_GPR64i64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundss_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_UInt32(a[31:0])
-	</operation>
-	<instruction form="r32, xmm {er}" name="VCVTSS2USI" xed="VCVTSS2USI_GPR32u32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundss_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_UInt64(a[31:0])
-	</operation>
-	<instruction form="r64, xmm {er}" name="VCVTSS2USI" xed="VCVTSS2USI_GPR64u64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_UInt32(a[31:0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTSS2USI" xed="VCVTSS2USI_GPR32u32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_UInt64(a[31:0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTSS2USI" xed="VCVTSS2USI_GPR64u64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".  [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {sae}" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {sae}" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {sae}" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttpd_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTTPD2DQ" xed="VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".  [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {sae}" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {sae}" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {sae}" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttpd_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 32*j
-	l := 64*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTTPD2UDQ" xed="VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".  [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttps_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTTPS2DQ" xed="VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".  [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttps_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTTPS2UDQ" xed="VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsd_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR32i32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsd_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
-	</operation>
-	<instruction form="r64, xmm {sae}" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR64i64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsd_si32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR32i32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsd_si64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
-	</operation>
-	<instruction form="r64, xmm {sae}" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR64i64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsd_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR32i32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsd_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTTSD2SI" xed="VCVTTSD2SI_GPR64i64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsd_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_UInt32_Truncate(a[63:0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTTSD2USI" xed="VCVTTSD2USI_GPR32u32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsd_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_UInt64_Truncate(a[63:0])
-	</operation>
-	<instruction form="r64, xmm {sae}" name="VCVTTSD2USI" xed="VCVTTSD2USI_GPR64u64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsd_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_UInt32_Truncate(a[63:0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTTSD2USI" xed="VCVTTSD2USI_GPR32u32_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsd_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_UInt64_Truncate(a[63:0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTTSD2USI" xed="VCVTTSD2USI_GPR64u64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundss_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR32i32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundss_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0])
-	</operation>
-	<instruction form="r64, xmm {sae}" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR64i64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundss_si32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR32i32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundss_si64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0])
-	</operation>
-	<instruction form="r64, xmm {sae}" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR64i64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttss_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR32i32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttss_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTTSS2SI" xed="VCVTTSS2SI_GPR64i64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundss_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_UInt32_Truncate(a[31:0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTTSS2USI" xed="VCVTTSS2USI_GPR32u32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundss_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".
-	[sae_note]</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_UInt64_Truncate(a[31:0])
-	</operation>
-	<instruction form="r64, xmm {sae}" name="VCVTTSS2USI" xed="VCVTTSS2USI_GPR64u64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttss_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_UInt32_Truncate(a[31:0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTTSS2USI" xed="VCVTTSS2USI_GPR32u32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttss_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_UInt64_Truncate(a[31:0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTTSS2USI" xed="VCVTTSS2USI_GPR64u64_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu32_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTUDQ2PD" xed="VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepu32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepu32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepu32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu32_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	IF k[j]
-		dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTUDQ2PS" xed="VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundu64_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the unsigned 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". 
-	[round_note]</description>
-	<operation>
-dst[63:0] := Convert_Int64_To_FP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64 {er}" name="VCVTUSI2SD" xed="VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtu32_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<description>Convert the unsigned 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := Convert_Int32_To_FP64(b[31:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32" name="VCVTUSI2SD" xed="VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtu64_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<description>Convert the unsigned 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := Convert_Int64_To_FP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64" name="VCVTUSI2SD" xed="VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundu32_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the unsigned 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32 {er}" name="VCVTUSI2SS" xed="VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundu64_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the unsigned 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". 
-	[round_note]</description>
-	<operation>
-dst[31:0] := Convert_Int64_To_FP32(b[63:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64 {er}" name="VCVTUSI2SS" xed="VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtu32_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<description>Convert the unsigned 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32" name="VCVTUSI2SS" xed="VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtu64_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<description>Convert the unsigned 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int64_To_FP32(b[63:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64" name="VCVTUSI2SS" xed="VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := Truncate8(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, zmm" name="VPMOVDB" xed="VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVDB" xed="VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := Truncate16(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVDW" xed="VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVDW" xed="VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVDW" xed="VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVDW" xed="VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := Truncate8(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, zmm" name="VPMOVQB" xed="VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Truncate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVQB" xed="VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := Truncate32(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVQD" xed="VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Truncate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVQD" xed="VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI32" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVQD" xed="VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Truncate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVQD" xed="VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := Truncate16(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, zmm" name="VPMOVQW" xed="VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Truncate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVQW" xed="VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := Saturate8(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, zmm" name="VPMOVSDB" xed="VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtsepi32_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVSDB" xed="VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := Saturate16(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVSDW" xed="VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVSDW" xed="VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI16" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVSDW" xed="VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtsepi32_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVSDW" xed="VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := Saturate8(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, zmm" name="VPMOVSQB" xed="VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtsepi64_epi8" tech="AVX-512">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := Saturate8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVSQB" xed="VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := Saturate32(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVSQD" xed="VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Saturate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVSQD" xed="VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI32" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVSQD" xed="VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtsepi64_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := Saturate32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVSQD" xed="VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := Saturate16(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtsepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="SI16" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, zmm" name="VPMOVSQW" xed="VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtsepi64_epi16" tech="AVX-512">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := Saturate16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVSQW" xed="VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi8_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 8*j
-	dst[i+31:i] := SignExtend32(a[k+7:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi8_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi8_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPMOVSXBD" xed="VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi8_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 8*j
-	dst[i+63:i] := SignExtend64(a[k+7:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi8_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi8_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPMOVSXBQ" xed="VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi32_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := SignExtend64(a[k+31:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VPMOVSXDQ" xed="VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VPMOVSXDQ" xed="VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi32_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VPMOVSXDQ" xed="VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi16_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 16*j
-	dst[i+31:i] := SignExtend32(a[k+15:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VPMOVSXWD" xed="VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi16_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	l := j*16
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VPMOVSXWD" xed="VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi16_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := SignExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VPMOVSXWD" xed="VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi16_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 16*j
-	dst[i+63:i] := SignExtend64(a[k+15:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi16_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi16_epi64" tech="AVX-512">
-	<return etype="SI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := SignExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPMOVSXWQ" xed="VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 8*j
-	dst[k+7:k] := SaturateU8(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi32_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, zmm" name="VPMOVUSDB" xed="VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtusepi32_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+31:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVUSDB" xed="VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 16*j
-	dst[k+15:k] := SaturateU16(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVUSDW" xed="VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVUSDW" xed="VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi32_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVUSDW" xed="VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtusepi32_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+31:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVUSDW" xed="VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 8*j
-	dst[k+7:k] := SaturateU8(a[i+63:i])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := src[l+7:l]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi64_storeu_epi8" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m64 {k}, zmm" name="VPMOVUSQB" xed="VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtusepi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[l+7:l] := SaturateU8(a[i+63:i])
-	ELSE
-		dst[l+7:l] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVUSQB" xed="VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 32*j
-	dst[k+31:k] := SaturateU32(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VPMOVUSQD" xed="VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := SaturateU32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VPMOVUSQD" xed="VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi64_storeu_epi32" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI32" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, zmm" name="VPMOVUSQD" xed="VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtusepi64_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[l+31:l] := SaturateU32(a[i+63:i])
-	ELSE
-		dst[l+31:l] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VPMOVUSQD" xed="VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 16*j
-	dst[k+15:k] := SaturateU16(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := src[l+15:l]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtusepi64_storeu_epi16" tech="AVX-512">
-	<category>Store</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, zmm" name="VPMOVUSQW" xed="VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtusepi64_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[l+15:l] := SaturateU16(a[i+63:i])
-	ELSE
-		dst[l+15:l] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VPMOVUSQW" xed="VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 8*j
-	dst[i+31:i] := ZeroExtend32(a[k+7:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu8_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 8*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+7:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPMOVZXBD" xed="VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu8_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 8*j
-	dst[i+63:i] := ZeroExtend64(a[k+7:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu8_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu8_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 8*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+7:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPMOVZXBQ" xed="VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu32_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := ZeroExtend64(a[k+31:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VPMOVZXDQ" xed="VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu32_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+31:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VPMOVZXDQ" xed="VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu32_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 32*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+31:l])
-	ELSE 
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VPMOVZXDQ" xed="VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu16_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	k := 16*j
-	dst[i+31:i] := ZeroExtend32(a[k+15:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VPMOVZXWD" xed="VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu16_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VPMOVZXWD" xed="VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu16_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := 32*j
-	l := 16*j
-	IF k[j]
-		dst[i+31:i] := ZeroExtend32(a[l+15:l])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VPMOVZXWD" xed="VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu16_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	k := 16*j
-	dst[i+63:i] := ZeroExtend64(a[k+15:k])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu16_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu16_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := 64*j
-	l := 16*j
-	IF k[j]
-		dst[i+63:i] := ZeroExtend64(a[l+15:l])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VPMOVZXWQ" xed="VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtss_f32" tech="AVX-512" vexEq="TRUE">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-	</operation>
-	<instruction form="m32, xmm" name="VMOVSS" xed="VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsd_f64" tech="AVX-512" vexEq="TRUE">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="m64, xmm" name="VMOVSD" xed="VMOVSD_MEMq_XMMq" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsi512_si32" tech="AVX-512" vexEq="TRUE">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-	</operation>
-	<instruction form="r32, xmm" name="VMOVD" xed="VMOVD_GPR32u32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".  [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {sae}" name="VMAXPD" xed="VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst".  [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {sae}" name="VMAXPS" xed="VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note][max_float_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MAX(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MAX(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note][max_float_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MAX(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MAX(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [sae_note][max_float_note]</description>
-	<operation>
-dst[63:0] := MAX(a[63:0], b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VMAXSD" xed="VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MAX(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MAX(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MAX(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MAX(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
-	<operation>
-dst[31:0] := MAX(a[31:0], b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VMAXSS" xed="VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note][min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note][min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".  [sae_note][min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {sae}" name="VMINPD" xed="VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).   [sae_note][min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note][min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst".  [sae_note][min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {sae}" name="VMINPS" xed="VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note][min_float_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MIN(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MIN(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note][min_float_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MIN(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := MIN(a[63:0], b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" , and copy the upper element from "a" to the upper element of "dst". [sae_note][min_float_note]</description>
-	<operation>
-dst[63:0] := MIN(a[63:0], b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VMINSD" xed="VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MIN(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MIN(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MIN(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := MIN(a[31:0], b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
-	<operation>
-dst[31:0] := MIN(a[31:0], b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VMINSS" xed="VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_abs_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ABS(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPABSD" xed="VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_abs_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ABS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPABSD" xed="VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_abs_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ABS(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPABSD" xed="VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ABS(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPABSQ" xed="VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ABS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPABSQ" xed="VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_abs_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ABS(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPABSQ" xed="VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0 
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMAXSD" xed="VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMAXSQ" xed="VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMAXSQ" xed="VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMAXSQ" xed="VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMAXUD" xed="VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMAXUQ" xed="VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMAXUQ" xed="VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMAXUQ" xed="VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMINSD" xed="VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMINSQ" xed="VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMINSQ" xed="VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="SI64" type="__m512i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMINSQ" xed="VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMINUD" xed="VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMINUQ" xed="VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMINUQ" xed="VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMINUQ" xed="VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mov_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mov_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_movedup_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[63:0] := a[63:0]
-tmp[127:64] := a[63:0]
-tmp[191:128] := a[191:128]
-tmp[255:192] := a[191:128]
-tmp[319:256] := a[319:256] 
-tmp[383:320] := a[319:256] 
-tmp[447:384] := a[447:384]
-tmp[511:448] := a[447:384]
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVDDUP" xed="VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_movedup_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[63:0] := a[63:0]
-tmp[127:64] := a[63:0]
-tmp[191:128] := a[191:128]
-tmp[255:192] := a[191:128]
-tmp[319:256] := a[319:256] 
-tmp[383:320] := a[319:256] 
-tmp[447:384] := a[447:384]
-tmp[511:448] := a[447:384]
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := tmp[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVDDUP" xed="VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movedup_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := a[63:0]
-dst[191:128] := a[191:128]
-dst[255:192] := a[191:128]
-dst[319:256] := a[319:256]
-dst[383:320] := a[319:256]
-dst[447:384] := a[447:384]
-dst[511:448] := a[447:384]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VMOVDDUP" xed="VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mov_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mov_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_move_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := b[63:0]
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMOVSD" xed="VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_move_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := b[63:0]
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMOVSD" xed="VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_movehdup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[63:32] 
-tmp[63:32] := a[63:32] 
-tmp[95:64] := a[127:96] 
-tmp[127:96] := a[127:96]
-tmp[159:128] := a[191:160] 
-tmp[191:160] := a[191:160] 
-tmp[223:192] := a[255:224] 
-tmp[255:224] := a[255:224]
-tmp[287:256] := a[319:288] 
-tmp[319:288] := a[319:288] 
-tmp[351:320] := a[383:352] 
-tmp[383:352] := a[383:352] 
-tmp[415:384] := a[447:416] 
-tmp[447:416] := a[447:416] 
-tmp[479:448] := a[511:480]
-tmp[511:480] := a[511:480]
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVSHDUP" xed="VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_movehdup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[63:32] 
-tmp[63:32] := a[63:32] 
-tmp[95:64] := a[127:96] 
-tmp[127:96] := a[127:96]
-tmp[159:128] := a[191:160] 
-tmp[191:160] := a[191:160] 
-tmp[223:192] := a[255:224] 
-tmp[255:224] := a[255:224]
-tmp[287:256] := a[319:288] 
-tmp[319:288] := a[319:288] 
-tmp[351:320] := a[383:352] 
-tmp[383:352] := a[383:352] 
-tmp[415:384] := a[447:416] 
-tmp[447:416] := a[447:416] 
-tmp[479:448] := a[511:480]
-tmp[511:480] := a[511:480]
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVSHDUP" xed="VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_movehdup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32] 
-dst[63:32] := a[63:32] 
-dst[95:64] := a[127:96] 
-dst[127:96] := a[127:96]
-dst[159:128] := a[191:160] 
-dst[191:160] := a[191:160] 
-dst[223:192] := a[255:224] 
-dst[255:224] := a[255:224]
-dst[287:256] := a[319:288] 
-dst[319:288] := a[319:288] 
-dst[351:320] := a[383:352] 
-dst[383:352] := a[383:352] 
-dst[415:384] := a[447:416] 
-dst[447:416] := a[447:416] 
-dst[479:448] := a[511:480]
-dst[511:480] := a[511:480]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VMOVSHDUP" xed="VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_moveldup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[31:0] 
-tmp[63:32] := a[31:0] 
-tmp[95:64] := a[95:64] 
-tmp[127:96] := a[95:64]
-tmp[159:128] := a[159:128] 
-tmp[191:160] := a[159:128] 
-tmp[223:192] := a[223:192] 
-tmp[255:224] := a[223:192]
-tmp[287:256] := a[287:256] 
-tmp[319:288] := a[287:256] 
-tmp[351:320] := a[351:320] 
-tmp[383:352] := a[351:320] 
-tmp[415:384] := a[415:384] 
-tmp[447:416] := a[415:384] 
-tmp[479:448] := a[479:448]
-tmp[511:480] := a[479:448]
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVSLDUP" xed="VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_moveldup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-tmp[31:0] := a[31:0] 
-tmp[63:32] := a[31:0] 
-tmp[95:64] := a[95:64] 
-tmp[127:96] := a[95:64]
-tmp[159:128] := a[159:128] 
-tmp[191:160] := a[159:128] 
-tmp[223:192] := a[223:192] 
-tmp[255:224] := a[223:192]
-tmp[287:256] := a[287:256] 
-tmp[319:288] := a[287:256] 
-tmp[351:320] := a[351:320] 
-tmp[383:352] := a[351:320] 
-tmp[415:384] := a[415:384] 
-tmp[447:416] := a[415:384] 
-tmp[479:448] := a[479:448]
-tmp[511:480] := a[479:448]
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VMOVSLDUP" xed="VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_moveldup_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] 
-dst[63:32] := a[31:0] 
-dst[95:64] := a[95:64] 
-dst[127:96] := a[95:64]
-dst[159:128] := a[159:128] 
-dst[191:160] := a[159:128] 
-dst[223:192] := a[223:192] 
-dst[255:224] := a[223:192]
-dst[287:256] := a[287:256] 
-dst[319:288] := a[287:256] 
-dst[351:320] := a[351:320] 
-dst[383:352] := a[351:320] 
-dst[415:384] := a[415:384] 
-dst[447:416] := a[415:384] 
-dst[479:448] := a[479:448]
-dst[511:480] := a[479:448]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VMOVSLDUP" xed="VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_move_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := b[31:0]
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMOVSS" xed="VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_move_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := b[31:0]
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMOVSS" xed="VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_and_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] AND b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_andnot_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPANDND" xed="VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_andnot_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPANDNQ" xed="VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_and_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPORD" xed="VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPORQ" xed="VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		FOR h := 0 to 31
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		FOR h := 0 to 31
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_ternarylogic_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 15
-	i := j*32
-	FOR h := 0 to 31
-		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPTERNLOGD" xed="VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		FOR h := 0 to 63
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		FOR h := 0 to 63
-			dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-		ENDFOR
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_ternarylogic_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used according to "imm8", and the result is written to the corresponding bit in "dst".</description>
-	<operation>
-DEFINE TernaryOP(imm8, a, b, c) {
-	CASE imm8[7:0] OF
-	0: dst[0] := 0                   // imm8[7:0] := 0
-	1: dst[0] := NOT (a OR b OR c)   // imm8[7:0] := NOT (_MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C)
-	// ...
-	254: dst[0] := a OR b OR c       // imm8[7:0] := _MM_TERNLOG_A OR _MM_TERNLOG_B OR _MM_TERNLOG_C
-	255: dst[0] := 1                 // imm8[7:0] := 1
-	ESAC
-}
-imm8[7:0] = LogicExp(_MM_TERNLOG_A, _MM_TERNLOG_B, _MM_TERNLOG_C)
-FOR j := 0 to 7
-	i := j*64
-	FOR h := 0 to 63
-		dst[i+h] := TernaryOP(imm8[7:0], a[i+h], b[i+h], c[i+h])
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPTERNLOGQ" xed="VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_test_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_test_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPTESTMQ" xed="VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_testn_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_testn_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPTESTNMD" xed="VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_testn_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_testn_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPTESTNMQ" xed="VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPXORD" xed="VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set1_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := a[7:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, r8" name="VPBROADCASTB" xed="VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_set1_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_set1_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[31:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, r32" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set1_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, r32" name="VPBROADCASTD" xed="VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_set1_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_set1_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[63:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set1_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, r64" name="VPBROADCASTQ" xed="VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set1_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast the low packed 16-bit integer from "a" to all all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := a[15:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, r16" name="VPBROADCASTW" xed="VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set1_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="a" />
-	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set1_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set4_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="d" />
-	<parameter etype="UI32" type="int" varname="c" />
-	<parameter etype="UI32" type="int" varname="b" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Set packed 32-bit integers in "dst" with the repeated 4 element sequence.</description>
-	<operation>
-dst[31:0] := a
-dst[63:32] := b
-dst[95:64] := c
-dst[127:96] := d
-dst[159:128] := a
-dst[191:160] := b
-dst[223:192] := c
-dst[255:224] := d
-dst[287:256] := a
-dst[319:288] := b
-dst[351:320] := c
-dst[383:352] := d
-dst[415:384] := a
-dst[447:416] := b
-dst[479:448] := c
-dst[511:480] := d
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set4_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="d" />
-	<parameter etype="UI64" type="__int64" varname="c" />
-	<parameter etype="UI64" type="__int64" varname="b" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Set packed 64-bit integers in "dst" with the repeated 4 element sequence.</description>
-	<operation>
-dst[63:0] := a
-dst[127:64] := b
-dst[191:128] := c
-dst[255:192] := d
-dst[319:256] := a
-dst[383:320] := b
-dst[447:384] := c
-dst[511:448] := d
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set4_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="d" />
-	<parameter etype="FP64" type="double" varname="c" />
-	<parameter etype="FP64" type="double" varname="b" />
-	<parameter etype="FP64" type="double" varname="a" />
-	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the repeated 4 element sequence.</description>
-	<operation>
-dst[63:0] := a
-dst[127:64] := b
-dst[191:128] := c
-dst[255:192] := d
-dst[319:256] := a
-dst[383:320] := b
-dst[447:384] := c
-dst[511:448] := d
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set4_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="float" varname="d" />
-	<parameter etype="FP32" type="float" varname="c" />
-	<parameter etype="FP32" type="float" varname="b" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the repeated 4 element sequence.</description>
-	<operation>
-dst[31:0] := a
-dst[63:32] := b
-dst[95:64] := c
-dst[127:96] := d
-dst[159:128] := a
-dst[191:160] := b
-dst[223:192] := c
-dst[255:224] := d
-dst[287:256] := a
-dst[319:288] := b
-dst[351:320] := c
-dst[383:352] := d
-dst[415:384] := a
-dst[447:416] := b
-dst[479:448] := c
-dst[511:480] := d
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set_epi8" sequence="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="char" varname="e63" />
-	<parameter etype="UI8" type="char" varname="e62" />
-	<parameter etype="UI8" type="char" varname="e61" />
-	<parameter etype="UI8" type="char" varname="e60" />
-	<parameter etype="UI8" type="char" varname="e59" />
-	<parameter etype="UI8" type="char" varname="e58" />
-	<parameter etype="UI8" type="char" varname="e57" />
-	<parameter etype="UI8" type="char" varname="e56" />
-	<parameter etype="UI8" type="char" varname="e55" />
-	<parameter etype="UI8" type="char" varname="e54" />
-	<parameter etype="UI8" type="char" varname="e53" />
-	<parameter etype="UI8" type="char" varname="e52" />
-	<parameter etype="UI8" type="char" varname="e51" />
-	<parameter etype="UI8" type="char" varname="e50" />
-	<parameter etype="UI8" type="char" varname="e49" />
-	<parameter etype="UI8" type="char" varname="e48" />
-	<parameter etype="UI8" type="char" varname="e47" />
-	<parameter etype="UI8" type="char" varname="e46" />
-	<parameter etype="UI8" type="char" varname="e45" />
-	<parameter etype="UI8" type="char" varname="e44" />
-	<parameter etype="UI8" type="char" varname="e43" />
-	<parameter etype="UI8" type="char" varname="e42" />
-	<parameter etype="UI8" type="char" varname="e41" />
-	<parameter etype="UI8" type="char" varname="e40" />
-	<parameter etype="UI8" type="char" varname="e39" />
-	<parameter etype="UI8" type="char" varname="e38" />
-	<parameter etype="UI8" type="char" varname="e37" />
-	<parameter etype="UI8" type="char" varname="e36" />
-	<parameter etype="UI8" type="char" varname="e35" />
-	<parameter etype="UI8" type="char" varname="e34" />
-	<parameter etype="UI8" type="char" varname="e33" />
-	<parameter etype="UI8" type="char" varname="e32" />
-	<parameter etype="UI8" type="char" varname="e31" />
-	<parameter etype="UI8" type="char" varname="e30" />
-	<parameter etype="UI8" type="char" varname="e29" />
-	<parameter etype="UI8" type="char" varname="e28" />
-	<parameter etype="UI8" type="char" varname="e27" />
-	<parameter etype="UI8" type="char" varname="e26" />
-	<parameter etype="UI8" type="char" varname="e25" />
-	<parameter etype="UI8" type="char" varname="e24" />
-	<parameter etype="UI8" type="char" varname="e23" />
-	<parameter etype="UI8" type="char" varname="e22" />
-	<parameter etype="UI8" type="char" varname="e21" />
-	<parameter etype="UI8" type="char" varname="e20" />
-	<parameter etype="UI8" type="char" varname="e19" />
-	<parameter etype="UI8" type="char" varname="e18" />
-	<parameter etype="UI8" type="char" varname="e17" />
-	<parameter etype="UI8" type="char" varname="e16" />
-	<parameter etype="UI8" type="char" varname="e15" />
-	<parameter etype="UI8" type="char" varname="e14" />
-	<parameter etype="UI8" type="char" varname="e13" />
-	<parameter etype="UI8" type="char" varname="e12" />
-	<parameter etype="UI8" type="char" varname="e11" />
-	<parameter etype="UI8" type="char" varname="e10" />
-	<parameter etype="UI8" type="char" varname="e9" />
-	<parameter etype="UI8" type="char" varname="e8" />
-	<parameter etype="UI8" type="char" varname="e7" />
-	<parameter etype="UI8" type="char" varname="e6" />
-	<parameter etype="UI8" type="char" varname="e5" />
-	<parameter etype="UI8" type="char" varname="e4" />
-	<parameter etype="UI8" type="char" varname="e3" />
-	<parameter etype="UI8" type="char" varname="e2" />
-	<parameter etype="UI8" type="char" varname="e1" />
-	<parameter etype="UI8" type="char" varname="e0" />
-	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[7:0] := e0
-dst[15:8] := e1
-dst[23:16] := e2
-dst[31:24] := e3
-dst[39:32] := e4
-dst[47:40] := e5
-dst[55:48] := e6
-dst[63:56] := e7
-dst[71:64] := e8
-dst[79:72] := e9
-dst[87:80] := e10
-dst[95:88] := e11
-dst[103:96] := e12
-dst[111:104] := e13
-dst[119:112] := e14
-dst[127:120] := e15
-dst[135:128] := e16
-dst[143:136] := e17
-dst[151:144] := e18
-dst[159:152] := e19
-dst[167:160] := e20
-dst[175:168] := e21
-dst[183:176] := e22
-dst[191:184] := e23
-dst[199:192] := e24
-dst[207:200] := e25
-dst[215:208] := e26
-dst[223:216] := e27
-dst[231:224] := e28
-dst[239:232] := e29
-dst[247:240] := e30
-dst[255:248] := e31
-dst[263:256] := e32
-dst[271:264] := e33
-dst[279:272] := e34
-dst[287:280] := e35
-dst[295:288] := e36
-dst[303:296] := e37
-dst[311:304] := e38
-dst[319:312] := e39
-dst[327:320] := e40
-dst[335:328] := e41
-dst[343:336] := e42
-dst[351:344] := e43
-dst[359:352] := e44
-dst[367:360] := e45
-dst[375:368] := e46
-dst[383:376] := e47
-dst[391:384] := e48
-dst[399:392] := e49
-dst[407:400] := e50
-dst[415:408] := e51
-dst[423:416] := e52
-dst[431:424] := e53
-dst[439:432] := e54
-dst[447:440] := e55
-dst[455:448] := e56
-dst[463:456] := e57
-dst[471:464] := e58
-dst[479:472] := e59
-dst[487:480] := e60
-dst[495:488] := e61
-dst[503:496] := e62
-dst[511:504] := e63
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set_epi16" sequence="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="e31" />
-	<parameter etype="UI16" type="short" varname="e30" />
-	<parameter etype="UI16" type="short" varname="e29" />
-	<parameter etype="UI16" type="short" varname="e28" />
-	<parameter etype="UI16" type="short" varname="e27" />
-	<parameter etype="UI16" type="short" varname="e26" />
-	<parameter etype="UI16" type="short" varname="e25" />
-	<parameter etype="UI16" type="short" varname="e24" />
-	<parameter etype="UI16" type="short" varname="e23" />
-	<parameter etype="UI16" type="short" varname="e22" />
-	<parameter etype="UI16" type="short" varname="e21" />
-	<parameter etype="UI16" type="short" varname="e20" />
-	<parameter etype="UI16" type="short" varname="e19" />
-	<parameter etype="UI16" type="short" varname="e18" />
-	<parameter etype="UI16" type="short" varname="e17" />
-	<parameter etype="UI16" type="short" varname="e16" />
-	<parameter etype="UI16" type="short" varname="e15" />
-	<parameter etype="UI16" type="short" varname="e14" />
-	<parameter etype="UI16" type="short" varname="e13" />
-	<parameter etype="UI16" type="short" varname="e12" />
-	<parameter etype="UI16" type="short" varname="e11" />
-	<parameter etype="UI16" type="short" varname="e10" />
-	<parameter etype="UI16" type="short" varname="e9" />
-	<parameter etype="UI16" type="short" varname="e8" />
-	<parameter etype="UI16" type="short" varname="e7" />
-	<parameter etype="UI16" type="short" varname="e6" />
-	<parameter etype="UI16" type="short" varname="e5" />
-	<parameter etype="UI16" type="short" varname="e4" />
-	<parameter etype="UI16" type="short" varname="e3" />
-	<parameter etype="UI16" type="short" varname="e2" />
-	<parameter etype="UI16" type="short" varname="e1" />
-	<parameter etype="UI16" type="short" varname="e0" />
-	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[15:0] := e0
-dst[31:16] := e1
-dst[47:32] := e2
-dst[63:48] := e3
-dst[79:64] := e4
-dst[95:80] := e5
-dst[111:96] := e6
-dst[127:112] := e7
-dst[143:128] := e8
-dst[159:144] := e9
-dst[175:160] := e10
-dst[191:176] := e11
-dst[207:192] := e12
-dst[223:208] := e13
-dst[239:224] := e14
-dst[255:240] := e15
-dst[271:256] := e16
-dst[287:272] := e17
-dst[303:288] := e18
-dst[319:304] := e19
-dst[335:320] := e20
-dst[351:336] := e21
-dst[367:352] := e22
-dst[383:368] := e23
-dst[399:384] := e24
-dst[415:400] := e25
-dst[431:416] := e26
-dst[447:432] := e27
-dst[463:448] := e28
-dst[479:464] := e29
-dst[495:480] := e30
-dst[511:496] := e31
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="e15" />
-	<parameter etype="UI32" type="int" varname="e14" />
-	<parameter etype="UI32" type="int" varname="e13" />
-	<parameter etype="UI32" type="int" varname="e12" />
-	<parameter etype="UI32" type="int" varname="e11" />
-	<parameter etype="UI32" type="int" varname="e10" />
-	<parameter etype="UI32" type="int" varname="e9" />
-	<parameter etype="UI32" type="int" varname="e8" />
-	<parameter etype="UI32" type="int" varname="e7" />
-	<parameter etype="UI32" type="int" varname="e6" />
-	<parameter etype="UI32" type="int" varname="e5" />
-	<parameter etype="UI32" type="int" varname="e4" />
-	<parameter etype="UI32" type="int" varname="e3" />
-	<parameter etype="UI32" type="int" varname="e2" />
-	<parameter etype="UI32" type="int" varname="e1" />
-	<parameter etype="UI32" type="int" varname="e0" />
-	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[31:0] := e0
-dst[63:32] := e1
-dst[95:64] := e2
-dst[127:96] := e3
-dst[159:128] := e4
-dst[191:160] := e5
-dst[223:192] := e6
-dst[255:224] := e7
-dst[287:256] := e8
-dst[319:288] := e9
-dst[351:320] := e10
-dst[383:352] := e11
-dst[415:384] := e12
-dst[447:416] := e13
-dst[479:448] := e14
-dst[511:480] := e15
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="e7" />
-	<parameter etype="UI64" type="__int64" varname="e6" />
-	<parameter etype="UI64" type="__int64" varname="e5" />
-	<parameter etype="UI64" type="__int64" varname="e4" />
-	<parameter etype="UI64" type="__int64" varname="e3" />
-	<parameter etype="UI64" type="__int64" varname="e2" />
-	<parameter etype="UI64" type="__int64" varname="e1" />
-	<parameter etype="UI64" type="__int64" varname="e0" />
-	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[63:0] := e0
-dst[127:64] := e1
-dst[191:128] := e2
-dst[255:192] := e3
-dst[319:256] := e4
-dst[383:320] := e5
-dst[447:384] := e6
-dst[511:448] := e7
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="e7" />
-	<parameter etype="FP64" type="double" varname="e6" />
-	<parameter etype="FP64" type="double" varname="e5" />
-	<parameter etype="FP64" type="double" varname="e4" />
-	<parameter etype="FP64" type="double" varname="e3" />
-	<parameter etype="FP64" type="double" varname="e2" />
-	<parameter etype="FP64" type="double" varname="e1" />
-	<parameter etype="FP64" type="double" varname="e0" />
-	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst[63:0] := e0
-dst[127:64] := e1
-dst[191:128] := e2
-dst[255:192] := e3
-dst[319:256] := e4
-dst[383:320] := e5
-dst[447:384] := e6
-dst[511:448] := e7
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="float" varname="e15" />
-	<parameter etype="FP32" type="float" varname="e14" />
-	<parameter etype="FP32" type="float" varname="e13" />
-	<parameter etype="FP32" type="float" varname="e12" />
-	<parameter etype="FP32" type="float" varname="e11" />
-	<parameter etype="FP32" type="float" varname="e10" />
-	<parameter etype="FP32" type="float" varname="e9" />
-	<parameter etype="FP32" type="float" varname="e8" />
-	<parameter etype="FP32" type="float" varname="e7" />
-	<parameter etype="FP32" type="float" varname="e6" />
-	<parameter etype="FP32" type="float" varname="e5" />
-	<parameter etype="FP32" type="float" varname="e4" />
-	<parameter etype="FP32" type="float" varname="e3" />
-	<parameter etype="FP32" type="float" varname="e2" />
-	<parameter etype="FP32" type="float" varname="e1" />
-	<parameter etype="FP32" type="float" varname="e0" />
-	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst[31:0] := e0
-dst[63:32] := e1
-dst[95:64] := e2
-dst[127:96] := e3
-dst[159:128] := e4
-dst[191:160] := e5
-dst[223:192] := e6
-dst[255:224] := e7
-dst[287:256] := e8
-dst[319:288] := e9
-dst[351:320] := e10
-dst[383:352] := e11
-dst[415:384] := e12
-dst[447:416] := e13
-dst[479:448] := e14
-dst[511:480] := e15
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr4_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="d" />
-	<parameter etype="UI32" type="int" varname="c" />
-	<parameter etype="UI32" type="int" varname="b" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Set packed 32-bit integers in "dst" with the repeated 4 element sequence in reverse order.</description>
-	<operation>
-dst[31:0] := d
-dst[63:32] := c
-dst[95:64] := b
-dst[127:96] := a
-dst[159:128] := d
-dst[191:160] := c
-dst[223:192] := b
-dst[255:224] := a
-dst[287:256] := d
-dst[319:288] := c
-dst[351:320] := b
-dst[383:352] := a
-dst[415:384] := d
-dst[447:416] := c
-dst[479:448] := b
-dst[511:480] := a
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr4_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="d" />
-	<parameter etype="UI64" type="__int64" varname="c" />
-	<parameter etype="UI64" type="__int64" varname="b" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Set packed 64-bit integers in "dst" with the repeated 4 element sequence in reverse order.</description>
-	<operation>
-dst[63:0] := d
-dst[127:64] := c
-dst[191:128] := b
-dst[255:192] := a
-dst[319:256] := d
-dst[383:320] := c
-dst[447:384] := b
-dst[511:448] := a
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr4_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="d" />
-	<parameter etype="FP64" type="double" varname="c" />
-	<parameter etype="FP64" type="double" varname="b" />
-	<parameter etype="FP64" type="double" varname="a" />
-	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the repeated 4 element sequence in reverse order.</description>
-	<operation>
-dst[63:0] := d
-dst[127:64] := c
-dst[191:128] := b
-dst[255:192] := a
-dst[319:256] := d
-dst[383:320] := c
-dst[447:384] := b
-dst[511:448] := a
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr4_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="float" varname="d" />
-	<parameter etype="FP32" type="float" varname="c" />
-	<parameter etype="FP32" type="float" varname="b" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the repeated 4 element sequence in reverse order.</description>
-	<operation>
-dst[31:0] := d
-dst[63:32] := c
-dst[95:64] := b
-dst[127:96] := a
-dst[159:128] := d
-dst[191:160] := c
-dst[223:192] := b
-dst[255:224] := a
-dst[287:256] := d
-dst[319:288] := c
-dst[351:320] := b
-dst[383:352] := a
-dst[415:384] := d
-dst[447:416] := c
-dst[479:448] := b
-dst[511:480] := a
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="e15" />
-	<parameter etype="UI32" type="int" varname="e14" />
-	<parameter etype="UI32" type="int" varname="e13" />
-	<parameter etype="UI32" type="int" varname="e12" />
-	<parameter etype="UI32" type="int" varname="e11" />
-	<parameter etype="UI32" type="int" varname="e10" />
-	<parameter etype="UI32" type="int" varname="e9" />
-	<parameter etype="UI32" type="int" varname="e8" />
-	<parameter etype="UI32" type="int" varname="e7" />
-	<parameter etype="UI32" type="int" varname="e6" />
-	<parameter etype="UI32" type="int" varname="e5" />
-	<parameter etype="UI32" type="int" varname="e4" />
-	<parameter etype="UI32" type="int" varname="e3" />
-	<parameter etype="UI32" type="int" varname="e2" />
-	<parameter etype="UI32" type="int" varname="e1" />
-	<parameter etype="UI32" type="int" varname="e0" />
-	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[31:0] := e15
-dst[63:32] := e14
-dst[95:64] := e13
-dst[127:96] := e12
-dst[159:128] := e11
-dst[191:160] := e10
-dst[223:192] := e9
-dst[255:224] := e8
-dst[287:256] := e7
-dst[319:288] := e6
-dst[351:320] := e5
-dst[383:352] := e4
-dst[415:384] := e3
-dst[447:416] := e2
-dst[479:448] := e1
-dst[511:480] := e0
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="e7" />
-	<parameter etype="UI64" type="__int64" varname="e6" />
-	<parameter etype="UI64" type="__int64" varname="e5" />
-	<parameter etype="UI64" type="__int64" varname="e4" />
-	<parameter etype="UI64" type="__int64" varname="e3" />
-	<parameter etype="UI64" type="__int64" varname="e2" />
-	<parameter etype="UI64" type="__int64" varname="e1" />
-	<parameter etype="UI64" type="__int64" varname="e0" />
-	<description>Set packed 64-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[63:0] := e7
-dst[127:64] := e6
-dst[191:128] := e5
-dst[255:192] := e4
-dst[319:256] := e3
-dst[383:320] := e2
-dst[447:384] := e1
-dst[511:448] := e0
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="e7" />
-	<parameter etype="FP64" type="double" varname="e6" />
-	<parameter etype="FP64" type="double" varname="e5" />
-	<parameter etype="FP64" type="double" varname="e4" />
-	<parameter etype="FP64" type="double" varname="e3" />
-	<parameter etype="FP64" type="double" varname="e2" />
-	<parameter etype="FP64" type="double" varname="e1" />
-	<parameter etype="FP64" type="double" varname="e0" />
-	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[63:0] := e7
-dst[127:64] := e6
-dst[191:128] := e5
-dst[255:192] := e4
-dst[319:256] := e3
-dst[383:320] := e2
-dst[447:384] := e1
-dst[511:448] := e0
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="float" varname="e15" />
-	<parameter etype="FP32" type="float" varname="e14" />
-	<parameter etype="FP32" type="float" varname="e13" />
-	<parameter etype="FP32" type="float" varname="e12" />
-	<parameter etype="FP32" type="float" varname="e11" />
-	<parameter etype="FP32" type="float" varname="e10" />
-	<parameter etype="FP32" type="float" varname="e9" />
-	<parameter etype="FP32" type="float" varname="e8" />
-	<parameter etype="FP32" type="float" varname="e7" />
-	<parameter etype="FP32" type="float" varname="e6" />
-	<parameter etype="FP32" type="float" varname="e5" />
-	<parameter etype="FP32" type="float" varname="e4" />
-	<parameter etype="FP32" type="float" varname="e3" />
-	<parameter etype="FP32" type="float" varname="e2" />
-	<parameter etype="FP32" type="float" varname="e1" />
-	<parameter etype="FP32" type="float" varname="e0" />
-	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[31:0] := e15
-dst[63:32] := e14
-dst[95:64] := e13
-dst[127:96] := e12
-dst[159:128] := e11
-dst[191:160] := e10
-dst[223:192] := e9
-dst[255:224] := e8
-dst[287:256] := e7
-dst[319:288] := e6
-dst[351:320] := e5
-dst[383:352] := e4
-dst[415:384] := e3
-dst[447:416] := e2
-dst[479:448] := e1
-dst[511:480] := e0
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setzero" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m512 with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setzero_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<description>Return vector of type __m512i with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setzero_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<description>Return vector of type __m512d with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setzero_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<description>Return vector of type __m512 with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setzero_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<description>Return vector of type __m512i with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPROLD" xed="VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPROLD" xed="VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rol_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPROLD" xed="VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPROLQ" xed="VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPROLQ" xed="VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rol_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPROLQ" xed="VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPROLVD" xed="VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPROLVD" xed="VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rolv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPROLVD" xed="VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPROLVQ" xed="VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPROLVQ" xed="VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rolv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE LEFT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &lt;&lt; count) OR (src &gt;&gt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPROLVQ" xed="VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPRORD" xed="VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPRORD" xed="VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_ror_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPRORD" xed="VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPRORQ" xed="VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPRORQ" xed="VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_ror_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPRORQ" xed="VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPRORVD" xed="VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rorv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_DWORDS(src, count_src) {
-	count := count_src % 32
-	RETURN (src &gt;&gt;count) OR (src &lt;&lt; (32 - count))
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPRORVD" xed="VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPRORVQ" xed="VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPRORVQ" xed="VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rorv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst".</description>
-	<operation>
-DEFINE RIGHT_ROTATE_QWORDS(src, count_src) {
-	count := count_src % 64
-	RETURN (src &gt;&gt; count) OR (src &lt;&lt; (64 - count))
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPRORVQ" xed="VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sll_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sll_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_slli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sll_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sll_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_slli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sll_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_slli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sll_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_slli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSLLQ" xed="VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sllv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSLLVD" xed="VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sllv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSLLVQ" xed="VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sllv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSLLVQ" xed="VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sllv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSLLVQ" xed="VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sra_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sra_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srai_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sra_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-		ELSE
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sra_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-	ELSE
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srai_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0)
-	ELSE
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSRAQ" xed="VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srav_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSRAVD" xed="VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSRAVQ" xed="VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSRAVQ" xed="VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srav_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := SignExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0)
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSRAVQ" xed="VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srl_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srl_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[63:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srl_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srl_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, xmm" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srl_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[63:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, xmm" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF imm8[7:0] &gt; 63
-			dst[i+63:i] := 0
-		ELSE
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srl_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, xmm" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srli_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSRLQ" xed="VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srlv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSRLVD" xed="VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srlv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSRLVQ" xed="VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_srlv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		IF count[i+63:i] &lt; 64
-			dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-		ELSE
-			dst[i+63:i] := 0
-		FI
-	ELSE
-		dst[i+63:i] := 0
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSRLVQ" xed="VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srlv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF count[i+63:i] &lt; 64
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSRLVQ" xed="VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VRCP14PD" xed="VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VRCP14PD" xed="VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rcp14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := (1.0 / a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VRCP14PD" xed="VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VRCP14PS" xed="VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VRCP14PS" xed="VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rcp14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (1.0 / a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VRCP14PS" xed="VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rcp14_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (1.0 / b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VRCP14SD" xed="VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rcp14_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (1.0 / b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VRCP14SD" xed="VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rcp14_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-dst[63:0] := (1.0 / b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VRCP14SD" xed="VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rcp14_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (1.0 / b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VRCP14SS" xed="VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rcp14_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (1.0 / b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VRCP14SS" xed="VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rcp14_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-dst[31:0] := (1.0 / b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VRCP14SS" xed="VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VRSQRT14PD" xed="VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VRSQRT14PD" xed="VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rsqrt14_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := (1.0 / SQRT(a[i+63:i]))
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VRSQRT14PD" xed="VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VRSQRT14PS" xed="VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VRSQRT14PS" xed="VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rsqrt14_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VRSQRT14PS" xed="VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rsqrt14_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (1.0 / SQRT(b[63:0]))
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VRSQRT14SD" xed="VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rsqrt14_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-IF k[0]
-	dst[63:0] := (1.0 / SQRT(b[63:0]))
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VRSQRT14SD" xed="VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rsqrt14_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-dst[63:0] := (1.0 / SQRT(b[63:0]))
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VRSQRT14SD" xed="VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rsqrt14_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (1.0 / SQRT(b[31:0]))
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VRSQRT14SS" xed="VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rsqrt14_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-IF k[0]
-	dst[31:0] := (1.0 / SQRT(b[31:0]))
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VRSQRT14SS" xed="VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rsqrt14_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14.</description>
-	<operation>
-dst[31:0] := (1.0 / SQRT(b[31:0]))
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VRSQRT14SS" xed="VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sqrt_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sqrt_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sqrt_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sqrt_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note].</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := SQRT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sqrt_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SQRT(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sqrt_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".
-	[round_note].</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := SQRT(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VSQRTPD" xed="VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sqrt_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sqrt_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sqrt_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sqrt_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := SQRT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sqrt_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SQRT(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sqrt_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".
-	[round_note].</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := SQRT(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VSQRTPS" xed="VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := SQRT(b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := SQRT(b[63:0])
-ELSE
-	dst[63:0] := src[63:0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[63:0] := SQRT(b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst[63:0] := SQRT(b[63:0])
-ELSE
-	dst[63:0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_round_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := SQRT(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSQRTSD" xed="VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := SQRT(b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := SQRT(b[31:0])
-ELSE
-	dst[31:0] := src[31:0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst[31:0] := SQRT(b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst[31:0] := SQRT(b[31:0])
-ELSE
-	dst[31:0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_round_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := SQRT(b[31:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSQRTSS" xed="VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castpd128_pd512" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are undefined. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castpd256_pd512" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are undefined. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castpd512_pd128" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Cast vector of type __m512d to type __m128d. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castps512_ps128" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Cast vector of type __m512 to type __m128. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castpd512_pd256" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Cast vector of type __m512d to type __m256d. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castps128_ps512" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Cast vector of type __m128 to type __m512; the upper 384 bits of the result are undefined. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castps256_ps512" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Cast vector of type __m256 to type __m512; the upper 256 bits of the result are undefined. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castps512_ps256" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Cast vector of type __m512 to type __m256. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castsi128_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" type="__m128i" varname="a" />
-	<description>Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are undefined. 
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castsi256_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" type="__m256i" varname="a" />
-	<description>Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are undefined.
-	 This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castsi512_si128" tech="AVX-512">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m512i" varname="a" />
-	<description>Cast vector of type __m512i to type __m128i.
-	 This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castsi512_si256" tech="AVX-512">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="M256" type="__m512i" varname="a" />
-	<description>Cast vector of type __m512i to type __m256i.
-	 This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_zextpd128_pd512" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_zextps128_ps512" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Cast vector of type __m128 to type __m512; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_zextsi128_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" type="__m128i" varname="a" />
-	<description>Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_zextpd256_pd512" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_zextps256_ps512" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Cast vector of type __m256 to type __m512; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_zextsi256_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" type="__m256i" varname="a" />
-	<description>Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_undefined" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m512 with undefined elements.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm512_undefined_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<description>Return vector of type __m512i with undefined elements.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm512_undefined_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<description>Return vector of type __m512d with undefined elements.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm512_undefined_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<description>Return vector of type __m512 with undefined elements.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] + b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] + b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VADDPD" xed="VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VADDPS" xed="VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE 
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PD" xed="VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PD" xed="VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PD" xed="VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PS" xed="VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PS" xed="VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PS" xed="VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PD" xed="VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PD" xed="VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PD" xed="VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PS" xed="VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PS" xed="VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PS" xed="VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".
-	 [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmadd_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmadd_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PD" xed="VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PD" xed="VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PD" xed="VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".  
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmadd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmadd_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PS" xed="VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PS" xed="VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PS" xed="VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".  
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := c[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmsub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmsub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="FP64" type="__m512d" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PD" xed="VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PD" xed="VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PD" xed="VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).  [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := c[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmsub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmsub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="FP32" type="__m512" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR	
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PS" xed="VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PS" xed="VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PS" xed="VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  RM.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] * b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] * b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] * b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VMULPD" xed="VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  RM.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	 [round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] * b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] * b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". 
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] * b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VMULPS" xed="VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPADDD" xed="VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPADDD" xed="VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mullo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp[63:0] := a[i+31:i] * b[i+31:i]
-		dst[i+31:i] := tmp[31:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULLD" xed="VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mullo_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	tmp[63:0] := a[i+31:i] * b[i+31:i]
-	dst[i+31:i] := tmp[31:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULLD" xed="VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSUBD" xed="VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSUBD" xed="VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] - b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] - b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VSUBPD" xed="VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VSUBPS" xed="VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_add_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed 32-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[31:0] + src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] + src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := 0
-	FI
-ENDFOR
-dst[31:0] := REDUCE_ADD(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_add_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed 64-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[63:0] + src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] + src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := 0
-	FI
-ENDFOR
-dst[63:0] := REDUCE_ADD(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_add_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[63:0] + src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] + src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := 0
-	FI
-ENDFOR
-dst[63:0] := REDUCE_ADD(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_add_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by addition using mask "k". Returns the sum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[31:0] + src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] + src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := 0
-	FI
-ENDFOR
-dst[31:0] := REDUCE_ADD(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_mul_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed 32-bit integers in "a" by multiplication using mask "k". Returns the product of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[31:0] * src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] * src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := 1
-	FI
-ENDFOR
-dst[31:0] := REDUCE_MUL(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_mul_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed 64-bit integers in "a" by multiplication using mask "k". Returns the product of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[63:0] * src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] * src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := 1
-	FI
-ENDFOR
-dst[63:0] := REDUCE_MUL(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_mul_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by multiplication using mask "k". Returns the product of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[63:0] * src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] * src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := 1.0
-	FI
-ENDFOR
-dst[63:0] := REDUCE_MUL(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_mul_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by multiplication using mask "k". Returns the product of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[31:0] * src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] * src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := FP32(1.0)
-	FI
-ENDFOR
-dst[31:0] := REDUCE_MUL(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_add_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed 32-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[31:0] + src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] + src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_ADD(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_add_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed 64-bit integers in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[63:0] + src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] + src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_ADD(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_add_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[63:0] + src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] + src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_ADD(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_add_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_ADD(src, len) {
-	IF len == 2
-		RETURN src[31:0] + src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] + src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_ADD(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_ADD(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_mul_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed 32-bit integers in "a" by multiplication. Returns the product of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[31:0] * src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] * src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_MUL(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_mul_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed 64-bit integers in "a" by multiplication. Returns the product of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[63:0] * src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] * src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_MUL(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_mul_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[63:0] * src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] * src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_MUL(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_mul_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MUL(src, len) {
-	IF len == 2
-		RETURN src[31:0] * src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] * src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_MUL(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_MUL(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_abs_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="v2" />
-	<description>Finds the absolute value of each packed single-precision (32-bit) floating-point element in "v2", storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ABS(v2[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, m512" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_abs_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="v2" />
-	<description>Finds the absolute value of each packed single-precision (32-bit) floating-point element in "v2", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ABS(v2[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, m512" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_abs_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="v2" />
-	<description>Finds the absolute value of each packed double-precision (64-bit) floating-point element in "v2", storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ABS(v2[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, m512" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_abs_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="v2" />
-	<description>Finds the absolute value of each packed double-precision (64-bit) floating-point element in "v2", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ABS(v2[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, m512" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 64 bytes (16 elements) in "dst".</description>
-	<operation>
-temp[1023:512] := a[511:0]
-temp[511:0] := b[511:0]
-temp[1023:0] := temp[1023:0] &gt;&gt; (32*imm8[3:0])
-dst[511:0] := temp[511:0]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VALIGND" xed="VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_alignr_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 64 bytes (16 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-temp[1023:512] := a[511:0]
-temp[511:0] := b[511:0]
-temp[1023:0] := temp[1023:0] &gt;&gt; (32*imm8[3:0])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := temp[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VALIGND" xed="VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getexp_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.
-	[sae_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getexp_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getexp_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.
-	[sae_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VGETEXPPD" xed="VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getexp_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.
-	[sae_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getexp_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getexp_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.
-	[sae_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VGETEXPPS" xed="VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getmant_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8 {sae}" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getmant_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getmant_round_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv)
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8 {sae}" name="VGETMANTPD" xed="VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getmant_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8 {sae}" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getmant_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getmant_round_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="interv" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sc" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8 {sae}" name="VGETMANTPS" xed="VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_blend_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VBLENDMPD" xed="VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_blend_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VBLENDMPS" xed="VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_blend_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMD" xed="VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_blend_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMQ" xed="VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutevar_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Note that this intrinsic shuffles across 128-bit lanes, unlike past intrinsics that use the "permutevar" name. This intrinsic is identical to "_mm512_mask_permutexvar_epi32", and it is recommended that you use that intrinsic name.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	id := idx[i+3:i]*32
-	IF k[j]
-		dst[i+31:i] := a[id+31:id]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutevar_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="idx" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". Note that this intrinsic shuffles across 128-bit lanes, unlike past intrinsics that use the "permutevar" name. This intrinsic is identical to "_mm512_permutexvar_epi32", and it is recommended that you use that intrinsic name.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	id := idx[i+3:i]*32
-	dst[i+31:i] := a[id+31:id]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMD" xed="VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shuffle_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4])
-tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6])
-tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4])
-tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6])
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := tmp_dst[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSHUFD" xed="VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shuffle_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_PERM" type="_MM_PERM_ENUM" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-dst[159:128] := SELECT4(a[255:128], imm8[1:0])
-dst[191:160] := SELECT4(a[255:128], imm8[3:2])
-dst[223:192] := SELECT4(a[255:128], imm8[5:4])
-dst[255:224] := SELECT4(a[255:128], imm8[7:6])
-dst[287:256] := SELECT4(a[383:256], imm8[1:0])
-dst[319:288] := SELECT4(a[383:256], imm8[3:2])
-dst[351:320] := SELECT4(a[383:256], imm8[5:4])
-dst[383:352] := SELECT4(a[383:256], imm8[7:6])
-dst[415:384] := SELECT4(a[511:384], imm8[1:0])
-dst[447:416] := SELECT4(a[511:384], imm8[3:2])
-dst[479:448] := SELECT4(a[511:384], imm8[5:4])
-dst[511:480] := SELECT4(a[511:384], imm8[7:6])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSHUFD" xed="VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_round_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm {sae}, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := (a[i+63:i] == b[i+63:i]) ? 1 : 0
-ENDFOR	
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := (a[i+63:i] &lt;= b[i+63:i]) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := (a[i+63:i] &lt; b[i+63:i]) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := (a[i+63:i] != b[i+63:i]) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpnle_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := (!(a[i+63:i] &lt;= b[i+63:i])) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpnlt_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k[j] := (!(a[i+63:i] &lt; b[i+63:i])) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpord_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	k[j] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 1 : 0 
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpunord_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k".</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	k[j] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 1 : 0 
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_round_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm {sae}, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := (a[i+63:i] == b[i+63:i]) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR	
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := (a[i+63:i] &lt;= b[i+63:i]) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := (a[i+63:i] &lt; b[i+63:i]) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := (a[i+63:i] != b[i+63:i]) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpnle_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := (!(a[i+63:i] &lt;= b[i+63:i])) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpnlt_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := (!(a[i+63:i] &lt; b[i+63:i])) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpord_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpunord_pd_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="FP64" type="__m512d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 7
-	i := j*64
-	IF k1[j]
-		k[j] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPD" xed="VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_round_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm {sae}, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := (a[i+31:i] == b[i+31:i]) ? 1 : 0
-ENDFOR	
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := (a[i+31:i] &lt;= b[i+31:i]) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := (a[i+31:i] &lt; b[i+31:i]) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := (a[i+31:i] != b[i+31:i]) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpnle_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := (!(a[i+31:i] &lt;= b[i+31:i])) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpnlt_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := (!(a[i+31:i] &lt; b[i+31:i])) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpord_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	k[j] := ((a[i+31:i] != NaN) AND (b[i+31:i] != NaN)) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpunord_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k".</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	k[j] := ((a[i+31:i] == NaN) OR (b[i+31:i] == NaN)) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_round_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).  [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q 
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ 
-26: OP := _CMP_NGT_UQ 
-27: OP := _CMP_FALSE_OS 
-28: OP := _CMP_NEQ_OS 
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm {sae}, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := (a[i+31:i] == b[i+31:i]) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR		
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := (a[i+31:i] &lt;= b[i+31:i]) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := (a[i+31:i] &lt; b[i+31:i]) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := (a[i+31:i] != b[i+31:i]) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpnle_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := (!(a[i+31:i] &lt;= b[i+31:i])) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpnlt_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := (!(a[i+31:i] &lt; b[i+31:i])) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpord_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ((a[i+31:i] != NaN) AND (b[i+31:i] != NaN)) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpunord_ps_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ((a[i+31:i] == NaN) OR (b[i+31:i] == NaN)) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPS" xed="VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPEQD" xed="VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpge_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpgt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPCMPGTD" xed="VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPEQD" xed="VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpge_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpgt_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPCMPGTD" xed="VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPD" xed="VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpeq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpge_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpgt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmple_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmplt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmpneq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immtype="_MM_CMPINT" type="_MM_CMPINT_ENUM" varname="imm8" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[2:0]) OF
-0: OP := _MM_CMPINT_EQ
-1: OP := _MM_CMPINT_LT
-2: OP := _MM_CMPINT_LE
-3: OP := _MM_CMPINT_FALSE
-4: OP := _MM_CMPINT_NE
-5: OP := _MM_CMPINT_NLT
-6: OP := _MM_CMPINT_NLE
-7: OP := _MM_CMPINT_TRUE
-ESAC
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpeq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpge_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpgt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &gt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmple_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmplt_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] &lt; b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmpneq_epu32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0
-	ELSE 
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VPCMPUD" xed="VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32gather_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="FP32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, vm32z" name="VGATHERDPS" xed="VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32gather_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="FP32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, vm32z" name="VGATHERDPS" xed="VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_load_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_load_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_load_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_load_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 16 packed 32-bit integers) from memory into "dst". 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_load_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits of integer data from memory into "dst". 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_load_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 8 packed 64-bit integers) from memory into "dst". 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_load_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32gather_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+31:i] := MEM[addr+31:addr]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, vm32z" name="VPGATHERDD" xed="VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32gather_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="UI32" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+31:i] := MEM[addr+31:addr]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, vm32z" name="VPGATHERDD" xed="VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32logather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Loads 8 64-bit integer elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" and stores them in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VPGATHERDQ" xed="VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32logather_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="UI64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Loads 8 64-bit integer elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VPGATHERDQ" xed="VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32logather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Loads 8 double-precision (64-bit) floating-point elements stored at memory locations starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" them in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	dst[i+63:i] := MEM[addr+63:addr]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VGATHERDPD" xed="VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32logather_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="vindex" />
-	<parameter etype="FP64" type="void const*" varname="base_addr" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Loads 8 double-precision (64-bit) floating-point elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		dst[i+63:i] := MEM[addr+63:addr]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VGATHERDPD" xed="VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mov_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVAPD" xed="VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mov_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mov_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVDQA32" xed="VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mov_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VMOVDQA64" xed="VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_store_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVAPD" xed="VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_store_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory.
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVAPD" xed="VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_store_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_store_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_store_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Store packed 32-bit integers from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_store_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Store 512-bits (composed of 16 packed 32-bit integers) from "a" into memory. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_store_si512" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="M512" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="M512" type="__m512i" varname="a" />
-	<description>Store 512-bits of integer data from "a" into memory. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVDQA32" xed="VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_store_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Store packed 64-bit integers from "a" into memory using writemask "k".
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_store_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="512" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Store 512-bits (composed of 8 packed 64-bit integers) from "a" into memory. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVDQA64" xed="VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32z, zmm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32scatter_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32z {k}, zmm" name="VPSCATTERDD" xed="VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+31:addr] := a[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="vm32z, zmm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32scatter_ps" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP32" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+31:addr] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="vm32z {k}, zmm" name="VSCATTERDPS" xed="VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32loscatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Stores 8 packed double-precision (64-bit) floating-point elements in "a" and to memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="m512, zmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32loscatter_pd" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Stores 8 packed double-precision (64-bit) floating-point elements in "a" to memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". Only those elements whose corresponding mask bit is set in writemask "k" are written to memory.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VSCATTERDPD" xed="VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_and_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] AND b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_and_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" type="__m512i" varname="a" />
-	<parameter etype="M512" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of 512 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[511:0] := (a[511:0] AND b[511:0])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_andnot_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPANDND" xed="VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_andnot_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" type="__m512i" varname="a" />
-	<parameter etype="M512" type="__m512i" varname="b" />
-	<description>Compute the bitwise NOT of 512 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
-	<operation>
-dst[511:0] := ((NOT a[511:0]) AND b[511:0])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPANDND" xed="VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_andnot_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPANDND" xed="VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_andnot_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise NOT of 512 bits (composed of packed 64-bit integers) in "a" and then AND with "b", and store the results in "dst".</description>
-	<operation>
-dst[511:0] := ((NOT a[511:0]) AND b[511:0])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPANDNQ" xed="VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_andnot_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPANDNQ" xed="VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_and_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of 512 bits (composed of packed 64-bit integers) in "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst[511:0] := (a[511:0] AND b[511:0])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_and_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] AND b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPANDQ" xed="VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPORD" xed="VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_or_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPORD" xed="VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_or_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" type="__m512i" varname="a" />
-	<parameter etype="M512" type="__m512i" varname="b" />
-	<description>Compute the bitwise OR of 512 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[511:0] := (a[511:0] OR b[511:0])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPORD" xed="VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPORQ" xed="VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_or_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the resut in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPORQ" xed="VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_test_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k1[j]
-		k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_test_epi32_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPTESTMD" xed="VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPXORD" xed="VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_xor_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORD" xed="VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_xor_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="M512" type="__m512i" varname="a" />
-	<parameter etype="M512" type="__m512i" varname="b" />
-	<description>Compute the bitwise XOR of 512 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[511:0] := (a[511:0] XOR b[511:0])
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORD" xed="VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_xor_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<description>Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_and_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed 32-bit integers in "a" by bitwise AND using mask "k". Returns the bitwise AND of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[31:0] AND src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] AND src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := 0xFFFFFFFF
-	FI
-ENDFOR
-dst[31:0] := REDUCE_AND(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_and_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed 64-bit integers in "a" by bitwise AND using mask "k". Returns the bitwise AND of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[63:0] AND src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] AND src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := 0xFFFFFFFFFFFFFFFF
-	FI
-ENDFOR
-dst[63:0] := REDUCE_AND(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_or_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed 32-bit integers in "a" by bitwise OR using mask "k". Returns the bitwise OR of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[31:0] OR src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] OR src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := 0
-	FI
-ENDFOR
-dst[31:0] := REDUCE_OR(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_or_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed 64-bit integers in "a" by bitwise OR using mask "k". Returns the bitwise OR of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[63:0] OR src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] OR src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := 0
-	FI
-ENDFOR
-dst[63:0] := REDUCE_OR(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_and_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed 32-bit integers in "a" by bitwise AND. Returns the bitwise AND of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[31:0] AND src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] AND src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_AND(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_and_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed 64-bit integers in "a" by bitwise AND. Returns the bitwise AND of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_AND(src, len) {
-	IF len == 2
-		RETURN src[63:0] AND src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] AND src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_AND(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_AND(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_or_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed 32-bit integers in "a" by bitwise OR. Returns the bitwise OR of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[31:0] OR src[63:32]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := src[i+31:i] OR src[i+32*len+31:i+32*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_OR(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_or_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed 64-bit integers in "a" by bitwise OR. Returns the bitwise OR of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_OR(src, len) {
-	IF len == 2
-		RETURN src[63:0] OR src[127:64]
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := src[i+63:i] OR src[i+64*len+63:i+64*len]
-	ENDFOR
-	RETURN REDUCE_OR(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_OR(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_and_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="v2" />
-	<parameter etype="UI32" type="__m512i" varname="v3" />
-	<description>Performs element-by-element bitwise AND between packed 32-bit integer elements of "v2" and "v3", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := v2[i+31:i] &amp; v3[i+31:i]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPANDD" xed="VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMAXSD" xed="VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMAXSD" xed="VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMAXUD" xed="VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMAXUD" xed="VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMINSD" xed="VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="SI32" type="__m512i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMINSD" xed="VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMINUD" xed="VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMINUD" xed="VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_max_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="SI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Reduce the packed signed 32-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := Int32(-0x80000000)
-	FI
-ENDFOR
-dst[31:0] := REDUCE_MAX(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_max_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="SI64" type="__int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Reduce the packed signed 64-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := Int64(-0x8000000000000000)
-	FI
-ENDFOR
-dst[63:0] := REDUCE_MAX(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_max_epu32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed unsigned 32-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := 0
-	FI
-ENDFOR
-dst[31:0] := REDUCE_MAX(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_max_epu64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed unsigned 64-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := 0
-	FI
-ENDFOR
-dst[63:0] := REDUCE_MAX(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_max_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := Cast_FP64(0xFFEFFFFFFFFFFFFF)
-	FI
-ENDFOR
-dst[63:0] := REDUCE_MAX(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_max_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum using mask "k". Returns the maximum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := Cast_FP32(0xFF7FFFFF)
-	FI
-ENDFOR
-dst[31:0] := REDUCE_MAX(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_min_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="SI32" type="int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Reduce the packed signed 32-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := Int32(0x7FFFFFFF)
-	FI
-ENDFOR
-dst[31:0] := REDUCE_MIN(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_min_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="SI64" type="__int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Reduce the packed signed 64-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := Int64(0x7FFFFFFFFFFFFFFF)
-	FI
-ENDFOR
-dst[63:0] := REDUCE_MIN(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_min_epu32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed unsigned 32-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := 0xFFFFFFFF
-	FI
-ENDFOR
-dst[31:0] := REDUCE_MIN(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_min_epu64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed unsigned 64-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := 0xFFFFFFFFFFFFFFFF
-	FI
-ENDFOR
-dst[63:0] := REDUCE_MIN(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_min_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". [min_float_note]</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[64*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 8
-	i := j*64
-	IF k[j]
-		tmp[i+63:i] := a[i+63:i]
-	ELSE
-		tmp[i+63:i] := Cast_FP64(0x7FEFFFFFFFFFFFFF)
-	FI
-ENDFOR
-dst[63:0] := REDUCE_MIN(tmp, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_min_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". [min_float_note]</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[32*len-1:0], len)
-}
-tmp := a
-FOR j := 0 to 16
-	i := j*32
-	IF k[j]
-		tmp[i+31:i] := a[i+31:i]
-	ELSE
-		tmp[i+31:i] := Cast_FP32(0x7F7FFFFF)
-	FI
-ENDFOR
-dst[31:0] := REDUCE_MIN(tmp, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_max_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="SI32" type="int" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Reduce the packed signed 32-bit integers in "a" by maximum. Returns the maximum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_MAX(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_max_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="SI64" type="__int64" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Reduce the packed signed 64-bit integers in "a" by maximum. Returns the maximum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_MAX(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_max_epu32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed unsigned 32-bit integers in "a" by maximum. Returns the maximum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_MAX(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_max_epu64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed unsigned 64-bit integers in "a" by maximum. Returns the maximum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_MAX(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_max_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &gt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &gt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_MAX(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_max_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MAX(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &gt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &gt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MAX(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_MAX(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_min_epi32" sequence="TRUE" tech="AVX-512">
-	<return etype="SI32" type="int" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Reduce the packed signed 32-bit integers in "a" by minimum. Returns the minimum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_MIN(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_min_epi64" sequence="TRUE" tech="AVX-512">
-	<return etype="SI64" type="__int64" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Reduce the packed signed 64-bit integers in "a" by minimum. Returns the minimum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_MIN(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_min_epu32" sequence="TRUE" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Reduce the packed unsigned 32-bit integers in "a" by minimum. Returns the minimum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_MIN(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_min_epu64" sequence="TRUE" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Reduce the packed unsigned 64-bit integers in "a" by minimum. Returns the minimum of all elements in "a".</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_MIN(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_min_pd" sequence="TRUE" tech="AVX-512">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Reduce the packed double-precision (64-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a". [min_float_note]</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[63:0] &lt; src[127:64] ? src[63:0] : src[127:64])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*64
-		src[i+63:i] := (src[i+63:i] &lt; src[i+64*len+63:i+64*len] ? src[i+63:i] : src[i+64*len+63:i+64*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[64*len-1:0], len)
-}
-dst[63:0] := REDUCE_MIN(a, 8)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_min_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Reduce the packed single-precision (32-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a". [min_float_note]</description>
-	<operation>
-DEFINE REDUCE_MIN(src, len) {
-	IF len == 2
-		RETURN (src[31:0] &lt; src[63:32] ? src[31:0] : src[63:32])
-	FI
-	len := len / 2
-	FOR j:= 0 to (len-1)
-		i := j*32
-		src[i+31:i] := (src[i+31:i] &lt; src[i+32*len+31:i+32*len] ? src[i+31:i] : src[i+32*len+31:i+32*len])
-	ENDFOR
-	RETURN REDUCE_MIN(src[32*len-1:0], len)
-}
-dst[31:0] := REDUCE_MIN(a, 16)
-	</operation>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_slli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_slli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSLLD" xed="VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sllv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSLLVD" xed="VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sllv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSLLVD" xed="VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srai_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-		ELSE
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srai_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="6" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSRAD" xed="VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srav_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSRAVD" xed="VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srav_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0)
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSRAVD" xed="VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF imm8[7:0] &gt; 31
-			dst[i+31:i] := 0
-		ELSE
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srli_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VPSRLD" xed="VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_srlv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		IF count[i+31:i] &lt; 32
-			dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-		ELSE
-			dst[i+31:i] := 0
-		FI
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI	
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSRLVD" xed="VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_srlv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF count[i+31:i] &lt; 32
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSRLVD" xed="VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castpd_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Cast vector of type __m512d to type __m512.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castpd_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Cast vector of type __m512d to type __m512i.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castps_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Cast vector of type __m512 to type __m512d.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castps_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Cast vector of type __m512 to type __m512i.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castsi512_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Cast vector of type __m512i to type __m512d.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castsi512_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Cast vector of type __m512i to type __m512.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtpslo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="v2" />
-	<description>Performs element-by-element conversion of the lower half of packed single-precision (32-bit) floating-point elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := j*64
-	dst[n+63:n] := Convert_FP32_To_FP64(v2[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTPS2PD" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpslo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="v2" />
-	<description>Performs element-by-element conversion of the lower half of packed single-precision (32-bit) floating-point elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[l+63:l] := Convert_FP32_To_FP64(v2[i+31:i])
-	ELSE
-		dst[l+63:l] := src[l+63:l]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTPS2PD" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi32lo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="v2" />
-	<description>Performs element-by-element conversion of the lower half of packed 32-bit integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	dst[l+63:l] := Convert_Int32_To_FP64(v2[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTDQ2PD" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32lo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="v2" />
-	<description>Performs element-by-element conversion of the lower half of packed 32-bit integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := j*64
-	IF k[j]
-		dst[n+63:n] := Convert_Int32_To_FP64(v2[i+31:i])
-	ELSE
-		dst[n+63:n] := src[n+63:n]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTDQ2PD" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu32lo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="v2" />
-	<description>Performs element-by-element conversion of the lower half of packed 32-bit unsigned integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	n := j*64
-	dst[n+63:n] := Convert_Int32_To_FP64(v2[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTUDQ2PD" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu32lo_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="v2" />
-	<description>Performs element-by-element conversion of the lower half of 32-bit unsigned integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	l := j*64
-	IF k[j]
-		dst[l+63:l] := Convert_Int32_To_FP64(v2[i+31:i])
-	ELSE
-		dst[l+63:l] := src[l+63:l]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTUDQ2PD" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtpd_pslo" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="v2" />
-	<description>Performs an element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to single-precision (32-bit) floating-point elements and stores them in "dst". The elements are stored in the lower half of the results vector, while the remaining upper half locations are set to 0.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	k := j*32
-	dst[k+31:k] := Convert_FP64_To_FP32(v2[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTPD2PS" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpd_pslo" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="v2" />
-	<description>Performs an element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to single-precision (32-bit) floating-point elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The elements are stored in the lower half of the results vector, while the remaining upper half locations are set to 0.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	l := j*32
-	IF k[j]
-		dst[l+31:l] := Convert_FP64_To_FP32(v2[i+63:i])
-	ELSE
-		dst[l+31:l] := src[l+31:l]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTPD2PS" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_i32loscatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Stores 8 packed 64-bit integer elements located in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-	MEM[addr+63:addr] := a[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="m512, zmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_i32loscatter_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="vindex" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" immtype="_MM_INDEX_SCALE" type="int" varname="scale" />
-	<description>Stores 8 packed 64-bit integer elements located in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using writemask "k" (elements whose corresponding mask bit is not set are not written to memory).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	m := j*32
-	IF k[j]
-		addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8
-		MEM[addr+63:addr] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VPSCATTERDQ" xed="VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512" />
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	
-<intrinsic name="_mm256_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMADD52LUQ" xed="VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMADD52LUQ" xed="VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMADD52LUQ" xed="VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMADD52HUQ" xed="VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMADD52HUQ" xed="VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMADD52HUQ" xed="VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_madd52lo_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMADD52LUQ" xed="VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-	dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_madd52hi_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i])
-		dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMADD52HUQ" xed="VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512IFMA52</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_maskz_popcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POPCNT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPOPCNTQ" xed="VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_popcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POPCNT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPOPCNTQ" xed="VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_popcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := POPCNT(a[i+63:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPOPCNTQ" xed="VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_popcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POPCNT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPOPCNTQ" xed="VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_popcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POPCNT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPOPCNTQ" xed="VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_popcnt_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := POPCNT(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPOPCNTQ" xed="VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := POPCNT(a[i+31:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPOPCNTD" xed="VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POPCNT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPOPCNTD" xed="VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POPCNT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPOPCNTD" xed="VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := POPCNT(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPOPCNTD" xed="VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POPCNT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPOPCNTD" xed="VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POPCNT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPOPCNTD" xed="VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := POPCNT(a[i+31:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPOPCNTD" xed="VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POPCNT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPOPCNTD" xed="VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_popcnt_epi32" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := POPCNT(a[i+31:i])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPOPCNTD" xed="VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_popcnt_epi64" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := POPCNT(a[i+63:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPOPCNTQ" xed="VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_popcnt_epi64" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POPCNT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPOPCNTQ" xed="VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_popcnt_epi64" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := POPCNT(a[i+63:i])
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPOPCNTQ" xed="VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512VPOPCNTDQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-	<intrinsic name="_mm512_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="BF16" type="__m256bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="BF16" type="__m256bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="BF16" type="__m256bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsbh_ss" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="BF16" type="__bfloat16" varname="a" />
-	<description>Convert the BF16 (16-bit) floating-point element in "a" to a floating-point element, and store the result in "dst". This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-dst[31:0] := Convert_BF16_To_FP32(a[15:0])
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m512bh" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	IF j &lt; 16
-		t := b.fp32[j]
-	ELSE
-		t := a.fp32[j-16]
-	FI
-	dst.word[j] := Convert_FP32_To_BF16(t)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m512bh" varname="dst" />
-	<parameter etype="BF16" type="__m512bh" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF j &lt; 16
-			t := b.fp32[j]
-		ELSE
-			t := a.fp32[j-16]
-		FI
-		dst.word[j] := Convert_FP32_To_BF16(t)
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m512bh" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="FP32" type="__m512" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF j &lt; 16
-			t := b.fp32[j]
-		ELSE
-			t := a.fp32[j-16]
-		FI
-		dst.word[j] := Convert_FP32_To_BF16(t)
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m256bh" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m256bh" varname="dst" />
-	<parameter etype="BF16" type="__m256bh" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m256bh" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="BF16" type="__m512bh" varname="a" />
-	<parameter etype="BF16" type="__m512bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst".</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 15
-	dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-	dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VDPBF16PS" xed="VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="BF16" type="__m512bh" varname="a" />
-	<parameter etype="BF16" type="__m512bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VDPBF16PS" xed="VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="BF16" type="__m512bh" varname="a" />
-	<parameter etype="BF16" type="__m512bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VDPBF16PS" xed="VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-	<intrinsic name="_mm_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*16
-	dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*16
-	dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtpbh_ps" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<description>Convert packed BF16 (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic neither raises any floating point exceptions nor turns sNAN into qNAN.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*16
-	IF k[j]
-		dst[i+31:i] := Convert_BF16_To_FP32(a[m+15:m])
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtness_sbh" sequence="TRUE" tech="AVX-512">
-	<return etype="BF16" type="__bfloat16" varname="dst" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Convert the single-precision (32-bit) floating-point element in "a" to a BF16 (16-bit) floating-point element, and store the result in "dst".</description>
-	<operation>
-dst[15:0] := Convert_FP32_To_BF16(a[31:0])
-	</operation>
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	IF j &lt; 4
-		t := b.fp32[j]
-	ELSE
-		t := a.fp32[j-4]
-	FI
-	dst.word[j] := Convert_FP32_To_BF16(t)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="BF16" type="__m128bh" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		IF j &lt; 4
-			t := b.fp32[j]
-		ELSE
-			t := a.fp32[j-4]
-		FI
-		dst.word[j] := Convert_FP32_To_BF16(t)
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		IF j &lt; 4
-			t := b.fp32[j]
-		ELSE
-			t := a.fp32[j-4]
-		FI
-		dst.word[j] := Convert_FP32_To_BF16(t)
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m256bh" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	IF j &lt; 8
-		t := b.fp32[j]
-	ELSE
-		t := a.fp32[j-8]
-	FI
-	dst.word[j] := Convert_FP32_To_BF16(t)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m256bh" varname="dst" />
-	<parameter etype="BF16" type="__m256bh" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		IF j &lt; 8
-			t := b.fp32[j]
-		ELSE
-			t := a.fp32[j-8]
-		FI
-		dst.word[j] := Convert_FP32_To_BF16(t)
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtne2ps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m256bh" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		IF j &lt; 8
-			t := b.fp32[j]
-		ELSE
-			t := a.fp32[j-8]
-		FI
-		dst.word[j] := Convert_FP32_To_BF16(t)
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VCVTNE2PS2BF16" xed="VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="BF16" type="__m128bh" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="BF16" type="__m128bh" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtneps_pbh" tech="AVX-512">
-	<return etype="BF16" type="__m128bh" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.word[j] := Convert_FP32_To_BF16(a.fp32[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTNEPS2BF16" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<parameter etype="BF16" type="__m128bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst".</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 3
-	dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-	dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VDPBF16PS" xed="VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<parameter etype="BF16" type="__m128bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 3
-	IF k[j]
-		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VDPBF16PS" xed="VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="BF16" type="__m128bh" varname="a" />
-	<parameter etype="BF16" type="__m128bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 3
-	IF k[j]
-		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VDPBF16PS" xed="VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="BF16" type="__m256bh" varname="a" />
-	<parameter etype="BF16" type="__m256bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst".</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 7
-	dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-	dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VDPBF16PS" xed="VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="BF16" type="__m256bh" varname="a" />
-	<parameter etype="BF16" type="__m256bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VDPBF16PS" xed="VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_dpbf16_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="BF16" type="__m256bh" varname="a" />
-	<parameter etype="BF16" type="__m256bh" varname="b" />
-	<description>Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE make_fp32(x[15:0]) {
-	y.fp32  := 0.0
-	y[31:16] := x[15:0]
-	RETURN y
-}
-dst := src
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1])
-		dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VDPBF16PS" xed="VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_BF16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_mask_bitshuffle_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 3 //Qword
-	FOR j := 0 to 7 // Byte
-		IF k[i*8+j]
-			m := c.qword[i].byte[j] &amp; 0x3F
-			dst[i*8+j] := b.qword[i].bit[m]
-		ELSE
-			dst[i*8+j] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_bitshuffle_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst".</description>
-	<operation>
-FOR i := 0 to 3 //Qword
-	FOR j := 0 to 7 // Byte
-		m := c.qword[i].byte[j] &amp; 0x3F
-		dst[i*8+j] := b.qword[i].bit[m]
-	ENDFOR
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="k, ymm, ymm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_bitshuffle_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 1 //Qword
-	FOR j := 0 to 7 // Byte
-		IF k[i*8+j]
-			m := c.qword[i].byte[j] &amp; 0x3F
-			dst[i*8+j] := b.qword[i].bit[m]
-		ELSE
-			dst[i*8+j] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_bitshuffle_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst".</description>
-	<operation>
-FOR i := 0 to 1 //Qword
-	FOR j := 0 to 7 // Byte
-		m := c.qword[i].byte[j] &amp; 0x3F
-		dst[i*8+j] := b.qword[i].bit[m]
-	ENDFOR
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="k, xmm, xmm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := POPCNT(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPOPCNTW" xed="VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POPCNT(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPOPCNTW" xed="VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POPCNT(a[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPOPCNTW" xed="VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := POPCNT(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPOPCNTW" xed="VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POPCNT(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPOPCNTW" xed="VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POPCNT(a[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPOPCNTW" xed="VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 31
-	i := j*8
-	dst[i+7:i] := POPCNT(a[i+7:i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VPOPCNTB" xed="VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := POPCNT(a[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPOPCNTB" xed="VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := POPCNT(a[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPOPCNTB" xed="VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := POPCNT(a[i+7:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VPOPCNTB" xed="VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := POPCNT(a[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPOPCNTB" xed="VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := POPCNT(a[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPOPCNTB" xed="VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_mask_bitshuffle_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 7 //Qword
-	FOR j := 0 to 7 // Byte
-		IF k[i*8+j]
-			m := c.qword[i].byte[j] &amp; 0x3F
-			dst[i*8+j] := b.qword[i].bit[m]
-		ELSE
-			dst[i*8+j] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_bitshuffle_epi64_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask64" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst".</description>
-	<operation>
-FOR i := 0 to 7 //Qword
-	FOR j := 0 to 7 // Byte
-		m := c.qword[i].byte[j] &amp; 0x3F
-		dst[i*8+j] := b.qword[i].bit[m]
-	ENDFOR
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="k, zmm, zmm" name="VPSHUFBITQMB" xed="VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := POPCNT(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPOPCNTW" xed="VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POPCNT(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPOPCNTW" xed="VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_popcnt_epi16" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POPCNT(a[i+15:i])
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPOPCNTW" xed="VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 63
-	i := j*8
-	dst[i+7:i] := POPCNT(a[i+7:i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VPOPCNTB" xed="VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := POPCNT(a[i+7:i])
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPOPCNTB" xed="VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_popcnt_epi8" vexEq="TRUE" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE POPCNT(a) {
-	count := 0
-	DO WHILE a &gt; 0
-		count += a[0]
-		a &gt;&gt;= 1
-	OD
-	RETURN count
-}
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := POPCNT(a[i+7:i])
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPOPCNTB" xed="VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512_BITALG</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-	<intrinsic name="_mm256_acos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ACOS(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_acosh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ACOSH(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_asin_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ASIN(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_asinh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ASINH(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_atan2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-		<parameter etype="FP16" type="__m256h" varname="b" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ATAN2(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_atan_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ATAN(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_atanh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ATANH(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_cbrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := CubeRoot(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_cdfnorm_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := CDFNormal(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_cdfnorminv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := InverseCDFNormal(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_cos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := COS(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_cosd_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := COSD(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_cosh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := COSH(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_erf_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ERF(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_erfc_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := 1.0 - ERF(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_erfcinv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := 1.0 / (1.0 - ERF(a[i+15:i]))
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_erfinv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := 1.0 / ERF(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_exp10_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the exponential value of 10 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := POW(FP16(10.0), a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_exp2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the exponential value of 2 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := POW(FP16(2.0), a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_exp_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := POW(FP16(e), a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_expm1_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := POW(FP16(e), a[i+15:i]) - 1.0
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_hypot_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-		<parameter etype="FP16" type="__m256h" varname="b" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := SQRT(POW(a[i+15:i], 2.0) + POW(b[i+15:i], 2.0))
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_invcbrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := InvCubeRoot(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_invsqrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the inverse square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := InvSQRT(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_log10_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the base-10 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_log1p_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the natural logarithm of one plus packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := LOG(1.0 + a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_log2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the base-2 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_log_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the natural logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_logb_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ConvertExpFP16(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_pow_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the exponential value of packed half-precision (16-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-		<parameter etype="FP16" type="__m256h" varname="b" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := POW(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_sin_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := SIN(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_sincos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the sine and cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-		<parameter etype="FP16" memwidth="256" type="__m256h*" varname="mem_addr" />
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := SIN(a[i+15:i])
-	MEM[mem_addr+i+15:mem_addr+i] := COS(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-cos_res[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_sind_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := SIND(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_sinh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := SINH(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_svml_ceil_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" up to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := CEIL(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_svml_floor_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" down to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := FLOOR(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_svml_round_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ROUND(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_svml_sqrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := SQRT(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_tan_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := TAN(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_tand_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := TAND(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_tanh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Compute the hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := TANH(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm256_trunc_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m256h" varname="dst" />
-		<description>Truncate the packed half-precision (16-bit) floating-point elements in "a", and store the results as packed half-precision floating-point elements in "dst"</description>
-		<parameter etype="FP16" type="__m256h" varname="a" />
-	<category>Special Math Functions</category><operation>FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := TRUNCATE(a[i+15:i])
-ENDFOR
-dst[MAX:256] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_acos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ACOS(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_acosh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ACOSH(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_asin_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ASIN(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_asinh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ASINH(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_atan2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-		<parameter etype="FP16" type="__m512h" varname="b" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ATAN2(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_atan_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" expressed in radians.</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ATAN(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_atanh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse hyperblic tangent of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" expressed in radians.</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ATANH(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_cbrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := CubeRoot(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_cdfnorm_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := CDFNormal(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_cdfnorminv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := InverseCDFNormal(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_ceil_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" up to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := CEIL(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_cos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := COS(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_cosd_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := COSD(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_cosh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := COSH(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_erf_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ERF(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_erfc_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := 1.0 - ERF(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_erfcinv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := 1.0 / (1.0 - ERF(a[i+15:i]))
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_erfinv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := 1.0 / ERF(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_exp10_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of 10 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := POW(FP16(10.0), a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_exp2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of 2 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := POW(FP16(2.0), a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_exp_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := POW(FP16(e), a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_expm1_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := POW(FP16(e), a[i+15:i]) - 1.0
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_floor_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" down to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := FLOOR(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_hypot_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-		<parameter etype="FP16" type="__m512h" varname="b" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := SQRT(POW(a[i+15:i], 2.0) + POW(b[i+15:i], 2.0))
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_invsqrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := InvSQRT(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_log10_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the base-10 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_log1p_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the natural logarithm of one plus packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := LOG(1.0 + a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_log2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the base-2 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_log_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the natural logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_logb_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ConvertExpFP16(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_acos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ACOS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_acosh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ACOSH(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_asin_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ASIN(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_asinh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ASINH(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_atan_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ATAN(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_atanh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ATANH(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_cbrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := CubeRoot(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_cdfnorm_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := CDFNormal(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_cdfnorminv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := InverseCDFNormal(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_ceil_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" up to an integer value, and store the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := CEIL(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_cos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := COS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_cosd_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := COSD(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_cosh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := COSH(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_erf_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ERF(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_erfc_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := 1.0 - ERF(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_erfcinv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := 1.0 / (1.0 - ERF(a[i+15:i]))
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_erfinv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := 1.0 / ERF(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_exp10_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of 10 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POW(FP16(10.0), a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_exp2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of 2 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POW(FP16(2.0), a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_exp_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POW(FP16(e), a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_expm1_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := POW(FP16(e), a[i+15:i]) - 1.0
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_floor_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" down to an integer value, and store the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := FLOOR(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_invsqrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the inverse square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := InvSQRT(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_log10_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the base-10 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := LOG(a[i+15:i]) / LOG(10.0)
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_log1p_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the natural logarithm of one plus packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := LOG(1.0 + a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_log2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the base-2 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := LOG(a[i+15:i]) / LOG(2.0)
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_log_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the natural logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := LOG(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_logb_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ConvertExpFP16(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_nearbyint_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Rounds each packed half-precision (16-bit) floating-point element in "a" to the nearest integer value and stores the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := NearbyInt(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_recip_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Computes the reciprocal of packed half-precision (16-bit) floating-point elements in "a", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := (1.0 / a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_rint_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Rounds the packed half-precision (16-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := RoundToNearestEven(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_sin_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SIN(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_sincos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the sine and cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", store the cosine into memory at "mem_addr". Elements are written to their respective locations using writemask "k" (elements are copied from "sin_src" or "cos_src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" memwidth="512" type="__m512h*" varname="mem_addr" />
-		<parameter etype="FP16" type="__m512h" varname="sin_src" />
-		<parameter etype="FP16" type="__m512h" varname="cos_src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SIN(a[i+15:i])
-		MEM[mem_addr+i+15:mem_addr+i] := COS(a[i+15:i])
-	ELSE
-		dst[i+15:i] := sin_src[i+15:i]
-		MEM[mem_addr+i+15:mem_addr+i] := cos_src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-cos_res[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_sind_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SIND(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_sinh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := SINH(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_svml_round_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ROUND(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_tan_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := TAN(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_tand_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := TAND(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_tanh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := TANH(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_mask_trunc_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Truncate the packed half-precision (16-bit) floating-point elements in "a", and store the results as packed half-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-		<parameter etype="FP16" type="__m512h" varname="src" />
-		<parameter etype="MASK" type="__mmask32" varname="k" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := TRUNCATE(a[i+15:i])
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_nearbyint_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Rounds each packed half-precision (16-bit) floating-point element in "a" to the nearest integer value and stores the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := NearbyInt(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_pow_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the exponential value of packed half-precision (16-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-		<parameter etype="FP16" type="__m512h" varname="b" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := POW(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_recip_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Computes the reciprocal of packed half-precision (16-bit) floating-point elements in "a", storing the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := (1.0 / a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_rint_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Rounds the packed half-precision (16-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := RoundToNearestEven(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_sin_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := SIN(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_sincos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the sine and cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-		<parameter etype="FP16" memwidth="512" type="__m512h*" varname="mem_addr" />
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := SIN(a[i+15:i])
-	MEM[mem_addr+i+15:mem_addr+i] := COS(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-cos_res[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_sind_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := SIND(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_sinh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := SINH(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_svml_round_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ROUND(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_tan_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := TAN(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_tand_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := TAND(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_tanh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Compute the hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := TANH(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm512_trunc_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m512h" varname="dst" />
-		<description>Truncate the packed half-precision (16-bit) floating-point elements in "a", and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m512h" varname="a" />
-	<category>Special Math Functions</category><operation>FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := TRUNCATE(a[i+15:i])
-ENDFOR
-dst[MAX:512] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_acos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ACOS(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_acosh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ACOSH(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_asin_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ASIN(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_asinh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ASINH(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_atan2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-		<parameter etype="FP16" type="__m128h" varname="b" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ATAN2(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_atan_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ATAN(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_atanh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ATANH(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_cbrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := CubeRoot(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_cdfnorm_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := CDFNormal(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_cdfnorminv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse cumulative distribution function of packed half-precision (16-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := InverseCDFNormal(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_cos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := COS(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_cosd_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := COSD(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_cosh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the hyperbolic cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := COSH(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_erf_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ERF(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_erfc_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := 1.0 - ERF(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_erfcinv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse complementary error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := 1.0 / (1.0 - ERF(a[i+15:i]))
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_erfinv_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse error function of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Probability/Statistics</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := 1.0 / ERF(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_exp10_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the exponential value of 10 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := POW(FP16(10.0), a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_exp2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the exponential value of 2 raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := POW(FP16(2.0), a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_exp_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := POW(FP16(e), a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_expm1_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the exponential value of "e" raised to the power of packed half-precision (16-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := POW(FP16(e), a[i+15:i]) - 1.0
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_hypot_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-		<parameter etype="FP16" type="__m128h" varname="b" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := SQRT(POW(a[i+15:i], 2.0) + POW(b[i+15:i], 2.0))
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_invcbrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse cube root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := InvCubeRoot(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_invsqrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the inverse square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := InvSQRT(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_log10_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the base-10 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_log1p_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the natural logarithm of one plus packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := LOG(1.0 + a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_log2_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the base-2 logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_log_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the natural logarithm of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := LOG(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_logb_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ConvertExpFP16(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_pow_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the exponential value of packed half-precision (16-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-		<parameter etype="FP16" type="__m128h" varname="b" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := POW(a[i+15:i], b[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_sin_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := SIN(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_sincos_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the sine and cosine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-		<parameter etype="FP16" memwidth="128" type="__m128h*" varname="mem_addr" />
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := SIN(a[i+15:i])
-	MEM[mem_addr+i+15:mem_addr+i] := COS(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-cos_res[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_sind_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the sine of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := SIND(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_sinh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the hyperbolic sine of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := SINH(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_svml_ceil_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" up to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := CEIL(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_svml_floor_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" down to an integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := FLOOR(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_svml_round_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Round the packed half-precision (16-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Special Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ROUND(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_svml_sqrt_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Elementary Math Functions</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := SQRT(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_tan_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := TAN(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_tand_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := TAND(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_tanh_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Compute the hyperbolic tangent of packed half-precision (16-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Trigonometry</category><operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := TANH(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-	<intrinsic name="_mm_trunc_ph" sequence="TRUE" tech="SVML">
-		<return etype="FP16" type="__m128h" varname="dst" />
-		<description>Truncate the packed half-precision (16-bit) floating-point elements in "a", and store the results as packed half-precision floating-point elements in "dst".</description>
-		<parameter etype="FP16" type="__m128h" varname="a" />
-	<category>Special Math Functions</category><operation>FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := TRUNCATE(a[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-</operation><header>immintrin.h</header><CPUID>AVX512_FP16</CPUID></intrinsic>
-<intrinsic name="_mm_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := a.fp16[j] + b.fp16[j]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VADDPH" xed="VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] + b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VADDPH" xed="VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] + b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VADDPH" xed="VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.fp16[j] := a.fp16[j] + b.fp16[j]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VADDPH" xed="VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] + b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VADDPH" xed="VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] + b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VADDPH" xed="VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := a.fp16[j] / b.fp16[j]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VDIVPH" xed="VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] / b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VDIVPH" xed="VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] / b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VDIVPH" xed="VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := a.fp16[j] / b.fp16[j]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VDIVPH" xed="VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] / b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VDIVPH" xed="VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] / b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VDIVPH" xed="VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADD132PH" xed="VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD213PH" xed="VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD231PH" xed="VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PH" xed="VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PH" xed="VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PH" xed="VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132PH" xed="VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213PH" xed="VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231PH" xed="VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132PH" xed="VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213PH" xed="VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231PH" xed="VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMADD132PH" xed="VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFMADD213PH" xed="VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFMADD231PH" xed="VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PH" xed="VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PH" xed="VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PH" xed="VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD132PH" xed="VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD213PH" xed="VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADD231PH" xed="VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD132PH" xed="VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD213PH" xed="VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADD231PH" xed="VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMADD132PH" xed="VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD213PH" xed="VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD231PH" xed="VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PH" xed="VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PH" xed="VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PH" xed="VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132PH" xed="VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213PH" xed="VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231PH" xed="VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132PH" xed="VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213PH" xed="VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231PH" xed="VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFNMADD132PH" xed="VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFNMADD213PH" xed="VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFNMADD231PH" xed="VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PH" xed="VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PH" xed="VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PH" xed="VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD132PH" xed="VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD213PH" xed="VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMADD231PH" xed="VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD132PH" xed="VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD213PH" xed="VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMADD231PH" xed="VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUB132PH" xed="VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB213PH" xed="VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB231PH" xed="VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PH" xed="VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PH" xed="VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PH" xed="VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132PH" xed="VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213PH" xed="VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231PH" xed="VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132PH" xed="VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213PH" xed="VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231PH" xed="VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMSUB132PH" xed="VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUB213PH" xed="VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUB231PH" xed="VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PH" xed="VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PH" xed="VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PH" xed="VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB132PH" xed="VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB213PH" xed="VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUB231PH" xed="VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB132PH" xed="VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB213PH" xed="VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUB231PH" xed="VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB132PH" xed="VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB213PH" xed="VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB231PH" xed="VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PH" xed="VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PH" xed="VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PH" xed="VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB132PH" xed="VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB213PH" xed="VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFNMSUB231PH" xed="VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB132PH" xed="VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB213PH" xed="VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFNMSUB231PH" xed="VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	IF ((j &amp; 1) == 0)
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	IF ((j &amp; 1) == 0)
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	IF ((j &amp; 1) == 0)
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	IF ((j &amp; 1) == 0)
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {k}, ymm, ymm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := a.fp16[j] - b.fp16[j]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSUBPH" xed="VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] - b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSUBPH" xed="VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] - b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSUBPH" xed="VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.fp16[j] := a.fp16[j] - b.fp16[j]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VSUBPH" xed="VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] - b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VSUBPH" xed="VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] - b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VSUBPH" xed="VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR i := 0 TO 7
-	dst.fp16[i] := a.fp16[i] * b.fp16[i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VMULPH" xed="VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 TO 7
-	IF k[i]
-		dst.fp16[i] := a.fp16[i] * b.fp16[i]
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMULPH" xed="VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 TO 7
-	IF k[i]
-		dst.fp16[i] := a.fp16[i] * b.fp16[i]
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMULPH" xed="VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR i := 0 TO 15
-	dst.fp16[i] := a.fp16[i] * b.fp16[i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMULPH" xed="VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 TO 15
-	IF k[i]
-		dst.fp16[i] := a.fp16[i] * b.fp16[i]
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMULPH" xed="VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 TO 15
-	IF k[i]
-		dst.fp16[i] := a.fp16[i] * b.fp16[i]
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMULPH" xed="VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMULCPH" xed="VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMULCPH" xed="VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFCMULCPH" xed="VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFCMULCPH" xed="VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADDCPH" xed="VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := a.fp16[2*i+0]
-		dst.fp16[2*i+1] := a.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDCPH" xed="VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := c.fp16[2*i+0]
-		dst.fp16[2*i+1] := c.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDCPH" xed="VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDCPH" xed="VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMADDCPH" xed="VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := a.fp16[2*i+0]
-		dst.fp16[2*i+1] := a.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDCPH" xed="VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := c.fp16[2*i+0]
-		dst.fp16[2*i+1] := c.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFMADDCPH" xed="VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFMADDCPH" xed="VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFCMADDCPH" xed="VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := a.fp16[2*i+0]
-		dst.fp16[2*i+1] := a.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFCMADDCPH" xed="VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := c.fp16[2*i+0]
-		dst.fp16[2*i+1] := c.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFCMADDCPH" xed="VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 3
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFCMADDCPH" xed="VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFCMADDCPH" xed="VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := a.fp16[2*i+0]
-		dst.fp16[2*i+1] := a.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFCMADDCPH" xed="VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask3_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := c.fp16[2*i+0]
-		dst.fp16[2*i+1] := c.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VFCMADDCPH" xed="VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="FP16" type="__m256h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VFCMADDCPH" xed="VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_add_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 7
-	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+8]
-ENDFOR
-FOR i := 0 to 3
-	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+4]
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+2]
-ENDFOR
-dst.fp16[0] := tmp.fp16[0] + tmp.fp16[1]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_mul_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Reduce the packed half-precision (316-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 7
-	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+8]
-ENDFOR
-FOR i := 0 to 3
-	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+4]
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+2]
-ENDFOR
-dst.fp16[0] := tmp.fp16[0] * tmp.fp16[1]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_max_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 7
-	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+8] ? tmp.fp16[i] : tmp.fp16[i+8])
-ENDFOR
-FOR i := 0 to 3
-	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
-ENDFOR
-dst.fp16[0] := (tmp.fp16[0] &gt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_min_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 7
-	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+8] ? tmp.fp16[i] : tmp.fp16[i+8])
-ENDFOR
-FOR i := 0 to 3
-	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
-ENDFOR
-dst.fp16[0] := (tmp.fp16[0] &lt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_add_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 3
-	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+4]
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+2]
-ENDFOR
-dst.fp16[0] := tmp.fp16[0] + tmp.fp16[1]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_mul_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 3
-	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+4]
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+2]
-ENDFOR
-dst.fp16[0] := tmp.fp16[0] * tmp.fp16[1]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_max_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 3
-	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
-ENDFOR
-dst.fp16[0] := (tmp.fp16[0] &gt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_min_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 3
-	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
-ENDFOR
-dst.fp16[0] := (tmp.fp16[0] &lt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_abs_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="v2" />
-	<description>Finds the absolute value of each packed half-precision (16-bit) floating-point element in "v2", storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := ABS(v2.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_abs_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="v2" />
-	<description>Finds the absolute value of each packed half-precision (16-bit) floating-point element in "v2", storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := ABS(v2.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	k[j] := (a.fp16[j] OP b.fp16[j]) ? 1 : 0
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 7
-	IF k1[j]
-		k[j] := ( a.fp16[j] OP b.fp16[j] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cmp_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 15
-	k[j] := (a.fp16[j] OP b.fp16[j]) ? 1 : 0
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, ymm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cmp_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 15
-	IF k1[j]
-		k[j] := ( a.fp16[j] OP b.fp16[j] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, ymm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTW2PH" xed="VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTW2PH" xed="VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTW2PH" xed="VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTW2PH" xed="VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTW2PH" xed="VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTW2PH" xed="VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTUW2PH" xed="VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTUW2PH" xed="VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTUW2PH" xed="VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTUW2PH" xed="VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTUW2PH" xed="VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTUW2PH" xed="VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTDQ2PH" xed="VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m256i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 96 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".  The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 to 3
-	dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).  The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).  The upper 64 bits of "dst" are zeroed out.</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, ymm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, ymm" name="VCVTPS2PHX" xed="VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPH2DQ" xed="VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 1
-	dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 1
-	dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 1
-	dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 1
-	dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 1
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 3
-	dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 3
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2W" xed="VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2W" xed="VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2W" xed="VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTPH2W" xed="VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTPH2W" xed="VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTPH2W" xed="VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPH2W" xed="VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPH2W" xed="VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPH2W" xed="VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTTPH2W" xed="VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTTPH2W" xed="VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTTPH2W" xed="VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2UW" xed="VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2UW" xed="VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2UW" xed="VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTPH2UW" xed="VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTPH2UW" xed="VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTPH2UW" xed="VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VCVTTPH2UW" xed="VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VCVTTPH2UW" xed="VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VCVTTPH2UW" xed="VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	IF k[j]
-		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-	ELSE
-		dst.fp64[j] := src.fp64[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	IF k[j]
-		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-	ELSE
-		dst.fp64[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-	ELSE
-		dst.fp64[j] := src.fp64[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-	ELSE
-		dst.fp64[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-	ELSE
-		dst.fp32[j] := src.fp32[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-	ELSE
-		dst.fp32[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-	ELSE
-		dst.fp32[j] := src.fp32[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-	ELSE
-		dst.fp32[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, xmm" name="VCVTPH2PSX" xed="VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VMAXPH" xed="VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMAXPH" xed="VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMAXPH" xed="VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMAXPH" xed="VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMAXPH" xed="VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMAXPH" xed="VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [max_float_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_max_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_max_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][max_float_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] &gt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMAXSH" xed="VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VMINPH" xed="VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMINPH" xed="VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMINPH" xed="VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VMINPH" xed="VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VMINPH" xed="VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VMINPH" xed="VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [min_float_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_min_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_min_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [sae_note][min_float_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] &lt; b.fp16[0] ? a.fp16[0] : b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VMINSH" xed="VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 7
-	dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-ENDFOR
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 15
-	dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-ENDFOR
-dest[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dest[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dest[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 7
-	dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VGETEXPPH" xed="VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VGETEXPPH" xed="VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VGETEXPPH" xed="VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 15
-	dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VGETEXPPH" xed="VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VGETEXPPH" xed="VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VGETEXPPH" xed="VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR i := 0 TO 7
-	dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR i := 0 TO 7
-	IF k[i]
-		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note]</description>
-	<operation>FOR i := 0 TO 7
-	IF k[i]
-		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-		[getmant_note]</description>
-	<operation>FOR i := 0 TO 15
-	dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VGETMANTPH" xed="VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-		[getmant_note]</description>
-	<operation>FOR i := 0 TO 15
-	IF k[i]
-		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VGETMANTPH" xed="VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-		[getmant_note]</description>
-	<operation>FOR i := 0 TO 15
-	IF k[i]
-		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VGETMANTPH" xed="VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 7
-	dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 15
-	dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, imm8" name="VREDUCEPH" xed="VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, imm8" name="VREDUCEPH" xed="VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, imm8" name="VREDUCEPH" xed="VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 7
-	dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSCALEFPH" xed="VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFPH" xed="VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFPH" xed="VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VSCALEFPH" xed="VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VSCALEFPH" xed="VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VSCALEFPH" xed="VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fpclass_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-		[fpclass_note]</description>
-	<operation>FOR i := 0 to 7
-	k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k, xmm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fpclass_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-		[fpclass_note]</description>
-	<operation>FOR i := 0 to 7
-	IF k1[i]
-		k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
-	ELSE
-		k[i] := 0
-	FI
-ENDFOR
-k[MAX:8] := 0
-	</operation>
-	<instruction form="k {k}, xmm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fpclass_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-			[fpclass_note]</description>
-	<operation>FOR i := 0 to 15
-	k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k, ymm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_fpclass_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="MASK" type="__mmask16" varname="k1" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-		[fpclass_note]</description>
-	<operation>FOR i := 0 to 15
-	IF k1[i]
-		k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
-	ELSE
-		k[i] := 0
-	FI
-ENDFOR
-k[MAX:16] := 0
-	</operation>
-	<instruction form="k {k}, ymm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutex2var_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Shuffle half-precision (16-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	off := idx[i+2:i]
-	dst.fp16[j] := idx[i+3] ? b.fp16[off] : a.fp16[off]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex2var_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Shuffle half-precision (16-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	off := idx[i+3:i]
-	dst.fp16[j] := idx[i+4] ? b.fp16[off] : a.fp16[off]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMI2W" xed="VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<instruction form="ymm, ymm, ymm" name="VPERMT2W" xed="VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_blend_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="FP16" type="__m256h" varname="b" />
-	<description>Blend packed half-precision (16-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := b.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPBLENDMW" xed="VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_blend_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Blend packed half-precision (16-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp16[j] := b.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPBLENDMW" xed="VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutexvar_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="idx" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Shuffle half-precision (16-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	id := idx[i+3:i]
-	dst.fp16[j] := a.fp16[id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMW" xed="VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutexvar_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="idx" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Shuffle half-precision (16-bit) floating-point elements in "a" using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	id := idx[i+2:i]
-	dst.fp16[j] := a.fp16[id]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMW" xed="VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VRSQRTPH" xed="VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VRSQRTPH" xed="VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VRSQRTPH" xed="VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VRSQRTPH" xed="VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VRSQRTPH" xed="VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VRSQRTPH" xed="VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[i] := SQRT(a.fp16[i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VSQRTPH" xed="VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := SQRT(a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VSQRTPH" xed="VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := SQRT(a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VSQRTPH" xed="VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[i] := SQRT(a.fp16[i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VSQRTPH" xed="VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := SQRT(a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VSQRTPH" xed="VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := SQRT(a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VSQRTPH" xed="VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[i] := (1.0 / a.fp16[i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VRCPPH" xed="VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := (1.0 / a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VRCPPH" xed="VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 7
-	IF k[i]
-		dst.fp16[i] := (1.0 / a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VRCPPH" xed="VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[i] := (1.0 / a.fp16[i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VRCPPH" xed="VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := (1.0 / a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VRCPPH" xed="VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := (1.0 / a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VRCPPH" xed="VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm256_load_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVAPS" xed="VMOVAPS_YMMqq_MEMqq" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m128" name="MOVAPS" xed="MOVAPS_XMMps_MEMps" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_loadu_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" memwidth="256" type="void const*" varname="mem_addr" />
-	<description>Load 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[255:0] := MEM[mem_addr+255:mem_addr]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, m256" name="VMOVUPS" xed="VMOVUPS_YMMqq_MEMqq" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" memwidth="128" type="void const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, m128" name="MOVUPS" xed="MOVUPS_XMMps_MEMps" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_store_ph" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP16" memwidth="256" type="void *" varname="mem_addr" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Store 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVAPS" xed="VMOVAPS_MEMqq_YMMqq" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_ph" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP16" memwidth="128" type="void *" varname="mem_addr" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Store 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVAPS" xed="MOVAPS_MEMps_XMMps" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_storeu_ph" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP16" memwidth="256" type="void *" varname="mem_addr" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Store 256-bits (composed of 16 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+255:mem_addr] := a[255:0]
-	</operation>
-	<instruction form="m256, ymm" name="VMOVUPS" xed="VMOVUPS_MEMqq_YMMqq" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_ph" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP16" memwidth="128" type="void *" varname="mem_addr" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Store 128-bits (composed of 8 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVUPS" xed="MOVUPS_MEMps_XMMps" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_undefined_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m256h with undefined elements.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_undefined_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m128h with undefined elements.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setzero_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m256h with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VXORPS" xed="VXORPS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setzero_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m128h with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="XORPS" xed="XORPS_XMMxud_XMMxud" />
-	<CPUID>AVX512_FP16</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.fp16[j] := a.fp16[j] + b.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] + b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] + b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_add_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.fp16[j] := a.fp16[j] + b.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_add_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] + b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_add_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] + b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VADDPH" xed="VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := a.fp16[0] + b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-dst.fp16[0] := a.fp16[0] + b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] + b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_add_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] + b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] + b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_add_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Add the lower half-precision (16-bit) floating-point elements in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] + b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VADDSH" xed="VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := a.fp16[j] / b.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] / b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_div_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] / b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_div_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := a.fp16[j] / b.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_div_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] / b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_div_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide packed half-precision (16-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] / b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VDIVPH" xed="VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := a.fp16[0] / b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] / b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] / b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-dst.fp16[0] := a.fp16[0] / b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_div_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] / b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_div_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Divide the lower half-precision (16-bit) floating-point element in "a" by the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] / b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VDIVSH" xed="VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD132PH" xed="VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD213PH" xed="VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADD231PH" xed="VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-FI
-dst[127:16] := c[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-FI
-dst[127:16] := c[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD132SH" xed="VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD213SH" xed="VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADD231SH" xed="VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD132PH" xed="VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD213PH" xed="VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMADD231PH" xed="VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-FI
-dst[127:16] := c[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmadd_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmadd_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-FI
-dst[127:16] := c[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmadd_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) + c.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD132SH" xed="VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD213SH" xed="VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMADD231SH" xed="VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB132PH" xed="VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB213PH" xed="VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUB231PH" xed="VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-FI
-dst[127:16] := c[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmsub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmsub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-FI
-dst[127:16] := c[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmsub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB132SH" xed="VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB213SH" xed="VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMSUB231SH" xed="VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fnmsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fnmsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fnmsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fnmsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := -(a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB132PH" xed="VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB213PH" xed="VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFNMSUB231PH" xed="VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-FI
-dst[127:16] := c[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm, xmm, xmm {er}" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fnmsub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fnmsub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 7 packed elements from "c" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-FI
-dst[127:16] := c[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fnmsub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := -(a.fp16[0] * b.fp16[0]) - c.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB132SH" xed="VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB213SH" xed="VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFNMSUB231SH" xed="VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	IF ((j &amp; 1) == 0)
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmaddsub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmaddsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".
-		[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF ((j &amp; 1) == 0)
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	ELSE
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmaddsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-		[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmaddsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
-		[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmaddsub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-		[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB132PH" xed="VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB213PH" xed="VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDSUB231PH" xed="VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	IF ((j &amp; 1) == 0)
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsubadd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmsubadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst".
-		[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF ((j &amp; 1) == 0)
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-	ELSE
-		dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm, zmm, zmm {er}" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmsubadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).
-		[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmsubadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set).
-		[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := c.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmsubadd_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-		[round_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		IF ((j &amp; 1) == 0)
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) + c.fp16[j]
-		ELSE
-			dst.fp16[j] := (a.fp16[j] * b.fp16[j]) - c.fp16[j]
-		FI
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD132PH" xed="VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD213PH" xed="VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMSUBADD231PH" xed="VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.fp16[j] := a.fp16[j] - b.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.fp16[j] := a.fp16[j] - b.fp16[j]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] - b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] - b.fp16[j]
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] - b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sub_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract packed half-precision (16-bit) floating-point elements in "b" from packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := a.fp16[j] - b.fp16[j]
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VSUBPH" xed="VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := a.fp16[0] - b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := a.fp16[0] - b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] - b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] - b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] - b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sub_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Subtract the lower half-precision (16-bit) floating-point element in "b" from the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] - b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSUBSH" xed="VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR i := 0 TO 31
-	dst.fp16[i] := a.fp16[i] * b.fp16[i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst".
-	 [round_note]</description>
-	<operation>
-FOR i := 0 TO 31
-	dst.fp16[i] := a.fp16[i] * b.fp16[i]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 TO 31
-	IF k[i]
-		dst.fp16[i] := a.fp16[i] * b.fp16[i]
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	 [round_note]</description>
-	<operation>
-FOR i := 0 TO 31
-	IF k[i]
-		dst.fp16[i] := a.fp16[i] * b.fp16[i]
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 TO 31
-	IF k[i]
-		dst.fp16[i] := a.fp16[i] * b.fp16[i]
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply packed half-precision (16-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	 [round_note]</description>
-	<operation>
-FOR i := 0 TO 31
-	IF k[i]
-		dst.fp16[i] := a.fp16[i] * b.fp16[i]
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VMULPH" xed="VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := a.fp16[0] * b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := a.fp16[0] * b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] * b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] * b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] * b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Multiply the lower half-precision (16-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := a.fp16[0] * b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VMULSH" xed="VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-			[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-			[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_mul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-			[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_mul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-			[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMULCPH" xed="VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-	dst.fp16[1] := src.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-	dst.fp16[1] := src.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-			[round_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-			[round_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-	dst.fp16[1] := src.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_mul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-	dst.fp16[1] := src.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-			[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_mul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-			[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMULCSH" xed="VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fcmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cmul_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fcmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fcmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := src.fp16[2*i+0]
-		dst.fp16[2*i+1] := src.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fcmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cmul_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1])
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1])
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFCMULCPH" xed="VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fcmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fcmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-	dst.fp16[1] := src.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-	dst.fp16[1] := src.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fcmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cmul_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fcmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fcmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-	dst.fp16[1] := src.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "src" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-	dst.fp16[1] := src.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fcmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cmul_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1])
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1])
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFCMULCSH" xed="VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "src", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := a.fp16[2*i+0]
-		dst.fp16[2*i+1] := a.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "src", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := c.fp16[2*i+0]
-		dst.fp16[2*i+1] := c.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fmadd_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fmadd_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := a.fp16[2*i+0]
-		dst.fp16[2*i+1] := a.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fmadd_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := c.fp16[2*i+0]
-		dst.fp16[2*i+1] := c.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fmadd_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" and "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) - (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) + (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFMADDCPH" xed="VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "a" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-	dst.fp16[1] := a.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower complex number in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "c" when mask bit 0 is not set), and copy the upper 6 packed elements from "c" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-	dst.fp16[1] := c.fp16[1]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fmadd_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "a" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-	dst.fp16[1] := a.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fmadd_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "c" when mask bit 0 is not set), and copy the upper 6 packed elements from "c" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-	dst.fp16[1] := c.fp16[1]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fmadd_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex numbers in "a" and "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) - (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) + (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFMADDCSH" xed="VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := a.fp16[2*i+0]
-		dst.fp16[2*i+1] := a.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := c.fp16[2*i+0]
-		dst.fp16[2*i+1] := c.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fcmadd_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fcmadd_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-	dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fcmadd_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := a.fp16[2*i+0]
-		dst.fp16[2*i+1] := a.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask3_fcmadd_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := c.fp16[2*i+0]
-		dst.fp16[2*i+1] := c.fp16[2*i+1]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_fcmadd_round_pch" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="FP16" type="__m512h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply packed complex numbers in "a" by the complex conjugates of packed complex numbers in "b", accumulate to the corresponding complex numbers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[2*i+0] := (a.fp16[2*i+0] * b.fp16[2*i+0]) + (a.fp16[2*i+1] * b.fp16[2*i+1]) + c.fp16[2*i+0]
-		dst.fp16[2*i+1] := (a.fp16[2*i+1] * b.fp16[2*i+0]) - (a.fp16[2*i+0] * b.fp16[2*i+1]) + c.fp16[2*i+1]
-	ELSE
-		dst.fp16[2*i+0] := 0
-		dst.fp16[2*i+1] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VFCMADDCPH" xed="VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fcmadd_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />	
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fcmadd_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "a" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-	dst.fp16[1] := a.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fcmadd_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "c" when mask bit 0 is not set), and copy the upper 6 packed elements from "c" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-	dst.fp16[1] := c.fp16[1]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fcmadd_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fcmadd_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst", and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fcmadd_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "a" when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := a.fp16[0]
-	dst.fp16[1] := a.fp16[1]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask3_fcmadd_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using writemask "k" (elements are copied from "c" when mask bit 0 is not set), and copy the upper 6 packed elements from "c" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := c.fp16[0]
-	dst.fp16[1] := c.fp16[1]
-FI
-dst[127:32] := c[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_fcmadd_round_sch" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="FP16" type="__m128h" varname="c" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Multiply the lower complex number in "a" by the complex conjugate of the lower complex number in "b", accumulate to the lower complex number in "c", and store the result in the lower elements of "dst" using zeromask "k" (elements are zeroed out when mask bit 0 is not set), and copy the upper 6 packed elements from "a" to the upper elements of "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (a.fp16[0] * b.fp16[0]) + (a.fp16[1] * b.fp16[1]) + c.fp16[0]
-	dst.fp16[1] := (a.fp16[1] * b.fp16[0]) - (a.fp16[0] * b.fp16[1]) + c.fp16[1]
-ELSE
-	dst.fp16[0] := 0
-	dst.fp16[1] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VFCMADDCSH" xed="VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_add_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP32" type="__m512h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 15
-	tmp.fp16[i] := tmp.fp16[i] + a.fp16[i+16]
-ENDFOR
-FOR i := 0 to 7
-	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+8]
-ENDFOR
-FOR i := 0 to 3
-	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+4]
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := tmp.fp16[i] + tmp.fp16[i+2]
-ENDFOR
-dst.fp16[0] := tmp.fp16[0] + tmp.fp16[1]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_mul_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP32" type="__m512h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a".</description>
-	<operation>
-tmp := a
-FOR i := 0 to 15
-	tmp.fp16[i] := tmp.fp16[i] * a.fp16[i+16]
-ENDFOR
-FOR i := 0 to 7
-	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+8]
-ENDFOR
-FOR i := 0 to 3
-	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+4]
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := tmp.fp16[i] * tmp.fp16[i+2]
-ENDFOR
-dst.fp16[0] := tmp.fp16[0] * tmp.fp16[1]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_max_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP32" type="__m512h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a". [max_float_note]</description>
-	<operation>
-tmp := a
-FOR i := 0 to 15
-	tmp.fp16[i] := (a.fp16[i] &gt; a.fp16[i+16] ? a.fp16[i] : a.fp16[i+16])
-ENDFOR
-FOR i := 0 to 7
-	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+8] ? tmp.fp16[i] : tmp.fp16[i+8])
-ENDFOR
-FOR i := 0 to 3
-	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := (tmp.fp16[i] &gt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
-ENDFOR
-dst.fp16[0] := (tmp.fp16[0] &gt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_min_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP32" type="__m512h" varname="a" />
-	<description>Reduce the packed half-precision (16-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a". [min_float_note]</description>
-	<operation>
-tmp := a
-FOR i := 0 to 15
-	tmp.fp16[i] := (a.fp16[i] &lt; a.fp16[i+16] ? tmp.fp16[i] : a.fp16[i+16])
-ENDFOR
-FOR i := 0 to 7
-	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+8] ? tmp.fp16[i] : tmp.fp16[i+8])
-ENDFOR
-FOR i := 0 to 3
-	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+4] ? tmp.fp16[i] : tmp.fp16[i+4])
-ENDFOR
-FOR i := 0 to 1
-	tmp.fp16[i] := (tmp.fp16[i] &lt; tmp.fp16[i+2] ? tmp.fp16[i] : tmp.fp16[i+2])
-ENDFOR
-dst.fp16[0] := (tmp.fp16[0] &lt; tmp.fp16[1] ? tmp.fp16[0] : tmp.fp16[1])
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_abs_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="v2" />
-	<description>Finds the absolute value of each packed half-precision (16-bit) floating-point element in "v2", storing the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := ABS(v2.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP32" type="__m512h" varname="dst" />
-	<parameter etype="FP32" type="__m512h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst". Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_conj_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the complex conjugates of complex numbers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each complex number is composed of two adjacent half-precision (16-bit) floating-point elements, which defines the complex number "complex = vec.fp16[0] + i * vec.fp16[1]", or the complex conjugate "conjugate = vec.fp16[0] - i * vec.fp16[1]".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := a[i+31:i] XOR FP32(-0.0)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 31
-	k[j] := (a.fp16[j] OP b.fp16[j]) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 31
-	IF k1[j]
-		k[j] := ( a.fp16[j] OP b.fp16[j] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cmp_round_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 31
-	k[j] := (a.fp16[j] OP b.fp16[j]) ? 1 : 0
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, zmm {sae}, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cmp_round_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>CASE (imm8[3:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-FOR j := 0 to 31
-	IF k1[j]
-		k[j] := ( a.fp16[j] OP b.fp16[j] ) ? 1 : 0
-	ELSE
-		k[j] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, zmm {sae}, imm8" name="VCMPPH" xed="VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_sh_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k".</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-k[0] := (a.fp16[0] OP b.fp16[0]) ? 1 : 0
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, xmm, imm8" name="VCMPSH" xed="VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmp_round_sh_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-k[0] := (a.fp16[0] OP b.fp16[0]) ? 1 : 0
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, xmm {sae}, imm8" name="VCMPSH" xed="VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_sh_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="const int" varname="imm8" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-IF k1[0]
-	k[0] := ( a.fp16[0] OP b.fp16[0] ) ? 1 : 0
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm, imm8" name="VCMPSH" xed="VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cmp_round_sh_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-IF k1[0]
-	k[0] := ( a.fp16[0] OP b.fp16[0] ) ? 1 : 0
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, xmm {sae}, imm8" name="VCMPSH" xed="VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comi_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1).</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-RETURN ( a.fp16[0] OP b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comi_round_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_CMP_" type="const int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1). [sae_note]</description>
-	<operation>CASE (imm8[4:0]) OF
-0: OP := _CMP_EQ_OQ
-1: OP := _CMP_LT_OS
-2: OP := _CMP_LE_OS
-3: OP := _CMP_UNORD_Q
-4: OP := _CMP_NEQ_UQ
-5: OP := _CMP_NLT_US
-6: OP := _CMP_NLE_US
-7: OP := _CMP_ORD_Q
-8: OP := _CMP_EQ_UQ
-9: OP := _CMP_NGE_US
-10: OP := _CMP_NGT_US
-11: OP := _CMP_FALSE_OQ
-12: OP := _CMP_NEQ_OQ
-13: OP := _CMP_GE_OS
-14: OP := _CMP_GT_OS
-15: OP := _CMP_TRUE_UQ
-16: OP := _CMP_EQ_OS
-17: OP := _CMP_LT_OQ
-18: OP := _CMP_LE_OQ
-19: OP := _CMP_UNORD_S
-20: OP := _CMP_NEQ_US
-21: OP := _CMP_NLT_UQ
-22: OP := _CMP_NLE_UQ
-23: OP := _CMP_ORD_S
-24: OP := _CMP_EQ_US
-25: OP := _CMP_NGE_UQ
-26: OP := _CMP_NGT_UQ
-27: OP := _CMP_FALSE_OS
-28: OP := _CMP_NEQ_OS
-29: OP := _CMP_GE_OQ
-30: OP := _CMP_GT_OQ
-31: OP := _CMP_TRUE_US
-ESAC
-RETURN ( a.fp16[0] OP b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm {sae}" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comieq_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for equality, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] == b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comilt_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for less-than, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &lt; b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comile_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &lt;= b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comigt_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for greater-than, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &gt; b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comige_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &gt;= b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comineq_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for not-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a.fp16[0] ==NaN OR b.fp16[0] ==NaN OR a.fp16[0] != b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCOMISH" xed="VCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomieq_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] == b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomilt_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &lt; b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomile_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &lt;= b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomigt_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &gt; b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomige_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a.fp16[0] !=NaN AND b.fp16[0] !=NaN AND a.fp16[0] &gt;= b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomineq_sh" tech="AVX-512">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compare the lower half-precision (16-bit) floating-point elements in "a" and "b" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a.fp16[0] ==NaN OR b.fp16[0] ==NaN OR a.fp16[0] != b.fp16[0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="VUCOMISH" xed="VUCOMISH_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepi16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTW2PH" xed="VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepu16_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.fp16[j] := Convert_Int16_To_FP16(a.word[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTUW2PH" xed="VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {er}" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {er}" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepi32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {er}" name="VCVTDQ2PH" xed="VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {er}" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {er}" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepu32_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 32-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.fp16[j] := Convert_Int32_To_FP16(a.dword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {er}" name="VCVTUDQ2PH" xed="VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm {er}" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm {er}" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepi64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed signed 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm {er}" name="VCVTQQ2PH" xed="VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm {er}" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm {er}" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundepu64_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed unsigned 64-bit integers in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_Int64_To_FP16(a.qword[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm {er}" name="VCVTUQQ2PH" xed="VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, zmm {er}" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, zmm {er}" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.fp16[j] := Convert_FP64_To_FP16(a.fp64[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, zmm {er}" name="VCVTPD2PH" xed="VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper element of "dst".</description>
-	<operation>
-dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvt_roundsd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvt_roundsd_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := Convert_FP64_To_FP16(b.fp64[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VCVTSD2SH" xed="VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtx_roundps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, zmm {er}" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtx_roundps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, zmm {er}" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtxps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtx_roundps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp16[j] := Convert_FP32_To_FP16(a.fp32[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, zmm {er}" name="VCVTPS2PHX" xed="VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundss_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtss_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvt_roundss_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtss_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvt_roundss_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a half-precision (16-bit) floating-point elements, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := Convert_FP32_To_FP16(b.fp32[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VCVTSS2SH" xed="VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {er}" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {er}" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {er}" name="VCVTPH2DQ" xed="VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {sae}" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {sae}" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundph_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_Int32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {sae}" name="VCVTTPH2DQ" xed="VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {er}" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {er}" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {er}" name="VCVTPH2UDQ" xed="VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {sae}" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {sae}" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundph_epu32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 15
-	IF k[j]
-		dst.dword[j] := Convert_FP16_To_UInt32_Truncate(a.fp16[j])
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {sae}" name="VCVTTPH2UDQ" xed="VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm {er}" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm {er}" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm {er}" name="VCVTPH2QQ" xed="VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm {sae}" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm {sae}" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundph_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_Int64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm {sae}" name="VCVTTPH2QQ" xed="VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm {er}" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm {er}" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm  {er}" name="VCVTPH2UQQ" xed="VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm {sae}" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := src.qword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm {sae}" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundph_epu64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 7
-	IF k[j]
-		dst.qword[j] := Convert_FP16_To_UInt64_Truncate(a.fp16[j])
-	ELSE
-		dst.qword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm {sae}" name="VCVTTPH2UQQ" xed="VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VCVTPH2W" xed="VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundph_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_Int16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPH2W" xed="VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VCVTPH2UW" xed="VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtt_roundph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtt_roundph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := src.word[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvttph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtt_roundph_epu16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed unsigned 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 TO 31
-	IF k[j]
-		dst.word[j] := Convert_FP16_To_UInt16_Truncate(a.fp16[j])
-	ELSE
-		dst.word[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VCVTTPH2UW" xed="VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvt_roundph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, xmm {sae}" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-	ELSE
-		dst.fp64[j] := src.fp64[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvt_roundph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-	ELSE
-		dst.fp64[j] := src.fp64[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, xmm {sae}" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-	ELSE
-		dst.fp64[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvt_roundph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		dst.fp64[j] := Convert_FP16_To_FP64(a.fp16[j])
-	ELSE
-		dst.fp64[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, xmm {sae}" name="VCVTPH2PD" xed="VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtx_roundph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, ymm {sae}" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-	ELSE
-		dst.fp32[j] := src.fp32[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_cvtx_roundph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-	ELSE
-		dst.fp32[j] := src.fp32[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, ymm {sae}" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtxph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-	ELSE
-		dst.fp32[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_cvtx_roundph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note]</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		dst.fp32[j] := Convert_FP16_To_FP32(a.fp16[j])
-	ELSE
-		dst.fp32[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, ymm {sae}" name="VCVTPH2PSX" xed="VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsh_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsh_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [sae_note]</description>
-	<operation>
-dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsh_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
-ELSE
-	dst.fp64[0] := src.fp64[0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvt_roundsh_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note]</description>
-	<operation>
-IF k[0]
-	dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
-ELSE
-	dst.fp64[0] := src.fp64[0]
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsh_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
-ELSE
-	dst.fp64[0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvt_roundsh_sd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note]</description>
-	<operation>
-IF k[0]
-	dst.fp64[0] := Convert_FP16_To_FP64(b.fp16[0])
-ELSE
-	dst.fp64[0] := 0
-FI
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VCVTSH2SD" xed="VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsh_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsh_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note]</description>
-	<operation>
-dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvtsh_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
-ELSE
-	dst.fp32[0] := src.fp32[0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_cvt_roundsh_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note]</description>
-	<operation>
-IF k[0]
-	dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
-ELSE
-	dst.fp32[0] := src.fp32[0]
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvtsh_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
-ELSE
-	dst.fp32[0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_cvt_roundsh_ss" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note]</description>
-	<operation>
-IF k[0]
-	dst.fp32[0] := Convert_FP16_To_FP32(b.fp16[0])
-ELSE
-	dst.fp32[0] := 0
-FI
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VCVTSH2SS" xed="VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsh_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst.dword := Convert_FP16_To_Int32(a.fp16[0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTSH2SI" xed="VCVTSH2SI_GPR32i32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsh_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst.dword := Convert_FP16_To_Int32(a.fp16[0])
-	</operation>
-	<instruction form="r32, xmm {er}" name="VCVTSH2SI" xed="VCVTSH2SI_GPR32i32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsh_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst.qword := Convert_FP16_To_Int64(a.fp16[0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTSH2SI" xed="VCVTSH2SI_GPR64i64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsh_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst.qword := Convert_FP16_To_Int64(a.fp16[0])
-	</operation>
-	<instruction form="r64, xmm {er}" name="VCVTSH2SI" xed="VCVTSH2SI_GPR64i64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsh_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst.dword := Convert_FP16_To_Int32_Truncate(a.fp16[0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTTSH2SI" xed="VCVTTSH2SI_GPR32i32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsh_i32" tech="AVX-512">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". [sae_note]</description>
-	<operation>
-dst.dword := Convert_FP16_To_Int32_Truncate(a.fp16[0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTTSH2SI" xed="VCVTTSH2SI_GPR32i32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsh_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst.qword := Convert_FP16_To_Int64_Truncate(a.fp16[0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTTSH2SI" xed="VCVTTSH2SI_GPR64i64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsh_i64" tech="AVX-512">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". [sae_note]</description>
-	<operation>
-dst.qword := Convert_FP16_To_Int64_Truncate(a.fp16[0])
-	</operation>
-	<instruction form="r64, xmm {sae}" name="VCVTTSH2SI" xed="VCVTTSH2SI_GPR64i64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsh_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst.dword := Convert_FP16_To_UInt32(a.fp16[0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTSH2USI" xed="VCVTSH2USI_GPR32u32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsh_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst". [sae_note]</description>
-	<operation>
-dst.dword := Convert_FP16_To_UInt32(a.fp16[0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTSH2USI" xed="VCVTSH2USI_GPR32u32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsh_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst.qword := Convert_FP16_To_UInt64(a.fp16[0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTSH2USI" xed="VCVTSH2USI_GPR64u64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundsh_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst". [round_note]</description>
-	<operation>
-dst.qword := Convert_FP16_To_UInt64(a.fp16[0])
-	</operation>
-	<instruction form="r64, xmm {er}" name="VCVTSH2USI" xed="VCVTSH2USI_GPR64u64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsh_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst.dword := Convert_FP16_To_UInt32_Truncate(a.fp16[0])
-	</operation>
-	<instruction form="r32, xmm" name="VCVTTSH2USI" xed="VCVTTSH2USI_GPR32u32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsh_u32" tech="AVX-512">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst". [sae_note]</description>
-	<operation>
-dst.dword := Convert_FP16_To_UInt32_Truncate(a.fp16[0])
-	</operation>
-	<instruction form="r32, xmm {sae}" name="VCVTTSH2USI" xed="VCVTTSH2USI_GPR32u32_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsh_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst.qword := Convert_FP16_To_UInt64_Truncate(a.fp16[0])
-	</operation>
-	<instruction form="r64, xmm" name="VCVTTSH2USI" xed="VCVTTSH2USI_GPR64u64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_roundsh_u64" tech="AVX-512">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Convert the lower half-precision (16-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst". [sae_note]</description>
-	<operation>
-dst.qword := Convert_FP16_To_UInt64_Truncate(a.fp16[0])
-	</operation>
-	<instruction form="r64, xmm {sae}" name="VCVTTSH2USI" xed="VCVTTSH2USI_GPR64u64_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvti32_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<description>Convert the signed 32-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := Convert_Int32_To_FP16(b.fp32[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32" name="VCVTSI2SH" xed="VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundi32_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the signed 32-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := Convert_Int32_To_FP16(b.fp32[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32 {er}" name="VCVTSI2SH" xed="VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtu32_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<description>Convert the unsigned 32-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := Convert_Int32_To_FP16(b.fp32[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32" name="VCVTUSI2SH" xed="VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundu32_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the unsigned 32-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := Convert_Int32_To_FP16(b.fp32[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r32 {er}" name="VCVTUSI2SH" xed="VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvti64_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<description>Convert the signed 64-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := Convert_Int64_To_FP16(b.fp64[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64" name="VCVTSI2SH" xed="VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundi64_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the signed 64-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := Convert_Int64_To_FP16(b.fp64[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64 {er}" name="VCVTSI2SH" xed="VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtu64_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<description>Convert the unsigned 64-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := Convert_Int64_To_FP16(b.fp64[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64" name="VCVTUSI2SH" xed="VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_roundu64_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the unsigned 64-bit integer "b" to a half-precision (16-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst.fp16[0] := Convert_Int64_To_FP16(b.fp64[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, r64 {er}" name="VCVTUSI2SH" xed="VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi16_si128" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Copy 16-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := a.fp16[0]
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm, r16" name="VMOVW" xed="VMOVW_XMMf16_GPR32f16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi128_si16" tech="AVX-512">
-	<return etype="UI16" type="short" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Copy the lower 16-bit integer in "a" to "dst".</description>
-	<operation>
-dst.fp16[0] := a.fp16[0]
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="r16, xmm" name="VMOVW" xed="VMOVW_GPR32f16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsh_h" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Copy the lower half-precision (16-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[15:0] := a.fp16[0]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtsh_h" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Copy the lower half-precision (16-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[15:0] := a.fp16[0]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_cvtsh_h" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="_Float16" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Copy the lower half-precision (16-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[15:0] := a.fp16[0]
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [max_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_max_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {sae}" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_max_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_max_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note][max_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &gt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMAXPH" xed="VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [min_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_min_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [sae_note] [min_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {sae}" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_min_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note][min_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := src.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {sae}" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_min_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="int" varname="sae" />
-	<description>Compare packed half-precision (16-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note][min_float_note]</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := (a.fp16[j] &lt; b.fp16[j] ? a.fp16[j] : b.fp16[j])
-	ELSE
-		dst.fp16[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {sae}" name="VMINPH" xed="VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_reduce_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-IF k[0]
-	dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_reduce_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-IF k[0]
-	dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-IF k[0]
-	dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_reduce_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Extract the reduced argument of the lower half-precision (16-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-IF k[0]
-	dst.fp16[0] := ReduceArgumentFP16(b.fp16[0], imm8)
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VREDUCESH" xed="VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" memwidth="16" type="void const*" varname="mem_addr" />
-	<description>Load a half-precision (16-bit) floating-point element from memory into the lower element of "dst", and zero the upper elements.</description>
-	<operation>
-dst.fp16[0] := MEM[mem_addr].fp16[0]
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm, m64" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_load_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" memwidth="16" type="void const*" varname="mem_addr" />
-	<description>Load a half-precision (16-bit) floating-point element from memory into the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and set the upper elements of "dst" to zero.</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := MEM[mem_addr].fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm {k}, m64" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_load_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" memwidth="16" type="void const*" varname="mem_addr" />
-	<description>Load a half-precision (16-bit) floating-point element from memory into the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and set the upper elements of "dst" to zero.</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := MEM[mem_addr].fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="xmm {z}, m64" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_load_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVAPS" xed="VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_loadu_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" memwidth="512" type="void const*" varname="mem_addr" />
-	<description>Load 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from memory into "dst". 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[511:0] := MEM[mem_addr+511:mem_addr]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, m512" name="VMOVUPS" xed="VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_sh" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP16" memwidth="16" type="void *" varname="mem_addr" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Store the lower half-precision (16-bit) floating-point element from "a" into memory.</description>
-	<operation>
-MEM[mem_addr].fp16[0] := a.fp16[0]
-	</operation>
-	<instruction form="m16, xmm" name="VMOVSH" xed="VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_store_sh" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP16" memwidth="16" type="void *" varname="mem_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Store the lower half-precision (16-bit) floating-point element from "a" into memory using writemask "k".</description>
-	<operation>
-IF k[0]
-	MEM[mem_addr].fp16[0] := a.fp16[0]
-FI
-	</operation>
-	<instruction form="m16 {k}, xmm" name="VMOVSH" xed="VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_store_ph" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP16" memwidth="512" type="void *" varname="mem_addr" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Store 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVAPS" xed="VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_storeu_ph" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="FP16" memwidth="512" type="void *" varname="mem_addr" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Store 512-bits (composed of 32 packed half-precision (16-bit) floating-point elements) from "a" into memory. 
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+511:mem_addr] := a[511:0]
-	</operation>
-	<instruction form="m512, zmm" name="VMOVUPS" xed="VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_move_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Move the lower half-precision (16-bit) floating-point element from "b" to the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := b.fp16[0]
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_move_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Move the lower half-precision (16-bit) floating-point element from "b" to the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := b.fp16[0]
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_move_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Move the lower half-precision (16-bit) floating-point element from "b" to the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := b.fp16[0]
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VMOVSH" xed="VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm512_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 31
-	dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-ENDFOR
-dest[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_roundscale_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 31
-	dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-ENDFOR
-dest[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dest[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_roundscale_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dest[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_roundscale_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dest[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_roundscale_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round packed half-precision (16-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := RoundScaleFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dest[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}, imm8" name="VRNDSCALEPH" xed="VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
-dst[127:16] := a[127:16]
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_roundscale_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
-dst[127:16] := a[127:16]
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-IF k[0]
-	dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_roundscale_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-IF k[0]
-	dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-IF k[0]
-	dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_roundscale_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Round the lower half-precision (16-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE RoundScaleFP16(src.fp16, imm8[7:0]) {
-	m.fp16 := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp.fp16 := POW(FP16(2.0), -m) * ROUND(POW(FP16(2.0), m) * src.fp16, imm8[3:0])
-	RETURN tmp.fp16
-}
-IF k[0]
-	dst.fp16[0] := RoundScaleFP16(b.fp16[0], imm8)
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dest[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VRNDSCALESH" xed="VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 31
-	dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getexp_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. [sae_note]</description>
-	<operation>FOR i := 0 to 31
-	dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getexp_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. [sae_note]</description>
-	<operation>FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getexp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getexp_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the exponent of each packed half-precision (16-bit) floating-point element in "a" to a half-precision (16-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. [sae_note]</description>
-	<operation>FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := ConvertExpFP16(a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}" name="VGETEXPPH" xed="VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>dst.fp16[0] := ConvertExpFP16(b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getexp_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. [sae_note]</description>
-	<operation>dst.fp16[0] := ConvertExpFP16(b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>IF k[0]
-	dst.fp16[0] := ConvertExpFP16(b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getexp_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. [sae_note]</description>
-	<operation>IF k[0]
-	dst.fp16[0] := ConvertExpFP16(b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element.</description>
-	<operation>IF k[0]
-	dst.fp16[0] := ConvertExpFP16(b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getexp_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Convert the exponent of the lower half-precision (16-bit) floating-point element in "b" to a half-precision (16-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. [sae_note]</description>
-	<operation>IF k[0]
-	dst.fp16[0] := ConvertExpFP16(b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}" name="VGETEXPSH" xed="VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-			[getmant_note]</description>
-	<operation>FOR i := 0 TO 31
-	dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_getmant_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-			[getmant_note][sae_note]</description>
-	<operation>FOR i := 0 TO 31
-	dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-			[getmant_note]</description>
-	<operation>FOR i := 0 TO 31
-	IF k[i]
-		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_getmant_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-			[getmant_note][sae_note]</description>
-	<operation>FOR i := 0 TO 31
-	IF k[i]
-		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getmant_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-			[getmant_note]</description>
-	<operation>FOR i := 0 TO 31
-	IF k[i]
-		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_getmant_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Normalize the mantissas of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-			[getmant_note][sae_note]</description>
-	<operation>FOR i := 0 TO 31
-	IF k[i]
-		dst.fp16[i] := GetNormalizedMantissaFP16(a.fp16[i], norm, sign)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}, imm8" name="VGETMANTPH" xed="VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note]</description>
-	<operation>dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_getmant_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {sae}, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note]</description>
-	<operation>IF k[0]
-	dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_getmant_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>IF k[0]
-	dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {sae}, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note]</description>
-	<operation>IF k[0]
-	dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_getmant_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_NORM" type="_MM_MANTISSA_NORM_ENUM" varname="norm" />
-	<parameter etype="IMM" immtype="_MM_MANTISSA_SIGN" type="_MM_MANTISSA_SIGN_ENUM" varname="sign" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Normalize the mantissas of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "&#177;(2^k)*|x.significand|", where "k" depends on the interval range defined by "norm" and the sign depends on "sign" and the source sign.
-	[getmant_note][sae_note]</description>
-	<operation>IF k[0]
-	dst.fp16[0] := GetNormalizedMantissaFP16(b.fp16[0], norm, sign)
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {sae}, imm8" name="VGETMANTSH" xed="VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 31
-	dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_reduce_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 31
-	dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {sae}, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_reduce_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {sae}, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_reduce_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_reduce_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immtype="_MM_REDUCE" type="int" varname="imm8" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND_SAE" type="const int" varname="sae" />
-	<description>Extract the reduced argument of packed half-precision (16-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note]</description>
-	<operation>
-DEFINE ReduceArgumentFP16(src[15:0], imm8[7:0]) {
-	m[15:0] := FP16(imm8[7:4]) // number of fraction bits after the binary point to be preserved
-	tmp[15:0] := POW(2.0, FP16(-m)) * ROUND(POW(2.0, FP16(m)) * src[15:0], imm8[3:0])
-	tmp[15:0] := src[15:0] - tmp[15:0]
-	IF IsInf(tmp[15:0])
-		tmp[15:0] := FP16(0.0)
-	FI
-	RETURN tmp[15:0]
-}
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := ReduceArgumentFP16(a.fp16[i], imm8)
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {sae}, imm8" name="VREDUCEPH" xed="VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst".</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_scalef_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst".
-	[round_note]</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm {er}" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_scalef_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm {er}" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_scalef_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_scalef_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Scale the packed half-precision (16-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-FOR i := 0 to 15
-	IF k[i]
-		dst.fp16[i] := ScaleFP16(a.fp16[i], b.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm {er}" name="VSCALEFPH" xed="VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_scalef_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-IF k[0]
-	dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_scalef_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-IF k[0]
-	dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-IF k[0]
-	dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_scalef_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>DEFINE ScaleFP16(src1, src2) {
-	denormal1 := (a.exp == 0) and (a.fraction != 0)
-	denormal2 := (b.exp == 0) and (b.fraction != 0)
-	tmp1 := src1
-	tmp2 := src2
-	IF MXCSR.DAZ
-		IF denormal1
-			tmp1 := 0
-		FI
-		IF denormal2
-			tmp2 := 0
-		FI
-	FI
-	RETURN tmp1 * POW(2.0, FLOOR(tmp2))
-}
-IF k[0]
-	dst.fp16[0] := ScaleFP16(a.fp16[0], b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSCALEFSH" xed="VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_fpclass_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k".
-				[fpclass_note]</description>
-	<operation>FOR i := 0 to 31
-	k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k, zmm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_fpclass_ph_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="MASK" type="__mmask32" varname="k1" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test packed half-precision (16-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set).
-			[fpclass_note]</description>
-	<operation>FOR i := 0 to 31
-	IF k1[i]
-		k[i] := CheckFPClass_FP16(a.fp16[i], imm8[7:0])
-	ELSE
-		k[i] := 0
-	FI
-ENDFOR
-k[MAX:32] := 0
-	</operation>
-	<instruction form="k {k}, zmm, imm8" name="VFPCLASSPH" xed="VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_fpclass_sh_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test the lower half-precision (16-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k".
-			[fpclass_note]</description>
-	<operation>k[0] := CheckFPClass_FP16(a.fp16[0], imm8[7:0])
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k, xmm, imm8" name="VFPCLASSSH" xed="VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_fpclass_sh_mask" tech="AVX-512">
-	<return etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="MASK" type="__mmask8" varname="k1" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Test the lower half-precision (16-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set).
-		[fpclass_note]</description>
-	<operation>IF k1[0]
-	k[0] := CheckFPClass_FP16(a.fp16[0], imm8[7:0])
-ELSE
-	k[0] := 0
-FI
-k[MAX:1] := 0
-	</operation>
-	<instruction form="k {k}, xmm, imm8" name="VFPCLASSSH" xed="VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex2var_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Shuffle half-precision (16-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	off := idx[i+4:i]
-	dst.fp16[j] := idx[i+5] ? b.fp16[off] : a.fp16[off]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMI2W" xed="VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<instruction form="zmm, zmm, zmm" name="VPERMT2W" xed="VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_blend_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="FP16" type="__m512h" varname="b" />
-	<description>Blend packed half-precision (16-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	IF k[j]
-		dst.fp16[j] := b.fp16[j]
-	ELSE
-		dst.fp16[j] := a.fp16[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPBLENDMW" xed="VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutexvar_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="idx" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Shuffle half-precision (16-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	id := idx[i+4:i]
-	dst.fp16[j] := a.fp16[id]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMW" xed="VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 31
-	dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VRSQRTPH" xed="VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VRSQRTPH" xed="VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rsqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := (1.0 / SQRT(a.fp16[i]))
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VRSQRTPH" xed="VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rsqrt_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-dst.fp16[0] := (1.0 / SQRT(b.fp16[0]))
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VRSQRTSH" xed="VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rsqrt_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (1.0 / SQRT(b.fp16[0]))
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VRSQRTSH" xed="VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rsqrt_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the approximate reciprocal square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (1.0 / SQRT(b.fp16[0]))
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VRSQRTSH" xed="VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR i := 0 to 31
-	dst.fp16[i] := SQRT(a.fp16[i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_sqrt_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst".
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 31
-	dst.fp16[i] := SQRT(a.fp16[i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm {er}" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := SQRT(a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_sqrt_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := SQRT(a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm {er}" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sqrt_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := SQRT(a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_sqrt_round_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Compute the square root of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).
-	[round_note]</description>
-	<operation>
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := SQRT(a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm {er}" name="VSQRTPH" xed="VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst.fp16[0] := SQRT(b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-dst.fp16[0] := SQRT(b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm {er}" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := SQRT(b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_sqrt_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := SQRT(b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm {er}" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := SQRT(b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_sqrt_round_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="const int" varname="rounding" />
-	<description>Compute the square root of the lower half-precision (16-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst".
-		[round_note]</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := SQRT(b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm {er}" name="VSQRTSH" xed="VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 31
-	dst.fp16[i] := (1.0 / a.fp16[i])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm" name="VRCPPH" xed="VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := (1.0 / a.fp16[i])
-	ELSE
-		dst.fp16[i] := src.fp16[i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VRCPPH" xed="VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_rcp_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Compute the approximate reciprocal of packed half-precision (16-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR i := 0 to 31
-	IF k[i]
-		dst.fp16[i] := (1.0 / a.fp16[i])
-	ELSE
-		dst.fp16[i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VRCPPH" xed="VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rcp_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-dst.fp16[0] := (1.0 / b.fp16[0])
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VRCPSH" xed="VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_rcp_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (1.0 / b.fp16[0])
-ELSE
-	dst.fp16[0] := src.fp16[0]
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VRCPSH" xed="VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_rcp_sh" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<parameter etype="FP16" type="__m128h" varname="b" />
-	<description>Compute the approximate reciprocal of the lower half-precision (16-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 7 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-IF k[0]
-	dst.fp16[0] := (1.0 / b.fp16[0])
-ELSE
-	dst.fp16[0] := 0
-FI
-dst[127:16] := a[127:16]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VRCPSH" xed="VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="e7" />
-	<parameter etype="FP16" type="_Float16" varname="e6" />
-	<parameter etype="FP16" type="_Float16" varname="e5" />
-	<parameter etype="FP16" type="_Float16" varname="e4" />
-	<parameter etype="FP16" type="_Float16" varname="e3" />
-	<parameter etype="FP16" type="_Float16" varname="e2" />
-	<parameter etype="FP16" type="_Float16" varname="e1" />
-	<parameter etype="FP16" type="_Float16" varname="e0" />
-	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst.fp16[0] := e0
-dst.fp16[1] := e1
-dst.fp16[2] := e2
-dst.fp16[3] := e3
-dst.fp16[4] := e4
-dst.fp16[5] := e5
-dst.fp16[6] := e6
-dst.fp16[7] := e7
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="e15" />
-	<parameter etype="FP16" type="_Float16" varname="e14" />
-	<parameter etype="FP16" type="_Float16" varname="e13" />
-	<parameter etype="FP16" type="_Float16" varname="e12" />
-	<parameter etype="FP16" type="_Float16" varname="e11" />
-	<parameter etype="FP16" type="_Float16" varname="e10" />
-	<parameter etype="FP16" type="_Float16" varname="e9" />
-	<parameter etype="FP16" type="_Float16" varname="e8" />
-	<parameter etype="FP16" type="_Float16" varname="e7" />
-	<parameter etype="FP16" type="_Float16" varname="e6" />
-	<parameter etype="FP16" type="_Float16" varname="e5" />
-	<parameter etype="FP16" type="_Float16" varname="e4" />
-	<parameter etype="FP16" type="_Float16" varname="e3" />
-	<parameter etype="FP16" type="_Float16" varname="e2" />
-	<parameter etype="FP16" type="_Float16" varname="e1" />
-	<parameter etype="FP16" type="_Float16" varname="e0" />
-	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst.fp16[0] := e0
-dst.fp16[1] := e1
-dst.fp16[2] := e2
-dst.fp16[3] := e3
-dst.fp16[4] := e4
-dst.fp16[5] := e5
-dst.fp16[6] := e6
-dst.fp16[7] := e7
-dst.fp16[8] := e8
-dst.fp16[9] := e9
-dst.fp16[10] := e10
-dst.fp16[11] := e11
-dst.fp16[12] := e12
-dst.fp16[13] := e13
-dst.fp16[14] := e14
-dst.fp16[15] := e15
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="e31" />
-	<parameter etype="FP16" type="_Float16" varname="e30" />
-	<parameter etype="FP16" type="_Float16" varname="e29" />
-	<parameter etype="FP16" type="_Float16" varname="e28" />
-	<parameter etype="FP16" type="_Float16" varname="e27" />
-	<parameter etype="FP16" type="_Float16" varname="e26" />
-	<parameter etype="FP16" type="_Float16" varname="e25" />
-	<parameter etype="FP16" type="_Float16" varname="e24" />
-	<parameter etype="FP16" type="_Float16" varname="e23" />
-	<parameter etype="FP16" type="_Float16" varname="e22" />
-	<parameter etype="FP16" type="_Float16" varname="e21" />
-	<parameter etype="FP16" type="_Float16" varname="e20" />
-	<parameter etype="FP16" type="_Float16" varname="e19" />
-	<parameter etype="FP16" type="_Float16" varname="e18" />
-	<parameter etype="FP16" type="_Float16" varname="e17" />
-	<parameter etype="FP16" type="_Float16" varname="e16" />
-	<parameter etype="FP16" type="_Float16" varname="e15" />
-	<parameter etype="FP16" type="_Float16" varname="e14" />
-	<parameter etype="FP16" type="_Float16" varname="e13" />
-	<parameter etype="FP16" type="_Float16" varname="e12" />
-	<parameter etype="FP16" type="_Float16" varname="e11" />
-	<parameter etype="FP16" type="_Float16" varname="e10" />
-	<parameter etype="FP16" type="_Float16" varname="e9" />
-	<parameter etype="FP16" type="_Float16" varname="e8" />
-	<parameter etype="FP16" type="_Float16" varname="e7" />
-	<parameter etype="FP16" type="_Float16" varname="e6" />
-	<parameter etype="FP16" type="_Float16" varname="e5" />
-	<parameter etype="FP16" type="_Float16" varname="e4" />
-	<parameter etype="FP16" type="_Float16" varname="e3" />
-	<parameter etype="FP16" type="_Float16" varname="e2" />
-	<parameter etype="FP16" type="_Float16" varname="e1" />
-	<parameter etype="FP16" type="_Float16" varname="e0" />
-	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst.fp16[0] := e0
-dst.fp16[1] := e1
-dst.fp16[2] := e2
-dst.fp16[3] := e3
-dst.fp16[4] := e4
-dst.fp16[5] := e5
-dst.fp16[6] := e6
-dst.fp16[7] := e7
-dst.fp16[8] := e8
-dst.fp16[9] := e9
-dst.fp16[10] := e10
-dst.fp16[11] := e11
-dst.fp16[12] := e12
-dst.fp16[13] := e13
-dst.fp16[14] := e14
-dst.fp16[15] := e15
-dst.fp16[16] := e16
-dst.fp16[17] := e17
-dst.fp16[18] := e18
-dst.fp16[19] := e19
-dst.fp16[20] := e20
-dst.fp16[21] := e21
-dst.fp16[22] := e22
-dst.fp16[23] := e23
-dst.fp16[24] := e24
-dst.fp16[25] := e25
-dst.fp16[26] := e26
-dst.fp16[27] := e27
-dst.fp16[28] := e28
-dst.fp16[29] := e29
-dst.fp16[30] := e30
-dst.fp16[31] := e31
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="e7" />
-	<parameter etype="FP16" type="_Float16" varname="e6" />
-	<parameter etype="FP16" type="_Float16" varname="e5" />
-	<parameter etype="FP16" type="_Float16" varname="e4" />
-	<parameter etype="FP16" type="_Float16" varname="e3" />
-	<parameter etype="FP16" type="_Float16" varname="e2" />
-	<parameter etype="FP16" type="_Float16" varname="e1" />
-	<parameter etype="FP16" type="_Float16" varname="e0" />
-	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst.fp16[0] := e7
-dst.fp16[1] := e6
-dst.fp16[2] := e5
-dst.fp16[3] := e4
-dst.fp16[4] := e3
-dst.fp16[5] := e2
-dst.fp16[6] := e1
-dst.fp16[7] := e0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_setr_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="e15" />
-	<parameter etype="FP16" type="_Float16" varname="e14" />
-	<parameter etype="FP16" type="_Float16" varname="e13" />
-	<parameter etype="FP16" type="_Float16" varname="e12" />
-	<parameter etype="FP16" type="_Float16" varname="e11" />
-	<parameter etype="FP16" type="_Float16" varname="e10" />
-	<parameter etype="FP16" type="_Float16" varname="e9" />
-	<parameter etype="FP16" type="_Float16" varname="e8" />
-	<parameter etype="FP16" type="_Float16" varname="e7" />
-	<parameter etype="FP16" type="_Float16" varname="e6" />
-	<parameter etype="FP16" type="_Float16" varname="e5" />
-	<parameter etype="FP16" type="_Float16" varname="e4" />
-	<parameter etype="FP16" type="_Float16" varname="e3" />
-	<parameter etype="FP16" type="_Float16" varname="e2" />
-	<parameter etype="FP16" type="_Float16" varname="e1" />
-	<parameter etype="FP16" type="_Float16" varname="e0" />
-	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst.fp16[0] := e15
-dst.fp16[1] := e14
-dst.fp16[2] := e13
-dst.fp16[3] := e12
-dst.fp16[4] := e11
-dst.fp16[5] := e10
-dst.fp16[6] := e9
-dst.fp16[7] := e8
-dst.fp16[8] := e7
-dst.fp16[9] := e6
-dst.fp16[10] := e5
-dst.fp16[11] := e4
-dst.fp16[12] := e3
-dst.fp16[13] := e2
-dst.fp16[14] := e1
-dst.fp16[15] := e0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setr_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="e31" />
-	<parameter etype="FP16" type="_Float16" varname="e30" />
-	<parameter etype="FP16" type="_Float16" varname="e29" />
-	<parameter etype="FP16" type="_Float16" varname="e28" />
-	<parameter etype="FP16" type="_Float16" varname="e27" />
-	<parameter etype="FP16" type="_Float16" varname="e26" />
-	<parameter etype="FP16" type="_Float16" varname="e25" />
-	<parameter etype="FP16" type="_Float16" varname="e24" />
-	<parameter etype="FP16" type="_Float16" varname="e23" />
-	<parameter etype="FP16" type="_Float16" varname="e22" />
-	<parameter etype="FP16" type="_Float16" varname="e21" />
-	<parameter etype="FP16" type="_Float16" varname="e20" />
-	<parameter etype="FP16" type="_Float16" varname="e19" />
-	<parameter etype="FP16" type="_Float16" varname="e18" />
-	<parameter etype="FP16" type="_Float16" varname="e17" />
-	<parameter etype="FP16" type="_Float16" varname="e16" />
-	<parameter etype="FP16" type="_Float16" varname="e15" />
-	<parameter etype="FP16" type="_Float16" varname="e14" />
-	<parameter etype="FP16" type="_Float16" varname="e13" />
-	<parameter etype="FP16" type="_Float16" varname="e12" />
-	<parameter etype="FP16" type="_Float16" varname="e11" />
-	<parameter etype="FP16" type="_Float16" varname="e10" />
-	<parameter etype="FP16" type="_Float16" varname="e9" />
-	<parameter etype="FP16" type="_Float16" varname="e8" />
-	<parameter etype="FP16" type="_Float16" varname="e7" />
-	<parameter etype="FP16" type="_Float16" varname="e6" />
-	<parameter etype="FP16" type="_Float16" varname="e5" />
-	<parameter etype="FP16" type="_Float16" varname="e4" />
-	<parameter etype="FP16" type="_Float16" varname="e3" />
-	<parameter etype="FP16" type="_Float16" varname="e2" />
-	<parameter etype="FP16" type="_Float16" varname="e1" />
-	<parameter etype="FP16" type="_Float16" varname="e0" />
-	<description>Set packed half-precision (16-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst.fp16[0] := e31
-dst.fp16[1] := e30
-dst.fp16[2] := e29
-dst.fp16[3] := e28
-dst.fp16[4] := e27
-dst.fp16[5] := e26
-dst.fp16[6] := e25
-dst.fp16[7] := e24
-dst.fp16[8] := e23
-dst.fp16[9] := e22
-dst.fp16[10] := e21
-dst.fp16[11] := e20
-dst.fp16[12] := e19
-dst.fp16[13] := e18
-dst.fp16[14] := e17
-dst.fp16[15] := e16
-dst.fp16[16] := e15
-dst.fp16[17] := e14
-dst.fp16[18] := e13
-dst.fp16[19] := e12
-dst.fp16[20] := e11
-dst.fp16[21] := e10
-dst.fp16[22] := e9
-dst.fp16[23] := e8
-dst.fp16[24] := e7
-dst.fp16[25] := e6
-dst.fp16[26] := e5
-dst.fp16[27] := e4
-dst.fp16[28] := e3
-dst.fp16[29] := e2
-dst.fp16[30] := e1
-dst.fp16[31] := e0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="a" />
-	<description>Broadcast half-precision (16-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[i] := a[15:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set1_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="a" />
-	<description>Broadcast half-precision (16-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[i] := a[15:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set1_ph" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="a" />
-	<description>Broadcast half-precision (16-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR i := 0 to 31
-	dst.fp16[i] := a[15:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="_Float16 _Complex" varname="a" />
-	<description>Broadcast half-precision (16-bit) complex floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR i := 0 to 3
-	dst.fp16[2*i+0] := a[15:0]
-	dst.fp16[2*i+1] := a[31:16]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm256_set1_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="_Float16 _Complex" varname="a" />
-	<description>Broadcast half-precision (16-bit) complex floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR i := 0 to 7
-	dst.fp16[2*i+0] := a[15:0]
-	dst.fp16[2*i+1] := a[31:16]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_set1_pch" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="_Float16 _Complex" varname="a" />
-	<description>Broadcast half-precision (16-bit) complex floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR i := 0 to 15
-	dst.fp16[2*i+0] := a[15:0]
-	dst.fp16[2*i+1] := a[31:16]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_sh" sequence="TRUE" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="_Float16" varname="a" />
-	<description>Copy half-precision (16-bit) floating-point element "a" to the lower element of "dst", and zero the upper 7 elements.</description>
-	<operation>
-dst.fp16[0] := a[15:0]
-dst[127:16] := 0
-	</operation>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm512_setzero_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<description>Return vector of type __m512h with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPXORQ" xed="VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_castph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Cast vector of type "__m128h" to type "__m128". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Cast vector of type "__m256h" to type "__m256". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castph_ps" tech="AVX-512">
-	<return etype="FP32" type="__m512" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Cast vector of type "__m512h" to type "__m512". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Cast vector of type "__m128h" to type "__m128d". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Cast vector of type "__m256h" to type "__m256d". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castph_pd" tech="AVX-512">
-	<return etype="FP64" type="__m512d" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Cast vector of type "__m512h" to type "__m512d". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castph_si128" tech="AVX-512">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Cast vector of type "__m128h" to type "__m128i". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castph_si256" tech="AVX-512">
-	<return etype="M256" type="__m256i" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Cast vector of type "__m256h" to type "__m256i". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castph_si512" tech="AVX-512">
-	<return etype="M512" type="__m512i" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Cast vector of type "__m512h" to type "__m512i". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Cast vector of type "__m128" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<description>Cast vector of type "__m256" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castps_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP32" type="__m512" varname="a" />
-	<description>Cast vector of type "__m512" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Cast vector of type "__m128d" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<description>Cast vector of type "__m256d" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castpd_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP64" type="__m512d" varname="a" />
-	<description>Cast vector of type "__m512d" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castsi128_ph" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Cast vector of type "__m128i" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castsi256_ph" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Cast vector of type "__m256i" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castsi512_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Cast vector of type "__m512i" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castph256_ph128" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Cast vector of type "__m256h" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castph512_ph128" tech="AVX-512">
-	<return etype="FP16" type="__m128h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Cast vector of type "__m512h" to type "__m128h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castph512_ph256" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m512h" varname="a" />
-	<description>Cast vector of type "__m512h" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_castph128_ph256" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Cast vector of type "__m128h" to type "__m256h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castph128_ph512" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Cast vector of type "__m128h" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_castph256_ph512" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Cast vector of type "__m256h" to type "__m512h". This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm256_zextph128_ph256" tech="AVX-512">
-	<return etype="FP16" type="__m256h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Cast vector of type "__m128h" to type "__m256h"; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_zextph128_ph512" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m128h" varname="a" />
-	<description>Cast vector of type "__m128h" to type "__m512h"; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_zextph256_ph512" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<parameter etype="FP16" type="__m256h" varname="a" />
-	<description>Cast vector of type "__m256h" to type "__m512h"; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm512_undefined_ph" tech="AVX-512">
-	<return etype="FP16" type="__m512h" varname="dst" />
-	<description>Return vector of type __m512h with undefined elements.</description>
-	<CPUID>AVX512_FP16</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst".</description>
-	<operation>
-FOR i := 0 to 3
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		dst[q+j*8+7:q+j*8] := tmp8[7:0]
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 3
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		IF k[i*8+j]
-			dst[q+j*8+7:q+j*8] := tmp8[7:0]
-		ELSE
-			dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 3
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		IF k[i*8+j]
-			dst[q+j*8+7:q+j*8] := tmp8[7:0]
-		ELSE
-			dst[q+j*8+7:q+j*8] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst".</description>
-	<operation>
-FOR i := 0 to 1
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		dst[q+j*8+7:q+j*8] := tmp8[7:0]
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 1
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		IF k[i*8+j]
-			dst[q+j*8+7:q+j*8] := tmp8[7:0]
-		ELSE
-			dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 1
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		IF k[i*8+j]
-			dst[q+j*8+7:q+j*8] := tmp8[7:0]
-		ELSE
-			dst[q+j*8+7:q+j*8] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="idx" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	id := idx[i+4:i]*8
-	dst[i+7:i] := a[id+7:id]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMB" xed="VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="idx" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	id := idx[i+4:i]*8
-	IF k[j]
-		dst[i+7:i] := a[id+7:id]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMB" xed="VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="idx" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	id := idx[i+4:i]*8
-	IF k[j]
-		dst[i+7:i] := a[id+7:id]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMB" xed="VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="idx" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	id := idx[i+3:i]*8
-	dst[i+7:i] := a[id+7:id]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMB" xed="VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="idx" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	id := idx[i+3:i]*8
-	IF k[j]
-		dst[i+7:i] := a[id+7:id]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMB" xed="VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="idx" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	id := idx[i+3:i]*8
-	IF k[j]
-		dst[i+7:i] := a[id+7:id]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMB" xed="VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="idx" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	off := 8*idx[i+4:i]
-	dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPERMI2B" xed="VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="idx" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+4:i]
-		dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMT2B" xed="VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask2_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="idx" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+4:i]
-		dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := idx[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPERMI2B" xed="VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="idx" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+4:i]
-		dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMI2B" xed="VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<instruction form="ymm {z}, ymm, ymm" name="VPERMT2B" xed="VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="idx" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	off := 8*idx[i+3:i]
-	dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPERMI2B" xed="VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="idx" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+3:i]
-		dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMT2B" xed="VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask2_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="idx" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+3:i]
-		dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := idx[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPERMI2B" xed="VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="idx" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+3:i]
-		dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMI2B" xed="VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<instruction form="xmm {z}, xmm, xmm" name="VPERMT2B" xed="VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst".</description>
-	<operation>
-FOR i := 0 to 7
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		dst[q+j*8+7:q+j*8] := tmp8[7:0]
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 7
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		IF k[i*8+j]
-			dst[q+j*8+7:q+j*8] := tmp8[7:0]
-		ELSE
-			dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_multishift_epi64_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR i := 0 to 7
-	q := i * 64
-	FOR j := 0 to 7
-		tmp8 := 0
-		ctrl := a[q+j*8+7:q+j*8] &amp; 63
-		FOR l := 0 to 7
-			tmp8[l] := b[q+((ctrl+l) &amp; 63)]
-		ENDFOR
-		IF k[i*8+j]
-			dst[q+j*8+7:q+j*8] := tmp8[7:0]
-		ELSE
-			dst[q+j*8+7:q+j*8] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPMULTISHIFTQB" xed="VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="idx" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	id := idx[i+5:i]*8
-	dst[i+7:i] := a[id+7:id]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMB" xed="VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="idx" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	id := idx[i+5:i]*8
-	IF k[j]
-		dst[i+7:i] := a[id+7:id]
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMB" xed="VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutexvar_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="idx" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	id := idx[i+5:i]*8
-	IF k[j]
-		dst[i+7:i] := a[id+7:id]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMB" xed="VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="idx" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	off := 8*idx[i+5:i]
-	dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPERMI2B" xed="VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="idx" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+5:i]
-		dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMT2B" xed="VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask2_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="idx" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+5:i]
-		dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := idx[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPERMI2B" xed="VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_permutex2var_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="idx" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		off := 8*idx[i+5:i]
-		dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off]
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMI2B" xed="VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<instruction form="zmm {z}, zmm, zmm" name="VPERMT2B" xed="VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_maskz_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSHRDVQ" xed="VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSHRDVQ" xed="VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSHRDVQ" xed="VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSHRDVQ" xed="VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSHRDVQ" xed="VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSHRDVQ" xed="VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSHRDVD" xed="VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSHRDVD" xed="VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSHRDVD" xed="VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSHRDVD" xed="VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSHRDVD" xed="VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSHRDVD" xed="VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="UI16" type="__m256i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSHRDVW" xed="VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="UI16" type="__m256i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSHRDVW" xed="VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="UI16" type="__m256i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSHRDVW" xed="VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="UI16" type="__m128i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSHRDVW" xed="VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="UI16" type="__m128i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSHRDVW" xed="VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="UI16" type="__m128i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSHRDVW" xed="VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHRDQ" xed="VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHRDQ" xed="VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPSHRDQ" xed="VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHRDD" xed="VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHRDD" xed="VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPSHRDD" xed="VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHRDD" xed="VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHRDD" xed="VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPSHRDD" xed="VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHRDW" xed="VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHRDW" xed="VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPSHRDW" xed="VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHRDW" xed="VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHRDW" xed="VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPSHRDW" xed="VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSHLDVQ" xed="VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSHLDVQ" xed="VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="UI64" type="__m256i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-	dst[i+63:i] := tmp[127:64]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSHLDVQ" xed="VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSHLDVQ" xed="VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSHLDVQ" xed="VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="UI64" type="__m128i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-	dst[i+63:i] := tmp[127:64]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSHLDVQ" xed="VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSHLDVD" xed="VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSHLDVD" xed="VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="UI32" type="__m256i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-	dst[i+31:i] := tmp[63:32]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSHLDVD" xed="VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSHLDVD" xed="VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSHLDVD" xed="VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-	dst[i+31:i] := tmp[63:32]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSHLDVD" xed="VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="UI16" type="__m256i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPSHLDVW" xed="VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="UI16" type="__m256i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPSHLDVW" xed="VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="UI16" type="__m256i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPSHLDVW" xed="VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="UI16" type="__m128i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPSHLDVW" xed="VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="UI16" type="__m128i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPSHLDVW" xed="VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="UI16" type="__m128i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPSHLDVW" xed="VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHLDQ" xed="VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHLDQ" xed="VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst").</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-	dst[i+63:i] := tmp[127:64]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPSHLDQ" xed="VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst").</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-	dst[i+63:i] := tmp[127:64]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHLDD" xed="VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHLDD" xed="VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m256i" varname="dst" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-	dst[i+31:i] := tmp[63:32]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPSHLDD" xed="VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHLDD" xed="VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHLDD" xed="VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-	dst[i+31:i] := tmp[63:32]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPSHLDD" xed="VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VPSHLDW" xed="VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VPSHLDW" xed="VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<parameter etype="UI16" type="__m256i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst").</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*16
-	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPSHLDW" xed="VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VPSHLDW" xed="VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VPSHLDW" xed="VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst").</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VPSHLDW" xed="VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expandloadu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" memwidth="256" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m256" name="VPEXPANDW" xed="VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expandloadu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" memwidth="256" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m256" name="VPEXPANDW" xed="VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expandloadu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" memwidth="128" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m128" name="VPEXPANDW" xed="VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expandloadu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" memwidth="128" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m128" name="VPEXPANDW" xed="VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expandloadu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" memwidth="256" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, m256" name="VPEXPANDB" xed="VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expandloadu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" memwidth="256" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, m256" name="VPEXPANDB" xed="VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expandloadu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" memwidth="128" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, m128" name="VPEXPANDB" xed="VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expandloadu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" memwidth="128" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, m128" name="VPEXPANDB" xed="VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expand_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[m+15:m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPEXPANDW" xed="VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expand_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[m+15:m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPEXPANDW" xed="VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expand_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[m+15:m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPEXPANDW" xed="VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expand_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[m+15:m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPEXPANDW" xed="VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_expand_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[m+7:m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPEXPANDB" xed="VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_expand_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[m+7:m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPEXPANDB" xed="VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_expand_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[m+7:m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPEXPANDB" xed="VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_expand_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[m+7:m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPEXPANDB" xed="VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_compress_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 16
-m := 0
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPCOMPRESSW" xed="VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compress_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m256i" varname="dst" />
-	<parameter etype="UI16" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 16
-m := 0
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		dst[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := src[255:m]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPCOMPRESSW" xed="VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_compress_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 16
-m := 0
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compress_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 16
-m := 0
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		dst[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := src[127:m]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_compress_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 8
-m := 0
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := 0
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm" name="VPCOMPRESSB" xed="VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compress_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 8
-m := 0
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		dst[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-dst[255:m] := src[255:m]
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm" name="VPCOMPRESSB" xed="VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_compress_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 8
-m := 0
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := 0
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compress_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 8
-m := 0
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		dst[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-dst[127:m] := src[127:m]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compressstoreu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI16" type="__m256i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 16
-m := base_addr
-FOR j := 0 to 15
-	i := j*16
-	IF k[j]
-		MEM[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VPCOMPRESSW" xed="VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compressstoreu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 16
-m := base_addr
-FOR j := 0 to 7
-	i := j*16
-	IF k[j]
-		MEM[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_compressstoreu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="256" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 8
-m := base_addr
-FOR j := 0 to 31
-	i := j*8
-	IF k[j]
-		MEM[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m256 {k}, ymm" name="VPCOMPRESSB" xed="VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_compressstoreu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="128" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 8
-m := base_addr
-FOR j := 0 to 15
-	i := j*8
-	IF k[j]
-		MEM[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m128 {k}, xmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_maskz_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSHRDVQ" xed="VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSHRDVQ" xed="VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shrdv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; (c[i+63:i] &amp; 63)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSHRDVQ" xed="VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSHRDVD" xed="VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSHRDVD" xed="VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shrdv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; (c[i+31:i] &amp; 31)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSHRDVD" xed="VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="UI16" type="__m512i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSHRDVW" xed="VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="UI16" type="__m512i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSHRDVW" xed="VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shrdv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="UI16" type="__m512i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; (c[i+15:i] &amp; 15)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSHRDVW" xed="VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shrdi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	dst[i+63:i] := ((b[i+63:i] &lt;&lt; 64)[127:0] | a[i+63:i]) &gt;&gt; imm8[5:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPSHRDQ" xed="VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHRDD" xed="VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHRDD" xed="VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shrdi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	dst[i+31:i] := ((b[i+31:i] &lt;&lt; 32)[63:0] | a[i+31:i]) &gt;&gt; imm8[4:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPSHRDD" xed="VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHRDW" xed="VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHRDW" xed="VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shrdi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	dst[i+15:i] := ((b[i+15:i] &lt;&lt; 16)[31:0] | a[i+15:i]) &gt;&gt; imm8[3:0]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPSHRDW" xed="VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSHLDVQ" xed="VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSHLDVQ" xed="VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shldv_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="UI64" type="__m512i" varname="c" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; (c[i+63:i] &amp; 63)
-	dst[i+63:i] := tmp[127:64]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSHLDVQ" xed="VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSHLDVD" xed="VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSHLDVD" xed="VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shldv_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="UI32" type="__m512i" varname="c" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; (c[i+31:i] &amp; 31)
-	dst[i+31:i] := tmp[63:32]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSHLDVD" xed="VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="UI16" type="__m512i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPSHLDVW" xed="VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="UI16" type="__m512i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPSHLDVW" xed="VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shldv_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="UI16" type="__m512i" varname="c" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; (c[i+15:i] &amp; 15)
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPSHLDVW" xed="VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	IF k[j]
-		tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-		dst[i+63:i] := tmp[127:64]
-	ELSE
-		dst[i+63:i] := src[i+63:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shldi_epi64" tech="AVX-512">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst").</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*64
-	tmp[127:0] := ((a[i+63:i] &lt;&lt; 64)[127:0] | b[i+63:i]) &lt;&lt; imm8[5:0]
-	dst[i+63:i] := tmp[127:64]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPSHLDQ" xed="VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHLDD" xed="VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	IF k[j]
-		tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-		dst[i+31:i] := tmp[63:32]
-	ELSE
-		dst[i+31:i] := src[i+31:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHLDD" xed="VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shldi_epi32" tech="AVX-512">
-	<return etype="UI32" type="__m512i" varname="dst" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*32
-	tmp[63:0] := ((a[i+31:i] &lt;&lt; 32)[63:0] | b[i+31:i]) &lt;&lt; imm8[4:0]
-	dst[i+31:i] := tmp[63:32]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPSHLDD" xed="VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VPSHLDW" xed="VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-		dst[i+15:i] := tmp[31:16]
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VPSHLDW" xed="VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_shldi_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<parameter etype="UI16" type="__m512i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst").</description>
-	<operation>
-FOR j := 0 to 31
-	i := j*16
-	tmp[31:0] := ((a[i+15:i] &lt;&lt; 16)[31:0] | b[i+15:i]) &lt;&lt; imm8[3:0]
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPSHLDW" xed="VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expandloadu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" memwidth="512" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VPEXPANDW" xed="VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expandloadu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" memwidth="512" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VPEXPANDW" xed="VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expandloadu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" memwidth="512" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, m512" name="VPEXPANDB" xed="VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expandloadu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" memwidth="512" type="const void*" varname="mem_addr" />
-	<description>Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, m512" name="VPEXPANDB" xed="VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expand_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[m+15:m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPEXPANDW" xed="VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expand_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[i+15:i] := a[m+15:m]
-		m := m + 16
-	ELSE
-		dst[i+15:i] := src[i+15:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPEXPANDW" xed="VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_expand_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[m+7:m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPEXPANDB" xed="VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_expand_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-m := 0
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[i+7:i] := a[m+7:m]
-		m := m + 8
-	ELSE
-		dst[i+7:i] := src[i+7:i]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPEXPANDB" xed="VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_compress_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 16
-m := 0
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := 0
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compress_epi16" tech="AVX-512">
-	<return etype="UI16" type="__m512i" varname="dst" />
-	<parameter etype="UI16" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 16
-m := 0
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		dst[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := src[511:m]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_compress_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero.</description>
-	<operation>
-size := 8
-m := 0
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := 0
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compress_epi8" tech="AVX-512">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src".</description>
-	<operation>
-size := 8
-m := 0
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		dst[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-dst[511:m] := src[511:m]
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compressstoreu_epi16" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="UI16" memwidth="512" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI16" type="__m512i" varname="a" />
-	<description>Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 16
-m := base_addr
-FOR j := 0 to 31
-	i := j*16
-	IF k[j]
-		MEM[m+size-1:m] := a[i+15:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VPCOMPRESSW" xed="VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_compressstoreu_epi8" tech="AVX-512">
-	<category>Swizzle</category>
-	<return type="void" />
-	<parameter etype="UI8" memwidth="512" type="void*" varname="base_addr" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<description>Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr".</description>
-	<operation>
-size := 8
-m := base_addr
-FOR j := 0 to 63
-	i := j*8
-	IF k[j]
-		MEM[m+size-1:m] := a[i+7:i]
-		m := m + size
-	FI
-ENDFOR
-	</operation>
-	<instruction form="m512 {k}, zmm" name="VPCOMPRESSB" xed="VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512" />
-	<CPUID>AVX512_VBMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_maskz_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPDPWSSDS" xed="VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPDPWSSDS" xed="VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPDPWSSDS" xed="VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPDPWSSDS" xed="VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPDPWSSDS" xed="VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPDPWSSDS" xed="VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPDPWSSD" xed="VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPDPWSSD" xed="VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="SI16" type="__m256i" varname="a" />
-	<parameter etype="SI16" type="__m256i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPDPWSSD" xed="VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPDPWSSD" xed="VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPDPWSSD" xed="VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPDPWSSD" xed="VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPDPBUSDS" xed="VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPDPBUSDS" xed="VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPDPBUSDS" xed="VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPDPBUSDS" xed="VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPDPBUSDS" xed="VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPDPBUSDS" xed="VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VPDPBUSD" xed="VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 7
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VPDPBUSD" xed="VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m256i" varname="dst" />
-	<parameter etype="SI32" type="__m256i" varname="src" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="SI8" type="__m256i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VPDPBUSD" xed="VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VPDPBUSD" xed="VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask8" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 3
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VPDPBUSD" xed="VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="src" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VPDPBUSD" xed="VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_maskz_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPDPWSSDS" xed="VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPDPWSSDS" xed="VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_dpwssds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPDPWSSDS" xed="VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPDPWSSD" xed="VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-		tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPDPWSSD" xed="VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_dpwssd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="SI16" type="__m512i" varname="a" />
-	<parameter etype="SI16" type="__m512i" varname="b" />
-	<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPDPWSSD" xed="VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPDPBUSDS" xed="VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPDPBUSDS" xed="VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_dpbusds_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPDPBUSDS" xed="VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-	ELSE
-		dst.dword[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VPDPBUSD" xed="VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-FOR j := 0 to 15
-	IF k[j]
-		tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-		tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-		tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-		tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-		dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-	ELSE
-		dst.dword[j] := src.dword[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VPDPBUSD" xed="VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_dpbusd_epi32" tech="AVX-512">
-	<return etype="SI32" type="__m512i" varname="dst" />
-	<parameter etype="SI32" type="__m512i" varname="src" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="SI8" type="__m512i" varname="b" />
-	<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VPDPBUSD" xed="VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512" />
-	<CPUID>AVX512_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_2intersect_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="__m512i" varname="a" />
-	<parameter etype="UI32" type="__m512i" varname="b" />
-	<parameter etype="MASK" memwidth="16" type="__mmask16*" varname="k1" />
-	<parameter etype="MASK" memwidth="16" type="__mmask16*" varname="k2" />
-	<description>Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
-	<operation>
-MEM[k1+15:k1] := 0
-MEM[k2+15:k2] := 0
-FOR i := 0 TO 15
-	FOR j := 0 TO 15
-		match := (a.dword[i] == b.dword[j] ? 1 : 0)
-		MEM[k1+15:k1].bit[i] |= match
-		MEM[k2+15:k2].bit[j] |= match
-	ENDFOR
-ENDFOR
-	</operation>
-	<instruction form="k, zmm, zmm" name="VP2INTERSECTD" xed="VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512" />
-	<CPUID>AVX512_VP2INTERSECT</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm512_2intersect_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="__m512i" varname="a" />
-	<parameter etype="UI64" type="__m512i" varname="b" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
-	<description>Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
-	<operation>
-MEM[k1+7:k1] := 0
-MEM[k2+7:k2] := 0
-FOR i := 0 TO 7
-	FOR j := 0 TO 7
-		match := (a.qword[i] == b.qword[j] ? 1 : 0)
-		MEM[k1+7:k1].bit[i] |= match
-		MEM[k2+7:k2].bit[j] |= match
-	ENDFOR
-ENDFOR
-	</operation>
-	<instruction form="k, zmm, zmm" name="VP2INTERSECTQ" xed="VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512" />
-	<CPUID>AVX512_VP2INTERSECT</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_2intersect_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
-	<description>Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
-	<operation>
-MEM[k1+7:k1] := 0
-MEM[k2+7:k2] := 0
-FOR i := 0 TO 3
-	FOR j := 0 TO 3
-		match := (a.dword[i] == b.dword[j] ? 1 : 0)
-		MEM[k1+7:k1].bit[i] |= match
-		MEM[k2+7:k2].bit[j] |= match
-	ENDFOR
-ENDFOR
-	</operation>
-	<instruction form="k, xmm, xmm" name="VP2INTERSECTD" xed="VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512" />
-	<CPUID>AVX512_VP2INTERSECT</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm256_2intersect_epi32" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI32" type="__m256i" varname="a" />
-	<parameter etype="UI32" type="__m256i" varname="b" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
-	<description>Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
-	<operation>
-MEM[k1+7:k1] := 0
-MEM[k2+7:k2] := 0
-FOR i := 0 TO 7
-	FOR j := 0 TO 7
-		match := (a.dword[i] == b.dword[j] ? 1 : 0)
-		MEM[k1+7:k1].bit[i] |= match
-		MEM[k2+7:k2].bit[j] |= match
-	ENDFOR
-ENDFOR
-	</operation>
-	<instruction form="k, ymm, ymm" name="VP2INTERSECTD" xed="VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512" />
-	<CPUID>AVX512_VP2INTERSECT</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm_2intersect_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
-	<description>Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
-	<operation>
-MEM[k1+7:k1] := 0
-MEM[k2+7:k2] := 0
-FOR i := 0 TO 1
-	FOR j := 0 TO 1
-		match := (a.qword[i] == b.qword[j] ? 1 : 0)
-		MEM[k1+7:k1].bit[i] |= match
-		MEM[k2+7:k2].bit[j] |= match
-	ENDFOR
-ENDFOR
-	</operation>
-	<instruction form="k, xmm, xmm" name="VP2INTERSECTQ" xed="VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512" />
-	<CPUID>AVX512_VP2INTERSECT</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	<intrinsic name="_mm256_2intersect_epi64" tech="AVX-512">
-	<return type="void" />
-	<parameter etype="UI64" type="__m256i" varname="a" />
-	<parameter etype="UI64" type="__m256i" varname="b" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k1" />
-	<parameter etype="MASK" memwidth="8" type="__mmask8*" varname="k2" />
-	<description>Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers.</description>
-	<operation>
-MEM[k1+7:k1] := 0
-MEM[k2+7:k2] := 0
-FOR i := 0 TO 3
-	FOR j := 0 TO 3
-		match := (a.qword[i] == b.qword[j] ? 1 : 0)
-		MEM[k1+7:k1].bit[i] |= match
-		MEM[k2+7:k2].bit[j] |= match
-	ENDFOR
-ENDFOR
-	</operation>
-	<instruction form="k, ymm, ymm" name="VP2INTERSECTQ" xed="VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512" />
-	<CPUID>AVX512_VP2INTERSECT</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Mask</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_madd52hi_avx_epu64" tech="AVX_ALL">
-	<return type="__m256i" varname="dst" etype="UI64" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
-	<instruction name="VPMADD52HUQ" form="ymm, ymm, ymm" xed="VPMADD52HUQ_YMMu64_YMMu64_YMMu64" />
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
-	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-	<parameter type="__m256i" varname="__X" etype="UI64" />
-	<parameter type="__m256i" varname="__Y" etype="UI64" />
-	<parameter type="__m256i" varname="__Z" etype="UI64" />
-	<CPUID>AVX_IFMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_madd52lo_avx_epu64" tech="AVX_ALL">
-	<return type="__m256i" varname="dst" etype="UI64" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
-	<instruction name="VPMADD52LUQ" form="ymm, ymm, ymm" xed="VPMADD52LUQ_YMMu64_YMMu64_YMMu64" />
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
-	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-	<parameter type="__m256i" varname="__X" etype="UI64" />
-	<parameter type="__m256i" varname="__Y" etype="UI64" />
-	<parameter type="__m256i" varname="__Z" etype="UI64" />
-	<CPUID>AVX_IFMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_madd52hi_avx_epu64" tech="AVX_ALL">
-	<return type="__m128i" varname="dst" etype="UI64" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
-	<instruction name="VPMADD52HUQ" form="xmm, xmm, xmm" xed="VPMADD52HUQ_XMMu64_XMMu64_XMMu64" />
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
-	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-	<parameter type="__m128i" varname="__X" etype="UI64" />
-	<parameter type="__m128i" varname="__Y" etype="UI64" />
-	<parameter type="__m128i" varname="__Z" etype="UI64" />
-	<CPUID>AVX_IFMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_madd52lo_avx_epu64" tech="AVX_ALL">
-	<return type="__m128i" varname="dst" etype="UI64" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
-	<instruction name="VPMADD52LUQ" form="xmm, xmm, xmm" xed="VPMADD52LUQ_XMMu64_XMMu64_XMMu64" />
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
-	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-	<parameter type="__m128i" varname="__X" etype="UI64" />
-	<parameter type="__m128i" varname="__Y" etype="UI64" />
-	<parameter type="__m128i" varname="__Z" etype="UI64" />
-	<CPUID>AVX_IFMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-<intrinsic name="_mm256_madd52hi_epu64" tech="AVX_ALL">
-	<return type="__m256i" varname="dst" etype="UI64" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
-	<instruction name="VPMADD52HUQ" form="ymm, ymm, ymm" xed="VPMADD52HUQ_YMMu64_YMMu64_YMMu64" />
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
-	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-	<parameter type="__m256i" varname="__X" etype="UI64" />
-	<parameter type="__m256i" varname="__Y" etype="UI64" />
-	<parameter type="__m256i" varname="__Z" etype="UI64" />
-	<CPUID>AVX_IFMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_madd52lo_epu64" tech="AVX_ALL">
-	<return type="__m256i" varname="dst" etype="UI64" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
-	<instruction name="VPMADD52LUQ" form="ymm, ymm, ymm" xed="VPMADD52LUQ_YMMu64_YMMu64_YMMu64" />
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
-	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-	<parameter type="__m256i" varname="__X" etype="UI64" />
-	<parameter type="__m256i" varname="__Y" etype="UI64" />
-	<parameter type="__m256i" varname="__Z" etype="UI64" />
-	<CPUID>AVX_IFMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_madd52hi_epu64" tech="AVX_ALL">
-	<return type="__m128i" varname="dst" etype="UI64" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
-	<instruction name="VPMADD52HUQ" form="xmm, xmm, xmm" xed="VPMADD52HUQ_XMMu64_XMMu64_XMMu64" />
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
-	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[103:52])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-	<parameter type="__m128i" varname="__X" etype="UI64" />
-	<parameter type="__m128i" varname="__Y" etype="UI64" />
-	<parameter type="__m128i" varname="__Z" etype="UI64" />
-	<CPUID>AVX_IFMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_madd52lo_epu64" tech="AVX_ALL">
-	<return type="__m128i" varname="dst" etype="UI64" />
-	<description>Multiply packed unsigned 52-bit integers in each 64-bit element of "__Y" and "__Z" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "__X", and store the results in "dst".</description>
-	<instruction name="VPMADD52LUQ" form="xmm, xmm, xmm" xed="VPMADD52LUQ_XMMu64_XMMu64_XMMu64" />
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	tmp[127:0] := ZeroExtend64(__Y[i+51:i]) * ZeroExtend64(__Z[i+51:i])
-	dst[i+63:i] := __X[i+63:i] + ZeroExtend64(tmp[51:0])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-	<parameter type="__m128i" varname="__X" etype="UI64" />
-	<parameter type="__m128i" varname="__Y" etype="UI64" />
-	<parameter type="__m128i" varname="__Z" etype="UI64" />
-	<CPUID>AVX_IFMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-<intrinsic name="_mm256_bcstnebf16_ps" tech="AVX_ALL">
-		<return type="__m256" varname="dst" etype="FP32" />
-		<description>Convert scalar BF16 (16-bit) floating-point element stored at memory locations starting at location "__A" to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VBCSTNEBF162PS" form="ymm, m16" xed="VBCSTNEBF162PS_YMMf32_MEMbf16" />
-		<operation>
-b := Convert_BF16_To_FP32(MEM[__A+15:__A])
-FOR j := 0 to 7
-	m := j*32
-	dst[m+31:m] := b
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="const __bf16*" memwidth="16" varname="__A" etype="BF16"/>
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_bcstnesh_ps" tech="AVX_ALL">
-		<return type="__m256" varname="dst" etype="FP32" />
-		<description>Convert scalar half-precision (16-bit) floating-point element stored at memory locations starting at location "__A" to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VBCSTNESH2PS" form="ymm, m16" xed="VBCSTNESH2PS_YMMf32_MEMf16" />
-		<operation>
-b := Convert_FP16_To_FP32(MEM[__A+15:__A])
-FOR j := 0 to 7
-	m := j*32
-	dst[m+31:m] := b
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="const _Float16*" memwidth="16" varname="__A" etype="FP16"/>
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtneebf16_ps" tech="AVX_ALL">
-		<return type="__m256" varname="dst" etype="FP32" />
-		<description>Convert packed BF16 (16-bit) floating-point even-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEEBF162PS" form="ymm, m256" xed="VCVTNEEBF162PS_YMMf32_MEMbf16" />
-		<operation>
-FOR j := 0 to 7
-	m := j*32
-	dst[m+31:m] := Convert_BF16_To_FP32(MEM[__A+m+15:__A+m])
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="const __m256bh*" memwidth="256" varname="__A" etype="BF16"/>
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtneeph_ps" tech="AVX_ALL">
-		<return type="__m256" varname="dst" etype="FP32" />
-		<description>Convert packed half-precision (16-bit) floating-point even-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEEPH2PS" form="ymm, m256" xed="VCVTNEEPH2PS_YMMf32_MEMf16" />
-		<operation>
-FOR j := 0 to 7
-	m := j*32
-	dst[m+31:m] := Convert_FP16_To_FP32(MEM[__A+m+15:__A+m])
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="const __m256h*" memwidth="256" etype="FP16" varname="__A" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtneobf16_ps" tech="AVX_ALL">
-		<return type="__m256" varname="dst" etype="FP32" />
-		<description>Convert packed BF16 (16-bit) floating-point odd-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEOBF162PS" form="ymm, m256" xed="VCVTNEOBF162PS_YMMf32_MEMbf16" />
-		<operation>
-FOR j := 0 to 7
-	m := j*32
-	dst[m+31:m] := Convert_BF16_To_FP32(MEM[__A+m+31:__A+m+16])
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="const __m256bh*" memwidth="256" etype="BF16" varname="__A" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtneoph_ps" tech="AVX_ALL">
-		<return type="__m256" varname="dst" etype="FP32" />
-		<description>Convert packed half-precision (16-bit) floating-point odd-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEOPH2PS" form="ymm, m256" xed="VCVTNEOPH2PS_YMMf32_MEMf16" />
-		<operation>
-FOR j := 0 to 7
-	m := j*32
-	dst[m+31:m] := Convert_FP16_To_FP32(MEM[__A+m+31:__A+m+16])
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="const __m256h*" memwidth="256" etype="FP16" varname="__A" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtneps_avx_pbh" tech="AVX_ALL">
-		<return type="__m128bh" varname="dst" etype="BF16" />
-		<description>Convert packed single-precision (32-bit) floating-point elements in "__A" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEPS2BF16" form="xmm, ymm" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
-		<operation>
-FOR j := 0 to 7
-	dst.word[j] := Convert_FP32_To_BF16(__A.fp32[j])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="__m256" varname="__A" etype="FP32" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_bcstnebf16_ps" tech="AVX_ALL">
-		<return type="__m128" varname="dst" etype="FP32" />
-		<description>Convert scalar BF16 (16-bit) floating-point element stored at memory locations starting at location "__A" to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VBCSTNEBF162PS" form="xmm, m16" xed="VBCSTNEBF162PS_XMMf32_MEMbf16" />
-		<operation>
-b := Convert_BF16_To_FP32(MEM[__A+15:__A])
-FOR j := 0 to 3
-	m := j*32
-	dst[m+31:m] := b
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="const __bf16*" varname="__A" memwidth="16" etype="BF16"/>
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_bcstnesh_ps" tech="AVX_ALL">
-		<return type="__m128" varname="dst" etype="FP32" />
-		<description>Convert scalar half-precision (16-bit) floating-point element stored at memory locations starting at location "__A" to a single-precision (32-bit) floating-point, broadcast it to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VBCSTNESH2PS" form="xmm, m16" xed="VBCSTNESH2PS_XMMf32_MEMf16" />
-		<operation>
-b := Convert_FP16_To_FP32(MEM[__A+15:__A])
-FOR j := 0 to 3
-	m := j*32
-	dst[m+31:m] := b
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="const _Float16*" varname="__A" memwidth="16" etype="FP16"/>
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtneebf16_ps" tech="AVX_ALL">
-		<return type="__m128" varname="dst" etype="FP32" />
-		<description>Convert packed BF16 (16-bit) floating-point even-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEEBF162PS" form="xmm, m128" xed="VCVTNEEBF162PS_XMMf32_MEMbf16" />
-		<operation>
-FOR j := 0 to 3
-	m := j*32
-	dst[m+31:m] := Convert_BF16_To_FP32(MEM[__A+m+15:__A+m])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="const __m128bh*" memwidth="128" etype="BF16" varname="__A" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtneeph_ps" tech="AVX_ALL">
-		<return type="__m128" varname="dst" etype="FP32" />
-		<description>Convert packed half-precision (16-bit) floating-point even-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEEPH2PS" form="xmm, m128" xed="VCVTNEEPH2PS_XMMf32_MEMf16" />
-		<operation>
-FOR j := 0 to 3
-	m := j*32
-	dst[m+31:m] := Convert_FP16_To_FP32(MEM[__A+m+15:__A+m])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="const __m128h*" memwidth="128" etype="FP16" varname="__A" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtneobf16_ps" tech="AVX_ALL">
-		<return type="__m128" varname="dst" etype="FP32" />
-		<description>Convert packed BF16 (16-bit) floating-point odd-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEOBF162PS" form="xmm, m128" xed="VCVTNEOBF162PS_XMMf32_MEMbf16" />
-		<operation>
-FOR j := 0 to 3
-	m := j*32
-	dst[m+31:m] := Convert_BF16_To_FP32(MEM[__A+m+31:__A+m+16])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="const __m128bh*" memwidth="128" etype="BF16" varname="__A" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtneoph_ps" tech="AVX_ALL">
-		<return type="__m128" varname="dst" etype="FP32" />
-		<description>Convert packed half-precision (16-bit) floating-point odd-indexed elements stored at memory locations starting at location "__A" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEOPH2PS" form="xmm, m128" xed="VCVTNEOPH2PS_XMMf32_MEMf16" />
-		<operation>
-FOR j := 0 to 3
-	m := j*32
-	dst[m+31:m] := Convert_FP16_To_FP32(MEM[__A+m+31:__A+m+16])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="const __m128h*" memwidth="128" etype="FP16" varname="__A" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtneps_avx_pbh" tech="AVX_ALL">
-		<return type="__m128bh" varname="dst" etype="BF16" />
-		<description>Convert packed single-precision (32-bit) floating-point elements in "__A" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEPS2BF16" form="xmm, xmm" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
-		<operation>
-FOR j := 0 to 3
-	dst.word[j] := Convert_FP32_To_BF16(__A.fp32[j])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="__m128" varname="__A" etype="FP32" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtneps_pbh" tech="AVX_ALL">
-		<return type="__m128bh" varname="dst" etype="BF16" />
-		<description>Convert packed single-precision (32-bit) floating-point elements in "__A" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEPS2BF16" form="xmm, ymm" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512" />
-		<operation>
-FOR j := 0 to 7
-	dst.word[j] := Convert_FP32_To_BF16(__A.fp32[j])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="__m256" varname="__A" etype="FP32" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtneps_pbh" tech="AVX_ALL">
-		<return type="__m128bh" varname="dst" etype="BF16" />
-		<description>Convert packed single-precision (32-bit) floating-point elements in "__A" to packed BF16 (16-bit) floating-point elements, and store the results in "dst".</description>
-		<instruction name="VCVTNEPS2BF16" form="xmm, xmm" xed="VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512" />
-		<operation>
-FOR j := 0 to 3
-	dst.word[j] := Convert_FP32_To_BF16(__A.fp32[j])
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="__m128" varname="__A" etype="FP32" />
-	<CPUID>AVX_NE_CONVERT</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-<intrinsic name="_mm256_dpbusd_avx_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<parameter type="__m256i" varname="src" etype="SI32" />
-		<parameter type="__m256i" varname="a" etype="UI8" />
-		<parameter type="__m256i" varname="b" etype="SI8" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:256] := 0
-		</operation>
-		<instruction name="VPDPBUSD" form="ymm, ymm, ymm" xed="VPDPBUSD_YMMi32_YMMu32_YMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbusds_avx_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<parameter type="__m256i" varname="src" etype="SI32" />
-		<parameter type="__m256i" varname="a" etype="UI8" />
-		<parameter type="__m256i" varname="b" etype="SI8" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:256] := 0
-		</operation>
-		<instruction name="VPDPBUSDS" form="ymm, ymm, ymm" xed="VPDPBUSDS_YMMi32_YMMu32_YMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpwssd_avx_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<parameter type="__m256i" varname="src" etype="SI32" />
-		<parameter type="__m256i" varname="a" etype="SI16" />
-		<parameter type="__m256i" varname="b" etype="SI16" />
-		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 7
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:256] := 0
-		</operation>
-		<instruction name="VPDPWSSD" form="ymm, ymm, ymm" xed="VPDPWSSD_YMMi32_YMMu32_YMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpwssds_avx_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<parameter type="__m256i" varname="src" etype="SI32" />
-		<parameter type="__m256i" varname="a" etype="SI16" />
-		<parameter type="__m256i" varname="b" etype="SI16" />
-		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 7
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:256] := 0
-		</operation>
-		<instruction name="VPDPWSSDS" form="ymm, ymm, ymm" xed="VPDPWSSDS_YMMi32_YMMu32_YMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbusd_avx_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<parameter type="__m128i" varname="src" etype="SI32" />
-		<parameter type="__m128i" varname="a" etype="SI16" />
-		<parameter type="__m128i" varname="b" etype="SI16" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:128] := 0
-		</operation>
-		<instruction name="VPDPBUSD" form="xmm, xmm, xmm" xed="VPDPBUSD_XMMi32_XMMu32_XMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbusds_avx_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<parameter type="__m128i" varname="src" etype="SI32" />
-		<parameter type="__m128i" varname="a" etype="UI8" />
-		<parameter type="__m128i" varname="b" etype="SI8" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:128] := 0
-		</operation>
-		<instruction name="VPDPBUSDS" form="xmm, xmm, xmm" xed="VPDPBUSDS_XMMi32_XMMu32_XMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpwssd_avx_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<parameter type="__m128i" varname="src" etype="SI32" />
-		<parameter type="__m128i" varname="a" etype="SI16" />
-		<parameter type="__m128i" varname="b" etype="SI16" />
-		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 3
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:128] := 0
-		</operation>
-		<instruction name="VPDPWSSD" form="xmm, xmm, xmm" xed="VPDPWSSD_XMMi32_XMMu32_XMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpwssds_avx_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<parameter type="__m128i" varname="src" etype="SI32" />
-		<parameter type="__m128i" varname="a" etype="SI16" />
-		<parameter type="__m128i" varname="b" etype="SI16" />
-		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 3
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:128] := 0
-		</operation>
-		<instruction name="VPDPWSSDS" form="xmm, xmm, xmm" xed="VPDPWSSDS_XMMi32_XMMu32_XMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-<intrinsic name="_mm256_dpbusd_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<parameter type="__m256i" varname="src" etype="SI32" />
-		<parameter type="__m256i" varname="a" etype="UI8" />
-		<parameter type="__m256i" varname="b" etype="SI8" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:256] := 0
-		</operation>
-		<instruction name="VPDPBUSD" form="ymm, ymm, ymm" xed="VPDPBUSD_YMMi32_YMMu32_YMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbusds_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<parameter type="__m256i" varname="src" etype="SI32" />
-		<parameter type="__m256i" varname="a" etype="UI8" />
-		<parameter type="__m256i" varname="b" etype="SI8" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:256] := 0
-		</operation>
-		<instruction name="VPDPBUSDS" form="ymm, ymm, ymm" xed="VPDPBUSDS_YMMi32_YMMu32_YMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpwssd_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<parameter type="__m256i" varname="src" etype="SI32" />
-		<parameter type="__m256i" varname="a" etype="SI16" />
-		<parameter type="__m256i" varname="b" etype="SI16" />
-		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 7
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:256] := 0
-		</operation>
-		<instruction name="VPDPWSSD" form="ymm, ymm, ymm" xed="VPDPWSSD_YMMi32_YMMu32_YMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpwssds_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<parameter type="__m256i" varname="src" etype="SI32" />
-		<parameter type="__m256i" varname="a" etype="SI16" />
-		<parameter type="__m256i" varname="b" etype="SI16" />
-		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 7
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:256] := 0
-		</operation>
-		<instruction name="VPDPWSSDS" form="ymm, ymm, ymm" xed="VPDPWSSDS_YMMi32_YMMu32_YMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbusd_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<parameter type="__m128i" varname="src" etype="SI32" />
-		<parameter type="__m128i" varname="a" etype="SI16" />
-		<parameter type="__m128i" varname="b" etype="SI16" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:128] := 0
-		</operation>
-		<instruction name="VPDPBUSD" form="xmm, xmm, xmm" xed="VPDPBUSD_XMMi32_XMMu32_XMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbusds_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<parameter type="__m128i" varname="src" etype="SI32" />
-		<parameter type="__m128i" varname="a" etype="UI8" />
-		<parameter type="__m128i" varname="b" etype="SI8" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j]))
-	tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1]))
-	tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2]))
-	tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3]))
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:128] := 0
-		</operation>
-		<instruction name="VPDPBUSDS" form="xmm, xmm, xmm" xed="VPDPBUSDS_XMMi32_XMMu32_XMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpwssd_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<parameter type="__m128i" varname="src" etype="SI32" />
-		<parameter type="__m128i" varname="a" etype="SI16" />
-		<parameter type="__m128i" varname="b" etype="SI16" />
-		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 3
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := src.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:128] := 0
-		</operation>
-		<instruction name="VPDPWSSD" form="xmm, xmm, xmm" xed="VPDPWSSD_XMMi32_XMMu32_XMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpwssds_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<parameter type="__m128i" varname="src" etype="SI32" />
-		<parameter type="__m128i" varname="a" etype="SI16" />
-		<parameter type="__m128i" varname="b" etype="SI16" />
-		<description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst".</description>
-		<operation>
-FOR j := 0 to 3
-	tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j])
-	tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1])
-	dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:128] := 0
-		</operation>
-		<instruction name="VPDPWSSDS" form="xmm, xmm, xmm" xed="VPDPWSSDS_XMMi32_XMMu32_XMMu32" />
-	<CPUID>AVX_VNNI</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-<intrinsic name="_mm256_dpwsud_epi32" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWSUD" form="ymm, ymm, ymm" xed="VPDPWSUD_YMMi32_YMMu32_YMMu32" />
-    <operation>
-FOR j := 0 to 7
-	tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
-	tmp2.dword := SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-    <parameter type="__m256i" varname="__W" etype="SI32" />
-    <parameter type="__m256i" varname="__A" etype="SI16" />
-    <parameter type="__m256i" varname="__B" etype="UI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm256_dpwsuds_epi32" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWSUDS" form="ymm, ymm, ymm" xed="VPDPWSUDS_YMMi32_YMMu32_YMMu32" />
-    <operation>
-FOR j := 0 to 7
-	tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
-	tmp2.dword := SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
-	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:256] := 0			</operation>
-    <parameter type="__m256i" varname="__W" etype="SI32" />
-    <parameter type="__m256i" varname="__A" etype="SI16" />
-    <parameter type="__m256i" varname="__B" etype="UI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm256_dpwusd_epi32" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding signed 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWUSD" form="ymm, ymm, ymm" xed="VPDPWUSD_YMMi32_YMMu32_YMMu32" />
-    <operation>
-FOR j := 0 to 7
-	tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
-	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-    <parameter type="__m256i" varname="__W" etype="SI32" />
-    <parameter type="__m256i" varname="__A" etype="UI16" />
-    <parameter type="__m256i" varname="__B" etype="SI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm256_dpwusds_epi32" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding signed 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWUSDS" form="ymm, ymm, ymm" xed="VPDPWUSDS_YMMi32_YMMu32_YMMu32" />
-    <operation>
-FOR j := 0 to 7
-	tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
-	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
-	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:256] := 0			</operation>
-    <parameter type="__m256i" varname="__W" etype="SI32" />
-    <parameter type="__m256i" varname="__A" etype="UI16" />
-    <parameter type="__m256i" varname="__B" etype="SI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm256_dpwuud_epi32" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWUUD" form="ymm, ymm, ymm" xed="VPDPWUUD_YMMi32_YMMu32_YMMu32" />
-    <operation>
-FOR j := 0 to 7
-	tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
-	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-    <parameter type="__m256i" varname="__W" etype="UI32" />
-    <parameter type="__m256i" varname="__A" etype="UI16" />
-    <parameter type="__m256i" varname="__B" etype="UI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm256_dpwuuds_epi32" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWUUDS" form="ymm, ymm, ymm" xed="VPDPWUUDS_YMMi32_YMMu32_YMMu32" />
-    <operation>
-FOR j := 0 to 7
-	tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
-	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
-	dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:256] := 0			</operation>
-    <parameter type="__m256i" varname="__W" etype="UI32" />
-    <parameter type="__m256i" varname="__A" etype="UI16" />
-    <parameter type="__m256i" varname="__B" etype="UI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm_dpwsud_epi32" tech="AVX_ALL">
-    <return type="__m128i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWSUD" form="xmm, xmm, xmm" xed="VPDPWSUD_XMMi32_XMMu32_XMMu32" />
-    <operation>
-FOR j := 0 to 3
-	tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
-	tmp2.dword := SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-    <parameter type="__m128i" varname="__W" etype="SI32" />
-    <parameter type="__m128i" varname="__A" etype="SI16" />
-    <parameter type="__m128i" varname="__B" etype="UI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm_dpwsuds_epi32" tech="AVX_ALL">
-    <return type="__m128i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of signed 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWSUDS" form="xmm, xmm, xmm" xed="VPDPWSUDS_XMMi32_XMMu32_XMMu32" />
-    <operation>
-FOR j := 0 to 3
-	tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
-	tmp2.dword := SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
-	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:128] := 0			</operation>
-    <parameter type="__m128i" varname="__W" etype="SI32" />
-    <parameter type="__m128i" varname="__A" etype="SI16" />
-    <parameter type="__m128i" varname="__B" etype="UI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm_dpwusd_epi32" tech="AVX_ALL">
-    <return type="__m128i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding signed 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWUSD" form="xmm, xmm, xmm" xed="VPDPWUSD_XMMi32_XMMu32_XMMu32" />
-    <operation>
-FOR j := 0 to 3
-	tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
-	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-    <parameter type="__m128i" varname="__W" etype="SI32" />
-    <parameter type="__m128i" varname="__A" etype="UI16" />
-    <parameter type="__m128i" varname="__B" etype="SI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm_dpwusds_epi32" tech="AVX_ALL">
-    <return type="__m128i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding signed 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWUSDS" form="xmm, xmm, xmm" xed="VPDPWUSDS_XMMi32_XMMu32_XMMu32" />
-    <operation>
-FOR j := 0 to 3
-	tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
-	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
-	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:128] := 0			</operation>
-    <parameter type="__m128i" varname="__W" etype="SI32" />
-    <parameter type="__m128i" varname="__A" etype="UI16" />
-    <parameter type="__m128i" varname="__B" etype="SI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm_dpwuud_epi32" tech="AVX_ALL">
-    <return type="__m128i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWUUD" form="xmm, xmm, xmm" xed="VPDPWUUD_XMMi32_XMMu32_XMMu32" />
-    <operation>
-FOR j := 0 to 3
-	tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
-	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-    <parameter type="__m128i" varname="__W" etype="UI32" />
-    <parameter type="__m128i" varname="__A" etype="UI16" />
-    <parameter type="__m128i" varname="__B" etype="UI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-  <intrinsic name="_mm_dpwuuds_epi32" tech="AVX_ALL">
-    <return type="__m128i" varname="dst" etype="SI32" />
-    <description>Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in "__A" with corresponding unsigned 16-bit integers in "__B", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-    <instruction name="VPDPWUUDS" form="xmm, xmm, xmm" xed="VPDPWUUDS_XMMi32_XMMu32_XMMu32" />
-    <operation>
-FOR j := 0 to 3
-	tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
-	tmp2.dword := ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
-	dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
-ENDFOR
-dst[MAX:128] := 0			</operation>
-    <parameter type="__m128i" varname="__W" etype="UI32" />
-    <parameter type="__m128i" varname="__A" etype="UI16" />
-    <parameter type="__m128i" varname="__B" etype="UI16" />
-  <CPUID>AVX_VNNI_INT16</CPUID>
-	<header>immintrin.h</header>
-  <category>Arithmetic</category>
-  </intrinsic>
-<intrinsic name="_mm256_dpbssd_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding signed 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBSSD" form="ymm, ymm, ymm" xed="VPDPBSSD_YMMi32_YMMu32_YMMu32" />
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := SignExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j])
-	tmp2.word := SignExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1])
-	tmp3.word := SignExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2])
-	tmp4.word := SignExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="__m256i" varname="__W" etype="SI32" />
-		<parameter type="__m256i" varname="__A" etype="SI8" />
-		<parameter type="__m256i" varname="__B" etype="SI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbssds_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding signed 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBSSDS" form="ymm, ymm, ymm" xed="VPDPBSSDS_YMMi32_YMMu32_YMMu32" />
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := SignExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j])
-	tmp2.word := SignExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1])
-	tmp3.word := SignExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2])
-	tmp4.word := SignExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3])
-	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:256] := 0			</operation>
-		<parameter type="__m256i" varname="__W" etype="SI32" />
-		<parameter type="__m256i" varname="__A" etype="SI8" />
-		<parameter type="__m256i" varname="__B" etype="SI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbsud_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBSUD" form="ymm, ymm, ymm" xed="VPDPBSUD_YMMi32_YMMu32_YMMu32" />
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := Signed(SignExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j]))
-	tmp2.word := Signed(SignExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1]))
-	tmp3.word := Signed(SignExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2]))
-	tmp4.word := Signed(SignExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3]))
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="__m256i" varname="__W" etype="SI32" />
-		<parameter type="__m256i" varname="__A" etype="SI8" />
-		<parameter type="__m256i" varname="__B" etype="UI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbsuds_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBSUDS" form="ymm, ymm, ymm" xed="VPDPBSUDS_YMMi32_YMMu32_YMMu32" />
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := Signed(SignExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j]))
-	tmp2.word := Signed(SignExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1]))
-	tmp3.word := Signed(SignExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2]))
-	tmp4.word := Signed(SignExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3]))
-	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:256] := 0			</operation>
-		<parameter type="__m256i" varname="__W" etype="SI32" />
-		<parameter type="__m256i" varname="__A" etype="SI8" />
-		<parameter type="__m256i" varname="__B" etype="UI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbuud_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBUUD" form="ymm, ymm, ymm" xed="VPDPBUUD_YMMi32_YMMu32_YMMu32" />
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := ZeroExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j])
-	tmp2.word := ZeroExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1])
-	tmp3.word := ZeroExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2])
-	tmp4.word := ZeroExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-		<parameter type="__m256i" varname="__W" etype="SI32" />
-		<parameter type="__m256i" varname="__A" etype="UI8" />
-		<parameter type="__m256i" varname="__B" etype="UI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_dpbuuds_epi32" tech="AVX_ALL">
-		<return type="__m256i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with unsigned saturation, and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBUUDS" form="ymm, ymm, ymm" xed="VPDPBUUDS_YMMi32_YMMu32_YMMu32" />
-		<operation>
-FOR j := 0 to 7
-	tmp1.word := ZeroExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j])
-	tmp2.word := ZeroExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1])
-	tmp3.word := ZeroExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2])
-	tmp4.word := ZeroExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3])
-	dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:256] := 0			</operation>
-		<parameter type="__m256i" varname="__W" etype="SI32" />
-		<parameter type="__m256i" varname="__A" etype="UI8" />
-		<parameter type="__m256i" varname="__B" etype="UI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbssd_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding signed 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBSSD" form="xmm, xmm, xmm" xed="VPDPBSSD_XMMi32_XMMu32_XMMu32" />
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := SignExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j])
-	tmp2.word := SignExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1])
-	tmp3.word := SignExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2])
-	tmp4.word := SignExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="__m128i" varname="__W" etype="SI32" />
-		<parameter type="__m128i" varname="__A" etype="SI8" />
-		<parameter type="__m128i" varname="__B" etype="SI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbssds_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding signed 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBSSDS" form="xmm, xmm, xmm" xed="VPDPBSSDS_XMMi32_XMMu32_XMMu32" />
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := SignExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j])
-	tmp2.word := SignExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1])
-	tmp3.word := SignExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2])
-	tmp4.word := SignExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3])
-	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:128] := 0			</operation>
-		<parameter type="__m128i" varname="__W" etype="SI32" />
-		<parameter type="__m128i" varname="__A" etype="SI8" />
-		<parameter type="__m128i" varname="__B" etype="SI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbsud_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBSUD" form="xmm, xmm, xmm" xed="VPDPBSUD_XMMi32_XMMu32_XMMu32" />
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := Signed(SignExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j]))
-	tmp2.word := Signed(SignExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1]))
-	tmp3.word := Signed(SignExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2]))
-	tmp4.word := Signed(SignExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3]))
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="__m128i" varname="__W" etype="SI32" />
-		<parameter type="__m128i" varname="__A" etype="SI8" />
-		<parameter type="__m128i" varname="__B" etype="UI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbsuds_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of signed 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with signed saturation, and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBSUDS" form="xmm, xmm, xmm" xed="VPDPBSUDS_XMMi32_XMMu32_XMMu32" />
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := Signed(SignExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j]))
-	tmp2.word := Signed(SignExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1]))
-	tmp3.word := Signed(SignExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2]))
-	tmp4.word := Signed(SignExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3]))
-	dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:128] := 0			</operation>
-		<parameter type="__m128i" varname="__W" etype="SI32" />
-		<parameter type="__m128i" varname="__A" etype="SI8" />
-		<parameter type="__m128i" varname="__B" etype="UI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbuud_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W", and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBUUD" form="xmm, xmm, xmm" xed="VPDPBUUD_XMMi32_XMMu32_XMMu32" />
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := ZeroExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j])
-	tmp2.word := ZeroExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1])
-	tmp3.word := ZeroExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2])
-	tmp4.word := ZeroExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3])
-	dst.dword[j] := __W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
-ENDFOR
-dst[MAX:128] := 0
-</operation>
-		<parameter type="__m128i" varname="__W" etype="SI32" />
-		<parameter type="__m128i" varname="__A" etype="UI8" />
-		<parameter type="__m128i" varname="__B" etype="UI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dpbuuds_epi32" tech="AVX_ALL">
-		<return type="__m128i" varname="dst" etype="SI32" />
-		<description>Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "__A" with corresponding unsigned 8-bit integers in "__B", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "__W" with unsigned saturation, and store the packed 32-bit results in "dst".</description>
-		<instruction name="VPDPBUUDS" form="xmm, xmm, xmm" xed="VPDPBUUDS_XMMi32_XMMu32_XMMu32" />
-		<operation>
-FOR j := 0 to 3
-	tmp1.word := ZeroExtend16(__A.byte[4*j]) * ZeroExtend16(__B.byte[4*j])
-	tmp2.word := ZeroExtend16(__A.byte[4*j+1]) * ZeroExtend16(__B.byte[4*j+1])
-	tmp3.word := ZeroExtend16(__A.byte[4*j+2]) * ZeroExtend16(__B.byte[4*j+2])
-	tmp4.word := ZeroExtend16(__A.byte[4*j+3]) * ZeroExtend16(__B.byte[4*j+3])
-	dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
-ENDFOR
-dst[MAX:128] := 0			</operation>
-		<parameter type="__m128i" varname="__W" etype="SI32" />
-		<parameter type="__m128i" varname="__A" etype="UI8" />
-		<parameter type="__m128i" varname="__B" etype="UI8" />
-	<CPUID>AVX_VNNI_INT8</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-<intrinsic name="_bextr_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="start" />
-	<parameter etype="UI32" type="unsigned int" varname="len" />
-	<description>Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst". Extract the number of bits specified by "len", starting at the bit specified by "start".</description>
-	<operation>
-tmp[511:0] := a
-dst[31:0] := ZeroExtend32(tmp[(start[7:0] + len[7:0] - 1):start[7:0]])
-	</operation>
-	<instruction form="r32, r32, r32" name="BEXTR" xed="BEXTR_VGPR32d_VGPR32d_VGPR32d" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bextr2_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="control" />
-	<description>Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst". Extract the number of bits specified by bits 15:8 of "control", starting at the bit specified by bits 0:7 of "control".</description>
-	<operation>
-start := control[7:0]
-len := control[15:8]
-tmp[511:0] := a
-dst[31:0] := ZeroExtend32(tmp[(start[7:0] + len[7:0] - 1):start[7:0]])
-	</operation>
-	<instruction form="r32, r32, r32" name="BEXTR" xed="BEXTR_VGPR32d_VGPR32d_VGPR32d" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bextr_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="start" />
-	<parameter etype="UI32" type="unsigned int" varname="len" />
-	<description>Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst". Extract the number of bits specified by "len", starting at the bit specified by "start".</description>
-	<operation>
-tmp[511:0] := a
-dst[63:0] := ZeroExtend64(tmp[(start[7:0] + len[7:0] - 1):start[7:0]])
-	</operation>
-	<instruction form="r64, r64, r64" name="BEXTR" xed="BEXTR_VGPR64q_VGPR64q_VGPR64q" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bextr2_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="control" />
-	<description>Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst". Extract the number of bits specified by bits 15:8 of "control", starting at the bit specified by bits 0:7 of "control"..</description>
-	<operation>
-start := control[7:0]
-len := control[15:8]
-tmp[511:0] := a
-dst[63:0] := ZeroExtend64(tmp[(start[7:0] + len[7:0] - 1):start[7:0]])
-	</operation>
-	<instruction form="r64, r64, r64" name="BEXTR" xed="BEXTR_VGPR64q_VGPR64q_VGPR64q" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_blsi_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Extract the lowest set bit from unsigned 32-bit integer "a" and set the corresponding bit in "dst". All other bits in "dst" are zeroed, and all bits are zeroed if no bits are set in "a".</description>
-	<operation>
-dst := (-a) AND a
-	</operation>
-	<instruction form="r32, r32" name="BLSI" xed="BLSI_VGPR32d_VGPR32d" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_blsi_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Extract the lowest set bit from unsigned 64-bit integer "a" and set the corresponding bit in "dst". All other bits in "dst" are zeroed, and all bits are zeroed if no bits are set in "a".</description>
-	<operation>
-dst := (-a) AND a
-	</operation>
-	<instruction form="r64, r64" name="BLSI" xed="BLSI_VGPR64q_VGPR64q" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_blsmsk_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 32-bit integer "a".</description>
-	<operation>
-dst := (a - 1) XOR a
-	</operation>
-	<instruction form="r32, r32" name="BLSMSK" xed="BLSMSK_VGPR32d_VGPR32d" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_blsmsk_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 64-bit integer "a".</description>
-	<operation>
-dst := (a - 1) XOR a
-	</operation>
-	<instruction form="r64, r64" name="BLSMSK" xed="BLSMSK_VGPR64q_VGPR64q" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_blsr_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a".</description>
-	<operation>
-dst := (a - 1) AND a
-	</operation>
-	<instruction form="r32, r32" name="BLSR" xed="BLSR_VGPR32d_VGPR32d" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_blsr_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a".</description>
-	<operation>
-dst := (a - 1) AND a
-	</operation>
-	<instruction form="r64, r64" name="BLSR" xed="BLSR_VGPR64q_VGPR64q" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_andn_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<description>Compute the bitwise NOT of 32-bit integer "a" and then AND with b, and store the results in dst.</description>
-	<operation>
-dst[31:0] := ((NOT a[31:0]) AND b[31:0])
-	</operation>
-	<instruction form="r32, r32, r32" name="ANDN" xed="ANDN_VGPR32d_VGPR32d_VGPR32d" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_andn_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<description>Compute the bitwise NOT of 64-bit integer "a" and then AND with b, and store the results in dst.</description>
-	<operation>
-dst[63:0] := ((NOT a[63:0]) AND b[63:0])
-	</operation>
-	<instruction form="r64, r64, r64" name="ANDN" xed="ANDN_VGPR64q_VGPR64q_VGPR64q" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_tzcnt_u16" tech="Other">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="UI16" type="unsigned short" varname="a" />
-	<description>Count the number of trailing zero bits in unsigned 16-bit integer "a", and return that count in "dst".</description>
-	<operation>
-tmp := 0
-dst := 0
-DO WHILE ((tmp &lt; 16) AND a[tmp] == 0)
-	tmp := tmp + 1
-	dst := dst + 1
-OD
-	</operation>
-	<instruction form="r16, r16" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_tzcnt_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Count the number of trailing zero bits in unsigned 32-bit integer "a", and return that count in "dst".</description>
-	<operation>
-tmp := 0
-dst := 0
-DO WHILE ((tmp &lt; 32) AND a[tmp] == 0)
-	tmp := tmp + 1
-	dst := dst + 1
-OD
-	</operation>
-	<instruction form="r32, r32" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_tzcnt_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Count the number of trailing zero bits in unsigned 64-bit integer "a", and return that count in "dst".</description>
-	<operation>
-tmp := 0
-dst := 0
-DO WHILE ((tmp &lt; 64) AND a[tmp] == 0)
-	tmp := tmp + 1
-	dst := dst + 1
-OD
-	</operation>
-	<instruction form="r64, r64" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_tzcnt_32" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Count the number of trailing zero bits in unsigned 32-bit integer "a", and return that count in "dst".</description>
-	<operation>
-tmp := 0
-dst := 0
-DO WHILE ((tmp &lt; 32) AND a[tmp] == 0)
-	tmp := tmp + 1
-	dst := dst + 1
-OD
-	</operation>
-	<instruction form="r32, r32" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_tzcnt_64" tech="Other">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Count the number of trailing zero bits in unsigned 64-bit integer "a", and return that count in "dst".</description>
-	<operation>
-tmp := 0
-dst := 0
-DO WHILE ((tmp &lt; 64) AND a[tmp] == 0)
-	tmp := tmp + 1
-	dst := dst + 1
-OD
-	</operation>
-	<instruction form="r64, r64" name="TZCNT" xed="TZCNT_GPRv_GPRv" />
-	<CPUID>BMI1</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_bzhi_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="index" />
-	<description>Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index".</description>
-	<operation>
-n := index[7:0]
-dst := a
-IF (n &lt; 32)
-	dst[31:n] := 0
-FI
-	</operation>
-	<instruction form="r32, r32, r32" name="BZHI" xed="BZHI_VGPR32d_VGPR32d_VGPR32d" />
-	<CPUID>BMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bzhi_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="index" />
-	<description>Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index".</description>
-	<operation>
-n := index[7:0]
-dst := a
-IF (n &lt; 64)
-	dst[63:n] := 0
-FI
-	</operation>
-	<instruction form="r64, r64, r64" name="BZHI" xed="BZHI_VGPR64q_VGPR64q_VGPR64q" />
-	<CPUID>BMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_pdep_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="mask" />
-	<description>Deposit contiguous low bits from unsigned 32-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"; all other bits in "dst" are set to zero.</description>
-	<operation>
-tmp := a
-dst := 0
-m := 0
-k := 0
-DO WHILE m &lt; 32
-	IF mask[m] == 1
-		dst[m] := tmp[k]
-		k := k + 1
-	FI
-	m := m + 1
-OD
-	</operation>
-	<instruction form="r32, r32, r32" name="PDEP" xed="PDEP_VGPR32d_VGPR32d_VGPR32d" />
-	<CPUID>BMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_pdep_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="mask" />
-	<description>Deposit contiguous low bits from unsigned 64-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"; all other bits in "dst" are set to zero.</description>
-	<operation>
-tmp := a
-dst := 0
-m := 0
-k := 0
-DO WHILE m &lt; 64
-	IF mask[m] == 1
-		dst[m] := tmp[k]
-		k := k + 1
-	FI
-	m := m + 1
-OD
-	</operation>
-	<instruction form="r64, r64, r64" name="PDEP" xed="PDEP_VGPR64q_VGPR64q_VGPR64q" />
-	<CPUID>BMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_pext_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="mask" />
-	<description>Extract bits from unsigned 32-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"; the remaining upper bits in "dst" are set to zero.</description>
-	<operation>
-tmp := a
-dst := 0
-m := 0
-k := 0
-DO WHILE m &lt; 32
-	IF mask[m] == 1
-		dst[k] := tmp[m]
-		k := k + 1
-	FI
-	m := m + 1
-OD
-	</operation>
-	<instruction form="r32, r32, r32" name="PEXT" xed="PEXT_VGPR32d_VGPR32d_VGPR32d" />
-	<CPUID>BMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_pext_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="mask" />
-	<description>Extract bits from unsigned 64-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"; the remaining upper bits in "dst" are set to zero.</description>
-	<operation>
-tmp := a
-dst := 0
-m := 0
-k := 0
-DO WHILE m &lt; 64
-	IF mask[m] == 1
-		dst[k] := tmp[m]
-		k := k + 1
-	FI
-	m := m + 1
-OD
-	</operation>
-	<instruction form="r64, r64, r64" name="PEXT" xed="PEXT_VGPR64q_VGPR64q_VGPR64q" />
-	<CPUID>BMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mulx_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<parameter etype="UI32" memwidth="32" type="unsigned int*" varname="hi" />
-	<description>Multiply unsigned 32-bit integers "a" and "b", store the low 32-bits of the result in "dst", and store the high 32-bits in "hi". This does not read or write arithmetic flags.</description>
-	<operation>
-dst[31:0] := (a * b)[31:0]
-MEM[hi+31:hi] := (a * b)[63:32]
-	</operation>
-	<instruction form="r32, r32, m32" name="MULX" xed="MULX_VGPR32d_VGPR32d_MEMd" />
-	<CPUID>BMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mulx_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<parameter etype="UI64" memwidth="64" type="unsigned __int64*" varname="hi" />
-	<description>Multiply unsigned 64-bit integers "a" and "b", store the low 64-bits of the result in "dst", and store the high 64-bits in "hi". This does not read or write arithmetic flags.</description>
-	<operation>
-dst[63:0] := (a * b)[63:0]
-MEM[hi+63:hi]  := (a * b)[127:64]
-	</operation>
-	<instruction form="r64, r64, m64" name="MULX" xed="MULX_VGPR64q_VGPR64q_MEMq" />
-	<CPUID>BMI2</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_incsspd" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a".</description>
-	<operation>
-SSP := SSP + a[7:0] * 4
-	</operation>
-	<instruction form="r32" name="INCSSPD" xed="INCSSPD_GPR32u8" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_incsspq" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Increment the shadow stack pointer by 8 times the value specified in bits [7:0] of "a".</description>
-	<operation>
-SSP := SSP + a[7:0] * 8
-	</operation>
-	<instruction form="r64" name="INCSSPQ" xed="INCSSPQ_GPR64u8" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_rdsspd_i32" tech="Other">
-	<return etype="UI32" type="__int32" varname="dst" />
-	<parameter type="void" />
-	<description>Read the low 32-bits of the current shadow stack pointer, and store the result in "dst".</description>
-	<operation>dst := SSP[31:0]
-	</operation>
-	<instruction form="r32" name="RDSSPD" xed="RDSSPD_GPR32u32" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_rdsspq_i64" tech="Other">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter type="void" />
-	<description>Read the current shadow stack pointer, and store the result in "dst".</description>
-	<operation>dst := SSP[63:0]
-	</operation>
-	<instruction form="r64" name="RDSSPQ" xed="RDSSPQ_GPR64u64" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_saveprevssp" tech="Other">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Save the previous shadow stack pointer context.</description>
-	<instruction name="SAVEPREVSSP" xed="SAVEPREVSSP" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_rstorssp" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="p" />
-	<description>Restore the saved shadow stack pointer from the shadow stack restore token previously created on shadow stack by saveprevssp.</description>
-	<instruction form="m64" name="RSTORSSP" xed="RSTORSSP_MEMu64" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_wrssd" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="__int32" varname="val" />
-	<parameter type="void *" varname="p" />
-	<description>Write 32-bit value in "val" to a shadow stack page in memory specified by "p".</description>
-	<instruction form="m32, r32" name="WRSSD" xed="WRSSD_MEMu32_GPR32u32" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_wrssq" tech="Other">
-	<return type="void" />
-	<parameter etype="UI64" type="__int64" varname="val" />
-	<parameter type="void *" varname="p" />
-	<description>Write 64-bit value in "val" to a shadow stack page in memory specified by "p".</description>
-	<instruction form="m64, r64" name="WRSSQ" xed="WRSSQ_MEMu64_GPR64u64" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_wrussd" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="__int32" varname="val" />
-	<parameter type="void *" varname="p" />
-	<description>Write 32-bit value in "val" to a user shadow stack page in memory specified by "p".</description>
-	<instruction form="m32, r32" name="WRUSSD" xed="WRUSSD_MEMu32_GPR32u32" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_wrussq" tech="Other">
-	<return type="void" />
-	<parameter etype="UI64" type="__int64" varname="val" />
-	<parameter type="void *" varname="p" />
-	<description>Write 64-bit value in "val" to a user shadow stack page in memory specified by "p".</description>
-	<instruction form="m64, r64" name="WRUSSQ" xed="WRUSSQ_MEMu64_GPR64u64" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_setssbsy" tech="Other">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Mark shadow stack pointed to by IA32_PL0_SSP as busy.</description>
-	<instruction name="SETSSBSY" xed="SETSSBSY" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_clrssbsy" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="p" />
-	<description>Mark shadow stack pointed to by "p" as not busy.</description>
-	<instruction form="m64" name="CLRSSBSY" xed="CLRSSBSY_MEMu64" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_get_ssp" tech="Other">
-	<return etype="UI32" type="__int32" varname="dst" />
-	<parameter type="void" />
-	<description>If CET is enabled, read the low 32-bits of the current shadow stack pointer, and store the result in "dst". Otherwise return 0.</description>
-	<operation>dst := SSP[31:0]
-	</operation>
-	<instruction form="r32" name="RDSSPD" xed="RDSSPD_GPR32u32" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_get_ssp" tech="Other">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter type="void" />
-	<description>If CET is enabled, read the current shadow stack pointer, and store the result in "dst". Otherwise return 0.</description>
-	<operation>dst := SSP[63:0]
-	</operation>
-	<instruction form="r64" name="RDSSPQ" xed="RDSSPQ_GPR64u64" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_inc_ssp" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a".</description>
-	<operation>
-SSP := SSP + a[7:0] * 4
-	</operation>
-	<instruction form="r32" name="INCSSPD" xed="INCSSPD_GPR32u8" />
-	<CPUID>CET_SS</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	
-<intrinsic name="_mm_cldemote" tech="Other">
-	<return type="void" />
-	<parameter type="void const *" varname="p" />
-	<description>Hint to hardware that the cache line that contains "p" should be demoted from the cache closest to the processor core to a level more distant from the processor core.</description>
-	<instruction form="m8" name="CLDEMOTE" xed="CLDEMOTE_MEMu8" />
-	<CPUID>CLDEMOTE</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_clflushopt" tech="Other">
-	<return type="void" />
-	<parameter type="void const *" varname="p" />
-	<description>Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy.</description>
-	<instruction form="m8" name="CLFLUSHOPT" xed="CLFLUSHOPT_MEMmprefetch" />
-	<CPUID>CLFLUSHOPT</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_clwb" tech="Other">
-	<return type="void" />
-	<parameter type="void const *" varname="p" />
-	<description>Write back to memory the cache line that contains "p" from any level of the cache hierarchy in the cache coherence domain.</description>
-	<instruction form="m8" name="CLWB" xed="CLWB_MEMmprefetch" />
-	<CPUID>CLWB</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-	<intrinsic name="_cmpccxadd_epi32" tech="Other">
-	<return etype="SI32" type="int" varname="dst" />
-	<parameter etype="SI32" type="void*" memwidth="32" varname="__A" />
-	<parameter etype="SI32" type="int" varname="__B" />
-	<parameter etype="SI32" type="int" varname="__C" />
-	<parameter etype="SI32" type="const int" varname="__D" />
-	<description>Compares the value from the memory "__A" with the value of "__B". If the specified condition "__D" is met, then add the third operand "__C" to the "__A" and write it into "__A", else the value of "__A" is unchanged. The return value is the original value of "__A".</description>
-	<operation>CASE (__D[3:0]) OF
-0: OP := _CMPCCX_O
-1: OP := _CMPCCX_NO
-2: OP := _CMPCCX_B
-3: OP := _CMPCCX_NB
-4: OP := _CMPCCX_Z
-5: OP := _CMPCCX_NZ
-6: OP := _CMPCCX_BE
-7: OP := _CMPCCX_NBE
-8: OP := _CMPCCX_S
-9: OP := _CMPCCX_NS
-10: OP := _CMPCCX_P
-11: OP := _CMPCCX_NP
-12: OP := _CMPCCX_L
-13: OP := _CMPCCX_NL
-14: OP := _CMPCCX_LE
-15: OP := _CMPCCX_NLE
-ESAC
-tmp1 := LOAD_LOCK(__A)
-tmp2 := tmp1 + __C
-IF (tmp1[31:0] OP __B[31:0])
-	STORE_UNLOCK(__A, tmp2)
-ELSE
-	STORE_UNLOCK(__A, tmp1)
-FI
-dst[31:0] := tmp1[31:0]
-	</operation>
-	<instruction name="CMPOXADD" form ="m32, r32, r32" xed="CMPOXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPNOXADD" form ="m32, r32, r32" xed="CMPNOXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPBXADD" form ="m32, r32, r32" xed="CMPBXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPNBXADD" form ="m32, r32, r32" xed="CMPNBXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPZXADD" form ="m32, r32, r32" xed="CMPZXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPNZXADD" form ="m32, r32, r32" xed="CMPNZXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPBEXADD" form ="m32, r32, r32" xed="CMPBEXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPNBEXADD" form ="m32, r32, r32" xed="CMPNBEXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPSXADD" form ="m32, r32, r32" xed="CMPSXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPNSXADD" form ="m32, r32, r32" xed="CMPNSXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPPXADD" form ="m32, r32, r32" xed="CMPPXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPNPXADD" form ="m32, r32, r32" xed="CMPNPXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPLXADD" form ="m32, r32, r32" xed="CMPLXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPNLXADD" form ="m32, r32, r32" xed="CMPNLXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPLEXADD" form ="m32, r32, r32" xed="CMPLEXADD_MEMu32_GPR32u32_GPR32u32" />
-	<instruction name="CMPNLEXADD" form ="m32, r32, r32" xed="CMPNLEXADD_MEMu32_GPR32u32_GPR32u32" />
-	<CPUID>CMPCCXADD</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_cmpccxadd_epi64" tech="Other">
-	<return etype="SI64" type="__int64" varname="dst" />
-	<parameter etype="SI64" type="void*" memwidth="32" varname="__A" />
-	<parameter etype="SI64" type="__int64" varname="__B" />
-	<parameter etype="SI64" type="__int64" varname="__C" />
-	<parameter etype="SI32" type="const int" varname="__D" />
-	<description>Compares the value from the memory "__A" with the value of "__B". If the specified condition "__D" is met, then add the third operand "__C" to the "__A" and write it into "__A", else the value of "__A" is unchanged. The return value is the original value of "__A".</description>
-	<operation>CASE (__D[3:0]) OF
-0: OP := _CMPCCX_O
-1: OP := _CMPCCX_NO
-2: OP := _CMPCCX_B
-3: OP := _CMPCCX_NB
-4: OP := _CMPCCX_Z
-5: OP := _CMPCCX_NZ
-6: OP := _CMPCCX_BE
-7: OP := _CMPCCX_NBE
-8: OP := _CMPCCX_S
-9: OP := _CMPCCX_NS
-10: OP := _CMPCCX_P
-11: OP := _CMPCCX_NP
-12: OP := _CMPCCX_L
-13: OP := _CMPCCX_NL
-14: OP := _CMPCCX_LE
-15: OP := _CMPCCX_NLE
-ESAC
-tmp1 := LOAD_LOCK(__A)
-tmp2 := tmp1 + __C
-IF (tmp1[63:0] OP __B[63:0])
-	STORE_UNLOCK(__A, tmp2)
-ELSE
-	STORE_UNLOCK(__A, tmp1)
-FI
-dst[63:0] := tmp1[63:0]
-	</operation>
-	<instruction name="CMPOXADD" form ="m64, r64, r64" xed="CMPOXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPNOXADD" form ="m64, r64, r64" xed="CMPNOXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPBXADD" form ="m64, r64, r64" xed="CMPBXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPNBXADD" form ="m64, r64, r64" xed="CMPNBXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPZXADD" form ="m64, r64, r64" xed="CMPZXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPNZXADD" form ="m64, r64, r64" xed="CMPNZXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPBEXADD" form ="m64, r64, r64" xed="CMPBEXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPNBEXADD" form ="m64, r64, r64" xed="CMPNBEXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPSXADD" form ="m64, r64, r64" xed="CMPSXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPNSXADD" form ="m64, r64, r64" xed="CMPNSXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPPXADD" form ="m64, r64, r64" xed="CMPPXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPNPXADD" form ="m64, r64, r64" xed="CMPNPXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPLXADD" form ="m64, r64, r64" xed="CMPLXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPNLXADD" form ="m64, r64, r64" xed="CMPNLXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPLEXADD" form ="m64, r64, r64" xed="CMPLEXADD_MEMu64_GPR64u64_GPR64u64" />
-	<instruction name="CMPNLEXADD" form ="m64, r64, r64" xed="CMPNLEXADD_MEMu64_GPR64u64_GPR64u64" />
-	<CPUID>CMPCCXADD</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_crc32_u8" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="crc" />
-	<parameter etype="UI8" type="unsigned char" varname="v" />
-	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst".</description>
-	<operation>tmp1[7:0] := v[0:7] // bit reflection
-tmp2[31:0] := crc[0:31] // bit reflection
-tmp3[39:0] := tmp1[7:0] &lt;&lt; 32 
-tmp4[39:0] := tmp2[31:0] &lt;&lt; 8
-tmp5[39:0] := tmp3[39:0] XOR tmp4[39:0]
-tmp6[31:0] := MOD2(tmp5[39:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
-dst[31:0] := tmp6[0:31] // bit reflection
-	</operation>
-	<instruction form="r32, r8" name="CRC32" xed="CRC32_GPRyy_GPR8b" />
-	<CPUID>CRC32</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_crc32_u16" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="crc" />
-	<parameter etype="UI16" type="unsigned short" varname="v" />
-	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst".</description>
-	<operation>tmp1[15:0] := v[0:15] // bit reflection
-tmp2[31:0] := crc[0:31] // bit reflection
-tmp3[47:0] := tmp1[15:0] &lt;&lt; 32
-tmp4[47:0] := tmp2[31:0] &lt;&lt; 16
-tmp5[47:0] := tmp3[47:0] XOR tmp4[47:0]
-tmp6[31:0] := MOD2(tmp5[47:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
-dst[31:0] := tmp6[0:31] // bit reflection
-	</operation>
-	<instruction form="r32, r16" name="CRC32" xed="CRC32_GPRyy_GPRv" />
-	<CPUID>CRC32</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_crc32_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="crc" />
-	<parameter etype="UI32" type="unsigned int" varname="v" />
-	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst".</description>
-	<operation>tmp1[31:0] := v[0:31] // bit reflection
-tmp2[31:0] := crc[0:31] // bit reflection
-tmp3[63:0] := tmp1[31:0] &lt;&lt; 32
-tmp4[63:0] := tmp2[31:0] &lt;&lt; 32
-tmp5[63:0] := tmp3[63:0] XOR tmp4[63:0]
-tmp6[31:0] := MOD2(tmp5[63:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
-dst[31:0] := tmp6[0:31] // bit reflection
-	</operation>
-	<instruction form="r32, r32" name="CRC32" xed="CRC32_GPRyy_GPRv" />
-	<CPUID>CRC32</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_crc32_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="crc" />
-	<parameter etype="UI64" type="unsigned __int64" varname="v" />
-	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst".</description>
-	<operation>tmp1[63:0] := v[0:63] // bit reflection
-tmp2[31:0] := crc[0:31] // bit reflection
-tmp3[95:0] := tmp1[31:0] &lt;&lt; 32
-tmp4[95:0] := tmp2[63:0] &lt;&lt; 64
-tmp5[95:0] := tmp3[95:0] XOR tmp4[95:0]
-tmp6[31:0] := MOD2(tmp5[95:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
-dst[31:0] := tmp6[0:31] // bit reflection
-	</operation>
-	<instruction form="r64, r64" name="CRC32" xed="CRC32_GPRyy_GPRv" />
-	<CPUID>CRC32</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_enqcmd" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter type="void*" memwidth="512" varname="__dst" />
-	<parameter type="const void*" memwidth="512" varname="__src" />
-	<description>Reads 64-byte command pointed by "__src", formats 64-byte enqueue store data, and performs 64-byte enqueue store to memory pointed by "__dst". This intrinsics may only be used in User mode.</description>
-	<instruction form="r16/r32/r64, m512" name="ENQCMD" xed="ENQCMD_GPRa_MEMu32" />
-	<CPUID>ENQCMD</CPUID>
-	<header>immintrin.h</header>
-	<category>Unknown</category>
-	</intrinsic>
-	<intrinsic name="_enqcmds" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter type="void*" memwidth="512" varname="__dst" />
-	<parameter type="const void*" memwidth="512" varname="__src" />
-	<description>Reads 64-byte command pointed by "__src", formats 64-byte enqueue store data, and performs 64-byte enqueue store to memory pointed by "__dst" This intrinsic may only be used in Privileged mode.</description>
-	<instruction form="r16/r32/r64, m512" name="ENQCMDS" xed="ENQCMDS_GPRa_MEMu32" />
-	<CPUID>ENQCMD</CPUID>
-	<header>immintrin.h</header>
-	<category>Unknown</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_cvtph_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP16" type="__m128i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	m := j*16
-	dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_YMMqq_XMMdq" />
-	<CPUID>F16C</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm256_cvtps_ph" tech="AVX_ALL">
-	<return etype="FP16" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_imm_note]</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	l := 32*j
-	dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, ymm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMdq_YMMqq_IMMb" />
-	<CPUID>F16C</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtph_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP16" type="__m128i" varname="a" />
-	<description>Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	m := j*16
-	dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="VCVTPH2PS" xed="VCVTPH2PS_XMMdq_XMMq" />
-	<CPUID>F16C</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_ph" tech="AVX_ALL">
-	<return etype="FP16" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_ROUND_MODE" type="int" varname="imm8" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst".
-	[round_imm_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := 16*j
-	l := 32*j
-	dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l])
-ENDFOR
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="VCVTPS2PH" xed="VCVTPS2PH_XMMq_XMMdq_IMMb" />
-	<CPUID>F16C</CPUID>
-	<header>immintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_fmadd_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADD132PD" xed="VFMADD132PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD213PD" xed="VFMADD213PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD231PD" xed="VFMADD231PD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmadd_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMADD132PD" xed="VFMADD132PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMADD213PD" xed="VFMADD213PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMADD231PD" xed="VFMADD231PD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADD132PS" xed="VFMADD132PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD213PS" xed="VFMADD213PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD231PS" xed="VFMADD231PS_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmadd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMADD132PS" xed="VFMADD132PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMADD213PS" xed="VFMADD213PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMADD231PS" xed="VFMADD231PS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_sd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] * b[63:0]) + c[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADD132SD" xed="VFMADD132SD_XMMdq_XMMq_XMMq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD213SD" xed="VFMADD213SD_XMMdq_XMMq_XMMq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD231SD" xed="VFMADD231SD_XMMdq_XMMq_XMMq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmadd_ss" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := (a[31:0] * b[31:0]) + c[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADD132SS" xed="VFMADD132SS_XMMdq_XMMd_XMMd" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD213SS" xed="VFMADD213SS_XMMdq_XMMd_XMMd" />
-	<instruction form="xmm, xmm, xmm" name="VFMADD231SS" xed="VFMADD231SS_XMMdq_XMMd_XMMd" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmaddsub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF ((j &amp; 1) == 0) 
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmaddsub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF ((j &amp; 1) == 0) 
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	ELSE
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB132PD" xed="VFMADDSUB132PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB213PD" xed="VFMADDSUB213PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB231PD" xed="VFMADDSUB231PD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmaddsub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF ((j &amp; 1) == 0) 
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmaddsub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF ((j &amp; 1) == 0) 
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	ELSE
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB132PS" xed="VFMADDSUB132PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB213PS" xed="VFMADDSUB213PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMADDSUB231PS" xed="VFMADDSUB231PS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUB132PD" xed="VFMSUB132PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB213PD" xed="VFMSUB213PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB231PD" xed="VFMSUB231PD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmsub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMSUB132PD" xed="VFMSUB132PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUB213PD" xed="VFMSUB213PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUB231PD" xed="VFMSUB231PD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUB132PS" xed="VFMSUB132PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB213PS" xed="VFMSUB213PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB231PS" xed="VFMSUB231PS_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmsub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMSUB132PS" xed="VFMSUB132PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUB213PS" xed="VFMSUB213PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUB231PS" xed="VFMSUB231PS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_sd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] * b[63:0]) - c[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUB132SD" xed="VFMSUB132SD_XMMdq_XMMq_XMMq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB213SD" xed="VFMSUB213SD_XMMdq_XMMq_XMMq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB231SD" xed="VFMSUB231SD_XMMdq_XMMq_XMMq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsub_ss" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := (a[31:0] * b[31:0]) - c[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUB132SS" xed="VFMSUB132SS_XMMdq_XMMd_XMMd" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB213SS" xed="VFMSUB213SS_XMMdq_XMMd_XMMd" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUB231SS" xed="VFMSUB231SS_XMMdq_XMMd_XMMd" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsubadd_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF ((j &amp; 1) == 0) 
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmsubadd_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	IF ((j &amp; 1) == 0) 
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i]
-	ELSE
-		dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD132PD" xed="VFMSUBADD132PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD213PD" xed="VFMSUBADD213PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD231PD" xed="VFMSUBADD231PD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fmsubadd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF ((j &amp; 1) == 0) 
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fmsubadd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	IF ((j &amp; 1) == 0) 
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i]
-	ELSE
-		dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD132PS" xed="VFMSUBADD132PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD213PS" xed="VFMSUBADD213PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFMSUBADD231PS" xed="VFMSUBADD231PS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMADD132PD" xed="VFNMADD132PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD213PD" xed="VFNMADD213PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD231PD" xed="VFNMADD231PD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fnmadd_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i]
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFNMADD132PD" xed="VFNMADD132PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFNMADD213PD" xed="VFNMADD213PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFNMADD231PD" xed="VFNMADD231PD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMADD132PS" xed="VFNMADD132PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD213PS" xed="VFNMADD213PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD231PS" xed="VFNMADD231PS_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fnmadd_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i]
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFNMADD132PS" xed="VFNMADD132PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFNMADD213PS" xed="VFNMADD213PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFNMADD231PS" xed="VFNMADD231PS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_sd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMADD132SD" xed="VFNMADD132SD_XMMdq_XMMq_XMMq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD213SD" xed="VFNMADD213SD_XMMdq_XMMq_XMMq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD231SD" xed="VFNMADD231SD_XMMdq_XMMq_XMMq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmadd_ss" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMADD132SS" xed="VFNMADD132SS_XMMdq_XMMd_XMMd" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD213SS" xed="VFNMADD213SS_XMMdq_XMMd_XMMd" />
-	<instruction form="xmm, xmm, xmm" name="VFNMADD231SS" xed="VFNMADD231SS_XMMdq_XMMd_XMMd" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB132PD" xed="VFNMSUB132PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB213PD" xed="VFNMSUB213PD_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB231PD" xed="VFNMSUB231PD_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fnmsub_pd" tech="AVX_ALL">
-	<return etype="FP64" type="__m256d" varname="dst" />
-	<parameter etype="FP64" type="__m256d" varname="a" />
-	<parameter etype="FP64" type="__m256d" varname="b" />
-	<parameter etype="FP64" type="__m256d" varname="c" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*64
-	dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i]
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB132PD" xed="VFNMSUB132PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB213PD" xed="VFNMSUB213PD_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB231PD" xed="VFNMSUB231PD_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-ENDFOR	
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB132PS" xed="VFNMSUB132PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB213PS" xed="VFNMSUB213PS_XMMdq_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB231PS" xed="VFNMSUB231PS_XMMdq_XMMdq_XMMdq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_fnmsub_ps" tech="AVX_ALL">
-	<return etype="FP32" type="__m256" varname="dst" />
-	<parameter etype="FP32" type="__m256" varname="a" />
-	<parameter etype="FP32" type="__m256" varname="b" />
-	<parameter etype="FP32" type="__m256" varname="c" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*32
-	dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i]
-ENDFOR	
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB132PS" xed="VFNMSUB132PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB213PS" xed="VFNMSUB213PS_YMMqq_YMMqq_YMMqq" />
-	<instruction form="ymm, ymm, ymm" name="VFNMSUB231PS" xed="VFNMSUB231PS_YMMqq_YMMqq_YMMqq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_sd" tech="AVX_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="c" />
-	<description>Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0]
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB132SD" xed="VFNMSUB132SD_XMMdq_XMMq_XMMq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB213SD" xed="VFNMSUB213SD_XMMdq_XMMq_XMMq" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB231SD" xed="VFNMSUB231SD_XMMdq_XMMq_XMMq" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_fnmsub_ss" tech="AVX_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="c" />
-	<description>Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0]
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB132SS" xed="VFNMSUB132SS_XMMdq_XMMd_XMMd" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB213SS" xed="VFNMSUB213SS_XMMdq_XMMd_XMMd" />
-	<instruction form="xmm, xmm, xmm" name="VFNMSUB231SS" xed="VFNMSUB231SS_XMMdq_XMMd_XMMd" />
-	<CPUID>FMA</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_readfsbase_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<description>Read the FS segment base register and store the 32-bit result in "dst".</description>
-	<operation>dst[31:0] := FS_Segment_Base_Register
-dst[63:32] := 0
-	</operation>
-	<instruction form="r32" name="RDFSBASE" xed="RDFSBASE_GPRy" />
-	<CPUID>FSGSBASE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_readfsbase_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<description>Read the FS segment base register and store the 64-bit result in "dst".</description>
-	<operation>dst[63:0] := FS_Segment_Base_Register
-	</operation>
-	<instruction form="r64" name="RDFSBASE" xed="RDFSBASE_GPRy" />
-	<CPUID>FSGSBASE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_readgsbase_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<description>Read the GS segment base register and store the 32-bit result in "dst".</description>
-	<operation>dst[31:0] := GS_Segment_Base_Register
-dst[63:32] := 0
-	</operation>
-	<instruction form="r32" name="RDGSBASE" xed="RDGSBASE_GPRy" />
-	<CPUID>FSGSBASE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_readgsbase_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<description>Read the GS segment base register and store the 64-bit result in "dst".</description>
-	<operation>dst[63:0] := GS_Segment_Base_Register
-	</operation>
-	<instruction form="r64" name="RDGSBASE" xed="RDGSBASE_GPRy" />
-	<CPUID>FSGSBASE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_writefsbase_u32" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Write the unsigned 32-bit integer "a" to the FS segment base register.</description>
-	<operation>
-FS_Segment_Base_Register[31:0] := a[31:0]
-FS_Segment_Base_Register[63:32] := 0
-	</operation>
-	<instruction form="r32" name="WRFSBASE" xed="WRFSBASE_GPRy" />
-	<CPUID>FSGSBASE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_writefsbase_u64" tech="Other">
-	<return type="void" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Write the unsigned 64-bit integer "a" to the FS segment base register.</description>
-	<operation>
-FS_Segment_Base_Register[63:0] := a[63:0]
-	</operation>
-	<instruction form="r64" name="WRFSBASE" xed="WRFSBASE_GPRy" />
-	<CPUID>FSGSBASE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_writegsbase_u32" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Write the unsigned 32-bit integer "a" to the GS segment base register.</description>
-	<operation>
-GS_Segment_Base_Register[31:0] := a[31:0]
-GS_Segment_Base_Register[63:32] := 0
-	</operation>
-	<instruction form="r32" name="WRGSBASE" xed="WRGSBASE_GPRy" />
-	<CPUID>FSGSBASE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_writegsbase_u64" tech="Other">
-	<return type="void" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Write the unsigned 64-bit integer "a" to the GS segment base register.</description>
-	<operation>
-GS_Segment_Base_Register[63:0] := a[63:0]
-	</operation>
-	<instruction form="r64" name="WRGSBASE" xed="WRGSBASE_GPRy" />
-	<CPUID>FSGSBASE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_fxrstor" tech="Other">
-	<return type="void" />
-	<parameter memwidth="4096" type="void *" varname="mem_addr" />
-	<description>Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr". This data should have been written to memory previously using the FXSAVE instruction, and in the same format as required by the operating mode. "mem_addr" must be aligned on a 16-byte boundary.</description>
-	<operation>state_x87_fpu_mmx_sse := fxrstor(MEM[mem_addr+512*8:mem_addr])
-	</operation>
-	<instruction form="m512" name="FXRSTOR" xed="FXRSTOR_MEMmfpxenv" />
-	<CPUID>FXSR</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_fxrstor64" tech="Other">
-	<return type="void" />
-	<parameter memwidth="4096" type="void *" varname="mem_addr" />
-	<description>Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr". This data should have been written to memory previously using the FXSAVE64 instruction, and in the same format as required by the operating mode. "mem_addr" must be aligned on a 16-byte boundary.</description>
-	<operation>state_x87_fpu_mmx_sse := fxrstor64(MEM[mem_addr+512*8:mem_addr])
-	</operation>
-	<instruction form="m512" name="FXRSTOR64" xed="FXRSTOR64_MEMmfpxenv" />
-	<CPUID>FXSR</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_fxsave" tech="Other">
-	<return type="void" />
-	<parameter memwidth="4096" type="void *" varname="mem_addr" />
-	<description>Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr". The layout of the 512-byte region depends on the operating mode. Bytes [511:464] are available for software use and will not be overwritten by the processor.</description>
-	<operation>MEM[mem_addr+512*8:mem_addr] := fxsave(state_x87_fpu_mmx_sse)
-	</operation>
-	<instruction form="m512" name="FXSAVE" xed="FXSAVE_MEMmfpxenv" />
-	<CPUID>FXSR</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_fxsave64" tech="Other">
-	<return type="void" />
-	<parameter memwidth="4096" type="void *" varname="mem_addr" />
-	<description>Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr". The layout of the 512-byte region depends on the operating mode. Bytes [511:464] are available for software use and will not be overwritten by the processor.</description>
-	<operation>MEM[mem_addr+512*8:mem_addr] := fxsave64(state_x87_fpu_mmx_sse)
-	</operation>
-	<instruction form="m512" name="FXSAVE64" xed="FXSAVE64_MEMmfpxenv" />
-	<CPUID>FXSR</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_maskz_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 63
-	IF k[j]
-		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-	ELSE
-		dst.byte[j] := 0
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm" name="VGF2P8MULB" xed="VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 63
-	IF k[j]
-		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-	ELSE
-		dst.byte[j] := src.byte[j]
-	FI
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm" name="VGF2P8MULB" xed="VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m512i" varname="dst" />
-	<parameter etype="UI8" type="__m512i" varname="a" />
-	<parameter etype="UI8" type="__m512i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 63
-	dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm" name="VGF2P8MULB" xed="VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="x" />
-	<parameter etype="UI64" type="__m512i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 7
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="x" />
-	<parameter etype="UI64" type="__m512i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 7
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := src.qword[j].byte[i]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="x" />
-	<parameter etype="UI64" type="__m512i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst".</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 7
-	FOR i := 0 to 7
-		dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_maskz_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="x" />
-	<parameter etype="UI64" type="__m512i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 7
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {z}, zmm, zmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_mask_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="src" />
-	<parameter etype="MASK" type="__mmask64" varname="k" />
-	<parameter etype="UI64" type="__m512i" varname="x" />
-	<parameter etype="UI64" type="__m512i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 7
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := src.qword[j].byte[b]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm {k}, zmm, zmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm512_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m512i" varname="dst" />
-	<parameter etype="UI64" type="__m512i" varname="x" />
-	<parameter etype="UI64" type="__m512i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst".</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 7
-	FOR i := 0 to 7
-		dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-	ENDFOR
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512F</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_maskz_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 31
-	IF k[j]
-		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-	ELSE
-		dst.byte[j] := 0
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm" name="VGF2P8MULB" xed="VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 31
-	IF k[j]
-		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-	ELSE
-		dst.byte[j] := src.byte[j]
-	FI
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm" name="VGF2P8MULB" xed="VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m256i" varname="dst" />
-	<parameter etype="UI8" type="__m256i" varname="a" />
-	<parameter etype="UI8" type="__m256i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 31
-	dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm" name="VGF2P8MULB" xed="VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 15
-	IF k[j]
-		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-	ELSE
-		dst.byte[j] := 0
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm" name="VGF2P8MULB" xed="VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 15
-	IF k[j]
-		dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-	ELSE
-		dst.byte[j] := src.byte[j]
-	FI
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm" name="VGF2P8MULB" xed="VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_gf2p8mul_epi8" tech="Other">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1.</description>
-	<operation>
-DEFINE gf2p8mul_byte(src1byte, src2byte) {
-	tword := 0
-	FOR i := 0 to 7
-		IF src2byte.bit[i]
-			tword := tword XOR (src1byte &lt;&lt; i)
-		FI
-	ENDFOR
-	FOR i := 14 downto 8
-		p := 0x11B &lt;&lt; (i-8)
-		IF tword.bit[i]
-			tword := tword XOR p
-		FI
-	ENDFOR
-	RETURN tword.byte[0]
-}
-FOR j := 0 TO 15
-	dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm" name="VGF2P8MULB" xed="VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="x" />
-	<parameter etype="UI64" type="__m256i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 3
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="x" />
-	<parameter etype="UI64" type="__m256i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 3
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := src.qword[j].byte[i]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="x" />
-	<parameter etype="UI64" type="__m256i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst".</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 3
-	FOR i := 0 to 7
-		dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="x" />
-	<parameter etype="UI64" type="__m128i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 1
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="x" />
-	<parameter etype="UI64" type="__m128i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 1
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := src.qword[j].byte[i]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_gf2p8affine_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="x" />
-	<parameter etype="UI64" type="__m128i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst".</description>
-	<operation>
-DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 1
-	FOR i := 0 to 7
-		dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b)
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VGF2P8AFFINEQB" xed="VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_maskz_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="x" />
-	<parameter etype="UI64" type="__m256i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 3
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {z}, ymm, ymm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_mask_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="src" />
-	<parameter etype="MASK" type="__mmask32" varname="k" />
-	<parameter etype="UI64" type="__m256i" varname="x" />
-	<parameter etype="UI64" type="__m256i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 3
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := src.qword[j].byte[i]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm {k}, ymm, ymm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm256_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m256i" varname="dst" />
-	<parameter etype="UI64" type="__m256i" varname="x" />
-	<parameter etype="UI64" type="__m256i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst".</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 3
-	FOR i := 0 to 7
-		dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-	ENDFOR
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskz_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="x" />
-	<parameter etype="UI64" type="__m128i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 1
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := 0
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {z}, xmm, xmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mask_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="src" />
-	<parameter etype="MASK" type="__mmask16" varname="k" />
-	<parameter etype="UI64" type="__m128i" varname="x" />
-	<parameter etype="UI64" type="__m128i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 1
-	FOR i := 0 to 7
-		IF k[j*8+i]
-			dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-		ELSE
-			dst.qword[j].byte[i] := src.qword[j].byte[i]
-		FI
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm {k}, xmm, xmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_gf2p8affineinv_epi64_epi8" tech="Other">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="x" />
-	<parameter etype="UI64" type="__m128i" varname="A" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="b" />
-	<description>Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst".</description>
-	<operation>DEFINE parity(x) {
-	t := 0
-	FOR i := 0 to 7
-		t := t XOR x.bit[i]
-	ENDFOR
-	RETURN t
-}
-DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) {
-	FOR i := 0 to 7
-		retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i]
-	ENDFOR
-	RETURN retbyte
-}
-FOR j := 0 TO 1
-	FOR i := 0 to 7
-		dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b)
-	ENDFOR
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm, xmm, imm8" name="VGF2P8AFFINEINVQB" xed="VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512" />
-	<CPUID>GFNI</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_hreset" tech="Other">
-	<return type="void" />
-	<parameter type="int" varname="__eax" etype="SI32" />
-	<description>Provides a hint to the processor to selectively reset the prediction history of the current logical processor specified by a signed 32-bit integer "__eax".</description>
-	<instruction name="HRESET" form="imm8" xed="HRESET_IMM8" />
-	<CPUID>HRESET</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-<intrinsic name="_invpcid" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="type" />
-	<parameter memwidth="128" type="void*" varname="descriptor" />
-	<description>Invalidate mappings in the Translation Lookaside Buffers (TLBs) and paging-structure caches for the processor context identifier (PCID) specified by "descriptor" based on the invalidation type specified in "type". 
-	The PCID "descriptor" is specified as a 16-byte memory operand (with no alignment restrictions) where bits [11:0] specify the PCID, and bits [127:64] specify the linear address; bits [63:12] are reserved.
-	The types supported are:
-		0) Individual-address invalidation: If "type" is 0, the logical processor invalidates mappings for a single linear address and tagged with the PCID specified in "descriptor", except global translations. The instruction may also invalidate global translations, mappings for other linear addresses, or mappings tagged with other PCIDs.
-		1) Single-context invalidation: If "type" is 1, the logical processor invalidates all mappings tagged with the PCID specified in "descriptor" except global translations. In some cases, it may invalidate mappings for other PCIDs as well.
-		2) All-context invalidation: If "type" is 2, the logical processor invalidates all mappings tagged with any PCID.
-		3) All-context invalidation, retaining global translations: If "type" is 3, the logical processor invalidates all mappings tagged with any PCID except global translations, ignoring "descriptor". The instruction may also invalidate global translations as well.</description>
-	<operation>
-CASE type[1:0] OF
-0: // individual-address invalidation retaining global translations
-	OP_PCID := MEM[descriptor+11:descriptor]
-	ADDR := MEM[descriptor+127:descriptor+64]
-	BREAK
-1: // single PCID invalidation retaining globals
-	OP_PCID := MEM[descriptor+11:descriptor]
-	// invalidate all mappings tagged with OP_PCID except global translations
-	BREAK
-2: // all PCID invalidation
-	// invalidate all mappings tagged with any PCID
-	BREAK
-3: // all PCID invalidation retaining global translations
-	// invalidate all mappings tagged with any PCID except global translations
-	BREAK
-ESAC
-	</operation>
-	<instruction form="r32, m128" name="INVPCID" xed="INVPCID_GPR32_MEMdq" />
-	<CPUID>INVPCID</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_aesdec128kl_u8" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="128" />
-		<parameter type="__m128i" varname="__idata" etype="UI8" />
-		<parameter type="const void*" varname="__h" etype="UI8" memwidth="384" />
-		<description>Decrypt 10 rounds of unsigned 8-bit integers in "__idata" using 128-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
-		<operation>MEM[__odata+127:__odata] := AES128Decrypt (__idata[127:0], __h[383:0])
-dst := ZF
-		</operation>
-		<instruction name="AESDEC128KL" form="xmm, m32" xed="AESDEC128KL_XMMu8_MEMu8" />
-	<CPUID>KEYLOCKER</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesdec256kl_u8" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="128" />
-		<parameter type="__m128i" varname="__idata" etype="UI8" />
-		<parameter type="const void*" varname="__h" etype="UI8" memwidth="512" />
-		<description>Decrypt 10 rounds of unsigned 8-bit integers in "__idata" using 256-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
-		<operation>MEM[__odata+127:__odata] := AES256Decrypt (__idata[127:0], __h[511:0])
-dst := ZF
-		</operation>
-		<instruction name="AESDEC256KL" form="xmm, m32" xed="AESDEC256KL_XMMu8_MEMu8" />
-	<CPUID>KEYLOCKER</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesenc128kl_u8" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="128" />
-		<parameter type="__m128i" varname="__idata" etype="UI8" />
-		<parameter type="const void*" varname="__h" etype="UI8" memwidth="384" />
-		<description>Encrypt 10 rounds of unsigned 8-bit integers in "__idata" using 128-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status.</description>
-		<operation>MEM[__odata+127:__odata] := AES128Encrypt (__idata[127:0], __h[383:0])
-dst := ZF
-		</operation>
-		<instruction name="AESENC128KL" form="xmm, m32" xed="AESENC128KL_XMMu8_MEMu8" />
-	<CPUID>KEYLOCKER</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesenc256kl_u8" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="128" />
-		<parameter type="__m128i" varname="__idata" etype="UI8" />
-		<parameter type="const void*" varname="__h" etype="UI8" memwidth="512" />
-		<description>Encrypt 10 rounds of unsigned 8-bit integers in "__idata" using 256-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
-		<operation>MEM[__odata+127:__odata] := AES256Encrypt (__idata[127:0], __h[511:0])
-dst := ZF
-		</operation>
-		<instruction name="AESENC256KL" form="xmm, m32" xed="AESENC256KL_XMMu8_MEMu8" />
-	<CPUID>KEYLOCKER</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_encodekey128_u32" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned int" varname="dst" etype="UI32" />
-		<parameter type="unsigned int" varname="__htype" etype="UI32" />
-		<parameter type="__m128i" varname="__key" etype="UI8" />
-		<parameter type="void*" varname="__h" etype="UI8" memwidth="768" />
-		<description>Wrap a 128-bit AES key from "__key" into a 384-bit key __h stored in "__h" and set IWKey's NoBackup and KeySource bits in "dst". The explicit source operand "__htype" specifies __h restrictions.</description>
-		<operation>__h[383:0] := WrapKey128(__key[127:0], __htype)
-dst[0] := IWKey.NoBackup
-dst[4:1] := IWKey.KeySource[3:0]
-		</operation>
-		<instruction name="ENCODEKEY128" form="r32, r32" xed="ENCODEKEY128_GPR32u8_GPR32u8" />
-	<CPUID>KEYLOCKER</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_encodekey256_u32" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned int" varname="dst" etype="UI32" />
-		<parameter type="unsigned int" varname="__htype" etype="UI32" />
-		<parameter type="__m128i" varname="__key_lo" etype="UI8" />
-		<parameter type="__m128i" varname="__key_hi" etype="UI8" />
-		<parameter type="void*" varname="__h" etype="UI8" memwidth="896" />
-		<description>Wrap a 256-bit AES key from "__key_hi" and "__key_lo" into a 512-bit key stored in "__h" and set IWKey's NoBackup and KeySource bits in "dst". The 32-bit "__htype" specifies __h restrictions.</description>
-		<operation>__h[511:0] := WrapKey256(__key_lo[127:0], __key_hi[127:0], __htype)
-dst[0] := IWKey.NoBackup
-dst[4:1] := IWKey.KeySource[3:0]
-		</operation>
-		<instruction name="ENCODEKEY256" form="r32, r32" xed="ENCODEKEY256_GPR32u8_GPR32u8" />
-	<CPUID>KEYLOCKER</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadiwkey" tech="Other">
-		<type>Flag</type>
-		<return type="void" />
-		<parameter type="unsigned int" varname="__ctl" etype="UI32" />
-		<parameter type="__m128i" varname="__intkey" etype="UI8" />
-		<parameter type="__m128i" varname="__enkey_lo" etype="UI8" />
-		<parameter type="__m128i" varname="__enkey_hi" etype="UI8" />
-		<description>Load internal wrapping key (IWKey). The 32-bit unsigned integer "__ctl" specifies IWKey's KeySource and whether backing up the key is permitted. IWKey's 256-bit encryption key is loaded from "__enkey_lo" and "__enkey_hi". IWKey's 128-bit integrity key is loaded from "__intkey".</description>
-		<instruction name="LOADIWKEY" form="xmm, xmm" xed="LOADIWKEY_XMMu8_XMMu8" />
-	<CPUID>KEYLOCKER</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-<intrinsic name="_mm_aesdecwide128kl_u8" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="1024" />
-		<parameter type="const __m128i*" varname="__idata" etype="UI8" memwidth="1024" />
-		<parameter type="const void*" varname="__h" etype="UI8" memwidth="384" />
-		<description>Decrypt 10 rounds of 8 groups of unsigned 8-bit integers in "__idata" using 128-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
-		<operation>FOR i := 0 to 7
-	__odata[i] := AES128Decrypt (__idata[i], __h[383:0])
-ENDFOR
-dst := ZF
-		</operation>
-		<instruction name="AESDECWIDE128KL" form="m32" xed="AESDECWIDE128KL_MEMu8" />
-	<CPUID>KEYLOCKER_WIDE</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesdecwide256kl_u8" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="1024" />
-		<parameter type="const __m128i*" varname="__idata" etype="UI8" memwidth="1024" />
-		<parameter type="const void*" varname="__h" etype="UI8" memwidth="512" />
-		<description>Decrypt 10 rounds of 8 groups of unsigned 8-bit integers in "__idata" using 256-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
-		<operation>FOR i := 0 to 7
-	__odata[i] := AES256Decrypt (__idata[i], __h[511:0])
-ENDFOR
-dst := ZF
-		</operation>
-		<instruction name="AESDECWIDE256KL" form="m32" xed="AESDECWIDE256KL_MEMu8" />
-	<CPUID>KEYLOCKER_WIDE</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesencwide128kl_u8" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="1024" />
-		<parameter type="const __m128i*" varname="__idata" etype="UI8" memwidth="1024" />
-		<parameter type="const void*" varname="__h" etype="UI8" memwidth="384" />
-		<description>Encrypt 10 rounds of 8 groups of unsigned 8-bit integers in "__idata" using 128-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
-		<operation>FOR i := 0 to 7
-	__odata[i] := AES128Encrypt (__idata[i], __h[383:0])
-ENDFOR
-dst := ZF
-		</operation>
-		<instruction name="AESENCWIDE128KL" form="m32" xed="AESENCWIDE128KL_MEMu8" />
-	<CPUID>KEYLOCKER_WIDE</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_aesencwide256kl_u8" tech="Other">
-		<type>Flag</type>
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="__m128i*" varname="__odata" etype="UI8" memwidth="1024" />
-		<parameter type="const __m128i*" varname="__idata" etype="UI8" memwidth="1024" />
-		<parameter type="const void*" varname="__h" etype="UI8" memwidth="512" />
-		<description>Encrypt 10 rounds of 8 groups of unsigned 8-bit integers in "__idata" using 256-bit AES key specified in "__h", store the resulting unsigned 8-bit integers into the corresponding elements of "__odata", and set "dst" to the ZF flag status. If exception happens, set ZF flag to 1 and zero initialize "__odata".</description>
-		<operation>FOR i := 0 to 7
-	__odata[i] := AES256Encrypt (__idata[i], __h[512:0])
-ENDFOR
-dst := ZF
-		</operation>
-		<instruction name="AESENCWIDE256KL" form="m32" xed="AESENCWIDE256KL_MEMu8" />
-	<CPUID>KEYLOCKER_WIDE</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	
-<intrinsic name="_lzcnt_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Count the number of leading zero bits in unsigned 32-bit integer "a", and return that count in "dst".</description>
-	<operation>
-tmp := 31
-dst := 0
-DO WHILE (tmp &gt;= 0 AND a[tmp] == 0)
-	tmp := tmp - 1
-	dst := dst + 1
-OD
-	</operation>
-	<instruction form="r32, r32" name="LZCNT" xed="LZCNT_GPRv_GPRv" />
-	<CPUID>LZCNT</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_lzcnt_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Count the number of leading zero bits in unsigned 64-bit integer "a", and return that count in "dst".</description>
-	<operation>
-tmp := 63
-dst := 0
-DO WHILE (tmp &gt;= 0 AND a[tmp] == 0)
-	tmp := tmp - 1
-	dst := dst + 1
-OD
-	</operation>
-	<instruction form="r64, r64" name="LZCNT" xed="LZCNT_GPRv_GPRv" />
-	<CPUID>LZCNT</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_m_from_int64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Copy 64-bit integer "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="mm, r64" name="MOVQ" xed="MOVQ_MMXq_GPR64" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_m_to_int64" tech="MMX">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m64" varname="a" />
-	<description>Copy 64-bit integer "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="r64, mm" name="MOVQ" xed="MOVQ_GPR64_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_m_from_int" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-dst[63:32] := 0
-	</operation>
-	<instruction form="mm, r32" name="MOVD" xed="MOVD_MMXq_GPR32" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_m_to_int" tech="MMX">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m64" varname="a" />
-	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-	</operation>
-	<instruction form="r32, mm" name="MOVD" xed="MOVD_GPR32_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi32_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-dst[63:32] := 0
-	</operation>
-	<instruction form="mm, r32" name="MOVD" xed="MOVD_MMXq_GPR32" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi64_si32" tech="MMX">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m64" varname="a" />
-	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-	</operation>
-	<instruction form="r32, mm" name="MOVD" xed="MOVD_GPR32_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtm64_si64" tech="MMX">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m64" varname="a" />
-	<description>Copy 64-bit integer "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="r64, mm" name="MOVQ" xed="MOVQ_GPR64_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi64_m64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Copy 64-bit integer "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="mm, r64" name="MOVQ" xed="MOVQ_MMXq_GPR64" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_m_empty" tech="MMX">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions. This instruction must be used at the end of all MMX technology procedures.</description>
-	<instruction name="EMMS" xed="EMMS" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_empty" tech="MMX">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions. This instruction must be used at the end of all MMX technology procedures.</description>
-	<instruction name="EMMS" xed="EMMS" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_m_packsswb" tech="MMX">
-	<return etype="SI8" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := Saturate8(a[15:0])
-dst[15:8] := Saturate8(a[31:16])
-dst[23:16] := Saturate8(a[47:32])
-dst[31:24] := Saturate8(a[63:48])
-dst[39:32] := Saturate8(b[15:0])
-dst[47:40] := Saturate8(b[31:16])
-dst[55:48] := Saturate8(b[47:32])
-dst[63:56] := Saturate8(b[63:48])
-	</operation>
-	<instruction form="mm, mm" name="PACKSSWB" xed="PACKSSWB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_m_packssdw" tech="MMX">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[31:0])
-dst[31:16] := Saturate16(a[63:32])
-dst[47:32] := Saturate16(b[31:0])
-dst[63:48] := Saturate16(b[63:32])
-	</operation>
-	<instruction form="mm, mm" name="PACKSSDW" xed="PACKSSDW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_m_packuswb" tech="MMX">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := SaturateU8(a[15:0])
-dst[15:8] := SaturateU8(a[31:16])
-dst[23:16] := SaturateU8(a[47:32])
-dst[31:24] := SaturateU8(a[63:48])
-dst[39:32] := SaturateU8(b[15:0])
-dst[47:40] := SaturateU8(b[31:16])
-dst[55:48] := SaturateU8(b[47:32])
-dst[63:56] := SaturateU8(b[63:48])
-	</operation>
-	<instruction form="mm, mm" name="PACKUSWB" xed="PACKUSWB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_packs_pi16" tech="MMX">
-	<return etype="SI8" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := Saturate8(a[15:0])
-dst[15:8] := Saturate8(a[31:16])
-dst[23:16] := Saturate8(a[47:32])
-dst[31:24] := Saturate8(a[63:48])
-dst[39:32] := Saturate8(b[15:0])
-dst[47:40] := Saturate8(b[31:16])
-dst[55:48] := Saturate8(b[47:32])
-dst[63:56] := Saturate8(b[63:48])
-	</operation>
-	<instruction form="mm, mm" name="PACKSSWB" xed="PACKSSWB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_packs_pi32" tech="MMX">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[31:0])
-dst[31:16] := Saturate16(a[63:32])
-dst[47:32] := Saturate16(b[31:0])
-dst[63:48] := Saturate16(b[63:32])
-	</operation>
-	<instruction form="mm, mm" name="PACKSSDW" xed="PACKSSDW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_packs_pu16" tech="MMX">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := SaturateU8(a[15:0])
-dst[15:8] := SaturateU8(a[31:16])
-dst[23:16] := SaturateU8(a[47:32])
-dst[31:24] := SaturateU8(a[63:48])
-dst[39:32] := SaturateU8(b[15:0])
-dst[47:40] := SaturateU8(b[31:16])
-dst[55:48] := SaturateU8(b[47:32])
-dst[63:56] := SaturateU8(b[63:48])
-	</operation>
-	<instruction form="mm, mm" name="PACKUSWB" xed="PACKUSWB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_m_punpckhbw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[63:0], src2[63:0]) {
-	dst[7:0] := src1[39:32]
-	dst[15:8] := src2[39:32] 
-	dst[23:16] := src1[47:40]
-	dst[31:24] := src2[47:40]
-	dst[39:32] := src1[55:48]
-	dst[47:40] := src2[55:48]
-	dst[55:48] := src1[63:56]
-	dst[63:56] := src2[63:56]
-	RETURN dst[63:0]
-}
-dst[63:0] := INTERLEAVE_HIGH_BYTES(a[63:0], b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKHBW" xed="PUNPCKHBW_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_punpckhwd" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[63:0], src2[63:0]) {
-	dst[15:0] := src1[47:32]
-	dst[31:16] := src2[47:32]
-	dst[47:32] := src1[63:48]
-	dst[63:48] := src2[63:48]
-	RETURN dst[63:0]
-}
-dst[63:0] := INTERLEAVE_HIGH_WORDS(a[63:0], b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKLBW" xed="PUNPCKLBW_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_punpckhdq" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32]
-dst[63:32] := b[63:32]
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKHDQ" xed="PUNPCKHDQ_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_punpcklbw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[63:0], src2[63:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	RETURN dst[63:0]	
-}
-dst[63:0] := INTERLEAVE_BYTES(a[63:0], b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKLBW" xed="PUNPCKLBW_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_punpcklwd" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[63:0], src2[63:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	RETURN dst[63:0]	
-}
-dst[63:0] := INTERLEAVE_WORDS(a[63:0], b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKLWD" xed="PUNPCKLWD_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_punpckldq" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-dst[63:32] := b[31:0]
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKLDQ" xed="PUNPCKLDQ_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_pi8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[63:0], src2[63:0]) {
-	dst[7:0] := src1[39:32]
-	dst[15:8] := src2[39:32] 
-	dst[23:16] := src1[47:40]
-	dst[31:24] := src2[47:40]
-	dst[39:32] := src1[55:48]
-	dst[47:40] := src2[55:48]
-	dst[55:48] := src1[63:56]
-	dst[63:56] := src2[63:56]
-	RETURN dst[63:0]	
-}
-dst[63:0] := INTERLEAVE_HIGH_BYTES(a[63:0], b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKHBW" xed="PUNPCKHBW_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[63:0], src2[63:0]) {
-	dst[15:0] := src1[47:32]
-	dst[31:16] := src2[47:32]
-	dst[47:32] := src1[63:48]
-	dst[63:48] := src2[63:48]
-	RETURN dst[63:0]
-}
-dst[63:0] := INTERLEAVE_HIGH_WORDS(a[63:0], b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKLBW" xed="PUNPCKLBW_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32]
-dst[63:32] := b[63:32]
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKHDQ" xed="PUNPCKHDQ_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_pi8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[63:0], src2[63:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	RETURN dst[63:0]	
-}
-dst[63:0] := INTERLEAVE_BYTES(a[63:0], b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKLBW" xed="PUNPCKLBW_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[63:0], src2[63:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	RETURN dst[63:0]	
-}
-dst[63:0] := INTERLEAVE_WORDS(a[63:0], b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKLWD" xed="PUNPCKLWD_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-dst[63:32] := b[31:0]
-	</operation>
-	<instruction form="mm, mm" name="PUNPCKLDQ" xed="PUNPCKLDQ_MMXq_MMXd" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_paddb" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := a[i+7:i] + b[i+7:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDB" xed="PADDB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_paddw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := a[i+15:i] + b[i+15:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDW" xed="PADDW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_paddd" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDD" xed="PADDD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_paddsb" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDSB" xed="PADDSB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_paddsw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDSW" xed="PADDSW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_paddusb" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDUSB" xed="PADDUSB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_paddusw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDUSW" xed="PADDUSW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psubb" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := a[i+7:i] - b[i+7:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBB" xed="PSUBB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psubw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := a[i+15:i] - b[i+15:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBW" xed="PSUBW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psubd" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBD" xed="PSUBD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psubsb" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBSB" xed="PSUBSB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psubsw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBSW" xed="PSUBSW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psubusb" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBUSB" xed="PSUBUSB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psubusw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBUSW" xed="PSUBUSW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_pmaddwd" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMADDWD" xed="PMADDWD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_pmulhw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMULHW" xed="PMULHW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_pmullw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	tmp[31:0] := a[i+15:i] * b[i+15:i]
-	dst[i+15:i] := tmp[15:0]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMULLW" xed="PMULLW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_pi8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := a[i+7:i] + b[i+7:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDB" xed="PADDB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := a[i+15:i] + b[i+15:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDW" xed="PADDW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDD" xed="PADDD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_adds_pi8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI8" type="__m64" varname="a" />
-	<parameter etype="SI8" type="__m64" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDSB" xed="PADDSB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_adds_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDSW" xed="PADDSW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_adds_pu8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDUSB" xed="PADDUSB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_adds_pu16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PADDUSW" xed="PADDUSW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_pi8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := a[i+7:i] - b[i+7:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBB" xed="PSUBB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := a[i+15:i] - b[i+15:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBW" xed="PSUBW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBD" xed="PSUBD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_subs_pi8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI8" type="__m64" varname="a" />
-	<parameter etype="SI8" type="__m64" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBSB" xed="PSUBSB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_subs_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBSW" xed="PSUBSW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_subs_pu8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBUSB" xed="PSUBUSB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_subs_pu16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSUBUSW" xed="PSUBUSW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_madd_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMADDWD" xed="PMADDWD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mulhi_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMULHW" xed="PMULHW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mullo_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	tmp[31:0] := a[i+15:i] * b[i+15:i]
-	dst[i+15:i] := tmp[15:0]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMULLW" xed="PMULLW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psllw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSLLW" xed="PSLLW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psllwi" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSLLW" xed="PSLLW_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_pslld" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSLLD" xed="PSLLD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_pslldi" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSLLD" xed="PSLLD_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psllq" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst".</description>
-	<operation>
-IF count[63:0] &gt; 63
-	dst[63:0] := 0
-ELSE
-	dst[63:0] := ZeroExtend64(a[63:0] &lt;&lt; count[63:0])
-FI
-	</operation>
-	<instruction form="mm, mm" name="PSLLQ" xed="PSLLQ_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psllqi" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst".</description>
-	<operation>
-IF imm8[7:0] &gt; 63
-	dst[63:0] := 0
-ELSE
-	dst[63:0] := ZeroExtend64(a[63:0] &lt;&lt; imm8[7:0])
-FI
-	</operation>
-	<instruction form="mm, imm8" name="PSLLQ" xed="PSLLQ_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psraw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSRAW" xed="PSRAW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psrawi" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSRAW" xed="PSRAW_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psrad" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSRAD" xed="PSRAD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psradi" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSRAD" xed="PSRAD_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psrlw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSRLW" xed="PSRLW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psrlwi" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSRLW" xed="PSRLW_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psrld" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSRLD" xed="PSRLD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psrldi" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSRLD" xed="PSRLD_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psrlq" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift 64-bit integer "a" right by "count" while shifting in zeros, and store the result in "dst".</description>
-	<operation>
-IF count[63:0] &gt; 63
-	dst[63:0] := 0
-ELSE
-	dst[63:0] := ZeroExtend64(a[63:0] &gt;&gt; count[63:0])
-FI
-	</operation>
-	<instruction form="mm, mm" name="PSRLQ" xed="PSRLQ_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_psrlqi" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst".</description>
-	<operation>
-IF imm8[7:0] &gt; 63
-	dst[63:0] := 0
-ELSE
-	dst[63:0] := ZeroExtend64(a[63:0] &gt;&gt; imm8[7:0])
-FI
-	</operation>
-	<instruction form="mm, imm8" name="PSRLQ" xed="PSRLQ_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sll_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSLLW" xed="PSLLW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_slli_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSLLW" xed="PSLLW_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sll_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSLLD" xed="PSLLD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_slli_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSLLD" xed="PSLLD_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sll_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst".</description>
-	<operation>
-IF count[63:0] &gt; 63
-	dst[63:0] := 0
-ELSE
-	dst[63:0] := ZeroExtend64(a[63:0] &lt;&lt; count[63:0])
-FI
-	</operation>
-	<instruction form="mm, mm" name="PSLLQ" xed="PSLLQ_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_slli_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst".</description>
-	<operation>
-IF imm8[7:0] &gt; 63
-	dst[63:0] := 0
-ELSE
-	dst[63:0] := ZeroExtend64(a[63:0] &lt;&lt; imm8[7:0])
-FI
-	</operation>
-	<instruction form="mm, imm8" name="PSLLQ" xed="PSLLQ_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sra_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSRAW" xed="PSRAW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srai_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSRAW" xed="PSRAW_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sra_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSRAD" xed="PSRAD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srai_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSRAD" xed="PSRAD_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srl_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSRLW" xed="PSRLW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srli_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSRLW" xed="PSRLW_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srl_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSRLD" xed="PSRLD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srli_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, imm8" name="PSRLD" xed="PSRLD_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srl_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="count" />
-	<description>Shift 64-bit integer "a" right by "count" while shifting in zeros, and store the result in "dst".</description>
-	<operation>
-IF count[63:0] &gt; 63
-	dst[63:0] := 0
-ELSE
-	dst[63:0] := ZeroExtend64(a[63:0] &gt;&gt; count[63:0])
-FI
-	</operation>
-	<instruction form="mm, mm" name="PSRLQ" xed="PSRLQ_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srli_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst".</description>
-	<operation>
-IF imm8[7:0] &gt; 63
-	dst[63:0] := 0
-ELSE
-	dst[63:0] := ZeroExtend64(a[63:0] &gt;&gt; imm8[7:0])
-FI
-	</operation>
-	<instruction form="mm, imm8" name="PSRLQ" xed="PSRLQ_MMXq_IMMb" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_m_pand" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] AND b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PAND" xed="PAND_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_m_pandn" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := ((NOT a[63:0]) AND b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PANDN" xed="PANDN_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_m_por" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] OR b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="POR" xed="POR_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_m_pxor" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] XOR b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PXOR" xed="PXOR_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_and_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] AND b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PAND" xed="PAND_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_andnot_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := ((NOT a[63:0]) AND b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PANDN" xed="PANDN_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_or_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] OR b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="POR" xed="POR_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_xor_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] XOR b[63:0])
-	</operation>
-	<instruction form="mm, mm" name="PXOR" xed="PXOR_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_m_pcmpeqb" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPEQB" xed="PCMPEQB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_m_pcmpeqw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPEQW" xed="PCMPEQW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_m_pcmpeqd" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPEQD" xed="PCMPEQD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_m_pcmpgtb" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPGTB" xed="PCMPGTB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_m_pcmpgtw" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPGTW" xed="PCMPGTW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_m_pcmpgtd" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI64" type="__m64" varname="a" />
-	<parameter etype="SI64" type="__m64" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPGTD" xed="PCMPGTD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_pi8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPEQB" xed="PCMPEQB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPEQW" xed="PCMPEQW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPEQD" xed="PCMPEQD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_pi8" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI8" type="__m64" varname="a" />
-	<parameter etype="SI8" type="__m64" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPGTB" xed="PCMPGTB_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_pi16" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPGTW" xed="PCMPGTW_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_pi32" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PCMPGTD" xed="PCMPGTD_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_setzero_si64" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m64 with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="mm, mm" name="PXOR" xed="PXOR_MMXq_MMXq" />
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_pi32" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="int" varname="e1" />
-	<parameter etype="UI32" type="int" varname="e0" />
-	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[31:0] := e0
-dst[63:32] := e1
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_pi16" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="short" varname="e3" />
-	<parameter etype="UI16" type="short" varname="e2" />
-	<parameter etype="UI16" type="short" varname="e1" />
-	<parameter etype="UI16" type="short" varname="e0" />
-	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[15:0] := e0
-dst[31:16] := e1
-dst[47:32] := e2
-dst[63:48] := e3
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_pi8" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="char" varname="e7" />
-	<parameter etype="UI8" type="char" varname="e6" />
-	<parameter etype="UI8" type="char" varname="e5" />
-	<parameter etype="UI8" type="char" varname="e4" />
-	<parameter etype="UI8" type="char" varname="e3" />
-	<parameter etype="UI8" type="char" varname="e2" />
-	<parameter etype="UI8" type="char" varname="e1" />
-	<parameter etype="UI8" type="char" varname="e0" />
-	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[7:0] := e0
-dst[15:8] := e1
-dst[23:16] := e2
-dst[31:24] := e3
-dst[39:32] := e4
-dst[47:40] := e5
-dst[55:48] := e6
-dst[63:56] := e7
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_pi32" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_pi16" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast 16-bit integer "a" to all all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := a[15:0]
-ENDFOR
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_pi8" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := a[7:0]
-ENDFOR
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_pi32" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="int" varname="e1" />
-	<parameter etype="UI32" type="int" varname="e0" />
-	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[31:0] := e1
-dst[63:32] := e0
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_pi16" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="short" varname="e3" />
-	<parameter etype="UI16" type="short" varname="e2" />
-	<parameter etype="UI16" type="short" varname="e1" />
-	<parameter etype="UI16" type="short" varname="e0" />
-	<description>Set packed 16-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[15:0] := e3
-dst[31:16] := e2
-dst[47:32] := e1
-dst[63:48] := e0
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_pi8" sequence="TRUE" tech="MMX">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="char" varname="e7" />
-	<parameter etype="UI8" type="char" varname="e6" />
-	<parameter etype="UI8" type="char" varname="e5" />
-	<parameter etype="UI8" type="char" varname="e4" />
-	<parameter etype="UI8" type="char" varname="e3" />
-	<parameter etype="UI8" type="char" varname="e2" />
-	<parameter etype="UI8" type="char" varname="e1" />
-	<parameter etype="UI8" type="char" varname="e0" />
-	<description>Set packed 8-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[7:0] := e7
-dst[15:8] := e6
-dst[23:16] := e5
-dst[31:24] := e4
-dst[39:32] := e3
-dst[47:40] := e2
-dst[55:48] := e1
-dst[63:56] := e0
-	</operation>
-	<CPUID>MMX</CPUID>
-	<header>mmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_monitor" tech="Other">
-	<return type="void" />
-	<parameter type="void const*" varname="p" />
-	<parameter etype="UI32" type="unsigned" varname="extensions" />
-	<parameter etype="UI32" type="unsigned" varname="hints" />
-	<description>Arm address monitoring hardware using the address specified in "p". A store to an address within the specified address range triggers the monitoring hardware. Specify optional extensions in "extensions", and optional hints in "hints".</description>
-	<instruction name="MONITOR" xed="MONITOR" />
-	<CPUID>MONITOR</CPUID>
-	<header>pmmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_mwait" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned" varname="extensions" />
-	<parameter etype="UI32" type="unsigned" varname="hints" />
-	<description>Hint to the processor that it can enter an implementation-dependent-optimized state while waiting for an event or store operation to the address range specified by MONITOR.</description>
-	<instruction name="MWAIT" xed="MWAIT" />
-	<CPUID>MONITOR</CPUID>
-	<header>pmmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_loadbe_i16" tech="Other">
-	<return etype="UI16" type="short" varname="dst" />
-	<parameter etype="UI16" memwidth="16" type="void const *" varname="ptr" />
-	<description>Load 16 bits from memory, perform a byte swap operation, and store the result in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*8
-	dst[i+7:i] := MEM[ptr+15-i:ptr+8-i]
-ENDFOR
-	</operation>
-	<instruction form="r16, m16" name="MOVBE" xed="MOVBE_GPRv_MEMv" />
-	<CPUID>MOVBE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_loadbe_i32" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="void const *" varname="ptr" />
-	<description>Load 32 bits from memory, perform a byte swap operation, and store the result in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*8
-	dst[i+7:i] := MEM[ptr+31-i:ptr+24-i]
-ENDFOR
-	</operation>
-	<instruction form="r32, m32" name="MOVBE" xed="MOVBE_GPRv_MEMv" />
-	<CPUID>MOVBE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_loadbe_i64" tech="Other">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" memwidth="64" type="void const *" varname="ptr" />
-	<description>Load 64 bits from memory, perform a byte swap operation, and store the result in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := MEM[ptr+63-i:ptr+56-i]
-ENDFOR
-	</operation>
-	<instruction form="r64, m64" name="MOVBE" xed="MOVBE_GPRv_MEMv" />
-	<CPUID>MOVBE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_storebe_i16" tech="Other">
-	<return type="void" />
-	<parameter etype="UI16" memwidth="16" type="void *" varname="ptr" />
-	<parameter etype="UI16" type="short" varname="data" />
-	<description>Perform a bit swap operation of the 16 bits in "data", and store the results to memory.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*8
-	MEM[ptr+i+7:ptr+i] := data[15-i:8-i]
-ENDFOR
-	</operation>
-	<instruction form="m16, r16" name="MOVBE" xed="MOVBE_MEMv_GPRv" />
-	<CPUID>MOVBE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_storebe_i32" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="32" type="void *" varname="ptr" />
-	<parameter etype="UI32" type="int" varname="data" />
-	<description>Perform a bit swap operation of the 32 bits in "data", and store the results to memory.</description>
-	<operation>
-addr := MEM[ptr]
-FOR j := 0 to 3
-	i := j*8
-	MEM[ptr+i+7:ptr+i] := data[31-i:24-i]
-ENDFOR
-	</operation>
-	<instruction form="m32, r32" name="MOVBE" xed="MOVBE_MEMv_GPRv" />
-	<CPUID>MOVBE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_storebe_i64" tech="Other">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="64" type="void *" varname="ptr" />
-	<parameter etype="UI64" type="__int64" varname="data" />
-	<description>Perform a bit swap operation of the 64 bits in "data", and store the results to memory.</description>
-	<operation>
-addr := MEM[ptr]
-FOR j := 0 to 7
-	i := j*8
-	MEM[ptr+i+7:ptr+i] := data[63-i:56-i]
-ENDFOR
-	</operation>
-	<instruction form="m64, r64" name="MOVBE" xed="MOVBE_MEMv_GPRv" />
-	<CPUID>MOVBE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_movdir64b" tech="Other">
-	<return type="void" />
-	<parameter etype="M512" memwidth="512" type="void*" varname="dst" />
-	<parameter etype="M512" memwidth="512" type="const void*" varname="src" />
-	<description>Move 64-byte (512-bit) value using direct store from source memory address "src" to destination memory address "dst".</description>
-	<operation>
-MEM[dst+511:dst] := MEM[src+511:src]
-	</operation>
-	<instruction form="r64, m512" name="MOVDIR64B" xed="MOVDIR64B_GPRa_MEM" />
-	<CPUID>MOVDIR64B</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_directstoreu_u64" tech="Other">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="64" type="void*" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="val" />
-	<description>Store 64-bit integer from "val" into memory using direct store.</description>
-	<operation>
-MEM[dst+63:dst] := val[63:0]
-	</operation>
-	<instruction form="m64, r64" name="MOVDIRI" xed="MOVDIRI_MEMu64_GPR64u64" />
-	<CPUID>MOVDIRI</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_directstoreu_u32" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="32" type="void*" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="val" />
-	<description>Store 32-bit integer from "val" into memory using direct store.</description>
-	<operation>
-MEM[dst+31:dst] := val[31:0]
-	</operation>
-	<instruction form="m32, r32" name="MOVDIRI" xed="MOVDIRI_MEMu32_GPR32u32" />
-	<CPUID>MOVDIRI</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_bnd_set_ptr_bounds" tech="Other">
-	<return type="void *" />
-	<parameter type="const void *" varname="srcmem" />
-	<parameter etype="UI64" type="size_t" varname="size" />
-	<description>Make a pointer with the value of "srcmem" and bounds set to ["srcmem", "srcmem" + "size" - 1], and store the result in "dst".</description>
-	<operation>dst := srcmem
-dst.LB := srcmem.LB
-dst.UB := srcmem + size - 1
-	</operation>
-	<instruction form="bnd, m32" name="BNDMK" xed="BNDMK_BND_AGEN" />
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_narrow_ptr_bounds" sequence="TRUE" tech="Other">
-	<return type="void *" />
-	<parameter type="const void *" varname="q" />
-	<parameter type="const void *" varname="r" />
-	<parameter etype="UI64" type="size_t" varname="size" />
-	<description>Narrow the bounds for pointer "q" to the intersection of the bounds of "r" and the bounds ["q", "q" + "size" - 1], and store the result in "dst".</description>
-	<operation>dst := q
-IF r.LB &gt; (q + size - 1) OR r.UB &lt; q
-	dst.LB := 1
-	dst.UB := 0
-ELSE
-	dst.LB := MAX(r.LB, q)
-	dst.UB := MIN(r.UB, (q + size - 1))
-FI
-	</operation>
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_copy_ptr_bounds" sequence="TRUE" tech="Other">
-	<return type="void *" />
-	<parameter type="const void *" varname="q" />
-	<parameter type="const void *" varname="r" />
-	<description>Make a pointer with the value of "q" and bounds set to the bounds of "r" (e.g. copy the bounds of "r" to pointer "q"), and store the result in "dst".</description>
-	<operation>dst := q
-dst.LB := r.LB
-dst.UB := r.UB
-	</operation>
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_init_ptr_bounds" sequence="TRUE" tech="Other">
-	<return type="void *" />
-	<parameter type="const void *" varname="q" />
-	<description>Make a pointer with the value of "q" and open bounds, which allow the pointer to access the entire virtual address space, and store the result in "dst".</description>
-	<operation>dst := q
-dst.LB := 0
-dst.UB := 0
-	</operation>
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_store_ptr_bounds" tech="Other">
-	<return type="void" />
-	<parameter type="const void **" varname="ptr_addr" />
-	<parameter type="const void *" varname="ptr_val" />
-	<description>Stores the bounds of "ptr_val" pointer in memory at address "ptr_addr".</description>
-	<operation>MEM[ptr_addr].LB := ptr_val.LB
-MEM[ptr_addr].UB := ptr_val.UB
-	</operation>
-	<instruction form="mib, bnd" name="BNDSTX" xed="BNDSTX_MEMbnd64_BND" />
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_chk_ptr_lbounds" tech="Other">
-	<return type="void" />
-	<parameter type="const void *" varname="q" />
-	<description>Checks if "q" is within its lower bound, and throws a #BR if not.</description>
-	<operation>IF q &lt; q.LB
-	#BR
-FI
-	</operation>
-	<instruction form="bnd, m64" name="BNDCL" xed="BNDCL_BND_AGEN" />
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_chk_ptr_ubounds" tech="Other">
-	<return type="void" />
-	<parameter type="const void *" varname="q" />
-	<description>Checks if "q" is within its upper bound, and throws a #BR if not.</description>
-	<operation>IF q &gt; q.UB
-	#BR
-FI
-	</operation>
-	<instruction form="bnd, m64" name="BNDCU" xed="BNDCU_BND_AGEN" />
-	<instruction form="bnd, m64" name="BNDCN" xed="BNDCN_BND_AGEN" />
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_chk_ptr_bounds" tech="Other">
-	<return type="void" />
-	<parameter type="const void *" varname="q" />
-	<parameter etype="UI64" type="size_t" varname="size" />
-	<description>Checks if ["q", "q" + "size" - 1] is within the lower and upper bounds of "q" and throws a #BR if not.</description>
-	<operation>IF (q + size - 1) &lt; q.LB OR (q + size - 1) &gt; q.UB
-	#BR
-FI
-	</operation>
-	<instruction form="bnd, m32" name="BNDCU" xed="BNDCU_BND_AGEN" />
-	<instruction form="bnd, m32" name="BNDCN" xed="BNDCN_BND_AGEN" />
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_get_ptr_lbound" sequence="TRUE" tech="Other">
-	<return type="const void *" />
-	<parameter type="const void *" varname="q" />
-	<description>Return the lower bound of "q".</description>
-	<operation>dst := q.LB
-	</operation>
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	<intrinsic name="_bnd_get_ptr_ubound" sequence="TRUE" tech="Other">
-	<return type="const void *" />
-	<parameter type="const void *" varname="q" />
-	<description>Return the upper bound of "q".</description>
-	<operation>dst := q.UB
-	</operation>
-	<CPUID>MPX</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	<supported icx="FALSE" />
-	</intrinsic>
-	
-<intrinsic name="_bit_scan_forward" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Set "dst" to the index of the lowest set bit in 32-bit integer "a". If no bits are set in "a" then "dst" is undefined.</description>
-	<operation>
-tmp := 0
-IF a == 0
-	// dst is undefined
-ELSE
-	DO WHILE ((tmp &lt; 32) AND a[tmp] == 0)
-		tmp := tmp + 1
-	OD
-FI
-dst := tmp
-	</operation>
-	<instruction form="r32, r32" name="BSF" xed="BSF_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bit_scan_reverse" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Set "dst" to the index of the highest set bit in 32-bit integer "a". If no bits are set in "a" then "dst" is undefined.</description>
-	<operation>
-tmp := 31
-IF a == 0
-	// dst is undefined
-ELSE
-	DO WHILE ((tmp &gt; 0) AND a[tmp] == 0)
-		tmp := tmp - 1
-	OD
-FI
-dst := tmp
-	</operation>
-	<instruction form="r32, r32" name="BSR" xed="BSR_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_BitScanForward" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="unsigned __int32*" varname="index" />
-	<parameter etype="UI32" type="unsigned __int32" varname="a" />
-	<description>Set "index" to the index of the lowest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1.</description>
-	<operation>
-tmp := 0
-IF a == 0
-	// MEM[index+31:index] is undefined
-	dst := 0
-ELSE
-	DO WHILE ((tmp &lt; 32) AND a[tmp] == 0)
-		tmp := tmp + 1
-	OD
-	MEM[index+31:index] := tmp
-	dst := (tmp == 31) ? 0 : 1
-FI
-	</operation>
-	<instruction form="r32, r32" name="BSF" xed="BSF_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_BitScanReverse" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="unsigned __int32*" varname="index" />
-	<parameter etype="UI32" type="unsigned __int32" varname="a" />
-	<description>Set "index" to the index of the highest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1.</description>
-	<operation>
-tmp := 31
-IF a == 0
-	// MEM[index+31:index] is undefined
-	dst := 0
-ELSE
-	DO WHILE ((tmp &gt; 0) AND a[tmp] == 0)
-		tmp := tmp - 1
-	OD
-	MEM[index+31:index] := tmp
-	dst := (tmp == 0) ? 0 : 1
-FI
-	</operation>
-	<instruction form="r32, r32" name="BSR" xed="BSR_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_BitScanForward64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="unsigned __int32*" varname="index" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Set "index" to the index of the lowest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1.</description>
-	<operation>
-tmp := 0
-IF a == 0
-	// MEM[index+31:index] is undefined
-	dst := 0
-ELSE
-	DO WHILE ((tmp &lt; 64) AND a[tmp] == 0)
-		tmp := tmp + 1
-	OD
-	MEM[index+31:index] := tmp
-	dst := (tmp == 63) ? 0 : 1
-FI
-	</operation>
-	<instruction form="r64, r64" name="BSF" xed="BSF_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_BitScanReverse64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="unsigned __int32*" varname="index" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Set "index" to the index of the highest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1.</description>
-	<operation>
-tmp := 63
-IF a == 0
-	// MEM[index+31:index] is undefined
-	dst := 0
-ELSE
-	DO WHILE ((tmp &gt; 0) AND a[tmp] == 0)
-		tmp := tmp - 1
-	OD
-	MEM[index+31:index] := tmp
-	dst := (tmp == 0) ? 0 : 1
-FI
-	</operation>
-	<instruction form="r64, r64" name="BSR" xed="BSR_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bittest" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="__int32*" varname="a" />
-	<parameter etype="IMM" immwidth="5" type="__int32" varname="b" />
-	<description>Return the bit at index "b" of 32-bit integer "a".</description>
-	<operation>
-addr := a + ZeroExtend64(b)
-dst[0] := MEM[addr]
-	</operation>
-	<instruction form="m32, r32" name="BT" xed="BT_MEMv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bittestandcomplement" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="__int32*" varname="a" />
-	<parameter etype="IMM" immwidth="5" type="__int32" varname="b" />
-	<description>Return the bit at index "b" of 32-bit integer "a", and set that bit to its complement.</description>
-	<operation>
-addr := a + ZeroExtend64(b)
-dst[0] := MEM[addr]
-MEM[addr] := ~dst[0]
-	</operation>
-	<instruction form="m32, r32" name="BTC" xed="BTC_MEMv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bittestandreset" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="__int32*" varname="a" />
-	<parameter etype="IMM" immwidth="5" type="__int32" varname="b" />
-	<description>Return the bit at index "b" of 32-bit integer "a", and set that bit to zero.</description>
-	<operation>
-addr := a + ZeroExtend64(b)
-dst[0] := MEM[addr]
-MEM[addr] := 0
-	</operation>
-	<instruction form="m32, r32" name="BTR" xed="BTR_MEMv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bittestandset" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="__int32*" varname="a" />
-	<parameter etype="IMM" immwidth="5" type="__int32" varname="b" />
-	<description>Return the bit at index "b" of 32-bit integer "a", and set that bit to one.</description>
-	<operation>
-addr := a + ZeroExtend64(b)
-dst[0] := MEM[addr]
-MEM[addr] := 1
-	</operation>
-	<instruction form="m32, r32" name="BTS" xed="BTS_MEMv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bittest64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI64" memwidth="32" type="__int64*" varname="a" />
-	<parameter etype="IMM" immwidth="6" type="__int64" varname="b" />
-	<description>Return the bit at index "b" of 64-bit integer "a".</description>
-	<operation>
-addr := a + b
-dst[0] := MEM[addr]
-	</operation>
-	<instruction form="r64, r64" name="BT" xed="BT_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bittestandcomplement64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI64" memwidth="32" type="__int64*" varname="a" />
-	<parameter etype="IMM" immwidth="6" type="__int64" varname="b" />
-	<description>Return the bit at index "b" of 64-bit integer "a", and set that bit to its complement.</description>
-	<operation>
-addr := a + b
-dst[0] := MEM[addr]
-MEM[addr] := ~dst[0]
-	</operation>
-	<instruction form="r64, r64" name="BTC" xed="BTC_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bittestandreset64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI64" memwidth="32" type="__int64*" varname="a" />
-	<parameter etype="IMM" immwidth="6" type="__int64" varname="b" />
-	<description>Return the bit at index "b" of 64-bit integer "a", and set that bit to zero.</description>
-	<operation>
-addr := a + b
-dst[0] := MEM[addr]
-MEM[addr] := 0
-	</operation>
-	<instruction form="r64, r64" name="BTR" xed="BTR_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bittestandset64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI64" memwidth="32" type="__int64*" varname="a" />
-	<parameter etype="IMM" immwidth="6" type="__int64" varname="b" />
-	<description>Return the bit at index "b" of 64-bit integer "a", and set that bit to one.</description>
-	<operation>
-addr := a + b
-dst[0] := MEM[addr]
-MEM[addr] := 1
-	</operation>
-	<instruction form="r64, r64" name="BTS" xed="BTS_GPRv_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bswap" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Reverse the byte order of 32-bit integer "a", and store the result in "dst". This intrinsic is provided for conversion between little and big endian values.</description>
-	<operation>
-dst[7:0] := a[31:24]
-dst[15:8] := a[23:16]
-dst[23:16] := a[15:8]
-dst[31:24] := a[7:0]
-	</operation>
-	<instruction form="r32" name="BSWAP" xed="BSWAP_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_bswap64" tech="Other">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Reverse the byte order of 64-bit integer "a", and store the result in "dst". This intrinsic is provided for conversion between little and big endian values.</description>
-	<operation>
-dst[7:0] := a[63:56]
-dst[15:8] := a[55:48]
-dst[23:16] := a[47:40]
-dst[31:24] := a[39:32]
-dst[39:32] := a[31:24]
-dst[47:40] := a[23:16]
-dst[55:48] := a[15:8]
-dst[63:56] := a[7:0]
-	</operation>
-	<instruction form="r64" name="BSWAP" xed="BSWAP_GPRv" />
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_castf32_u32" tech="Other">
-	<return etype="UI32" type="unsigned __int32" varname="dst" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Cast from type float to type unsigned __int32 without conversion.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_castf64_u64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="FP64" type="double" varname="a" />
-	<description>Cast from type double to type unsigned __int64 without conversion.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_castu32_f32" tech="Other">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="UI32" type="unsigned __int32" varname="a" />
-	<description>Cast from type unsigned __int32 to type float without conversion.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_castu64_f64" tech="Other">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Cast from type unsigned __int64 to type double without conversion.
-	This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<header>immintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_lrotl" tech="Other">
-	<return etype="UI32" type="unsigned long" varname="dst" />
-	<parameter etype="UI32" type="unsigned long" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="shift" />
-	<description>Shift the bits of unsigned long integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".</description>
-	<operation>// size := 32 or 64
-dst := a
-count := shift AND (size - 1)
-DO WHILE (count &gt; 0)
-	tmp[0] := dst[size - 1]
-	dst := (dst &lt;&lt; 1) OR tmp[0]
-	count := count - 1
-OD
-	</operation>
-	<instruction form="r64, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
-	<instruction form="r32, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_lrotr" tech="Other">
-	<return etype="UI32" type="unsigned long" varname="dst" />
-	<parameter etype="UI32" type="unsigned long" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="shift" />
-	<description>Shift the bits of unsigned long integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".</description>
-	<operation>// size := 32 or 64
-dst := a
-count := shift AND (size - 1)
-DO WHILE (count &gt; 0)
-	tmp[size - 1] := dst[0]
-	dst := (dst &gt;&gt; 1) OR tmp[size - 1]
-	count := count - 1
-OD
-	</operation>
-	<instruction form="r64, imm8" name="ROR" xed="ROR_GPRv_IMMb" />
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_rotl" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="IMM" immwidth="5" type="int" varname="shift" />
-	<description>Shift the bits of unsigned 32-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".</description>
-	<operation>
-dst := a
-count := shift AND 31
-DO WHILE (count &gt; 0)
-	tmp[0] := dst[31]
-	dst := (dst &lt;&lt; 1) OR tmp[0]
-	count := count - 1
-OD
-	</operation>
-	<instruction form="r32, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_rotr" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="IMM" immwidth="5" type="int" varname="shift" />
-	<description>Shift the bits of unsigned 32-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".</description>
-	<operation>
-dst := a
-count := shift AND 31
-DO WHILE (count &gt; 0)
-	tmp[31] := dst[0]
-	dst := (dst &gt;&gt; 1) OR tmp
-	count := count - 1
-OD
-	</operation>
-	<instruction form="r32, imm8" name="ROR" xed="ROR_GPRv_IMMb" />
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_rotwl" tech="Other">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="UI16" type="unsigned short" varname="a" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="shift" />
-	<description>Shift the bits of unsigned 16-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".</description>
-	<operation>
-dst := a
-count := shift AND 15
-DO WHILE (count &gt; 0)
-	tmp[0] := dst[15]
-	dst := (dst &lt;&lt; 1) OR tmp[0]
-	count := count - 1
-OD
-	</operation>
-	<instruction form="r16, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_rotwr" tech="Other">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="UI16" type="unsigned short" varname="a" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="shift" />
-	<description>Shift the bits of unsigned 16-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".</description>
-	<operation>
-dst := a
-count := shift AND 15
-DO WHILE (count &gt; 0)
-	tmp[15] := dst[0]
-	dst := (dst &gt;&gt; 1) OR tmp
-	count := count - 1
-OD
-	</operation>
-	<instruction form="r16, imm8" name="ROR" xed="ROR_GPRv_IMMb" />
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_rotl64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="IMM" immwidth="6" type="int" varname="shift" />
-	<description>Shift the bits of unsigned 64-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst".</description>
-	<operation>
-dst := a
-count := shift AND 63
-DO WHILE (count &gt; 0)
-	tmp[0] := dst[63]
-	dst := (dst &lt;&lt; 1) OR tmp[0]
-	count := count - 1
-OD
-	</operation>
-	<instruction form="r64, imm8" name="ROL" xed="ROL_GPRv_IMMb" />
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_rotr64" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="IMM" immwidth="6" type="int" varname="shift" />
-	<description>Shift the bits of unsigned 64-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst".</description>
-	<operation>
-dst := a
-count := shift AND 63
-DO WHILE (count &gt; 0)
-	tmp[63] := dst[0]
-	dst := (dst &gt;&gt; 1) OR tmp[63]
-	count := count - 1
-OD
-	</operation>
-	<instruction form="r64, imm8" name="ROR" xed="ROR_GPRv_IMMb" />
-	<header>immintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_allow_cpu_features" sequence="TRUE" tech="Other">
-	<return type="void" />
-	<parameter etype="IMM" immwidth="8" type="unsigned __int64" varname="a" />
-	<description>Treat the processor-specific feature(s) specified in "a" as available. Multiple features may be OR'd together. See the valid feature flags below:</description>
-	<operation>
-_FEATURE_GENERIC_IA32
-_FEATURE_FPU
-_FEATURE_CMOV
-_FEATURE_MMX
-_FEATURE_FXSAVE
-_FEATURE_SSE
-_FEATURE_SSE2
-_FEATURE_SSE3
-_FEATURE_SSSE3
-_FEATURE_SSE4_1
-_FEATURE_SSE4_2
-_FEATURE_MOVBE
-_FEATURE_POPCNT
-_FEATURE_PCLMULQDQ
-_FEATURE_AES
-_FEATURE_F16C
-_FEATURE_AVX
-_FEATURE_RDRND
-_FEATURE_FMA
-_FEATURE_BMI
-_FEATURE_LZCNT
-_FEATURE_HLE
-_FEATURE_RTM
-_FEATURE_AVX2
-_FEATURE_KNCNI
-_FEATURE_AVX512F
-_FEATURE_ADX
-_FEATURE_RDSEED
-_FEATURE_AVX512ER
-_FEATURE_AVX512PF
-_FEATURE_AVX512CD
-_FEATURE_SHA
-_FEATURE_MPX
-_FEATURE_AVX512BW
-_FEATURE_AVX512VL
-_FEATURE_AVX512VBMI
-_FEATURE_AVX512_4FMAPS
-_FEATURE_AVX512_4VNNIW
-_FEATURE_AVX512_VPOPCNTDQ
-_FEATURE_AVX512_BITALG
-_FEATURE_AVX512_VBMI2
-_FEATURE_GFNI
-_FEATURE_VAES
-_FEATURE_VPCLMULQDQ
-_FEATURE_AVX512_VNNI
-_FEATURE_CLWB
-_FEATURE_RDPID
-_FEATURE_IBT
-_FEATURE_SHSTK
-_FEATURE_SGX
-_FEATURE_WBNOINVD
-_FEATURE_PCONFIG
-_FEATURE_AXV512_4VNNIB
-_FEATURE_AXV512_4FMAPH
-_FEATURE_AXV512_BITALG2
-_FEATURE_AXV512_VP2INTERSECT
-	</operation>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_may_i_use_cpu_feature" sequence="TRUE" tech="Other">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="IMM" immwidth="8" type="unsigned __int64" varname="a" />
-	<description>Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available, and return true or false (1 or 0) if the set of features is available. Multiple features may be OR'd together. This function is limited to bitmask values in the first 'page' of the libirc cpu-id information. This intrinsic does not check the processor vendor. See the valid feature flags below:</description>
-	<operation>
-_FEATURE_GENERIC_IA32
-_FEATURE_FPU
-_FEATURE_CMOV
-_FEATURE_MMX
-_FEATURE_FXSAVE
-_FEATURE_SSE
-_FEATURE_SSE2
-_FEATURE_SSE3
-_FEATURE_SSSE3
-_FEATURE_SSE4_1
-_FEATURE_SSE4_2
-_FEATURE_MOVBE
-_FEATURE_POPCNT
-_FEATURE_PCLMULQDQ
-_FEATURE_AES
-_FEATURE_F16C
-_FEATURE_AVX
-_FEATURE_RDRND
-_FEATURE_FMA
-_FEATURE_BMI
-_FEATURE_LZCNT
-_FEATURE_HLE
-_FEATURE_RTM
-_FEATURE_AVX2
-_FEATURE_KNCNI
-_FEATURE_AVX512F
-_FEATURE_ADX
-_FEATURE_RDSEED
-_FEATURE_AVX512ER
-_FEATURE_AVX512PF
-_FEATURE_AVX512CD
-_FEATURE_SHA
-_FEATURE_MPX
-_FEATURE_AVX512BW
-_FEATURE_AVX512VL
-_FEATURE_AVX512VBMI
-_FEATURE_AVX512_4FMAPS
-_FEATURE_AVX512_4VNNIW
-_FEATURE_AVX512_VPOPCNTDQ
-_FEATURE_AVX512_BITALG
-_FEATURE_AVX512_VBMI2
-_FEATURE_GFNI
-_FEATURE_VAES
-_FEATURE_VPCLMULQDQ
-_FEATURE_AVX512_VNNI
-_FEATURE_CLWB
-_FEATURE_RDPID
-_FEATURE_IBT
-_FEATURE_SHSTK
-_FEATURE_SGX
-_FEATURE_WBNOINVD
-_FEATURE_PCONFIG
-_FEATURE_AXV512_4VNNIB
-_FEATURE_AXV512_4FMAPH
-_FEATURE_AXV512_BITALG2
-_FEATURE_AXV512_VP2INTERSECT
-_FEATURE_AXV512_FP16
-	</operation>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_may_i_use_cpu_feature_ext" sequence="TRUE" tech="Other">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="IMM" immwidth="8" type="unsigned __int64" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="unsigned" varname="page" />
-	<description>Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available, and return true or false (1 or 0) if the set of features is available. Multiple features may be OR'd together. This works identically to the previous variant, except it also accepts a 'page' index that permits checking features on the 2nd page of the libirc information. When provided with a '0' in the 'page' parameter, this works identically to _may_i_use_cpu_feature. This intrinsic does not check the processor vendor. See the valid feature flags on the 2nd page below: (provided with a '1' in the 'page' parameter)</description>
-	<operation>
-_FEATURE_CLDEMOTE
-_FEATURE_MOVDIRI
-_FEATURE_MOVDIR64B
-_FEATURE_WAITPKG
-_FEATURE_AVX512_Bf16
-_FEATURE_ENQCMD
-_FEATURE_AVX_VNNI
-_FEATURE_AMX_TILE
-_FEATURE_AMX_INT8
-_FEATURE_AMX_BF16
-_FEATURE_KL
-_FEATURE_WIDE_KL
-_FEATURE_HRESET
-_FEATURE_UINTR
-_FEATURE_PREFETCHI
-_FEATURE_AVXVNNIINT8
-_FEATURE_CMPCCXADD
-_FEATURE_AVXIFMA
-_FEATURE_AVXNECONVERT
-_FEATURE_RAOINT
-_FEATURE_AMX_FP16
-_FEATURE_AMX_COMPLEX
-_FEATURE_SHA512
-_FEATURE_SM3
-_FEATURE_SM4
-_FEATURE_AVXVNNIINT16
-_FEATURE_USERMSR
-_FEATURE_AVX10_1_256
-_FEATURE_AVX10_1_512
-_FEATURE_APXF
-_FEATURE_MSRLIST
-_FEATURE_WRMSRNS
-_FEATURE_PBNDKB
-	</operation>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_may_i_use_cpu_feature_str" sequence="TRUE" tech="Other">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter type="string literal" varname="feature, ..." />
-	<description>Dynamically query the processor to determine if the processor-specific feature(s) specified a series of compile-time string literals in "feature, ..." are available, and return true or false (1 or 0) if the set of features is available. These feature names are converted to a bitmask and uses the same infrastructure as _may_i_use_cpu_feature_ext to validate it. The behavior is the same as the previous variants. This intrinsic does not check the processor vendor. Supported string literals are one-to-one corresponding in the "Operation" sections of _may_i_use_cpu_feature and _may_i_use_cpu_feature_ext. Example string literals are "avx2", "bmi", "avx512fp16", "amx-int8"...</description>
-	<operation>
-	</operation>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_rdpmc" tech="Other">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Read the Performance Monitor Counter (PMC) specified by "a", and store up to 64-bits in "dst". The width of performance counters is implementation specific.</description>
-	<operation>dst[63:0] := ReadPMC(a)
-	</operation>
-	<instruction name="RDPMC" xed="RDPMC" />
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_addcarry_u32" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="unsigned char" varname="c_in" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<parameter etype="UI32" memwidth="32" type="unsigned int *" varname="out" />
-	<description>Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
-	<operation>
-tmp[32:0] := a[31:0] + b[31:0] + (c_in &gt; 0 ? 1 : 0)
-MEM[out+31:out] := tmp[31:0]
-dst[0] := tmp[32]
-dst[7:1] := 0
-	</operation>
-	<instruction form="r32, r32" name="ADC" xed="ADC_GPRv_GPRv_11" />
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_addcarry_u64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="unsigned char" varname="c_in" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<parameter etype="UI64" memwidth="64" type="unsigned __int64 *" varname="out" />
-	<description>Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
-	<operation>
-tmp[64:0] := a[63:0] + b[63:0] + (c_in &gt; 0 ? 1 : 0)
-MEM[out+63:out] := tmp[63:0]
-dst[0] := tmp[64]
-dst[7:1] := 0
-	</operation>
-	<instruction form="r64, r64" name="ADC" xed="ADC_GPRv_GPRv_11" />
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_subborrow_u32" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="unsigned char" varname="c_in" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI32" type="unsigned int" varname="b" />
-	<parameter etype="UI32" memwidth="32" type="unsigned int *" varname="out" />
-	<description>Add unsigned 8-bit borrow "c_in" (carry flag) to unsigned 32-bit integer "b", and subtract the result from unsigned 32-bit integer "a". Store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
-	<operation>
-tmp[32:0] := a[31:0] - (b[31:0] + (c_in &gt; 0 ? 1 : 0))
-MEM[out+31:out] := tmp[31:0]
-dst[0] := tmp[32]
-dst[7:1] := 0
-	</operation>
-	<instruction form="r32, r32" name="SBB" xed="SBB_GPRv_GPRv_19" />
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_subborrow_u64" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI8" type="unsigned char" varname="c_in" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="b" />
-	<parameter etype="UI64" memwidth="64" type="unsigned __int64 *" varname="out" />
-	<description>Add unsigned 8-bit borrow "c_in" (carry flag) to unsigned 64-bit integer "b", and subtract the result from unsigned 64-bit integer "a". Store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag).</description>
-	<operation>
-tmp[64:0] := a[63:0] - (b[63:0] + (c_in &gt; 0 ? 1 : 0))
-MEM[out+63:out] := tmp[63:0]
-dst[0] := tmp[64]
-dst[7:1] := 0
-	</operation>
-	<instruction form="r64, r64" name="SBB" xed="SBB_GPRv_GPRv_19" />
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_ptwrite32" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Insert the 32-bit data from "a" into a Processor Trace stream via a PTW packet. The PTW packet will be inserted if tracing is currently enabled and ptwrite is currently enabled. The current IP will also be inserted via a FUP packet if FUPonPTW is enabled.</description>
-	<instruction form="r32" name="PTWRITE" xed="PTWRITE_GPRy" />
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_ptwrite64" tech="Other">
-	<return type="void" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Insert the 64-bit data from "a" into a Processor Trace stream via a PTW packet. The PTW packet will be inserted if tracing is currently enabled and ptwrite is currently enabled. The current IP will also be inserted via a FUP packet if FUPonPTW is enabled.</description>
-	<instruction form="r64" name="PTWRITE" xed="PTWRITE_GPRy" />
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_enclu_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="const int" varname="a" />
-	<parameter etype="UI64" type="size_t*" varname="__data" />
-	<description>Invoke the Intel SGX enclave user (non-privilege) leaf function specified by "a", and return the error code. The "__data" array contains 3 32- or 64-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.</description>
-	<instruction name="ENCLU" xed="ENCLU" />
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_encls_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="const int" varname="a" />
-	<parameter etype="UI64" type="size_t*" varname="__data" />
-	<description>Invoke the Intel SGX enclave system (privileged) leaf function specified by "a", and return the error code. The "__data" array contains 3 32- or 64-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.</description>
-	<instruction name="ENCLS" xed="ENCLS" />
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_enclv_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="const int" varname="a" />
-	<parameter etype="UI64" type="size_t*" varname="__data" />
-	<description>Invoke the Intel SGX enclave virtualized (VMM) leaf function specified by "a", and return the error code. The "__data" array contains 3 32- or 64-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx.</description>
-	<instruction name="ENCLV" xed="ENCLV" />
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_wbinvd" tech="Other">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Write back and flush internal caches.
-		Initiate writing-back and flushing of external
-		caches.</description>
-	<instruction name="WBINVD" xed="WBINVD" />
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_cvtsh_ss" sequence="TRUE" tech="Other">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="UI16" type="unsigned short" varname="a" />
-	<description>Convert the half-precision (16-bit) floating-point value "a" to a single-precision (32-bit) floating-point value, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP16_To_FP32(a[15:0])
-	</operation>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_cvtss_sh" sequence="TRUE" tech="Other">
-	<return etype="UI16" type="unsigned short" varname="dst" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<parameter etype="IMM" hint="TRUE" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Convert the single-precision (32-bit) floating-point value "a" to a half-precision (16-bit) floating-point value, and store the result in "dst".
-	[round_note]</description>
-	<operation>
-dst[15:0] := Convert_FP32_To_FP16(a[31:0])
-	</operation>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	
-<intrinsic name="_mm_clmulepi64_si128" vexEq="TRUE" tech="Other">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Perform a carry-less multiplication of two 64-bit integers, selected from "a" and "b" according to "imm8", and store the results in "dst".</description>
-	<operation>
-IF (imm8[0] == 0)
-	TEMP1 := a[63:0]
-ELSE
-	TEMP1 := a[127:64]
-FI 
-IF (imm8[4] == 0)
-	TEMP2 := b[63:0]
-ELSE 
-	TEMP2 := b[127:64]
-FI
-FOR i := 0 to 63
-	TEMP[i] := (TEMP1[0] and TEMP2[i])
-	FOR j := 1 to i
-		TEMP[i] := TEMP[i] XOR (TEMP1[j] AND TEMP2[i-j])
-	ENDFOR 
-	dst[i] := TEMP[i]
-ENDFOR
-FOR i := 64 to 127
-	TEMP[i] := 0
-	FOR j := (i - 63) to 63
-		TEMP[i] := TEMP[i] XOR (TEMP1[j] AND TEMP2[i-j])
-	ENDFOR
-	dst[i] := TEMP[i]
-ENDFOR
-dst[127] := 0
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCLMULQDQ" xed="PCLMULQDQ_XMMdq_XMMdq_IMMb" />
-	<CPUID>PCLMULQDQ</CPUID>
-	<header>wmmintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_pconfig_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<parameter etype="UI64" type="size_t*" varname="__data" />
-	<description>Invoke the PCONFIG leaf function specified by "a". The "__data" array contains 3 32- or 64-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx. May return the value in eax, depending on the semantics of the specified leaf function.</description>
-	<instruction name="PCONFIG" xed="PCONFIG" />
-	<CPUID>PCONFIG</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_popcnt_u32" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Count the number of bits set to 1 in unsigned 32-bit integer "a", and return that count in "dst".</description>
-	<operation>
-dst := 0
-FOR i := 0 to 31
-	IF a[i]
-		dst := dst + 1
-	FI
-ENDFOR
-	</operation>
-	<instruction form="r32, r32" name="POPCNT" xed="POPCNT_GPRv_GPRv" />
-	<CPUID>POPCNT</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_mm_popcnt_u64" tech="Other">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="a" />
-	<description>Count the number of bits set to 1 in unsigned 64-bit integer "a", and return that count in "dst".</description>
-	<operation>
-dst := 0
-FOR i := 0 to 63
-	IF a[i]
-		dst := dst + 1
-	FI
-ENDFOR
-	</operation>
-	<instruction form="r64, r64" name="POPCNT" xed="POPCNT_GPRv_GPRv" />
-	<CPUID>POPCNT</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_popcnt32" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Count the number of bits set to 1 in 32-bit integer "a", and return that count in "dst".</description>
-	<operation>
-dst := 0
-FOR i := 0 to 31
-	IF a[i]
-		dst := dst + 1
-	FI
-ENDFOR
-	</operation>
-	<instruction form="r32, r32" name="POPCNT" xed="POPCNT_GPRv_GPRv" />
-	<CPUID>POPCNT</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	<intrinsic name="_popcnt64" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Count the number of bits set to 1 in 64-bit integer "a", and return that count in "dst".</description>
-	<operation>
-dst := 0
-FOR i := 0 to 63
-	IF a[i]
-		dst := dst + 1
-	FI
-ENDFOR
-	</operation>
-	<instruction form="r64, r64" name="POPCNT" xed="POPCNT_GPRv_GPRv" />
-	<CPUID>POPCNT</CPUID>
-	<header>immintrin.h</header>
-	<category>Bit Manipulation</category>
-	</intrinsic>
-	
-	
-	<intrinsic name="_m_prefetchit0" tech="Other">
-	<return type="void" />
-	<parameter type="const void*" memwidth="32" etype="UI8" varname="__P" />
-	<description>Loads an instruction sequence containing the specified memory address into all level cache.</description>
-	<instruction form="m8" name="PREFETCHIT0" xed="PREFETCHIT0_MEMu8"/>
-	<CPUID>PREFETCHI</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_m_prefetchit1" tech="Other">
-	<return type="void" />
-	<parameter type="const void*" memwidth="32" etype="UI8" varname="__P" />
-	<description>Loads an instruction sequence containing the specified memory address into all but the first-level cache.</description>
-	<instruction form="m8" name="PREFETCHIT1" xed="PREFETCHIT1_MEMu8"/>
-	<CPUID>PREFETCHI</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-<intrinsic name="_mm_prefetch" tech="Other">
-	<return type="void" />
-	<parameter etype="UI8" type="char const*" varname="p" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="i" />
-	<description>Fetch the line of data from memory that contains address "p" to a location in the cache hierarchy specified by the locality hint "i", which can be one of:&lt;ul&gt;
-    &lt;li&gt;_MM_HINT_ET0  // 7, move data using the ET0 hint. The PREFETCHW instruction will be generated.&lt;/li&gt;
-    &lt;li&gt;_MM_HINT_T0   // 3, move data using the T0 hint. The PREFETCHT0 instruction will be generated.&lt;/li&gt;
-    &lt;li&gt;_MM_HINT_T1   // 2, move data using the T1 hint. The PREFETCHT1 instruction will be generated.&lt;/li&gt;
-    &lt;li&gt;_MM_HINT_T2   // 1, move data using the T2 hint. The PREFETCHT2 instruction will be generated.&lt;/li&gt;
-    &lt;li&gt;_MM_HINT_NTA  // 0, move data using the non-temporal access (NTA) hint. The PREFETCHNTA instruction will be generated.&lt;/li&gt;
-</description>
-	<instruction form="m8" name="PREFETCHW" />
-	<instruction form="m8" name="PREFETCHNTA" xed="PREFETCHNTA_MEMmprefetch" />
-	<instruction form="m8" name="PREFETCHT0" xed="PREFETCHT0_MEMmprefetch" />
-	<instruction form="m8" name="PREFETCHT1" xed="PREFETCHT1_MEMmprefetch" />
-	<instruction form="m8" name="PREFETCHT2" xed="PREFETCHT2_MEMmprefetch" />
-	<CPUID>PRFCHW</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_aadd_i32" tech="Other">
-		<return type="void" />
-		<description>Atomically add a 32-bit value at memory operand "__A" and a 32-bit "__B", and store the result to the same memory location.</description>
-		<instruction name="AADD" form="m32, r32" xed="AADD_MEM32_GPR32" />
-		<operation>
-MEM[__A+31:__A] := MEM[__A+31:__A] + __B[31:0]
-</operation>
-		<parameter type="int*" memwidth="32" etype="SI32" varname="__A" />
-		<parameter type="int" etype="SI32" varname="__B" />
-	<CPUID>RAO_INT</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_aadd_i64" tech="Other">
-		<return type="void" />
-		<description>Atomically add a 64-bit value at memory operand "__A" and a 64-bit "__B", and store the result to the same memory location.</description>
-		<instruction name="AADD" form="m64, r64" xed="AADD_MEM64_GPR64" />
-		<operation>
-MEM[__A+63:__A] := MEM[__A+63:__A] + __B[63:0]
-</operation>
-		<parameter type="__int64*" memwidth="64" etype="SI64" varname="__A" />
-		<parameter type="__int64" etype="SI64" varname="__B" />
-	<CPUID>RAO_INT</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_aand_i32" tech="Other">
-		<return type="void" />
-		<description>Atomically and a 32-bit value at memory operand "__A" and a 32-bit "__B", and store the result to the same memory location.</description>
-		<instruction name="AAND" form="m32, r32" xed="AAND_MEM32_GPR32" />
-		<operation>
-MEM[__A+31:__A] := MEM[__A+31:__A] AND __B[31:0]
-</operation>
-		<parameter type="int*" memwidth="32" etype="SI32" varname="__A" />
-		<parameter type="int" etype="SI32" varname="__B" />
-	<CPUID>RAO_INT</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_aand_i64" tech="Other">
-		<return type="void" />
-		<description>Atomically and a 64-bit value at memory operand "__A" and a 64-bit "__B", and store the result to the same memory location.</description>
-		<instruction name="AAND" form="m64, r64" xed="AAND_MEM64_GPR64" />
-		<operation>
-MEM[__A+63:__A] := MEM[__A+63:__A] AND __B[63:0]
-</operation>
-		<parameter type="__int64*" memwidth="64" etype="SI64" varname="__A" />
-		<parameter type="__int64" etype="SI64" varname="__B" />
-	<CPUID>RAO_INT</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_aor_i32" tech="Other">
-		<return type="void" />
-		<description>Atomically or a 32-bit value at memory operand "__A" and a 32-bit "__B", and store the result to the same memory location.</description>
-		<instruction name="AOR" form="m32, r32" xed="AOR_MEM32_GPR32" />
-		<operation>
-MEM[__A+31:__A] := MEM[__A+31:__A] OR __B[31:0]
-</operation>
-		<parameter type="int*" memwidth="32" etype="SI32" varname="__A" />
-		<parameter type="int" etype="SI32" varname="__B" />
-	<CPUID>RAO_INT</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_aor_i64" tech="Other">
-		<return type="void" />
-		<description>Atomically or a 64-bit value at memory operand "__A" and a 64-bit "__B", and store the result to the same memory location.</description>
-		<instruction name="AOR" form="m64, r64" xed="AOR_MEM64_GPR64" />
-		<operation>
-MEM[__A+63:__A] := MEM[__A+63:__A] OR __B[63:0]
-</operation>
-		<parameter type="__int64*" memwidth="64" etype="SI64" varname="__A" />
-		<parameter type="__int64" etype="SI64" varname="__B" />
-	<CPUID>RAO_INT</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_axor_i32" tech="Other">
-		<return type="void" />
-		<description>Atomically xor a 32-bit value at memory operand "__A" and a 32-bit "__B", and store the result to the same memory location.</description>
-		<instruction name="AXOR" form="m32, r32" xed="AXOR_MEM32_GPR32" />
-		<operation>
-MEM[__A+31:__A] := MEM[__A+31:__A] XOR __B[31:0]
-</operation>
-		<parameter type="int*" memwidth="32" etype="SI32" varname="__A" />
-		<parameter type="int" etype="SI32" varname="__B" />
-	<CPUID>RAO_INT</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_axor_i64" tech="Other">
-		<return type="void" />
-		<description>Atomically xor a 64-bit value at memory operand "__A" and a 64-bit "__B", and store the result to the same memory location.</description>
-		<instruction name="AXOR" form="m64, r64" xed="AXOR_MEM64_GPR64" />
-		<operation>
-MEM[__A+63:__A] := MEM[__A+63:__A] XOR __B[63:0]
-</operation>
-		<parameter type="__int64*" memwidth="64" etype="SI64" varname="__A" />
-		<parameter type="__int64" etype="SI64" varname="__B" />
-	<CPUID>RAO_INT</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-<intrinsic name="_rdpid_u32" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter type="void" />
-	<description>Copy the IA32_TSC_AUX MSR (signature value) into "dst".</description>
-	<operation>dst[31:0] := IA32_TSC_AUX[31:0]
-	</operation>
-	<instruction form="r32" name="RDPID" xed="RDPID_GPR32u32" />
-	<CPUID>RDPID</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_rdrand16_step" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI16" memwidth="16" type="unsigned short*" varname="val" />
-	<description>Read a hardware generated 16-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
-	<operation>IF HW_RND_GEN.ready == 1
-	val[15:0] := HW_RND_GEN.data
-	dst := 1
-ELSE
-	val[15:0] := 0
-	dst := 0
-FI
-	</operation>
-	<instruction form="r16" name="RDRAND" xed="RDRAND_GPRv" />
-	<CPUID>RDRAND</CPUID>
-	<header>immintrin.h</header>
-	<category>Random</category>
-	</intrinsic>
-	<intrinsic name="_rdrand32_step" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="unsigned int*" varname="val" />
-	<description>Read a hardware generated 32-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
-	<operation>IF HW_RND_GEN.ready == 1
-	val[31:0] := HW_RND_GEN.data
-	dst := 1
-ELSE
-	val[31:0] := 0
-	dst := 0
-FI
-	</operation>
-	<instruction form="r32" name="RDRAND" xed="RDRAND_GPRv" />
-	<CPUID>RDRAND</CPUID>
-	<header>immintrin.h</header>
-	<category>Random</category>
-	</intrinsic>
-	<intrinsic name="_rdrand64_step" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI64" memwidth="64" type="unsigned __int64*" varname="val" />
-	<description>Read a hardware generated 64-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
-	<operation>IF HW_RND_GEN.ready == 1
-	val[63:0] := HW_RND_GEN.data
-	dst := 1
-ELSE
-	val[63:0] := 0
-	dst := 0
-FI
-	</operation>
-	<instruction form="r64" name="RDRAND" xed="RDRAND_GPRv" />
-	<CPUID>RDRAND</CPUID>
-	<header>immintrin.h</header>
-	<category>Random</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_rdseed16_step" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI16" type="unsigned short *" varname="val" />
-	<description>Read a 16-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
-	<operation>IF HW_NRND_GEN.ready == 1
-	val[15:0] := HW_NRND_GEN.data
-	dst := 1
-ELSE
-	val[15:0] := 0
-	dst := 0
-FI
-	</operation>
-	<instruction form="r16" name="RDSEED" xed="RDSEED_GPRv" />
-	<CPUID>RDSEED</CPUID>
-	<header>immintrin.h</header>
-	<category>Random</category>
-	</intrinsic>
-	<intrinsic name="_rdseed32_step" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int *" varname="val" />
-	<description>Read a 32-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
-	<operation>IF HW_NRND_GEN.ready == 1
-	val[31:0] := HW_NRND_GEN.data
-	dst := 1
-ELSE
-	val[31:0] := 0
-	dst := 0
-FI
-	</operation>
-	<instruction form="r32" name="RDSEED" xed="RDSEED_GPRv" />
-	<CPUID>RDSEED</CPUID>
-	<header>immintrin.h</header>
-	<category>Random</category>
-	</intrinsic>
-	<intrinsic name="_rdseed64_step" tech="Other">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64 *" varname="val" />
-	<description>Read a 64-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise.</description>
-	<operation>IF HW_NRND_GEN.ready == 1
-	val[63:0] := HW_NRND_GEN.data
-	dst := 1
-ELSE
-	val[63:0] := 0
-	dst := 0
-FI
-	</operation>
-	<instruction form="r64" name="RDSEED" xed="RDSEED_GPRv" />
-	<CPUID>RDSEED</CPUID>
-	<header>immintrin.h</header>
-	<category>Random</category>
-	</intrinsic>
-	
-	
-<intrinsic name="__rdtscp" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="unsigned int *" varname="mem_addr" />
-	<description>Copy the current 64-bit value of the processor's time-stamp counter into "dst", and store the IA32_TSC_AUX MSR (signature value) into memory at "mem_addr".</description>
-	<operation>dst[63:0] := TimeStampCounter
-MEM[mem_addr+31:mem_addr] := IA32_TSC_AUX[31:0]
-	</operation>
-	<instruction name="RDTSCP" xed="RDTSCP" />
-	<CPUID>RDTSCP</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_xabort" tech="Other">
-	<return type="void" />
-	<parameter etype="IMM" immwidth="8" type="const unsigned int" varname="imm8" />
-	<description>Force an RTM abort. The EAX register is updated to reflect an XABORT instruction caused the abort, and the "imm8" parameter will be provided in bits [31:24] of EAX.
-	Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction.</description>
-	<operation>IF RTM_ACTIVE == 0
-	// nop
-ELSE
-	// restore architectural register state
-	// discard memory updates performed in transaction
-	// update EAX with status and imm8 value
-	eax[31:24] := imm8[7:0]
-	RTM_NEST_COUNT := 0
-	RTM_ACTIVE := 0
-	IF _64_BIT_MODE
-		RIP := fallbackRIP
-	ELSE
-		EIP := fallbackEIP
-	FI
-FI
-	</operation>
-	<instruction form="imm8" name="XABORT" xed="XABORT_IMMb" />
-	<CPUID>RTM</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_xbegin" tech="Other">
-	<return etype="UI32" type="unsigned int" varname="k" />
-	<parameter type="void" />
-	<description>Specify the start of an RTM code region. 
-	If the logical processor was not already in transactional execution, then this call causes the logical processor to transition into transactional execution. 
-	On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution, restores architectural state, and starts execution beginning at the fallback address computed from the outermost XBEGIN instruction. Return status of ~0 (0xFFFF) if continuing inside transaction; all other codes are aborts.</description>
-	<operation>IF RTM_NEST_COUNT &lt; MAX_RTM_NEST_COUNT
-	RTM_NEST_COUNT := RTM_NEST_COUNT + 1
-	IF RTM_NEST_COUNT == 1
-		IF _64_BIT_MODE
-			fallbackRIP := RIP
-		ELSE IF _32_BIT_MODE
-			fallbackEIP := EIP
-		FI
-		
-		RTM_ACTIVE := 1
-		// enter RTM execution, record register state, start tracking memory state
-	FI
-ELSE
-	// RTM abort (see _xabort)
-FI
-	</operation>
-	<instruction form="r32" name="XBEGIN" xed="XBEGIN_RELBRz" />
-	<CPUID>RTM</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_xend" tech="Other">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Specify the end of an RTM code region.
-	If this corresponds to the outermost scope, the logical processor will attempt to commit the logical processor state atomically. 
-	If the commit fails, the logical processor will perform an RTM abort.</description>
-	<operation>IF RTM_ACTIVE == 1
-	RTM_NEST_COUNT := RTM_NEST_COUNT - 1
-	IF RTM_NEST_COUNT == 0
-		// try to commit transaction
-		IF FAIL_TO_COMMIT_TRANSACTION
-			// RTM abort (see _xabort)
-		ELSE
-			RTM_ACTIVE := 0
-		FI
-	FI
-FI
-	</operation>
-	<instruction name="XEND" xed="XEND" />
-	<CPUID>RTM</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_xtest" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter type="void" />
-	<description>Query the transactional execution status, return 1 if inside a transactionally executing RTM or HLE region, and return 0 otherwise.</description>
-	<operation>IF (RTM_ACTIVE == 1 OR HLE_ACTIVE == 1)
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction name="XTEST" xed="XTEST" />
-	<CPUID>RTM</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_serialize" tech="Other">
-	<return type="void" />
-	<description>Serialize instruction execution, ensuring all modifications to flags, registers, and memory by previous instructions are completed before the next instruction is fetched.</description>
-	<instruction name="SERIALIZE" xed="SERIALIZE" />
-	<CPUID>SERIALIZE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_sha1msg1_epu32" tech="Other">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Perform an intermediate calculation for the next four SHA1 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst".</description>
-	<operation>
-W0 := a[127:96]
-W1 := a[95:64]
-W2 := a[63:32]
-W3 := a[31:0]
-W4 := b[127:96]
-W5 := b[95:64]
-dst[127:96] := W2 XOR W0
-dst[95:64] := W3 XOR W1
-dst[63:32] := W4 XOR W2
-dst[31:0] := W5 XOR W3
-	</operation>
-	<instruction form="xmm, xmm" name="SHA1MSG1" xed="SHA1MSG1_XMMi32_XMMi32_SHA" />
-	<CPUID>SHA</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_sha1msg2_epu32" tech="Other">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Perform the final calculation for the next four SHA1 message values (unsigned 32-bit integers) using the intermediate result in "a" and the previous message values in "b", and store the result in "dst".</description>
-	<operation>
-W13 := b[95:64]
-W14 := b[63:32]
-W15 := b[31:0]
-W16 := (a[127:96] XOR W13) &lt;&lt;&lt; 1
-W17 := (a[95:64] XOR W14) &lt;&lt;&lt; 1
-W18 := (a[63:32] XOR W15) &lt;&lt;&lt; 1
-W19 := (a[31:0] XOR W16) &lt;&lt;&lt; 1
-dst[127:96] := W16
-dst[95:64] := W17
-dst[63:32] := W18
-dst[31:0] := W19
-	</operation>
-	<instruction form="xmm, xmm" name="SHA1MSG2" xed="SHA1MSG2_XMMi32_XMMi32_SHA" />
-	<CPUID>SHA</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_sha1nexte_epu32" tech="Other">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Calculate SHA1 state variable E after four rounds of operation from the current SHA1 state variable "a", add that value to the scheduled values (unsigned 32-bit integers) in "b", and store the result in "dst".</description>
-	<operation>
-tmp := (a[127:96] &lt;&lt;&lt; 30)
-dst[127:96] := b[127:96] + tmp
-dst[95:64] := b[95:64]
-dst[63:32] := b[63:32]
-dst[31:0] := b[31:0]
-	</operation>
-	<instruction form="xmm, xmm" name="SHA1NEXTE" xed="SHA1NEXTE_XMMi32_XMMi32_SHA" />
-	<CPUID>SHA</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_sha1rnds4_epu32" tech="Other">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="func" />
-	<description>Perform four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from "a" and some pre-computed sum of the next 4 round message values (unsigned 32-bit integers), and state variable E from "b", and store the updated SHA1 state (A,B,C,D) in "dst". "func" contains the logic functions and round constants.</description>
-	<operation>IF (func[1:0] == 0)
-	f := f0()
-	K := K0
-ELSE IF (func[1:0] == 1)
-	f := f1()
-	K := K1
-ELSE IF (func[1:0] == 2)
-	f := f2()
-	K := K2
-ELSE IF (func[1:0] == 3)
-	f := f3()
-	K := K3
-FI
-A := a[127:96]
-B := a[95:64]
-C := a[63:32]
-D := a[31:0]
-W[0] := b[127:96]
-W[1] := b[95:64]
-W[2] := b[63:32]
-W[3] := b[31:0]
-A[1] := f(B, C, D) + (A &lt;&lt;&lt; 5) + W[0] + K
-B[1] := A
-C[1] := B &lt;&lt;&lt; 30
-D[1] := C
-E[1] := D
-FOR i := 1 to 3
-	A[i+1] := f(B[i], C[i], D[i]) + (A[i] &lt;&lt;&lt; 5) + W[i] + E[i] + K
-	B[i+1] := A[i]
-	C[i+1] := B[i] &lt;&lt;&lt; 30
-	D[i+1] := C[i]
-	E[i+1] := D[i]
-ENDFOR
-dst[127:96] := A[4]
-dst[95:64] := B[4]
-dst[63:32] := C[4]
-dst[31:0] := D[4]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="SHA1RNDS4" xed="SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA" />
-	<CPUID>SHA</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_sha256msg1_epu32" tech="Other">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Perform an intermediate calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst".</description>
-	<operation>W4 := b[31:0]
-W3 := a[127:96]
-W2 := a[95:64]
-W1 := a[63:32]
-W0 := a[31:0]
-dst[127:96] := W3 + sigma0(W4)
-dst[95:64] := W2 + sigma0(W3)
-dst[63:32] := W1 + sigma0(W2)
-dst[31:0] := W0 + sigma0(W1)
-	</operation>
-	<instruction form="xmm, xmm" name="SHA256MSG1" xed="SHA256MSG1_XMMi32_XMMi32_SHA" />
-	<CPUID>SHA</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_sha256msg2_epu32" tech="Other">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Perform the final calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst"."</description>
-	<operation>W14 := b[95:64]
-W15 := b[127:96]
-W16 := a[31:0] + sigma1(W14)
-W17 := a[63:32] + sigma1(W15)
-W18 := a[95:64] + sigma1(W16)
-W19 := a[127:96] + sigma1(W17)
-dst[127:96] := W19
-dst[95:64] := W18
-dst[63:32] := W17
-dst[31:0] := W16
-	</operation>
-	<instruction form="xmm, xmm" name="SHA256MSG2" xed="SHA256MSG2_XMMi32_XMMi32_SHA" />
-	<CPUID>SHA</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_sha256rnds2_epu32" tech="Other">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="__m128i" varname="k" />
-	<description>Perform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from "a", an initial SHA256 state (A,B,E,F) from "b", and a pre-computed sum of the next 2 round message values (unsigned 32-bit integers) and the corresponding round constants from "k", and store the updated SHA256 state (A,B,E,F) in "dst".</description>
-	<operation>A[0] := b[127:96]
-B[0] := b[95:64]
-C[0] := a[127:96]
-D[0] := a[95:64]
-E[0] := b[63:32]
-F[0] := b[31:0]
-G[0] := a[63:32]
-H[0] := a[31:0]
-W_K[0] := k[31:0]
-W_K[1] := k[63:32]
-FOR i := 0 to 1
-	A[i+1] := Ch(E[i], F[i], G[i]) + sum1(E[i]) + W_K[i] + H[i] + Maj(A[i], B[i], C[i]) + sum0(A[i])
-	B[i+1] := A[i]
-	C[i+1] := B[i]
-	D[i+1] := C[i]
-	E[i+1] := Ch(E[i], F[i], G[i]) + sum1(E[i]) + W_K[i] + H[i] + D[i]
-	F[i+1] := E[i]
-	G[i+1] := F[i]
-	H[i+1] := G[i]
-ENDFOR
-dst[127:96] := A[2]
-dst[95:64] := B[2]
-dst[63:32] := E[2]
-dst[31:0] := F[2]
-	</operation>
-	<instruction form="xmm, xmm" name="SHA256RNDS2" xed="SHA256RNDS2_XMMi32_XMMi32_SHA" />
-	<CPUID>SHA</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_sha512msg1_epi64" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="UI64" />
-    <description>This intrinisc is one of the two SHA512 message scheduling instructions. The intrinsic performs an intermediate calculation for the next four SHA512 message qwords. The calculated results are stored in "dst".</description>
-    <instruction name="VSHA512MSG1" form="ymm, xmm" xed="VSHA512MSG1_YMMu64_XMMu64" />
-    <operation>
-DEFINE ROR64(qword, n) {
-	count := n % 64
-	dest := (qword &gt;&gt; count) | (qword &lt;&lt; (64 - count))
-	RETURN dest
-}
-DEFINE SHR64(qword, n) {
-	RETURN qword &gt;&gt; n
-}
-DEFINE s0(qword) {
-	RETURN ROR64(qword,1) ^ ROR64(qword, 8) ^ SHR64(qword, 7)
-}
-W.qword[4] := __B.qword[0]
-W.qword[3] := __A.qword[3]
-W.qword[2] := __A.qword[2]
-W.qword[1] := __A.qword[1]
-W.qword[0] := __A.qword[0]
-dst.qword[3] := W.qword[3] + s0(W.qword[4])
-dst.qword[2] := W.qword[2] + s0(W.qword[3])
-dst.qword[1] := W.qword[1] + s0(W.qword[2])
-dst.qword[0] := W.qword[0] + s0(W.qword[1])
-</operation>
-    <parameter type="__m256i" varname="__A" etype="UI64" />
-    <parameter type="__m128i" varname="__B" etype="UI64" />
-  <CPUID>SHA512</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-  <intrinsic name="_mm256_sha512msg2_epi64" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="UI64" />
-    <description>This intrinisc is one of the two SHA512 message scheduling instructions. The intrinsic performs the final calculation for the next four SHA512 message qwords. The calculated results are stored in "dst".</description>
-    <instruction name="VSHA512MSG2" form="ymm, ymm" xed="VSHA512MSG2_YMMu64_YMMu64" />
-    <operation>
-DEFINE ROR64(qword, n) {
-	count := n % 64
-	dest := (qword &gt;&gt; count) | (qword &lt;&lt; (64 - count))
-	RETURN dest
-}
-DEFINE SHR64(qword, n) {
-	RETURN qword &gt;&gt; n
-}
-DEFINE s1(qword) {
-	RETURN ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)
-}
-W.qword[14] := __B.qword[2]
-W.qword[15] := __B.qword[3]
-W.qword[16] := __A.qword[0] + s1(W.qword[14])
-W.qword[17] := __A.qword[1] + s1(W.qword[15])
-W.qword[18] := __A.qword[2] + s1(W.qword[16])
-W.qword[19] := __A.qword[3] + s1(W.qword[17])
-dst.qword[3] := W.qword[19]
-dst.qword[2] := W.qword[18]
-dst.qword[1] := W.qword[17]
-dst.qword[0] := W.qword[16]
-</operation>
-    <parameter type="__m256i" varname="__A" etype="UI64" />
-    <parameter type="__m256i" varname="__B" etype="UI64" />
-  <CPUID>SHA512</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-  <intrinsic name="_mm256_sha512rnds2_epi64" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="UI64" />
-    <description>This intrinisc performs two rounds of SHA512 operation using initial SHA512 state (C,D,G,H) from "__A", an initial SHA512 state (A,B,E,F) from "__B", and a pre-computed sum of the next two round message qwords and the corresponding round constants from "__C" (only the two lower qwords of the third operand). The updated SHA512 state (A,B,E,F) is written to "dst", and "dst" can be used as the updated state (C,D,G,H) in later rounds.</description>
-    <instruction name="VSHA512RNDS2" form="ymm, ymm, xmm" xed="VSHA512RNDS2_YMMu64_YMMu64_XMMu64" />
-    <operation>
-DEFINE ROR64(qword, n) {
-	count := n % 64
-	dest := (qword &gt;&gt; count) | (qword &lt;&lt; (64 - count))
-	RETURN dest
-}
-DEFINE SHR64(qword, n) {
-	RETURN qword &gt;&gt; n
-}
-DEFINE cap_sigma0(qword) {
-	RETURN ROR64(qword, 28) ^ ROR64(qword, 34) ^ ROR64(qword, 39)
-}
-DEFINE cap_sigma1(qword) {
-	RETURN ROR64(qword, 14) ^ ROR64(qword, 18) ^ ROR64(qword, 41)
-}
-DEFINE MAJ(a,b,c) {
-	RETURN (a &amp; b) ^ (a &amp; c) ^ (b &amp; c)
-}
-DEFINE CH(a,b,c) {
-	RETURN (a &amp; b) ^ (c &amp; ~a)
-}
-A.qword[0] := __B.qword[3]
-B.qword[0] := __B.qword[2]
-C.qword[0] := __A.qword[3]
-D.qword[0] := __A.qword[2]
-E.qword[0] := __B.qword[1]
-F.qword[0] := __B.qword[0]
-G.qword[0] := __A.qword[1]
-H.qword[0] := __A.qword[0]
-WK.qword[0]:= __C.qword[0]
-WK.qword[1]:= __C.qword[1]
-FOR i := 0 to 1
-	A.qword[i+1] := CH(E.qword[i], F.qword[i], G.qword[i]) + cap_sigma1(E.qword[i]) + WK.qword[i] + H.qword[i] + MAJ(A.qword[i], B.qword[i], C.qword[i]) + cap_sigma0(A.qword[i])
-	B.qword[i+1] := A.qword[i]
-	C.qword[i+1] := B.qword[i]
-	D.qword[i+1] := C.qword[i]
-	E.qword[i+1] := CH(E.qword[i], F.qword[i], G.qword[i]) + cap_sigma1(E.qword[i]) + WK.qword[i] + H.qword[i] + D.qword[i]
-	F.qword[i+1] := E.qword[i]
-	G.qword[i+1] := F.qword[i]
-	H.qword[i+1] := G.qword[i]
-ENDFOR
-dst.qword[3] := A.qword[2]
-dst.qword[2] := B.qword[2]
-dst.qword[1] := E.qword[2]
-dst.qword[0] := F.qword[2]
-</operation>
-    <parameter type="__m256i" varname="__A" etype="UI64" />
-    <parameter type="__m256i" varname="__B" etype="UI64" />
-    <parameter type="__m128i" varname="__C" etype="UI64" />
-  <CPUID>SHA512</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-<intrinsic name="_mm_sm3msg1_epi32" tech="AVX_ALL">
-    <return etype="UI32" type="__m128i" varname="dst" />
-    <description>The VSM3MSG1 intrinsic is one of the two SM3 message scheduling intrinsics. The intrinsic performs an initial calculation for the next four SM3 message words. The calculated results are stored in "dst".</description>
-    <instruction form="xmm, xmm, xmm" name="VSM3MSG1" xed="VSM3MSG1_XMMu32_XMMu32_XMMu32" />
-    <operation>
-DEFINE ROL32(dword, n) {
-	count := n % 32
-	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32 - count))
-	RETURN dest
-}
-DEFINE P1(x) {
-	RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
-}
-W.dword[0] := __C.dword[0]
-W.dword[1] := __C.dword[1]
-W.dword[2] := __C.dword[2]
-W.dword[3] := __C.dword[3]
-W.dword[7] := __A.dword[0]
-W.dword[8] := __A.dword[1]
-W.dword[9] := __A.dword[2]
-W.dword[10] := __A.dword[3]
-W.dword[13] := __B.dword[0]
-W.dword[14] := __B.dword[1]
-W.dword[15] := __B.dword[2]
-TMP0 := W.dword[7] ^ W.dword[0] ^ ROL32(W.dword[13], 15)
-TMP1 := W.dword[8] ^ W.dword[1] ^ ROL32(W.dword[14], 15)
-TMP2 := W.dword[9] ^ W.dword[2] ^ ROL32(W.dword[15], 15)
-TMP3 := W.dword[10] ^ W.dword[3]
-dst.dword[0] := P1(TMP0)
-dst.dword[1] := P1(TMP1)
-dst.dword[2] := P1(TMP2)
-dst.dword[3] := P1(TMP3)
-</operation>
-    <parameter etype="UI32" type="__m128i" varname="__A" />
-    <parameter etype="UI32" type="__m128i" varname="__B" />
-    <parameter etype="UI32" type="__m128i" varname="__C" />
-  <CPUID>SM3</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-  <intrinsic name="_mm_sm3msg2_epi32" tech="AVX_ALL">
-    <return etype="UI32" type="__m128i" varname="dst" />
-    <description>The VSM3MSG2 intrinsic is one of the two SM3 message scheduling intrinsics. The intrinsic performs the final calculation for the next four SM3 message words. The calculated results are stored in "dst".</description>
-    <instruction form="xmm, xmm, xmm" name="VSM3MSG2" xed="VSM3MSG2_XMMu32_XMMu32_XMMu32" />
-    <operation>
-DEFINE ROL32(dword, n) {
-	count := n % 32
-	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
-	RETURN dest
-}
-WTMP.dword[0] := __A.dword[0]
-WTMP.dword[1] := __A.dword[1]
-WTMP.dword[2] := __A.dword[2]
-WTMP.dword[3] := __A.dword[3]
-W.dword[3] := __B.dword[0]
-W.dword[4] := __B.dword[1]
-W.dword[5] := __B.dword[2]
-W.dword[6] := __B.dword[3]
-W.dword[10] := __C.dword[0]
-W.dword[11] := __C.dword[1]
-W.dword[12] := __C.dword[2]
-W.dword[13] := __C.dword[3]
-W.dword[16] := ROL32(W.dword[3], 7) ^ W.dword[10] ^ WTMP.dword[0]
-W.dword[17] := ROL32(W.dword[4], 7) ^ W.dword[11] ^ WTMP.dword[1]
-W.dword[18] := ROL32(W.dword[5], 7) ^ W.dword[12] ^ WTMP.dword[2]
-W.dword[19] := ROL32(W.dword[6], 7) ^ W.dword[13] ^ WTMP.dword[3]
-W.dword[19] := W.dword[19] ^ ROL32(W.dword[16], 6) ^ ROL32(W.dword[16], 15) ^ ROL32(W.dword[16], 30)
-dst.dword[0] := W.dword[16]
-dst.dword[1] := W.dword[17]
-dst.dword[2] := W.dword[18]
-dst.dword[3] := W.dword[19]
-</operation>
-    <parameter etype="UI32" type="__m128i" varname="__A" />
-    <parameter etype="UI32" type="__m128i" varname="__B" />
-    <parameter etype="UI32" type="__m128i" varname="__C" />
-  <CPUID>SM3</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-  <intrinsic name="_mm_sm3rnds2_epi32" tech="AVX_ALL">
-    <return etype="UI32" type="__m128i" varname="dst" />
-    <description>The intrinsic performs two rounds of SM3 operation using initial SM3 state (C, D, G, H) from "__A", an initial SM3 states (A, B, E, F) from "__B" and a pre-computed words from the "__C". "__A" with initial SM3 state of (C, D, G, H) assumes input of non-rotated left variables from previous state. The updated SM3 state (A, B, E, F) is written to "__A". The "imm8" should contain the even round number for the first of the two rounds computed by this instruction. The computation masks the "imm8" value by ANDing it with 0x3E so that only even round numbers from 0 through 62 are used for this operation. The calculated results are stored in "dst".</description>
-    <instruction form="xmm, xmm, xmm, imm8" name="VSM3RNDS2" xed="VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8" />
-    <operation>
-DEFINE ROL32(dword, n) {
-	count := n % 32
-	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
-	RETURN dest
-}
-DEFINE P0(x) {
-	RETURN x ^ ROL32(x, 9) ^ ROL32(x, 17)
-}
-DEFINE FF(x, y, z, round) {
-	IF round &lt; 16
-		RETURN (x ^ y ^ z)
-	ELSE
-		RETURN (x &amp; y) | (x &amp; z) | (y &amp; z)
-	FI
-}
-DEFINE GG(x, y, z, round){
-	IF round &lt; 16
-		RETURN (x ^ y ^ z)
-	ELSE
-		RETURN (x &amp; y) | (~x &amp; z)
-	FI
-}
-A.dword[0] := __B.dword[3]
-B.dword[0] := __B.dword[2]
-C.dword[0] := __A.dword[3]
-D.dword[0] := __A.dword[2]
-E.dword[0] := __B.dword[1]
-F.dword[0] := __B.dword[0]
-G.dword[0] := __A.dword[1]
-H.dword[0] := __A.dword[0]
-W.dword[0] := __C.dword[0]
-W.dword[1] := __C.dword[1]
-W.dword[4] := __C.dword[2]
-W.dword[5] := __C.dword[3]
-C.dword[0] := ROL32(C.dword[0], 9)
-D.dword[0] := ROL32(D.dword[0], 9)
-G.dword[0] := ROL32(G.dword[0], 19)
-H.dword[0] := ROL32(H.dword[0], 19)
-ROUND := imm8 &amp; 0x3E
-IF ROUND &lt; 16
-	CONST.dword[0] := 0x79CC4519
-ELSE
-	CONST.dword[0] := 0x7A879D8A
-FI
-CONST.dword[0] := ROL32(CONST.dword[0], ROUND)
-FOR i:= 0 to 1
-	temp.dword[0] := ROL32(A.dword[i], 12) + E.dword[i] + CONST.dword[0]
-	S1.dword[0] := ROL32(temp.dword[0], 7)
-	S2.dword[0] := S1.dword[0] ^ ROL32(A.dword[i], 12)
-	T1.dword[0] := FF(A.dword[i], B.dword[i], C.dword[i], ROUND) + D.dword[i] + S2.dword[0] + (W.dword[i] ^ W.dword[i+4])
-	T2.dword[0] := GG(E.dword[i], F.dword[i], G.dword[i], ROUND) + H.dword[i] + S1.dword[0] + W.dword[i]
-	D.dword[i+1] := C.dword[i]
-	C.dword[i+1] := ROL32(B.dword[i], 9)
-	B.dword[i+1] := A.dword[i]
-	A.dword[i+1] := T1.dword[0]
-	H.dword[i+1] := G.dword[i]
-	G.dword[i+1] := ROL32(F.dword[i], 19)
-	F.dword[i+1] := E.dword[i]
-	E.dword[i+1] := P0(T2.dword[0])
-	CONST.dword[0] := ROL32(CONST.dword[0], 1)
-ENDFOR
-dst.dword[3] := A.dword[2]
-dst.dword[2] := B.dword[2]
-dst.dword[1] := E.dword[2]
-dst.dword[0] := F.dword[2]
-</operation>
-    <parameter etype="UI32" type="__m128i" varname="__A" />
-    <parameter etype="UI32" type="__m128i" varname="__B" />
-    <parameter etype="UI32" type="__m128i" varname="__C" />
-    <parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-  <CPUID>SM3</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-<intrinsic name="_mm256_sm4key4_epi32" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="UI32" />
-    <description>This intrinsic performs four rounds of SM4 key expansion. The intrinsic operates on independent 128-bit lanes. The calculated results are stored in "dst". </description>
-    <instruction name="VSM4KEY4" form="ymm, ymm, ymm" xed="VSM4KEY4_YMMu32_YMMu32_YMMu32" />
-    <operation>
-BYTE sbox[256] = {
-0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
-0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
-0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
-0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
-0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
-0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
-0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
-0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
-0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
-0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
-0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
-0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
-0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
-0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
-0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
-0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
-}
-DEFINE ROL32(dword, n) {
-	count := n % 32
-	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
-	RETURN dest
-}
-DEFINE SBOX_BYTE(dword, i) {
-	RETURN sbox[dword.byte[i]]
-}
-DEFINE lower_t(dword) {
-	tmp.byte[0] := SBOX_BYTE(dword, 0)
-	tmp.byte[1] := SBOX_BYTE(dword, 1)
-	tmp.byte[2] := SBOX_BYTE(dword, 2)
-	tmp.byte[3] := SBOX_BYTE(dword, 3)
-	RETURN tmp
-}
-DEFINE L_KEY(dword) {
-	RETURN dword ^ ROL32(dword, 13) ^ ROL32(dword, 23)
-}
-DEFINE T_KEY(dword) {
-	RETURN L_KEY(lower_t(dword))
-}
-DEFINE F_KEY(X0, X1, X2, X3, round_key) {
-	RETURN X0 ^ T_KEY(X1 ^ X2 ^ X3 ^ round_key)
-}
-FOR i:= 0 to 1
-	P.dword[0] := __A.dword[4*i]
-	P.dword[1] := __A.dword[4*i+1]
-	P.dword[2] := __A.dword[4*i+2]
-	P.dword[3] := __A.dword[4*i+3]
-	C.dword[0] := F_KEY(P.dword[0], P.dword[1], P.dword[2], P.dword[3], __B.dword[4*i])
-	C.dword[1] := F_KEY(P.dword[1], P.dword[2], P.dword[3], C.dword[0], __B.dword[4*i+1])
-	C.dword[2] := F_KEY(P.dword[2], P.dword[3], C.dword[0], C.dword[1], __B.dword[4*i+2])
-	C.dword[3] := F_KEY(P.dword[3], C.dword[0], C.dword[1], C.dword[2], __B.dword[4*i+3])
-	dst.dword[4*i] := C.dword[0]
-	dst.dword[4*i+1] := C.dword[1]
-	dst.dword[4*i+2] := C.dword[2]
-	dst.dword[4*i+3] := C.dword[3]
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-    <parameter type="__m256i" varname="__A" etype="UI32" />
-    <parameter type="__m256i" varname="__B" etype="UI32" />
-  <CPUID>SM4</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-  <intrinsic name="_mm256_sm4rnds4_epi32" tech="AVX_ALL">
-    <return type="__m256i" varname="dst" etype="UI32" />
-    <description>This intrinisc performs four rounds of SM4 encryption. The intrinisc operates on independent 128-bit lanes. The calculated results are stored in "dst". </description>
-    <instruction name="VSM4RNDS4" form="ymm, ymm, ymm" xed="VSM4RNDS4_YMMu32_YMMu32_YMMu32" />
-    <operation>BYTE sbox[256] = {
-0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
-0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
-0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
-0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
-0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
-0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
-0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
-0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
-0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
-0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
-0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
-0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
-0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
-0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
-0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
-0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
-}
-DEFINE ROL32(dword, n) {
-	count := n % 32
-	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
-	RETURN dest
-}
-DEFINE SBOX_BYTE(dword, i) {
-	RETURN sbox[dword.byte[i]]
-}
-DEFINE lower_t(dword) {
-	tmp.byte[0] := SBOX_BYTE(dword, 0)
-	tmp.byte[1] := SBOX_BYTE(dword, 1)
-	tmp.byte[2] := SBOX_BYTE(dword, 2)
-	tmp.byte[3] := SBOX_BYTE(dword, 3)
-	RETURN tmp
-}
-DEFINE L_RND(dword) {
-	tmp := dword
-	tmp := tmp ^ ROL32(dword, 2)
-	tmp := tmp ^ ROL32(dword, 10)
-	tmp := tmp ^ ROL32(dword, 18)
-	tmp := tmp ^ ROL32(dword, 24)
-	RETURN tmp
-}
-DEFINE T_RND(dword) {
-	RETURN L_RND(lower_t(dword))
-}
-DEFINE F_RND(X0, X1, X2, X3, round_key) {
-	RETURN X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key)
-}
-FOR i:= 0 to 1
-	P.dword[0] := __A.dword[4*i]
-	P.dword[1] := __A.dword[4*i+1]
-	P.dword[2] := __A.dword[4*i+2]
-	P.dword[3] := __A.dword[4*i+3]
-	C.dword[0] := F_RND(P.dword[0], P.dword[1], P.dword[2], P.dword[3], __B.dword[4*i])
-	C.dword[1] := F_RND(P.dword[1], P.dword[2], P.dword[3], C.dword[0], __B.dword[4*i+1])
-	C.dword[2] := F_RND(P.dword[2], P.dword[3], C.dword[0], C.dword[1], __B.dword[4*i+2])
-	C.dword[3] := F_RND(P.dword[3], C.dword[0], C.dword[1], C.dword[2], __B.dword[4*i+3])
-	dst.dword[4*i] := C.dword[0]
-	dst.dword[4*i+1] := C.dword[1]
-	dst.dword[4*i+2] := C.dword[2]
-	dst.dword[4*i+3] := C.dword[3]
-ENDFOR
-dst[MAX:256] := 0
-</operation>
-    <parameter type="__m256i" varname="__A" etype="UI32" />
-    <parameter type="__m256i" varname="__B" etype="UI32" />
-  <CPUID>SM4</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-  <intrinsic name="_mm_sm4key4_epi32" tech="AVX_ALL">
-    <return type="__m128i" varname="dst" etype="UI32" />
-    <description>This intrinsic performs four rounds of SM4 key expansion. The intrinsic operates on independent 128-bit lanes. The calculated results are stored in "dst". </description>
-    <instruction name="VSM4KEY4" form="xmm, xmm, xmm" xed="VSM4KEY4_XMMu32_XMMu32_XMMu32" />
-    <operation>
-BYTE sbox[256] = {
-0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
-0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
-0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
-0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
-0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
-0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
-0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
-0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
-0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
-0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
-0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
-0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
-0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
-0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
-0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
-0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
-}
-DEFINE ROL32(dword, n) {
-	count := n % 32
-	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
-	RETURN dest
-}
-DEFINE SBOX_BYTE(dword, i) {
-	RETURN sbox[dword.byte[i]]
-}
-DEFINE lower_t(dword) {
-	tmp.byte[0] := SBOX_BYTE(dword, 0)
-	tmp.byte[1] := SBOX_BYTE(dword, 1)
-	tmp.byte[2] := SBOX_BYTE(dword, 2)
-	tmp.byte[3] := SBOX_BYTE(dword, 3)
-	RETURN tmp
-}
-DEFINE L_KEY(dword) {
-	RETURN dword ^ ROL32(dword, 13) ^ ROL32(dword, 23)
-}
-DEFINE T_KEY(dword) {
-	RETURN L_KEY(lower_t(dword))
-}
-DEFINE F_KEY(X0, X1, X2, X3, round_key) {
-	RETURN X0 ^ T_KEY(X1 ^ X2 ^ X3 ^ round_key)
-}
-P.dword[0] := __A.dword[0]
-P.dword[1] := __A.dword[1]
-P.dword[2] := __A.dword[2]
-P.dword[3] := __A.dword[3]
-C.dword[0] := F_KEY(P.dword[0], P.dword[1], P.dword[2], P.dword[3], __B.dword[0])
-C.dword[1] := F_KEY(P.dword[1], P.dword[2], P.dword[3], C.dword[0], __B.dword[1])
-C.dword[2] := F_KEY(P.dword[2], P.dword[3], C.dword[0], C.dword[1], __B.dword[2])
-C.dword[3] := F_KEY(P.dword[3], C.dword[0], C.dword[1], C.dword[2], __B.dword[3])
-dst.dword[0] := C.dword[0]
-dst.dword[1] := C.dword[1]
-dst.dword[2] := C.dword[2]
-dst.dword[3] := C.dword[3]
-dst[MAX:128] := 0
-</operation>
-    <parameter type="__m128i" varname="__A" etype="UI32" />
-    <parameter type="__m128i" varname="__B" etype="UI32" />
-  <CPUID>SM4</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-  <intrinsic name="_mm_sm4rnds4_epi32" tech="AVX_ALL">
-    <return type="__m128i" varname="dst" etype="UI32" />
-    <description>This intrinisc performs four rounds of SM4 encryption. The intrinisc operates on independent 128-bit lanes. The calculated results are stored in "dst". </description>
-    <instruction name="VSM4RNDS4" form="xmm, xmm, xmm" xed="VSM4RNDS4_XMMu32_XMMu32_XMMu32" />
-    <operation>
-BYTE sbox[256] = {
-0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05,
-0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
-0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
-0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6,
-0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8,
-0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
-0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87,
-0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E,
-0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
-0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3,
-0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F,
-0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
-0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,
-0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0,
-0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
-0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48
-}
-DEFINE ROL32(dword, n) {
-	count := n % 32
-	dest := (dword &lt;&lt; count) | (dword &gt;&gt; (32-count))
-	RETURN dest
-}
-DEFINE SBOX_BYTE(dword, i) {
-	RETURN sbox[dword.byte[i]]
-}
-DEFINE lower_t(dword) {
-	tmp.byte[0] := SBOX_BYTE(dword, 0)
-	tmp.byte[1] := SBOX_BYTE(dword, 1)
-	tmp.byte[2] := SBOX_BYTE(dword, 2)
-	tmp.byte[3] := SBOX_BYTE(dword, 3)
-	RETURN tmp
-}
-DEFINE L_RND(dword) {
-	tmp := dword
-	tmp := tmp ^ ROL32(dword, 2)
-	tmp := tmp ^ ROL32(dword, 10)
-	tmp := tmp ^ ROL32(dword, 18)
-	tmp := tmp ^ ROL32(dword, 24)
-	RETURN tmp
-}
-DEFINE T_RND(dword) {
-	RETURN L_RND(lower_t(dword))
-}
-DEFINE F_RND(X0, X1, X2, X3, round_key) {
-	RETURN X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key)
-}
-P.dword[0] := __A.dword[0]
-P.dword[1] := __A.dword[1]
-P.dword[2] := __A.dword[2]
-P.dword[3] := __A.dword[3]
-C.dword[0] := F_RND(P.dword[0], P.dword[1], P.dword[2], P.dword[3], __B.dword[0])
-C.dword[1] := F_RND(P.dword[1], P.dword[2], P.dword[3], C.dword[0], __B.dword[1])
-C.dword[2] := F_RND(P.dword[2], P.dword[3], C.dword[0], C.dword[1], __B.dword[2])
-C.dword[3] := F_RND(P.dword[3], C.dword[0], C.dword[1], C.dword[2], __B.dword[3])
-dst.dword[0] := C.dword[0]
-dst.dword[1] := C.dword[1]
-dst.dword[2] := C.dword[2]
-dst.dword[3] := C.dword[3]
-dst[MAX:128] := 0
-</operation>
-    <parameter type="__m128i" varname="__A" etype="UI32" />
-    <parameter type="__m128i" varname="__B" etype="UI32" />
-  <CPUID>SM4</CPUID>
-  <CPUID>AVX</CPUID>
-	<header>immintrin.h</header>
-  <category>Cryptography</category>
-  </intrinsic>
-<intrinsic name="_mm_acos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ACOS(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_acos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ACOS(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_acosh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ACOSH(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_acosh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ACOSH(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_asin_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ASIN(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_asin_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ASIN(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_asinh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ASINH(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_asinh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ASINH(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_atan_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ATAN(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_atan_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ATAN(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_atan2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_atan2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_atanh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ATANH(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_atanh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ATANH(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_cos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := COS(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_cos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := COS(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_cosd_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := COSD(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_cosd_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := COSD(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_cosh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := COSH(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_cosh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := COSH(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_hypot_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0))
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_hypot_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0))
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_sin_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SIN(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_sin_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SIN(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_sincos_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="128" type="__m128d *" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SIN(a[i+63:i])
-	MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_sincos_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="128" type="__m128 *" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SIN(a[i+31:i])
-	MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_sind_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SIND(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_sind_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SIND(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_sinh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SINH(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_sinh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SINH(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_tan_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := TAN(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_tan_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := TAN(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_tand_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := TAND(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_tand_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := TAND(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_tanh_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := TANH(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_tanh_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := TANH(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Trigonometry</category>
-	</intrinsic>
-	<intrinsic name="_mm_cbrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := CubeRoot(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_cbrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := CubeRoot(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_cexp_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
-	<operation>
-DEFINE CEXP(a[31:0], b[31:0]) {
-	result[31:0]  := POW(FP32(e), a[31:0]) * COS(b[31:0])
-	result[63:32] := POW(FP32(e), a[31:0]) * SIN(b[31:0])
-	RETURN result
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := CEXP(a[i+31:i], a[i+63:i+32])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_clog_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the natural logarithm of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
-	<operation>
-DEFINE CLOG(a[31:0], b[31:0]) {
-	result[31:0]  := LOG(SQRT(POW(a, 2.0) + POW(b, 2.0)))
-	result[63:32] := ATAN2(b, a)
-	RETURN result
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := CLOG(a[i+31:i], a[i+63:i+32])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_csqrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the square root of packed complex snumbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]".</description>
-	<operation>
-DEFINE CSQRT(a[31:0], b[31:0]) {
-	sign[31:0] := (b &lt; 0.0) ? -FP32(1.0) : FP32(1.0)
-	result[31:0]  := SQRT((a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
-	result[63:32] := sign * SQRT((-a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0)
-	RETURN result
-}
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := CSQRT(a[i+31:i], a[i+63:i+32])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_exp_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := POW(e, a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_exp_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := POW(FP32(e), a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_exp10_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := POW(10.0, a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_exp10_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := POW(FP32(10.0), a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_exp2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := POW(2.0, a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_exp2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := POW(FP32(2.0), a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_expm1_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := POW(e, a[i+63:i]) - 1.0
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_expm1_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_invcbrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := InvCubeRoot(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_invcbrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := InvCubeRoot(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_invsqrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := InvSQRT(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_invsqrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := InvSQRT(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_log_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_log_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_log10_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_log10_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_log1p_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := LOG(1.0 + a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_log1p_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := LOG(1.0 + a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_log2_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_log2_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0)
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_logb_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ConvertExpFP64(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_logb_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element.</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ConvertExpFP32(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_pow_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := POW(a[i+63:i], b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_pow_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := POW(a[i+31:i], b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_svml_sqrt_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SQRT(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_svml_sqrt_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SQRT(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_cdfnorm_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := CDFNormal(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_cdfnorm_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := CDFNormal(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_cdfnorminv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := InverseCDFNormal(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_cdfnorminv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := InverseCDFNormal(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_erf_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ERF(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_erfc_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := 1.0 - ERF(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_erfc_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+63:i] := 1.0 - ERF(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_erfcinv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i]))
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_erfcinv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i]))
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_erfinv_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := 1.0 / ERF(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_erfinv_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+63:i] := 1.0 / ERF(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_epi8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 8*j
-	IF b[i+7:i] == 0
-		#DE
-	FI
-	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_epi16" sequence="TRUE" tech="SVML">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	IF b[i+15:i] == 0
-		#DE
-	FI
-	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_epi32" sequence="TRUE" tech="SVML">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF b[i+31:i] == 0
-		#DE
-	FI
-	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_epi64" sequence="TRUE" tech="SVML">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	IF b[i+63:i] == 0
-		#DE
-	FI
-	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_epu8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := 8*j
-	IF b[i+7:i] == 0
-		#DE
-	FI
-	dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_epu16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := 16*j
-	IF b[i+15:i] == 0
-		#DE
-	FI
-	dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_epu32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	IF b[i+31:i] == 0
-		#DE
-	FI
-	dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_epu64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	IF b[i+63:i] == 0
-		#DE
-	FI
-	dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_erf_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ERF(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_idiv_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_idivrem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" memwidth="128" type="__m128i *" varname="mem_addr" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr".</description>
-	<operation>FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
-	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_irem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rem_epi8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := 8*j
-	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rem_epi16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 16*j
-	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rem_epi64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := 64*j
-	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rem_epu8" sequence="TRUE" tech="SVML">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 15
-	i := 8*j
-	dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rem_epu16" sequence="TRUE" tech="SVML">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 7
-	i := 16*j
-	dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rem_epu32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_rem_epu64" sequence="TRUE" tech="SVML">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := 64*j
-	dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_udiv_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_udivrem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" memwidth="128" type="__m128i *" varname="mem_addr" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr".</description>
-	<operation>FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i])
-	MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_urem_epi32" sequence="TRUE" tech="SVML">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_svml_ceil_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := CEIL(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_svml_ceil_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := CEIL(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_svml_floor_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := FLOOR(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_svml_floor_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := FLOOR(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_svml_round_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ROUND(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_svml_round_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ROUND(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_trunc_pd" sequence="TRUE" tech="SVML">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction.</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := TRUNCATE(a[i+63:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_trunc_ps" sequence="TRUE" tech="SVML">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction.</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := TRUNCATE(a[i+31:i])
-ENDFOR
-dst[MAX:128] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_MM_TRANSPOSE4_PS" sequence="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" type="__m128" varname="row0" />
-	<parameter etype="FP32" type="__m128" varname="row1" />
-	<parameter etype="FP32" type="__m128" varname="row2" />
-	<parameter etype="FP32" type="__m128" varname="row3" />
-	<description>Macro: Transpose the 4x4 matrix formed by the 4 rows of single-precision (32-bit) floating-point elements in "row0", "row1", "row2", and "row3", and store the transposed matrix in these vectors ("row0" now contains column 0, etc.).</description>
-	<operation>
-__m128 tmp3, tmp2, tmp1, tmp0;
-tmp0 := _mm_unpacklo_ps(row0, row1);
-tmp2 := _mm_unpacklo_ps(row2, row3);
-tmp1 := _mm_unpackhi_ps(row0, row1);
-tmp3 := _mm_unpackhi_ps(row2, row3);
-row0 := _mm_movelh_ps(tmp0, tmp2);
-row1 := _mm_movehl_ps(tmp2, tmp0);
-row2 := _mm_movelh_ps(tmp1, tmp3);
-row3 := _mm_movehl_ps(tmp3, tmp1);
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_extract_pi16" tech="SSE_ALL">
-	<return etype="UI16" type="int" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".</description>
-	<operation>
-dst[15:0] := (a[63:0] &gt;&gt; (imm8[1:0] * 16))[15:0]
-dst[31:16] := 0
-	</operation>
-	<instruction form="r32, mm, imm8" name="PEXTRW" xed="PEXTRW_GPR32_MMXq_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_pextrw" tech="SSE_ALL">
-	<return etype="UI16" type="int" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".</description>
-	<operation>
-dst[15:0] := (a[63:0] &gt;&gt; (imm8[1:0] * 16))[15:0]
-dst[31:16] := 0
-	</operation>
-	<instruction form="r32, mm, imm8" name="PEXTRW" xed="PEXTRW_GPR32_MMXq_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_insert_pi16" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="int" varname="i" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[63:0] := a[63:0]
-sel := imm8[1:0]*16
-dst[sel+15:sel] := i[15:0]
-	</operation>
-	<instruction form="mm, r32, imm8" name="PINSRW" xed="PINSRW_MMXq_GPR32_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_pinsrw" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="int" varname="i" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[63:0] := a[63:0]
-sel := imm8[1:0]*16
-dst[sel+15:sel] := i[15:0]
-	</operation>
-	<instruction form="mm, r32, imm8" name="PINSRW" xed="PINSRW_MMXq_GPR32_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_shuffle_pi16" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[15:0] := src[15:0]
-	1:	tmp[15:0] := src[31:16]
-	2:	tmp[15:0] := src[47:32]
-	3:	tmp[15:0] := src[63:48]
-	ESAC
-	RETURN tmp[15:0]
-}
-dst[15:0] := SELECT4(a[63:0], imm8[1:0])
-dst[31:16] := SELECT4(a[63:0], imm8[3:2])
-dst[47:32] := SELECT4(a[63:0], imm8[5:4])
-dst[63:48] := SELECT4(a[63:0], imm8[7:6])
-	</operation>
-	<instruction form="mm, mm, imm8" name="PSHUFW" xed="PSHUFW_MMXq_MMXq_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_m_pshufw" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[15:0] := src[15:0]
-	1:	tmp[15:0] := src[31:16]
-	2:	tmp[15:0] := src[47:32]
-	3:	tmp[15:0] := src[63:48]
-	ESAC
-	RETURN tmp[15:0]
-}
-dst[15:0] := SELECT4(a[63:0], imm8[1:0])
-dst[31:16] := SELECT4(a[63:0], imm8[3:2])
-dst[47:32] := SELECT4(a[63:0], imm8[5:4])
-dst[63:48] := SELECT4(a[63:0], imm8[7:6])
-	</operation>
-	<instruction form="mm, mm, imm8" name="PSHUFW" xed="PSHUFW_MMXq_MMXq_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_shuffle_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="unsigned int" varname="imm8" />
-	<description>Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(b[127:0], imm8[5:4])
-dst[127:96] := SELECT4(b[127:0], imm8[7:6])
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="SHUFPS" xed="SHUFPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the high half "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="UNPCKHPS" xed="UNPCKHPS_XMMps_XMMdq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="UNPCKLPS" xed="UNPCKLPS_XMMps_XMMq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_getcsr" tech="SSE_ALL">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter type="void" />
-	<description>Get the unsigned 32-bit value of the MXCSR control and status register.</description>
-	<operation>dst[31:0] := MXCSR
-	</operation>
-	<instruction form="m32" name="STMXCSR" xed="STMXCSR_MEMd" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_setcsr" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Set the MXCSR control and status register with the value in unsigned 32-bit integer "a".</description>
-	<operation>
-MXCSR := a[31:0]
-	</operation>
-	<instruction form="m32" name="LDMXCSR" xed="LDMXCSR_MEMd" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_MM_GET_EXCEPTION_STATE" tech="SSE_ALL">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<description>Macro: Get the exception state bits from the MXCSR control and status register. The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT</description>
-	<operation>dst[31:0] := MXCSR &amp; _MM_EXCEPT_MASK
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_MM_SET_EXCEPTION_STATE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Macro: Set the exception state bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT</description>
-	<operation>MXCSR := a[31:0] AND ~_MM_EXCEPT_MASK
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_MM_GET_EXCEPTION_MASK" tech="SSE_ALL">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<description>Macro: Get the exception mask bits from the MXCSR control and status register. The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT</description>
-	<operation>dst[31:0] := MXCSR &amp; _MM_MASK_MASK
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_MM_SET_EXCEPTION_MASK" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Macro: Set the exception mask bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT</description>
-	<operation>MXCSR := a[31:0] AND ~_MM_MASK_MASK
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_MM_GET_ROUNDING_MODE" tech="SSE_ALL">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<description>Macro: Get the rounding mode bits from the MXCSR control and status register. The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO</description>
-	<operation>dst[31:0] := MXCSR &amp; _MM_ROUND_MASK
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_MM_SET_ROUNDING_MODE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO</description>
-	<operation>MXCSR := a[31:0] AND ~_MM_ROUND_MASK
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_MM_GET_FLUSH_ZERO_MODE" tech="SSE_ALL">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<description>Macro: Get the flush zero bits from the MXCSR control and status register. The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF</description>
-	<operation>dst[31:0] := MXCSR &amp; _MM_FLUSH_MASK
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_MM_SET_FLUSH_ZERO_MODE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Macro: Set the flush zero bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF</description>
-	<operation>MXCSR := a[31:0] AND ~_MM_FLUSH_MASK
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_prefetch" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI8" type="char const*" varname="p" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="i" />
-	<description>Fetch the line of data from memory that contains address "p" to a location in the cache hierarchy specified by the locality hint "i", which can be one of:&lt;ul&gt;
-    &lt;li&gt;_MM_HINT_T0   // 3, move data using the T0 hint. The PREFETCHT0 instruction will be generated.&lt;/li&gt;
-    &lt;li&gt;_MM_HINT_T1   // 2, move data using the T1 hint. The PREFETCHT1 instruction will be generated.&lt;/li&gt;
-    &lt;li&gt;_MM_HINT_T2   // 1, move data using the T2 hint. The PREFETCHT2 instruction will be generated.&lt;/li&gt;
-    &lt;li&gt;_MM_HINT_NTA  // 0, move data using the non-temporal access (NTA) hint. The PREFETCHNTA instruction will be generated.&lt;/li&gt;
-</description>
-	<instruction form="m8" name="PREFETCHNTA" xed="PREFETCHNTA_MEMmprefetch" />
-	<instruction form="m8" name="PREFETCHT0" xed="PREFETCHT0_MEMmprefetch" />
-	<instruction form="m8" name="PREFETCHT1" xed="PREFETCHT1_MEMmprefetch" />
-	<instruction form="m8" name="PREFETCHT2" xed="PREFETCHT2_MEMmprefetch" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_sfence" tech="SSE_ALL">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Perform a serializing operation on all store-to-memory instructions that were issued prior to this instruction. Guarantees that every store instruction that precedes, in program order, is globally visible before any store instruction which follows the fence in program order.</description>
-	<instruction name="SFENCE" xed="SFENCE" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_malloc" tech="SSE_ALL">
-	<return type="void*" />
-	<parameter etype="UI64" type="size_t" varname="size" />
-	<parameter etype="UI64" type="size_t" varname="align" />
-	<description>Allocate "size" bytes of memory, aligned to the alignment specified in "align", and return a pointer to the allocated memory. "_mm_free" should be used to free memory that is allocated with "_mm_malloc".</description>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_free" tech="SSE_ALL">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<description>Free aligned memory that was allocated with "_mm_malloc".</description>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_undefined_ps" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m128 with undefined elements.</description>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_pi16" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMAXSW" xed="PMAXSW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_m_pmaxsw" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMAXSW" xed="PMAXSW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_pu8" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMAXUB" xed="PMAXUB_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_m_pmaxub" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMAXUB" xed="PMAXUB_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_pi16" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMINSW" xed="PMINSW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_m_pminsw" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMINSW" xed="PMINSW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_pu8" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMINUB" xed="PMINUB_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_m_pminub" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMINUB" xed="PMINUB_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper element of "dst". [min_float_note]</description>
-	<operation>
-dst[31:0] := MIN(a[31:0], b[31:0])
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="MINSS" xed="MINSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="MINPS" xed="MINPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper element of "dst". [max_float_note]</description>
-	<operation>
-dst[31:0] := MAX(a[31:0], b[31:0])
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="MAXSS" xed="MAXSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="MAXPS" xed="MAXPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_mulhi_pu16" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	tmp[31:0] := a[i+15:i] * b[i+15:i]
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMULHUW" xed="PMULHUW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_pmulhuw" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	tmp[31:0] := a[i+15:i] * b[i+15:i]
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMULHUW" xed="PMULHUW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sad_pu8" tech="SSE_ALL">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
-ENDFOR
-dst[15:0] := tmp[7:0] + tmp[15:8] + tmp[23:16] + tmp[31:24] + tmp[39:32] + tmp[47:40] + tmp[55:48] + tmp[63:56]
-dst[63:16] := 0
-	</operation>
-	<instruction form="mm, mm" name="PSADBW" xed="PSADBW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_m_psadbw" tech="SSE_ALL">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
-ENDFOR
-dst[15:0] := tmp[7:0] + tmp[15:8] + tmp[23:16] + tmp[31:24] + tmp[39:32] + tmp[47:40] + tmp[55:48] + tmp[63:56]
-dst[63:16] := 0
-	</operation>
-	<instruction form="mm, mm" name="PSADBW" xed="PSADBW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] + b[31:0]
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="ADDSS" xed="ADDSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ADDPS" xed="ADDPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] - b[31:0]
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="SUBSS" xed="SUBSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="SUBPS" xed="SUBPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] * b[31:0]
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="MULSS" xed="MULSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] * b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="MULPS" xed="MULPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] / b[31:0]
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="DIVSS" xed="DIVSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := a[i+31:i] / b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="DIVPS" xed="DIVPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_avg_pu8" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PAVGB" xed="PAVGB_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_m_pavgb" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PAVGB" xed="PAVGB_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_avg_pu16" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PAVGW" xed="PAVGW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_m_pavgw" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<parameter etype="UI16" type="__m64" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PAVGW" xed="PAVGW_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi32_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, r32" name="CVTSI2SS" xed="CVTSI2SS_XMMss_GPR32d" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_si2ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<description>Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, r32" name="CVTSI2SS" xed="CVTSI2SS_XMMss_GPR32d" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi64_ss" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<description>Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int64_To_FP32(b[63:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, r64" name="CVTSI2SS" xed="CVTSI2SS_XMMss_GPR64q" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpi32_ps" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Convert packed 32-bit integers in "b" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", and copy the upper 2 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[63:32] := Convert_Int32_To_FP32(b[63:32])
-dst[95:64] := a[95:64]
-dst[127:96] := a[127:96]
-	</operation>
-	<instruction form="xmm, mm" name="CVTPI2PS" xed="CVTPI2PS_XMMq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_pi2ps" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Convert packed signed 32-bit integers in "b" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", and copy the upper 2 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(b[31:0])
-dst[63:32] := Convert_Int32_To_FP32(b[63:32])
-dst[95:64] := a[95:64]
-dst[127:96] := a[127:96]
-	</operation>
-	<instruction form="xmm, mm" name="CVTPI2PS" xed="CVTPI2PS_XMMq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpi16_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<description>Convert packed 16-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	m := j*32
-	dst[m+31:m] := Convert_Int16_To_FP32(a[i+15:i])
-ENDFOR
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpu16_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="UI16" type="__m64" varname="a" />
-	<description>Convert packed unsigned 16-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	m := j*32
-	dst[m+31:m] := Convert_Int16_To_FP32(a[i+15:i])
-ENDFOR
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpi8_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="SI8" type="__m64" varname="a" />
-	<description>Convert the lower packed 8-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*8
-	m := j*32
-	dst[m+31:m] := Convert_Int8_To_FP32(a[i+7:i])
-ENDFOR
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpu8_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<description>Convert the lower packed unsigned 8-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*8
-	m := j*32
-	dst[m+31:m] := Convert_Int8_To_FP32(a[i+7:i])
-ENDFOR
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpi32x2_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", then covert the packed signed 32-bit integers in "b" to single-precision (32-bit) floating-point element, and store the results in the upper 2 elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_Int32_To_FP32(a[31:0])
-dst[63:32] := Convert_Int32_To_FP32(a[63:32])
-dst[95:64] := Convert_Int32_To_FP32(b[31:0])
-dst[127:96] := Convert_Int32_To_FP32(b[63:32])
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_si32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32(a[31:0])
-	</operation>
-	<instruction form="r32, xmm" name="CVTSS2SI" xed="CVTSS2SI_GPR32d_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_ss2si" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32(a[31:0])
-	</operation>
-	<instruction form="r32, xmm" name="CVTSS2SI" xed="CVTSS2SI_GPR32d_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_si64" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_Int64(a[31:0])
-	</operation>
-	<instruction form="r64, xmm" name="CVTSS2SI" xed="CVTSS2SI_GPR64q_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_f32" tech="SSE_ALL">
-	<return etype="FP32" type="float" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Copy the lower single-precision (32-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-	</operation>
-	<instruction form="m32, xmm" name="MOVSS" xed="MOVSS_MEMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_pi32" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, xmm" name="CVTPS2PI" xed="CVTPS2PI_MMXq_XMMq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvt_ps2pi" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, xmm" name="CVTPS2PI" xed="CVTPS2PI_MMXq_XMMq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttss_si32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
-	</operation>
-	<instruction form="r32, xmm" name="CVTTSS2SI" xed="CVTTSS2SI_GPR32d_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_ss2si" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0])
-	</operation>
-	<instruction form="r32, xmm" name="CVTTSS2SI" xed="CVTTSS2SI_GPR32d_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttss_si64" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0])
-	</operation>
-	<instruction form="r64, xmm" name="CVTTSS2SI" xed="CVTTSS2SI_GPR64q_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttps_pi32" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, xmm" name="CVTTPS2PI" xed="CVTTPS2PI_MMXq_XMMq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtt_ps2pi" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, xmm" name="CVTTPS2PI" xed="CVTTPS2PI_MMXq_XMMq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_pi16" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst". Note: this intrinsic will generate 0x7FFF, rather than 0x8000, for input values between 0x7FFF and 0x7FFFFFFF.</description>
-	<operation>
-FOR j := 0 to 3
-	i := 16*j
-	k := 32*j
-	IF a[k+31:k] &gt;= FP32(0x7FFF) &amp;&amp; a[k+31:k] &lt;= FP32(0x7FFFFFFF)
-		dst[i+15:i] := 0x7FFF
-	ELSE
-		dst[i+15:i] := Convert_FP32_To_Int16(a[k+31:k])
-	FI
-ENDFOR
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_pi8" sequence="TRUE" tech="SSE_ALL">
-	<return etype="SI8" type="__m64" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 8-bit integers, and store the results in lower 4 elements of "dst". Note: this intrinsic will generate 0x7F, rather than 0x80, for input values between 0x7F and 0x7FFFFFFF.</description>
-	<operation>
-FOR j := 0 to 3
-	i := 8*j
-	k := 32*j
-	IF a[k+31:k] &gt;= FP32(0x7F) &amp;&amp; a[k+31:k] &lt;= FP32(0x7FFFFFFF)
-		dst[i+7:i] := 0x7F
-	ELSE
-		dst[i+7:i] := Convert_FP32_To_Int8(a[k+31:k])
-	FI
-ENDFOR
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_stream_pi" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="64" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<description>Store 64-bits of integer data from "a" into memory using a non-temporal memory hint.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-	</operation>
-	<instruction form="m64, mm" name="MOVNTQ" xed="MOVNTQ_MEMq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskmove_si64" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="mask" />
-	<parameter etype="UI8" memwidth="64" type="char*" varname="mem_addr" />
-	<description>Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	IF mask[i+7]
-		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="MASKMOVQ" xed="MASKMOVQ_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_m_maskmovq" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="mask" />
-	<parameter etype="UI8" memwidth="64" type="char*" varname="mem_addr" />
-	<description>Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element).</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	IF mask[i+7]
-		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="MASKMOVQ" xed="MASKMOVQ_MMXq_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_stream_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVNTPS" xed="MOVNTPS_MEMdq_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeh_pi" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="64" type="__m64*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store the upper 2 single-precision (32-bit) floating-point elements from "a" into memory.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[95:64]
-MEM[mem_addr+63:mem_addr+32] := a[127:96]
-	</operation>
-	<instruction form="m64, xmm" name="MOVHPS" xed="MOVHPS_MEMq_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storel_pi" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="64" type="__m64*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store the lower 2 single-precision (32-bit) floating-point elements from "a" into memory.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[31:0]
-MEM[mem_addr+63:mem_addr+32] := a[63:32]
-	</operation>
-	<instruction form="m64, xmm" name="MOVLPS" xed="MOVLPS_MEMq_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="32" type="float*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store the lower single-precision (32-bit) floating-point element from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[31:0]
-	</operation>
-	<instruction form="m32, xmm" name="MOVSS" xed="MOVSS_MEMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store1_ps" sequence="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="32" type="float*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store the lower single-precision (32-bit) floating-point element from "a" into 4 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[31:0]
-MEM[mem_addr+63:mem_addr+32] := a[31:0]
-MEM[mem_addr+95:mem_addr+64] := a[31:0]
-MEM[mem_addr+127:mem_addr+96] := a[31:0]
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_ps1" sequence="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="32" type="float*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store the lower single-precision (32-bit) floating-point element from "a" into 4 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[31:0]
-MEM[mem_addr+63:mem_addr+32] := a[31:0]
-MEM[mem_addr+95:mem_addr+64] := a[31:0]
-MEM[mem_addr+127:mem_addr+96] := a[31:0]
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_ps" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="float*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory.
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVAPS" xed="MOVAPS_MEMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="float*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory.
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVUPS" xed="MOVUPS_MEMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storer_ps" sequence="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP32" memwidth="128" type="float*" varname="mem_addr" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Store 4 single-precision (32-bit) floating-point elements from "a" into memory in reverse order.
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[127:96]
-MEM[mem_addr+63:mem_addr+32] := a[95:64]
-MEM[mem_addr+95:mem_addr+64] := a[63:32]
-MEM[mem_addr+127:mem_addr+96] := a[31:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVUPS" xed="MOVUPS_MEMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_movemask_pi8" tech="SSE_ALL">
-	<return etype="UI8" type="int" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[j] := a[i+7]
-ENDFOR
-dst[MAX:8] := 0
-	</operation>
-	<instruction form="r32, mm" name="PMOVMSKB" xed="PMOVMSKB_GPR32_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_m_pmovmskb" tech="SSE_ALL">
-	<return etype="UI8" type="int" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[j] := a[i+7]
-ENDFOR
-dst[MAX:8] := 0
-	</operation>
-	<instruction form="r32, mm" name="PMOVMSKB" xed="PMOVMSKB_GPR32_MMXq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movemask_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF a[i+31]
-		dst[j] := 1
-	ELSE
-		dst[j] := 0
-	FI
-ENDFOR
-dst[MAX:4] := 0
-	</operation>
-	<instruction form="r32, xmm" name="MOVMSKPS" xed="MOVMSKPS_GPR32_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the square root of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := SQRT(a[31:0])
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="SQRTSS" xed="SQRTSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SQRT(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="SQRTPS" xed="SQRTPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rcp_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-dst[31:0] := (1.0 / a[31:0])
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="RCPSS" xed="RCPSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rcp_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (1.0 / a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="RCPPS" xed="RCPPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rsqrt_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-dst[31:0] := (1.0 / SQRT(a[31:0]))
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="RSQRTSS" xed="RSQRTSS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_rsqrt_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (1.0 / SQRT(a[i+31:i]))
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="RSQRTPS" xed="RSQRTPS_XMMps_XMMps" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_and_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (a[i+31:i] AND b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ANDPS" xed="ANDPS_XMMxud_XMMxud" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_andnot_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ANDNPS" xed="ANDNPS_XMMxud_XMMxud" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_or_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] OR b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ORPS" xed="ORPS_XMMxud_XMMxud" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_xor_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] XOR b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="XORPS" xed="XORPS_XMMxud_XMMxud" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for equality, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := ( a[31:0] == b[31:0] ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for less-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := ( a[31:0] &lt; b[31:0] ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &lt; b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := ( a[31:0] &lt;= b[31:0] ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &lt;= b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for greater-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := ( a[31:0] &gt; b[31:0] ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for greater-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := ( a[31:0] &gt;= b[31:0] ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &gt;= b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := ( a[31:0] != b[31:0] ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] != b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnlt_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := (!( a[31:0] &lt; b[31:0] )) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnlt_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := !( a[i+31:i] &lt; b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnle_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := (!( a[31:0] &lt;= b[31:0] )) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnle_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (!( a[i+31:i] &lt;= b[i+31:i] )) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpngt_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := (!( a[31:0] &gt; b[31:0] )) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpngt_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (!( a[i+31:i] &gt; b[i+31:i] )) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnge_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := (!( a[31:0] &gt;= b[31:0] )) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnge_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := (!( a[i+31:i] &gt;= b[i+31:i] )) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpord_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>dst[31:0] := ( a[31:0] != NaN AND b[31:0] != NaN ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpord_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] != NaN AND b[i+31:i] != NaN ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpunord_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>dst[31:0] := ( a[31:0] == NaN OR b[31:0] == NaN ) ? 0xFFFFFFFF : 0
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSS" xed="CMPSS_XMMss_XMMss_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpunord_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] == NaN OR b[i+31:i] == NaN ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPS" xed="CMPPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comieq_ss" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] == b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comilt_ss" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &lt; b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comile_ss" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &lt;= b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comigt_ss" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &gt; b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comige_ss" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &gt;= b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comineq_ss" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[31:0] == NaN OR b[31:0] == NaN OR a[31:0] != b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISS" xed="COMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomieq_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] == b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomilt_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &lt; b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomile_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &lt;= b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomigt_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &gt; b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomige_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[31:0] != NaN AND b[31:0] != NaN AND a[31:0] &gt;= b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomineq_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[31:0] == NaN OR b[31:0] == NaN OR a[31:0] != b[31:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISS" xed="UCOMISS_XMMss_XMMss" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_ss" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Copy single-precision (32-bit) floating-point element "a" to the lower element of "dst", and zero the upper 3 elements.</description>
-	<operation>
-dst[31:0] := a[31:0]
-dst[127:32] := 0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_ps1" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="float" varname="a" />
-	<description>Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="float" varname="e3" />
-	<parameter etype="FP32" type="float" varname="e2" />
-	<parameter etype="FP32" type="float" varname="e1" />
-	<parameter etype="FP32" type="float" varname="e0" />
-	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst[31:0] := e0
-dst[63:32] := e1
-dst[95:64] := e2
-dst[127:96] := e3
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="float" varname="e3" />
-	<parameter etype="FP32" type="float" varname="e2" />
-	<parameter etype="FP32" type="float" varname="e1" />
-	<parameter etype="FP32" type="float" varname="e0" />
-	<description>Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[31:0] := e3
-dst[63:32] := e2
-dst[95:64] := e1
-dst[127:96] := e0
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setzero_ps" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m128 with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="XORPS" xed="XORPS_XMMxud_XMMxud" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadh_pi" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" memwidth="64" type="__m64 const*" varname="mem_addr" />
-	<description>Load 2 single-precision (32-bit) floating-point elements from memory into the upper 2 elements of "dst", and copy the lower 2 elements from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[31:0] := a[31:0]
-dst[63:32] := a[63:32]
-dst[95:64] := MEM[mem_addr+31:mem_addr]
-dst[127:96] := MEM[mem_addr+63:mem_addr+32]
-	</operation>
-	<instruction form="xmm, m64" name="MOVHPS" xed="MOVHPS_XMMq_MEMq" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadl_pi" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" memwidth="64" type="__m64 const*" varname="mem_addr" />
-	<description>Load 2 single-precision (32-bit) floating-point elements from memory into the lower 2 elements of "dst", and copy the upper 2 elements from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[31:0] := MEM[mem_addr+31:mem_addr]
-dst[63:32] := MEM[mem_addr+63:mem_addr+32]
-dst[95:64] := a[95:64]
-dst[127:96] := a[127:96]
-	</operation>
-	<instruction form="xmm, m64" name="MOVLPS" xed="MOVLPS_XMMq_MEMq" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="32" type="float const*" varname="mem_addr" />
-	<description>Load a single-precision (32-bit) floating-point element from memory into the lower of "dst", and zero the upper 3 elements. "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[31:0] := MEM[mem_addr+31:mem_addr]
-dst[127:32] := 0
-	</operation>
-	<instruction form="xmm, m32" name="MOVSS" xed="MOVSS_XMMdq_MEMss" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load1_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="32" type="float const*" varname="mem_addr" />
-	<description>Load a single-precision (32-bit) floating-point element from memory into all elements of "dst".</description>
-	<operation>
-dst[31:0] := MEM[mem_addr+31:mem_addr]
-dst[63:32] := MEM[mem_addr+31:mem_addr]
-dst[95:64] := MEM[mem_addr+31:mem_addr]
-dst[127:96] := MEM[mem_addr+31:mem_addr]
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_ps1" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="32" type="float const*" varname="mem_addr" />
-	<description>Load a single-precision (32-bit) floating-point element from memory into all elements of "dst".</description>
-	<operation>
-dst[31:0] := MEM[mem_addr+31:mem_addr]
-dst[63:32] := MEM[mem_addr+31:mem_addr]
-dst[95:64] := MEM[mem_addr+31:mem_addr]
-dst[127:96] := MEM[mem_addr+31:mem_addr]
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="128" type="float const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into "dst".
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVAPS" xed="MOVAPS_XMMps_MEMps" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="128" type="float const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into "dst".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVUPS" xed="MOVUPS_XMMps_MEMps" />
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadr_ps" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" memwidth="128" type="float const*" varname="mem_addr" />
-	<description>Load 4 single-precision (32-bit) floating-point elements from memory into "dst" in reverse order. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[31:0] := MEM[mem_addr+127:mem_addr+96]
-dst[63:32] := MEM[mem_addr+95:mem_addr+64]
-dst[95:64] := MEM[mem_addr+63:mem_addr+32]
-dst[127:96] := MEM[mem_addr+31:mem_addr]
-	</operation>
-	<CPUID>SSE</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_move_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := b[31:0]
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm" name="MOVSS" xed="MOVSS_XMMss_XMMss_0F10" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_movehl_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Move the upper 2 single-precision (32-bit) floating-point elements from "b" to the lower 2 elements of "dst", and copy the upper 2 elements from "a" to the upper 2 elements of "dst".</description>
-	<operation>
-dst[31:0] := b[95:64]
-dst[63:32] := b[127:96]
-dst[95:64] := a[95:64]
-dst[127:96] := a[127:96]
-	</operation>
-	<instruction form="xmm, xmm" name="MOVHLPS" xed="MOVHLPS_XMMq_XMMq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_movelh_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Move the lower 2 single-precision (32-bit) floating-point elements from "b" to the upper 2 elements of "dst", and copy the lower 2 elements from "a" to the lower 2 elements of "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-dst[63:32] := a[63:32]
-dst[95:64] := b[31:0]
-dst[127:96] := b[63:32]
-	</operation>
-	<instruction form="xmm, xmm" name="MOVLHPS" xed="MOVLHPS_XMMq_XMMq" />
-	<CPUID>SSE</CPUID>
-	<header>xmmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_undefined_pd" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m128d with undefined elements.</description>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_undefined_si128" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m128i with undefined elements.</description>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_pause" tech="SSE_ALL">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Provide a hint to the processor that the code sequence is a spin-wait loop. This can help improve the performance and power consumption of spin-wait loops.</description>
-	<instruction name="PAUSE" xed="PAUSE" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_clflush" tech="SSE_ALL">
-	<return type="void" />
-	<parameter type="void const*" varname="p" />
-	<description>Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy.</description>
-	<instruction form="m8" name="CLFLUSH" xed="CLFLUSH_MEMmprefetch" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_lfence" tech="SSE_ALL">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Perform a serializing operation on all load-from-memory instructions that were issued prior to this instruction. Guarantees that every load instruction that precedes, in program order, is globally visible before any load instruction which follows the fence in program order.</description>
-	<instruction name="LFENCE" xed="LFENCE" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_mfence" tech="SSE_ALL">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Perform a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior to this instruction. Guarantees that every memory access that precedes, in program order, the memory fence instruction is globally visible before any memory instruction which follows the fence in program order.</description>
-	<instruction name="MFENCE" xed="MFENCE" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_si64" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" memwidth="64" type="void const*" varname="mem_addr" />
-	<description>Load unaligned 64-bit integer from memory into the first element of "dst".</description>
-	<operation>
-dst[63:0] := MEM[mem_addr+63:mem_addr]
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, m64" name="MOVQ" xed="MOVQ_XMMdq_MEMq_0F6E" />
-	<CPUID>SSE2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_si16" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" memwidth="16" type="void const*" varname="mem_addr" />
-	<description>Load unaligned 16-bit integer from memory into the first element of "dst".</description>
-	<operation>
-dst[15:0] := MEM[mem_addr+15:mem_addr]
-dst[MAX:16] := 0
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>immintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_si32" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" memwidth="32" type="void const*" varname="mem_addr" />
-	<description>Load unaligned 32-bit integer from memory into the first element of "dst".</description>
-	<operation>
-dst[31:0] := MEM[mem_addr+31:mem_addr]
-dst[MAX:32] := 0
-	</operation>
-	<instruction form="xmm, m32" name="MOVD" xed="MOVD_XMMdq_MEMd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadl_epi64" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" memwidth="64" type="__m128i const*" varname="mem_addr" />
-	<description>Load 64-bit integer from memory into the first element of "dst".</description>
-	<operation>
-dst[63:0] := MEM[mem_addr+63:mem_addr]
-dst[MAX:64] := 0
-	</operation>
-	<instruction form="xmm, m64" name="MOVQ" xed="MOVQ_XMMdq_MEMq_0F7E" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="mem_addr" />
-	<description>Load 128-bits of integer data from memory into "dst". 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVDQA" xed="MOVDQA_XMMdq_MEMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="mem_addr" />
-	<description>Load 128-bits of integer data from memory into "dst".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVDQU" xed="MOVDQU_XMMdq_MEMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="128" type="double const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into "dst".
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVAPD" xed="MOVAPD_XMMpd_MEMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load1_pd" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
-	<description>Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".</description>
-	<operation>
-dst[63:0] := MEM[mem_addr+63:mem_addr]
-dst[127:64] := MEM[mem_addr+63:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVAPD" xed="MOVAPD_XMMpd_MEMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_pd1" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
-	<description>Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".</description>
-	<operation>
-dst[63:0] := MEM[mem_addr+63:mem_addr]
-dst[127:64] := MEM[mem_addr+63:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVAPD" xed="MOVAPD_XMMpd_MEMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadr_pd" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="128" type="double const*" varname="mem_addr" />
-	<description>Load 2 double-precision (64-bit) floating-point elements from memory into "dst" in reverse order. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[63:0] := MEM[mem_addr+127:mem_addr+64]
-dst[127:64] := MEM[mem_addr+63:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVAPD" xed="MOVAPD_XMMpd_MEMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadu_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="128" type="double const*" varname="mem_addr" />
-	<description>Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into "dst".
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVUPD" xed="MOVUPD_XMMpd_MEMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_load_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
-	<description>Load a double-precision (64-bit) floating-point element from memory into the lower of "dst", and zero the upper element. "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[63:0] := MEM[mem_addr+63:mem_addr]
-dst[127:64] := 0
-	</operation>
-	<instruction form="xmm, m64" name="MOVSD" xed="MOVSD_XMM_XMMdq_MEMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadh_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
-	<description>Load a double-precision (64-bit) floating-point element from memory into the upper element of "dst", and copy the lower element from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := MEM[mem_addr+63:mem_addr]
-	</operation>
-	<instruction form="xmm, m64" name="MOVHPD" xed="MOVHPD_XMMsd_MEMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loadl_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
-	<description>Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst", and copy the upper element from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-dst[63:0] := MEM[mem_addr+63:mem_addr]
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, m64" name="MOVLPD" xed="MOVLPD_XMMsd_MEMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_si16" sequence="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI16" memwidth="16" type="void*" varname="mem_addr" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Store 16-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+15:mem_addr] := a[15:0]
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_si64" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="64" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Store 64-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-	</operation>
-	<instruction form="m64, xmm" name="MOVQ" xed="MOVQ_MEMq_XMMq_0F7E" />
-	<CPUID>SSE2</CPUID>
-	<header>immintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_si32" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="32" type="void*" varname="mem_addr" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Store 32-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[31:0]
-	</operation>
-	<instruction form="m32, xmm" name="MOVD" xed="MOVD_MEMd_XMMd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_maskmoveu_si128" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="mask" />
-	<parameter etype="UI8" memwidth="128" type="char*" varname="mem_addr" />
-	<description>Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint. "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF mask[i+7]
-		MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="MASKMOVDQU" xed="MASKMOVDQU_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="M128" memwidth="128" type="__m128i*" varname="mem_addr" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Store 128-bits of integer data from "a" into memory. 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVDQA" xed="MOVDQA_MEMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="M128" memwidth="128" type="__m128i*" varname="mem_addr" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Store 128-bits of integer data from "a" into memory.
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVDQU" xed="MOVDQU_MEMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storel_epi64" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="64" type="__m128i*" varname="mem_addr" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Store 64-bit integer from the first element of "a" into memory.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-	</operation>
-	<instruction form="m64, xmm" name="MOVQ" xed="MOVQ_MEMq_XMMq_0F7E" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_stream_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="M128" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Store 128-bits of integer data from "a" into memory using a non-temporal memory hint. 
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVNTDQ" xed="MOVNTDQ_MEMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_stream_si32" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI32" memwidth="32" type="void*" varname="mem_addr" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Store 32-bit integer "a" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address "mem_addr" is already in the cache, the cache will be updated.</description>
-	<operation>
-MEM[mem_addr+31:mem_addr] := a[31:0]
-	</operation>
-	<instruction form="m32, r32" name="MOVNTI" xed="MOVNTI_MEMd_GPR32" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_stream_si64" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="UI64" memwidth="64" type="void*" varname="mem_addr" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Store 64-bit integer "a" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address "mem_addr" is already in the cache, the cache will be updated.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-	</operation>
-	<instruction form="m64, r64" name="MOVNTI" xed="MOVNTI_MEMq_GPR64" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_stream_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="void*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint.
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVNTPD" xed="MOVNTPD_MEMdq_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store the lower double-precision (64-bit) floating-point element from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-	</operation>
-	<instruction form="m64, xmm" name="MOVSD" xed="MOVSD_XMM_MEMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store1_pd" sequence="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store the lower double-precision (64-bit) floating-point element from "a" into 2 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-MEM[mem_addr+127:mem_addr+64] := a[63:0]
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_pd1" sequence="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store the lower double-precision (64-bit) floating-point element from "a" into 2 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-MEM[mem_addr+127:mem_addr+64] := a[63:0]
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_store_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="double*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory.
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVAPD" xed="MOVAPD_MEMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeu_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="double*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory.
-	"mem_addr" does not need to be aligned on any particular boundary.</description>
-	<operation>
-MEM[mem_addr+127:mem_addr] := a[127:0]
-	</operation>
-	<instruction form="m128, xmm" name="MOVUPD" xed="MOVUPD_MEMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storer_pd" sequence="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="128" type="double*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store 2 double-precision (64-bit) floating-point elements from "a" into memory in reverse order.
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[127:64]
-MEM[mem_addr+127:mem_addr+64] := a[63:0]
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storeh_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store the upper double-precision (64-bit) floating-point element from "a" into memory.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[127:64]
-	</operation>
-	<instruction form="m64, xmm" name="MOVHPD" xed="MOVHPD_MEMq_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_storel_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return type="void" />
-	<parameter etype="FP64" memwidth="64" type="double*" varname="mem_addr" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Store the lower double-precision (64-bit) floating-point element from "a" into memory.</description>
-	<operation>
-MEM[mem_addr+63:mem_addr] := a[63:0]
-	</operation>
-	<instruction form="m64, xmm" name="MOVLPD" xed="MOVLPD_MEMq_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Store</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Add packed 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := a[i+7:i] + b[i+7:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PADDB" xed="PADDB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Add packed 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := a[i+15:i] + b[i+15:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PADDW" xed="PADDW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Add packed 32-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] + b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PADDD" xed="PADDD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_si64" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Add 64-bit integers "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := a[63:0] + b[63:0]
-	</operation>
-	<instruction form="mm, mm" name="PADDQ" xed="PADDQ_MMXq_MMXq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Add packed 64-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] + b[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PADDQ" xed="PADDQ_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_adds_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PADDSB" xed="PADDSB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_adds_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PADDSW" xed="PADDSW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_adds_epu8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] )
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PADDUSB" xed="PADDUSB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_adds_epu16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] )
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PADDUSW" xed="PADDUSW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_madd_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMADDWD" xed="PMADDWD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mulhi_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMULHW" xed="PMULHW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mulhi_epu16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	tmp[31:0] := a[i+15:i] * b[i+15:i]
-	dst[i+15:i] := tmp[31:16]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMULHUW" xed="PMULHUW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mullo_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])
-	dst[i+15:i] := tmp[15:0]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMULLW" xed="PMULLW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_su32" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI32" type="__m64" varname="a" />
-	<parameter etype="UI32" type="__m64" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from "a" and "b", and store the unsigned 64-bit result in "dst".</description>
-	<operation>
-dst[63:0] := a[31:0] * b[31:0]
-	</operation>
-	<instruction form="mm, mm" name="PMULUDQ" xed="PMULUDQ_MMXq_MMXq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_epu32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+31:i] * b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMULUDQ" xed="PMULUDQ_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sad_epu8" vexEq="TRUE" tech="SSE_ALL">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce two unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i])
-ENDFOR
-FOR j := 0 to 1
-	i := j*64
-	dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \
-	               tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56]
-	dst[i+63:i+16] := 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSADBW" xed="PSADBW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := a[i+7:i] - b[i+7:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSUBB" xed="PSUBB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := a[i+15:i] - b[i+15:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSUBW" xed="PSUBW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[i+31:i] - b[i+31:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSUBD" xed="PSUBD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_si64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<parameter etype="UI64" type="__m64" varname="b" />
-	<description>Subtract 64-bit integer "b" from 64-bit integer "a", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := a[63:0] - b[63:0]
-	</operation>
-	<instruction form="mm, mm" name="PSUBQ" xed="PSUBQ_MMXq_MMXq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] - b[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSUBQ" xed="PSUBQ_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_subs_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i])	
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSUBSB" xed="PSUBSB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_subs_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSUBSW" xed="PSUBSW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_subs_epu8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i])	
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSUBUSB" xed="PSUBUSB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_subs_epu16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i])	
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSUBUSW" xed="PSUBUSW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := a[63:0] + b[63:0]
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="ADDSD" xed="ADDSD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_add_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] + b[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ADDPD" xed="ADDPD_XMMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := a[63:0] / b[63:0]
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="DIVSD" xed="DIVSD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_div_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	dst[i+63:i] := a[i+63:i] / b[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="DIVPD" xed="DIVPD_XMMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := a[63:0] * b[63:0]
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="MULSD" xed="MULSD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] * b[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="MULPD" xed="MULPD_XMMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := a[63:0] - b[63:0]
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="SUBSD" xed="SUBSD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sub_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] - b[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="SUBPD" xed="SUBPD_XMMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_avg_epu8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) &gt;&gt; 1
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PAVGB" xed="PAVGB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_avg_epu16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) &gt;&gt; 1
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PAVGW" xed="PAVGW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Probability/Statistics</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMAXSW" xed="PMAXSW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_epu8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMAXUB" xed="PMAXUB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMINSW" xed="PMINSW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_epu8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMINUB" xed="PMINUB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [max_float_note]</description>
-	<operation>
-dst[63:0] := MAX(a[63:0], b[63:0])
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="MAXSD" xed="MAXSD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [max_float_note]</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := MAX(a[i+63:i], b[i+63:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="MAXPD" xed="MAXPD_XMMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [min_float_note]</description>
-	<operation>
-dst[63:0] := MIN(a[63:0], b[63:0])
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="MINSD" xed="MINSD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [min_float_note]</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := MIN(a[i+63:i], b[i+63:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="MINPD" xed="MINPD_XMMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_slli_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
-	</operation>
-	<instruction form="xmm, imm8" name="PSLLDQ" xed="PSLLDQ_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_bslli_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &lt;&lt; (tmp*8)
-	</operation>
-	<instruction form="xmm, imm8" name="PSLLDQ" xed="PSLLDQ_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_bsrli_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
-	</operation>
-	<instruction form="xmm, imm8" name="PSRLDQ" xed="PSRLDQ_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_slli_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, imm8" name="PSLLW" xed="PSLLW_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sll_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSLLW" xed="PSLLW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_slli_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, imm8" name="PSLLD" xed="PSLLD_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sll_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSLLD" xed="PSLLD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_slli_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, imm8" name="PSLLQ" xed="PSLLQ_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sll_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &lt;&lt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSLLQ" xed="PSLLQ_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srai_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="5" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, imm8" name="PSRAW" xed="PSRAW_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sra_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0)
-	ELSE
-		dst[i+15:i] := SignExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSRAW" xed="PSRAW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srai_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, imm8" name="PSRAD" xed="PSRAD_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_sra_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0)
-	ELSE
-		dst[i+31:i] := SignExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSRAD" xed="PSRAD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srli_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-tmp := imm8[7:0]
-IF tmp &gt; 15
-	tmp := 16
-FI
-dst[127:0] := a[127:0] &gt;&gt; (tmp*8)
-	</operation>
-	<instruction form="xmm, imm8" name="PSRLDQ" xed="PSRLDQ_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srli_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF imm8[7:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, imm8" name="PSRLW" xed="PSRLW_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srl_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="count" />
-	<description>Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF count[63:0] &gt; 15
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := ZeroExtend16(a[i+15:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSRLW" xed="PSRLW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srli_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF imm8[7:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, imm8" name="PSRLD" xed="PSRLD_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srl_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="count" />
-	<description>Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF count[63:0] &gt; 31
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := ZeroExtend32(a[i+31:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSRLD" xed="PSRLD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srli_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF imm8[7:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; imm8[7:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, imm8" name="PSRLQ" xed="PSRLQ_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_srl_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="count" />
-	<description>Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF count[63:0] &gt; 63
-		dst[i+63:i] := 0
-	ELSE
-		dst[i+63:i] := ZeroExtend64(a[i+63:i] &gt;&gt; count[63:0])
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSRLQ" xed="PSRLQ_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Shift</category>
-	</intrinsic>
-	<intrinsic name="_mm_and_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[127:0] := (a[127:0] AND b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PAND" xed="PAND_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_andnot_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<description>Compute the bitwise NOT of 128 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst".</description>
-	<operation>
-dst[127:0] := ((NOT a[127:0]) AND b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PANDN" xed="PANDN_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_or_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<description>Compute the bitwise OR of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[127:0] := (a[127:0] OR b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="POR" xed="POR_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_xor_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<description>Compute the bitwise XOR of 128 bits (representing integer data) in "a" and "b", and store the result in "dst".</description>
-	<operation>
-dst[127:0] := (a[127:0] XOR b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PXOR" xed="PXOR_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_and_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] AND b[i+63:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ANDPD" xed="ANDPD_XMMxuq_XMMxuq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_andnot_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ANDNPD" xed="ANDNPD_XMMxuq_XMMxuq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_or_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] OR b[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ORPD" xed="ORPD_XMMxuq_XMMxuq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_xor_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[i+63:i] XOR b[i+63:i]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="XORPD" xed="XORPD_XMMxuq_XMMxuq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPEQB" xed="PCMPEQB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPEQW" xed="PCMPEQW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPEQD" xed="PCMPEQD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] &gt; b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPGTB" xed="PCMPGTB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] &gt; b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPGTW" xed="PCMPGTW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &gt; b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPGTD" xed="PCMPGTD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtb instruction with the order of the operands switched.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := ( a[i+7:i] &lt; b[i+7:i] ) ? 0xFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPGTB" xed="PCMPGTB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtw instruction with the order of the operands switched.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ( a[i+15:i] &lt; b[i+15:i] ) ? 0xFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPGTW" xed="PCMPGTW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtd instruction with the order of the operands switched.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ( a[i+31:i] &lt; b[i+31:i] ) ? 0xFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPGTD" xed="PCMPGTD_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for equality, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] == b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for less-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] &lt; b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] &lt;= b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for greater-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] &gt; b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for greater-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] &gt;= b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpord_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>dst[63:0] := (a[63:0] != NaN AND b[63:0] != NaN) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpunord_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>dst[63:0] := (a[63:0] == NaN OR b[63:0] == NaN) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (a[63:0] != b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnlt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (!(a[63:0] &lt; b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnle_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (!(a[63:0] &lt;= b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpngt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (!(a[63:0] &gt; b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnge_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := (!(a[63:0] &gt;= b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPSD" xed="CMPSD_XMM_XMMsd_XMMsd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] == b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmplt_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] &lt; b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmple_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] &lt;= b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] &gt; b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpge_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] &gt;= b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpord_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpunord_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpneq_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (a[i+63:i] != b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnlt_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (!(a[i+63:i] &lt; b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnle_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (!(a[i+63:i] &lt;= b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpngt_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (!(a[i+63:i] &gt; b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpnge_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := (!(a[i+63:i] &gt;= b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="CMPPD" xed="CMPPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comieq_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] == b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comilt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &lt; b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comile_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &lt;= b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comigt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &gt; b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comige_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &gt;= b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_comineq_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1).</description>
-	<operation>RETURN ( a[63:0] == NaN OR b[63:0] == NaN OR a[63:0] != b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="COMISD" xed="COMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomieq_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] == b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomilt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &lt; b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomile_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &lt;= b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomigt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &gt; b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomige_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[63:0] != NaN AND b[63:0] != NaN AND a[63:0] &gt;= b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_ucomineq_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.</description>
-	<operation>RETURN ( a[63:0] == NaN OR b[63:0] == NaN OR a[63:0] != b[63:0] ) ? 1 : 0
-	</operation>
-	<instruction form="xmm, xmm" name="UCOMISD" xed="UCOMISD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi32_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="CVTDQ2PD" xed="CVTDQ2PD_XMMpd_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi32_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="SI32" type="int" varname="b" />
-	<description>Convert the signed 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := Convert_Int32_To_FP64(b[31:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, r32" name="CVTSI2SD" xed="CVTSI2SD_XMMsd_GPR32d" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi64_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := Convert_Int64_To_FP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, r64" name="CVTSI2SD" xed="CVTSI2SD_XMMsd_GPR64q" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi64x_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="SI64" type="__int64" varname="b" />
-	<description>Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := Convert_Int64_To_FP64(b[63:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, r64" name="CVTSI2SD" xed="CVTSI2SD_XMMsd_GPR64q" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi32_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="CVTDQ2PS" xed="CVTDQ2PS_XMMps_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpi32_pd" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<description>Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	m := j*64
-	dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, mm" name="CVTPI2PD" xed="CVTPI2PD_XMMpd_MMXq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi32_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-dst[127:32] := 0
-	</operation>
-	<instruction form="xmm, r32" name="MOVD" xed="MOVD_XMMdq_GPR32" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi64_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element.</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := 0
-	</operation>
-	<instruction form="xmm, r64" name="MOVQ" xed="MOVQ_XMMdq_GPR64" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi64x_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element.</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := 0
-	</operation>
-	<instruction form="xmm, r64" name="MOVQ" xed="MOVQ_XMMdq_GPR64" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi128_si32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Copy the lower 32-bit integer in "a" to "dst".</description>
-	<operation>
-dst[31:0] := a[31:0]
-	</operation>
-	<instruction form="r32, xmm" name="MOVD" xed="MOVD_GPR32_XMMd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi128_si64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Copy the lower 64-bit integer in "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="r64, xmm" name="MOVQ" xed="MOVQ_GPR64_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsi128_si64x" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Copy the lower 64-bit integer in "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="r64, xmm" name="MOVQ" xed="MOVQ_GPR64_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpd_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k])
-ENDFOR
-dst[127:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="CVTPD2PS" xed="CVTPD2PS_XMMps_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="CVTPS2PD" xed="CVTPS2PD_XMMpd_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpd_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="CVTPD2DQ" xed="CVTPD2DQ_XMMdq_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_si32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_Int32(a[63:0])
-	</operation>
-	<instruction form="r32, xmm" name="CVTSD2SI" xed="CVTSD2SI_GPR32d_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_si64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64(a[63:0])
-	</operation>
-	<instruction form="r64, xmm" name="CVTSD2SI" xed="CVTSD2SI_GPR64q_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_si64x" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64(a[63:0])
-	</operation>
-	<instruction form="r64, xmm" name="CVTSD2SI" xed="CVTSD2SI_GPR64q_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_FP32(b[63:0])
-dst[127:32] := a[127:32]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="CVTSD2SS" xed="CVTSD2SS_XMMss_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtsd_f64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="double" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Copy the lower double-precision (64-bit) floating-point element of "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="m64, xmm" name="MOVSD" xed="MOVSD_XMM_MEMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtss_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP32_To_FP64(b[31:0])
-dst[127:64] := a[127:64]
-dst[MAX:128] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="CVTSS2SD" xed="CVTSS2SD_XMMsd_XMMss" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttpd_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="CVTTPD2DQ" xed="CVTTPD2DQ_XMMdq_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsd_si32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0])
-	</operation>
-	<instruction form="r32, xmm" name="CVTTSD2SI" xed="CVTTSD2SI_GPR32d_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsd_si64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
-	</operation>
-	<instruction form="r64, xmm" name="CVTTSD2SI" xed="CVTTSD2SI_GPR64q_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttsd_si64x" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst".</description>
-	<operation>
-dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0])
-	</operation>
-	<instruction form="r64, xmm" name="CVTTSD2SI" xed="CVTTSD2SI_GPR64q_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtps_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="CVTPS2DQ" xed="CVTPS2DQ_XMMdq_XMMps" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttps_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="CVTTPS2DQ" xed="CVTTPS2DQ_XMMdq_XMMps" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtpd_pi32" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k])
-ENDFOR
-	</operation>
-	<instruction form="mm, xmm" name="CVTPD2PI" xed="CVTPD2PI_MMXq_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvttpd_pi32" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 32*j
-	k := 64*j
-	dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k])
-ENDFOR
-	</operation>
-	<instruction form="mm, xmm" name="CVTTPD2PI" xed="CVTTPD2PI_MMXq_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_epi64" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="e1" />
-	<parameter etype="UI64" type="__m64" varname="e0" />
-	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[63:0] := e0
-dst[127:64] := e1
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_epi64x" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="e1" />
-	<parameter etype="UI64" type="__int64" varname="e0" />
-	<description>Set packed 64-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[63:0] := e0
-dst[127:64] := e1
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_epi32" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="e3" />
-	<parameter etype="UI32" type="int" varname="e2" />
-	<parameter etype="UI32" type="int" varname="e1" />
-	<parameter etype="UI32" type="int" varname="e0" />
-	<description>Set packed 32-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[31:0] := e0
-dst[63:32] := e1
-dst[95:64] := e2
-dst[127:96] := e3
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_epi16" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="e7" />
-	<parameter etype="UI16" type="short" varname="e6" />
-	<parameter etype="UI16" type="short" varname="e5" />
-	<parameter etype="UI16" type="short" varname="e4" />
-	<parameter etype="UI16" type="short" varname="e3" />
-	<parameter etype="UI16" type="short" varname="e2" />
-	<parameter etype="UI16" type="short" varname="e1" />
-	<parameter etype="UI16" type="short" varname="e0" />
-	<description>Set packed 16-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[15:0] := e0
-dst[31:16] := e1
-dst[47:32] := e2
-dst[63:48] := e3
-dst[79:64] := e4
-dst[95:80] := e5
-dst[111:96] := e6
-dst[127:112] := e7
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_epi8" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="char" varname="e15" />
-	<parameter etype="UI8" type="char" varname="e14" />
-	<parameter etype="UI8" type="char" varname="e13" />
-	<parameter etype="UI8" type="char" varname="e12" />
-	<parameter etype="UI8" type="char" varname="e11" />
-	<parameter etype="UI8" type="char" varname="e10" />
-	<parameter etype="UI8" type="char" varname="e9" />
-	<parameter etype="UI8" type="char" varname="e8" />
-	<parameter etype="UI8" type="char" varname="e7" />
-	<parameter etype="UI8" type="char" varname="e6" />
-	<parameter etype="UI8" type="char" varname="e5" />
-	<parameter etype="UI8" type="char" varname="e4" />
-	<parameter etype="UI8" type="char" varname="e3" />
-	<parameter etype="UI8" type="char" varname="e2" />
-	<parameter etype="UI8" type="char" varname="e1" />
-	<parameter etype="UI8" type="char" varname="e0" />
-	<description>Set packed 8-bit integers in "dst" with the supplied values.</description>
-	<operation>
-dst[7:0] := e0
-dst[15:8] := e1
-dst[23:16] := e2
-dst[31:24] := e3
-dst[39:32] := e4
-dst[47:40] := e5
-dst[55:48] := e6
-dst[63:56] := e7
-dst[71:64] := e8
-dst[79:72] := e9
-dst[87:80] := e10
-dst[95:88] := e11
-dst[103:96] := e12
-dst[111:104] := e13
-dst[119:112] := e14
-dst[127:120] := e15
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_epi64" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_epi64x" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__int64" varname="a" />
-	<description>Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_epi32" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="a" />
-	<description>Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastd".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := a[31:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_epi16" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="a" />
-	<description>Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate "vpbroadcastw".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := a[15:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_epi8" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="char" varname="a" />
-	<description>Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastb".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := a[7:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_epi64" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="e1" />
-	<parameter etype="UI64" type="__m64" varname="e0" />
-	<description>Set packed 64-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[63:0] := e1
-dst[127:64] := e0
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_epi32" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="int" varname="e3" />
-	<parameter etype="UI32" type="int" varname="e2" />
-	<parameter etype="UI32" type="int" varname="e1" />
-	<parameter etype="UI32" type="int" varname="e0" />
-	<description>Set packed 32-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[31:0] := e3
-dst[63:32] := e2
-dst[95:64] := e1
-dst[127:96] := e0
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_epi16" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="short" varname="e7" />
-	<parameter etype="UI16" type="short" varname="e6" />
-	<parameter etype="UI16" type="short" varname="e5" />
-	<parameter etype="UI16" type="short" varname="e4" />
-	<parameter etype="UI16" type="short" varname="e3" />
-	<parameter etype="UI16" type="short" varname="e2" />
-	<parameter etype="UI16" type="short" varname="e1" />
-	<parameter etype="UI16" type="short" varname="e0" />
-	<description>Set packed 16-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[15:0] := e7
-dst[31:16] := e6
-dst[47:32] := e5
-dst[63:48] := e4
-dst[79:64] := e3
-dst[95:80] := e2
-dst[111:96] := e1
-dst[127:112] := e0
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_epi8" sequence="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="char" varname="e15" />
-	<parameter etype="UI8" type="char" varname="e14" />
-	<parameter etype="UI8" type="char" varname="e13" />
-	<parameter etype="UI8" type="char" varname="e12" />
-	<parameter etype="UI8" type="char" varname="e11" />
-	<parameter etype="UI8" type="char" varname="e10" />
-	<parameter etype="UI8" type="char" varname="e9" />
-	<parameter etype="UI8" type="char" varname="e8" />
-	<parameter etype="UI8" type="char" varname="e7" />
-	<parameter etype="UI8" type="char" varname="e6" />
-	<parameter etype="UI8" type="char" varname="e5" />
-	<parameter etype="UI8" type="char" varname="e4" />
-	<parameter etype="UI8" type="char" varname="e3" />
-	<parameter etype="UI8" type="char" varname="e2" />
-	<parameter etype="UI8" type="char" varname="e1" />
-	<parameter etype="UI8" type="char" varname="e0" />
-	<description>Set packed 8-bit integers in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[7:0] := e15
-dst[15:8] := e14
-dst[23:16] := e13
-dst[31:24] := e12
-dst[39:32] := e11
-dst[47:40] := e10
-dst[55:48] := e9
-dst[63:56] := e8
-dst[71:64] := e7
-dst[79:72] := e6
-dst[87:80] := e5
-dst[95:88] := e4
-dst[103:96] := e3
-dst[111:104] := e2
-dst[119:112] := e1
-dst[127:120] := e0
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setzero_si128" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<description>Return vector of type __m128i with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="PXOR" xed="PXOR_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_sd" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="a" />
-	<description>Copy double-precision (64-bit) floating-point element "a" to the lower element of "dst", and zero the upper element.</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := 0
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set1_pd" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="a" />
-	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_pd1" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="a" />
-	<description>Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := a[63:0]
-ENDFOR
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_set_pd" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="e1" />
-	<parameter etype="FP64" type="double" varname="e0" />
-	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values.</description>
-	<operation>
-dst[63:0] := e0
-dst[127:64] := e1
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setr_pd" sequence="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="double" varname="e1" />
-	<parameter etype="FP64" type="double" varname="e0" />
-	<description>Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order.</description>
-	<operation>
-dst[63:0] := e1
-dst[127:64] := e0
-	</operation>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_setzero_pd" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter type="void" />
-	<description>Return vector of type __m128d with all elements set to zero.</description>
-	<operation>
-dst[MAX:0] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="XORPD" xed="XORPD_XMMxuq_XMMxuq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Set</category>
-	</intrinsic>
-	<intrinsic name="_mm_movepi64_pi64" tech="SSE_ALL">
-	<return etype="FP32" type="__m64" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Copy the lower 64-bit integer in "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-	</operation>
-	<instruction form="mm, xmm" name="MOVDQ2Q" xed="MOVDQ2Q_MMXq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_packs_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI8" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := Saturate8(a[15:0])
-dst[15:8] := Saturate8(a[31:16])
-dst[23:16] := Saturate8(a[47:32])
-dst[31:24] := Saturate8(a[63:48])
-dst[39:32] := Saturate8(a[79:64])
-dst[47:40] := Saturate8(a[95:80])
-dst[55:48] := Saturate8(a[111:96])
-dst[63:56] := Saturate8(a[127:112])
-dst[71:64] := Saturate8(b[15:0])
-dst[79:72] := Saturate8(b[31:16])
-dst[87:80] := Saturate8(b[47:32])
-dst[95:88] := Saturate8(b[63:48])
-dst[103:96] := Saturate8(b[79:64])
-dst[111:104] := Saturate8(b[95:80])
-dst[119:112] := Saturate8(b[111:96])
-dst[127:120] := Saturate8(b[127:112])
-	</operation>
-	<instruction form="xmm, xmm" name="PACKSSWB" xed="PACKSSWB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_packs_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[31:0])
-dst[31:16] := Saturate16(a[63:32])
-dst[47:32] := Saturate16(a[95:64])
-dst[63:48] := Saturate16(a[127:96])
-dst[79:64] := Saturate16(b[31:0])
-dst[95:80] := Saturate16(b[63:32])
-dst[111:96] := Saturate16(b[95:64])
-dst[127:112] := Saturate16(b[127:96])
-	</operation>
-	<instruction form="xmm, xmm" name="PACKSSDW" xed="PACKSSDW_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_packus_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst".</description>
-	<operation>
-dst[7:0] := SaturateU8(a[15:0])
-dst[15:8] := SaturateU8(a[31:16])
-dst[23:16] := SaturateU8(a[47:32])
-dst[31:24] := SaturateU8(a[63:48])
-dst[39:32] := SaturateU8(a[79:64])
-dst[47:40] := SaturateU8(a[95:80])
-dst[55:48] := SaturateU8(a[111:96])
-dst[63:56] := SaturateU8(a[127:112])
-dst[71:64] := SaturateU8(b[15:0])
-dst[79:72] := SaturateU8(b[31:16])
-dst[87:80] := SaturateU8(b[47:32])
-dst[95:88] := SaturateU8(b[63:48])
-dst[103:96] := SaturateU8(b[79:64])
-dst[111:104] := SaturateU8(b[95:80])
-dst[119:112] := SaturateU8(b[111:96])
-dst[127:120] := SaturateU8(b[127:112])
-	</operation>
-	<instruction form="xmm, xmm" name="PACKUSWB" xed="PACKUSWB_XMMdq_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movemask_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="MASK" type="int" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[j] := a[i+7]
-ENDFOR
-dst[MAX:16] := 0
-	</operation>
-	<instruction form="r32, xmm" name="PMOVMSKB" xed="PMOVMSKB_GPR32_XMMdq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movemask_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="MASK" type="int" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF a[i+63]
-		dst[j] := 1
-	ELSE
-		dst[j] := 0
-	FI
-ENDFOR
-dst[MAX:2] := 0
-	</operation>
-	<instruction form="r32, xmm" name="MOVMSKPD" xed="MOVMSKPD_GPR32_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_movpi64_epi64" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m64" varname="a" />
-	<description>Copy the 64-bit integer "a" to the lower element of "dst", and zero the upper element.</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := 0
-	</operation>
-	<instruction form="xmm, mm" name="MOVQ2DQ" xed="MOVQ2DQ_XMMdq_MMXq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_move_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Copy the lower 64-bit integer in "a" to the lower element of "dst", and zero the upper element.</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="MOVQ" xed="MOVQ_XMMdq_XMMq_0F7E" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_move_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := b[63:0]
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="MOVSD" xed="MOVSD_XMM_XMMsd_XMMsd_0F10" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_extract_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="int" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="3" type="int" varname="imm8" />
-	<description>Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".</description>
-	<operation>
-dst[15:0] := (a[127:0] &gt;&gt; (imm8[2:0] * 16))[15:0]
-dst[31:16] := 0
-	</operation>
-	<instruction form="r32, xmm, imm8" name="PEXTRW" xed="PEXTRW_GPR32_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_insert_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="int" varname="i" />
-	<parameter etype="IMM" immwidth="3" type="int" varname="imm8" />
-	<description>Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[127:0] := a[127:0]
-sel := imm8[2:0]*16
-dst[sel+15:sel] := i[15:0]
-	</operation>
-	<instruction form="xmm, r32, imm8" name="PINSRW" xed="PINSRW_XMMdq_GPR32_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_shuffle_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-DEFINE SELECT4(src, control) {
-	CASE(control[1:0]) OF
-	0:	tmp[31:0] := src[31:0]
-	1:	tmp[31:0] := src[63:32]
-	2:	tmp[31:0] := src[95:64]
-	3:	tmp[31:0] := src[127:96]
-	ESAC
-	RETURN tmp[31:0]
-}
-dst[31:0] := SELECT4(a[127:0], imm8[1:0])
-dst[63:32] := SELECT4(a[127:0], imm8[3:2])
-dst[95:64] := SELECT4(a[127:0], imm8[5:4])
-dst[127:96] := SELECT4(a[127:0], imm8[7:6])
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PSHUFD" xed="PSHUFD_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_shufflehi_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[79:64] := (a &gt;&gt; (imm8[1:0] * 16))[79:64]
-dst[95:80] := (a &gt;&gt; (imm8[3:2] * 16))[79:64]
-dst[111:96] := (a &gt;&gt; (imm8[5:4] * 16))[79:64]
-dst[127:112] := (a &gt;&gt; (imm8[7:6] * 16))[79:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PSHUFHW" xed="PSHUFHW_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_shufflelo_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="8" type="int" varname="imm8" />
-	<description>Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst".</description>
-	<operation>
-dst[15:0] := (a &gt;&gt; (imm8[1:0] * 16))[15:0]
-dst[31:16] := (a &gt;&gt; (imm8[3:2] * 16))[15:0]
-dst[47:32] := (a &gt;&gt; (imm8[5:4] * 16))[15:0]
-dst[63:48] := (a &gt;&gt; (imm8[7:6] * 16))[15:0]
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PSHUFLW" xed="PSHUFLW_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[71:64] 
-	dst[15:8] := src2[71:64] 
-	dst[23:16] := src1[79:72] 
-	dst[31:24] := src2[79:72] 
-	dst[39:32] := src1[87:80] 
-	dst[47:40] := src2[87:80] 
-	dst[55:48] := src1[95:88] 
-	dst[63:56] := src2[95:88] 
-	dst[71:64] := src1[103:96] 
-	dst[79:72] := src2[103:96] 
-	dst[87:80] := src1[111:104] 
-	dst[95:88] := src2[111:104] 
-	dst[103:96] := src1[119:112] 
-	dst[111:104] := src2[119:112] 
-	dst[119:112] := src1[127:120] 
-	dst[127:120] := src2[127:120] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PUNPCKHBW" xed="PUNPCKHBW_XMMdq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[79:64]
-	dst[31:16] := src2[79:64] 
-	dst[47:32] := src1[95:80] 
-	dst[63:48] := src2[95:80] 
-	dst[79:64] := src1[111:96] 
-	dst[95:80] := src2[111:96] 
-	dst[111:96] := src1[127:112] 
-	dst[127:112] := src2[127:112] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PUNPCKHWD" xed="PUNPCKHWD_XMMdq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[95:64] 
-	dst[63:32] := src2[95:64] 
-	dst[95:64] := src1[127:96] 
-	dst[127:96] := src2[127:96] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PUNPCKHDQ" xed="PUNPCKHDQ_XMMdq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PUNPCKHQDQ" xed="PUNPCKHQDQ_XMMdq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) {
-	dst[7:0] := src1[7:0] 
-	dst[15:8] := src2[7:0] 
-	dst[23:16] := src1[15:8] 
-	dst[31:24] := src2[15:8] 
-	dst[39:32] := src1[23:16] 
-	dst[47:40] := src2[23:16] 
-	dst[55:48] := src1[31:24] 
-	dst[63:56] := src2[31:24] 
-	dst[71:64] := src1[39:32]
-	dst[79:72] := src2[39:32] 
-	dst[87:80] := src1[47:40] 
-	dst[95:88] := src2[47:40] 
-	dst[103:96] := src1[55:48] 
-	dst[111:104] := src2[55:48] 
-	dst[119:112] := src1[63:56] 
-	dst[127:120] := src2[63:56] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PUNPCKLBW" xed="PUNPCKLBW_XMMdq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) {
-	dst[15:0] := src1[15:0] 
-	dst[31:16] := src2[15:0] 
-	dst[47:32] := src1[31:16] 
-	dst[63:48] := src2[31:16] 
-	dst[79:64] := src1[47:32] 
-	dst[95:80] := src2[47:32] 
-	dst[111:96] := src1[63:48] 
-	dst[127:112] := src2[63:48] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PUNPCKLWD" xed="PUNPCKLWD_XMMdq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) {
-	dst[31:0] := src1[31:0] 
-	dst[63:32] := src2[31:0] 
-	dst[95:64] := src1[63:32] 
-	dst[127:96] := src2[63:32] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PUNPCKLDQ" xed="PUNPCKLDQ_XMMdq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="PUNPCKLQDQ" xed="PUNPCKLQDQ_XMMdq_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpackhi_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[127:64] 
-	dst[127:64] := src2[127:64] 
-	RETURN dst[127:0]	
-}
-dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="UNPCKHPD" xed="UNPCKHPD_XMMpd_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_unpacklo_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst".</description>
-	<operation>
-DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) {
-	dst[63:0] := src1[63:0] 
-	dst[127:64] := src2[63:0] 
-	RETURN dst[127:0]
-}
-dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0])
-	</operation>
-	<instruction form="xmm, xmm" name="UNPCKLPD" xed="UNPCKLPD_XMMpd_XMMq" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_shuffle_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="int" varname="imm8" />
-	<description>Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst".</description>
-	<operation>
-dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64]
-dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="SHUFPD" xed="SHUFPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := SQRT(b[63:0])
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="SQRTSD" xed="SQRTSD_XMMsd_XMMsd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_sqrt_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SQRT(a[i+63:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="SQRTPD" xed="SQRTPD_XMMpd_XMMpd" />
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Elementary Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_castpd_ps" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Cast vector of type __m128d to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castpd_si128" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Cast vector of type __m128d to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castps_pd" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Cast vector of type __m128 to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castps_si128" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Cast vector of type __m128 to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castsi128_pd" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<description>Cast vector of type __m128i to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	<intrinsic name="_mm_castsi128_ps" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Cast vector of type __m128i to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency.</description>
-	<CPUID>SSE2</CPUID>
-	<header>emmintrin.h</header>
-	<category>Cast</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_addsub_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF ((j &amp; 1) == 0)
-		dst[i+31:i] := a[i+31:i] - b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i] + b[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ADDSUBPS" xed="ADDSUBPS_XMMps_XMMps" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_addsub_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF ((j &amp; 1) == 0)
-		dst[i+63:i] := a[i+63:i] - b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i] + b[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="ADDSUBPD" xed="ADDSUBPD_XMMpd_XMMpd" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hadd_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
-	<operation>
-dst[63:0] := a[127:64] + a[63:0]
-dst[127:64] := b[127:64] + b[63:0]
-	</operation>
-	<instruction form="xmm, xmm" name="HADDPD" xed="HADDPD_XMMpd_XMMpd" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hadd_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32] + a[31:0]
-dst[63:32] := a[127:96] + a[95:64]
-dst[95:64] := b[63:32] + b[31:0]
-dst[127:96] := b[127:96] + b[95:64]
-	</operation>
-	<instruction form="xmm, xmm" name="HADDPS" xed="HADDPS_XMMps_XMMps" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hsub_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
-	<operation>
-dst[63:0] := a[63:0] - a[127:64]
-dst[127:64] := b[63:0] - b[127:64]
-	</operation>
-	<instruction form="xmm, xmm" name="HSUBPD" xed="HSUBPD_XMMpd_XMMpd" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hsub_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] - a[63:32]
-dst[63:32] := a[95:64] - a[127:96]
-dst[95:64] := b[31:0] - b[63:32]
-dst[127:96] := b[95:64] - b[127:96]
-	</operation>
-	<instruction form="xmm, xmm" name="HSUBPS" xed="HSUBPS_XMMps_XMMps" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_lddqu_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" memwidth="128" type="__m128i const*" varname="mem_addr" />
-	<description>Load 128-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm_loadu_si128" when the data crosses a cache line boundary.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="LDDQU" xed="LDDQU_XMMpd_MEMdq" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_loaddup_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" memwidth="64" type="double const*" varname="mem_addr" />
-	<description>Load a double-precision (64-bit) floating-point element from memory into both elements of "dst".</description>
-	<operation>
-dst[63:0] := MEM[mem_addr+63:mem_addr]
-dst[127:64] := MEM[mem_addr+63:mem_addr]
-	</operation>
-	<instruction form="xmm, m64" name="MOVDDUP" xed="MOVDDUP_XMMdq_MEMq" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	<intrinsic name="_mm_movedup_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Duplicate the low double-precision (64-bit) floating-point element from "a", and store the results in "dst".</description>
-	<operation>
-dst[63:0] := a[63:0]
-dst[127:64] := a[63:0]
-	</operation>
-	<instruction form="xmm, xmm" name="MOVDDUP" xed="MOVDDUP_XMMdq_XMMq" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_movehdup_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32] 
-dst[63:32] := a[63:32]
-dst[95:64] := a[127:96] 
-dst[127:96] := a[127:96]
-	</operation>
-	<instruction form="xmm, xmm" name="MOVSHDUP" xed="MOVSHDUP_XMMps_XMMps" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	<intrinsic name="_mm_moveldup_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] 
-dst[63:32] := a[31:0]
-dst[95:64] := a[95:64] 
-dst[127:96] := a[95:64]
-	</operation>
-	<instruction form="xmm, xmm" name="MOVSLDUP" xed="MOVSLDUP_XMMps_XMMps" />
-	<CPUID>SSE3</CPUID>
-	<header>pmmintrin.h</header>
-	<category>Move</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_blend_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF imm8[j]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="BLENDPD" xed="BLENDPD_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_blend_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF imm8[j]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="BLENDPS" xed="BLENDPS_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_blendv_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="FP64" type="__m128d" varname="mask" />
-	<description>Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	IF mask[i+63]
-		dst[i+63:i] := b[i+63:i]
-	ELSE
-		dst[i+63:i] := a[i+63:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="BLENDVPD" xed="BLENDVPD_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_blendv_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="FP32" type="__m128" varname="mask" />
-	<description>Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF mask[i+31]
-		dst[i+31:i] := b[i+31:i]
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="BLENDVPS" xed="BLENDVPS_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_blendv_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="UI8" type="__m128i" varname="mask" />
-	<description>Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF mask[i+7]
-		dst[i+7:i] := b[i+7:i]
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PBLENDVB" xed="PBLENDVB_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_blend_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Blend packed 16-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF imm8[j]
-		dst[i+15:i] := b[i+15:i]
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PBLENDW" xed="PBLENDW_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_extract_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Extract a single-precision (32-bit) floating-point element from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-dst[31:0] := (a[127:0] &gt;&gt; (imm8[1:0] * 32))[31:0]
-	</operation>
-	<instruction form="r32, xmm, imm8" name="EXTRACTPS" xed="EXTRACTPS_GPR32d_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_extract_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="int" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Extract an 8-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst".</description>
-	<operation>
-dst[7:0] := (a[127:0] &gt;&gt; (imm8[3:0] * 8))[7:0]
-dst[31:8] := 0
-	</operation>
-	<instruction form="r32, xmm, imm8" name="PEXTRB" xed="PEXTRB_GPR32d_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_extract_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Extract a 32-bit integer from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-dst[31:0] := (a[127:0] &gt;&gt; (imm8[1:0] * 32))[31:0]
-	</operation>
-	<instruction form="r32, xmm, imm8" name="PEXTRD" xed="PEXTRD_GPR32d_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_extract_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Extract a 64-bit integer from "a", selected with "imm8", and store the result in "dst".</description>
-	<operation>
-dst[63:0] := (a[127:0] &gt;&gt; (imm8[0] * 64))[63:0]
-	</operation>
-	<instruction form="r64, xmm, imm8" name="PEXTRQ" xed="PEXTRQ_GPR64q_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_insert_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Copy "a" to "tmp", then insert a single-precision (32-bit) floating-point element from "b" into "tmp" using the control in "imm8". Store "tmp" to "dst" using the mask in "imm8" (elements are zeroed out when the corresponding bit is set).</description>
-	<operation>
-tmp2[127:0] := a[127:0]
-CASE (imm8[7:6]) OF
-0: tmp1[31:0] := b[31:0]
-1: tmp1[31:0] := b[63:32]
-2: tmp1[31:0] := b[95:64]
-3: tmp1[31:0] := b[127:96]
-ESAC
-CASE (imm8[5:4]) OF
-0: tmp2[31:0] := tmp1[31:0]
-1: tmp2[63:32] := tmp1[31:0]
-2: tmp2[95:64] := tmp1[31:0]
-3: tmp2[127:96] := tmp1[31:0]
-ESAC
-FOR j := 0 to 3
-	i := j*32
-	IF imm8[j%8]
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := tmp2[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="INSERTPS" xed="INSERTPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_insert_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="int" varname="i" />
-	<parameter etype="IMM" immwidth="4" type="const int" varname="imm8" />
-	<description>Copy "a" to "dst", and insert the lower 8-bit integer from "i" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[127:0] := a[127:0]
-sel := imm8[3:0]*8
-dst[sel+7:sel] := i[7:0]
-	</operation>
-	<instruction form="xmm, r32, imm8" name="PINSRB" xed="PINSRB_XMMdq_GPR32d_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_insert_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="int" varname="i" />
-	<parameter etype="IMM" immwidth="2" type="const int" varname="imm8" />
-	<description>Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[127:0] := a[127:0]
-sel := imm8[1:0]*32
-dst[sel+31:sel] := i[31:0]
-	</operation>
-	<instruction form="xmm, r32, imm8" name="PINSRD" xed="PINSRD_XMMdq_GPR32d_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_insert_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__int64" varname="i" />
-	<parameter etype="IMM" immwidth="1" type="const int" varname="imm8" />
-	<description>Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "imm8".</description>
-	<operation>
-dst[127:0] := a[127:0]
-sel := imm8[0]*64
-dst[sel+63:sel] := i[63:0]
-	</operation>
-	<instruction form="xmm, r64, imm8" name="PINSRQ" xed="PINSRQ_XMMdq_GPR64q_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_dp_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Conditionally multiply the packed double-precision (64-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".</description>
-	<operation>
-DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
-	FOR j := 0 to 1
-		i := j*64
-		IF imm8[(4+j)%8]
-			temp[i+63:i] := a[i+63:i] * b[i+63:i]
-		ELSE
-			temp[i+63:i] := 0.0
-		FI
-	ENDFOR
-	
-	sum[63:0] := temp[127:64] + temp[63:0]
-	
-	FOR j := 0 to 1
-		i := j*64
-		IF imm8[j%8]
-			tmpdst[i+63:i] := sum[63:0]
-		ELSE
-			tmpdst[i+63:i] := 0.0
-		FI
-	ENDFOR
-	RETURN tmpdst[127:0]
-}
-dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="DPPD" xed="DPPD_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_dp_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8".</description>
-	<operation>
-DEFINE DP(a[127:0], b[127:0], imm8[7:0]) {
-	FOR j := 0 to 3
-		i := j*32
-		IF imm8[(4+j)%8]
-			temp[i+31:i] := a[i+31:i] * b[i+31:i]
-		ELSE
-			temp[i+31:i] := 0
-		FI
-	ENDFOR
-	
-	sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0])
-	
-	FOR j := 0 to 3
-		i := j*32
-		IF imm8[j%8]
-			tmpdst[i+31:i] := sum[31:0]
-		ELSE
-			tmpdst[i+31:i] := 0
-		FI
-	ENDFOR
-	RETURN tmpdst[127:0]
-}
-dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0])
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="DPPS" xed="DPPS_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mul_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMULDQ" xed="PMULDQ_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mullo_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	tmp[63:0] := a[i+31:i] * b[i+31:i]
-	dst[i+31:i] := tmp[31:0]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMULLD" xed="PMULLD_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mpsadbw_epu8" vexEq="TRUE" tech="SSE_ALL">
-	<category>Miscellaneous</category>
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst".
-	Eight SADs are performed using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8".</description>
-	<operation>
-DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) {
-	a_offset := imm8[2]*32
-	b_offset := imm8[1:0]*32
-	FOR j := 0 to 7
-		i := j*8
-		k := a_offset+i
-		l := b_offset
-		tmp[i*2+15:i*2] := ABS(Signed(a[k+7:k] - b[l+7:l])) + ABS(Signed(a[k+15:k+8] - b[l+15:l+8])) + \
-		                   ABS(Signed(a[k+23:k+16] - b[l+23:l+16])) + ABS(Signed(a[k+31:k+24] - b[l+31:l+24]))
-	ENDFOR
-	RETURN tmp[127:0]
-}
-dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0])
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="MPSADBW" xed="MPSADBW_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := MAX(a[i+7:i], b[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMAXSB" xed="PMAXSB_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMAXSD" xed="PMAXSD_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_epu32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := MAX(a[i+31:i], b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMAXUD" xed="PMAXUD_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_max_epu16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := MAX(a[i+15:i], b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMAXUW" xed="PMAXUW_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := MIN(a[i+7:i], b[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMINSB" xed="PMINSB_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMINSD" xed="PMINSD_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_epu32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := MIN(a[i+31:i], b[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMINUD" xed="PMINUD_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_min_epu16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<parameter etype="UI16" type="__m128i" varname="b" />
-	<description>Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := MIN(a[i+15:i], b[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMINUW" xed="PMINUW_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_round_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ROUND(a[i+63:i], rounding)
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDPD" xed="ROUNDPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_floor_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := FLOOR(a[i+63:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDPD" xed="ROUNDPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_ceil_pd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<description>Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := CEIL(a[i+63:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDPD" xed="ROUNDPD_XMMpd_XMMpd_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_round_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst".
-	[round_note]</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ROUND(a[i+31:i], rounding)
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDPS" xed="ROUNDPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_floor_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := FLOOR(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDPS" xed="ROUNDPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_ceil_ps" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<description>Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := CEIL(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDPS" xed="ROUNDPS_XMMps_XMMps_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_round_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" using the "rounding" parameter, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".
-	[round_note]</description>
-	<operation>
-dst[63:0] := ROUND(b[63:0], rounding)
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDSD" xed="ROUNDSD_XMMq_XMMq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_floor_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" down to an integer value, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := FLOOR(b[63:0])
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDSD" xed="ROUNDSD_XMMq_XMMq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_ceil_sd" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP64" type="__m128d" varname="dst" />
-	<parameter etype="FP64" type="__m128d" varname="a" />
-	<parameter etype="FP64" type="__m128d" varname="b" />
-	<description>Round the lower double-precision (64-bit) floating-point element in "b" up to an integer value, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst".</description>
-	<operation>
-dst[63:0] := CEIL(b[63:0])
-dst[127:64] := a[127:64]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDSD" xed="ROUNDSD_XMMq_XMMq_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_round_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<parameter etype="IMM" immtype="_MM_FROUND" type="int" varname="rounding" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" using the "rounding" parameter, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".
-	[round_note]</description>
-	<operation>
-dst[31:0] := ROUND(b[31:0], rounding)
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDSS" xed="ROUNDSS_XMMd_XMMd_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_floor_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" down to an integer value, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := FLOOR(b[31:0])
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDSS" xed="ROUNDSS_XMMd_XMMd_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_ceil_ss" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="FP32" type="__m128" varname="dst" />
-	<parameter etype="FP32" type="__m128" varname="a" />
-	<parameter etype="FP32" type="__m128" varname="b" />
-	<description>Round the lower single-precision (32-bit) floating-point element in "b" up to an integer value, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst".</description>
-	<operation>
-dst[31:0] := CEIL(b[31:0])
-dst[127:32] := a[127:32]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="ROUNDSS" xed="ROUNDSS_XMMd_XMMd_IMMb" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_packus_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<category>Miscellaneous</category>
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst".</description>
-	<operation>
-dst[15:0] := SaturateU16(a[31:0])
-dst[31:16] := SaturateU16(a[63:32])
-dst[47:32] := SaturateU16(a[95:64])
-dst[63:48] := SaturateU16(a[127:96])
-dst[79:64] := SaturateU16(b[31:0])
-dst[95:80] := SaturateU16(b[63:32])
-dst[111:96] := SaturateU16(b[95:64])
-dst[127:112] := SaturateU16(b[127:96])
-	</operation>
-	<instruction form="xmm, xmm" name="PACKUSDW" xed="PACKUSDW_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi8_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	l := j*16
-	dst[l+15:l] := SignExtend16(a[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVSXBW" xed="PMOVSXBW_XMMdq_XMMq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi8_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 8*j
-	dst[i+31:i] := SignExtend32(a[k+7:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVSXBD" xed="PMOVSXBD_XMMdq_XMMd" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi8_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 8*j
-	dst[i+63:i] := SignExtend64(a[k+7:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVSXBQ" xed="PMOVSXBQ_XMMdq_XMMw" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi16_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 16*j
-	dst[i+31:i] := SignExtend32(a[k+15:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVSXWD" xed="PMOVSXWD_XMMdq_XMMq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi16_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 16*j
-	dst[i+63:i] := SignExtend64(a[k+15:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVSXWQ" xed="PMOVSXWQ_XMMdq_XMMd" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepi32_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI64" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := SignExtend64(a[k+31:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVSXDQ" xed="PMOVSXDQ_XMMdq_XMMq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu8_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	l := j*16
-	dst[l+15:l] := ZeroExtend16(a[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVZXBW" xed="PMOVZXBW_XMMdq_XMMq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu8_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 8*j
-	dst[i+31:i] := ZeroExtend32(a[k+7:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVZXBD" xed="PMOVZXBD_XMMdq_XMMd" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu8_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 8*j
-	dst[i+63:i] := ZeroExtend64(a[k+7:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVZXBQ" xed="PMOVZXBQ_XMMdq_XMMw" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu16_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := 32*j
-	k := 16*j
-	dst[i+31:i] := ZeroExtend32(a[k+15:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVZXWD" xed="PMOVZXWD_XMMdq_XMMq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu16_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 16*j
-	dst[i+63:i] := ZeroExtend64(a[k+15:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVZXWQ" xed="PMOVZXWQ_XMMdq_XMMd" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cvtepu32_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI32" type="__m128i" varname="a" />
-	<description>Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := 64*j
-	k := 32*j
-	dst[i+63:i] := ZeroExtend64(a[k+31:k])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMOVZXDQ" xed="PMOVZXDQ_XMMdq_XMMq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Convert</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpeq_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="UI64" type="__m128i" varname="a" />
-	<parameter etype="UI64" type="__m128i" varname="b" />
-	<description>Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPEQQ" xed="PCMPEQQ_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_testz_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value.</description>
-	<operation>
-IF ((a[127:0] AND b[127:0]) == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-IF (((NOT a[127:0]) AND b[127:0]) == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-RETURN ZF
-	</operation>
-	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_testc_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="k" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value.</description>
-	<operation>
-IF ((a[127:0] AND b[127:0]) == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-IF (((NOT a[127:0]) AND b[127:0]) == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-RETURN CF
-	</operation>
-	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_testnzc_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
-	<operation>
-IF ((a[127:0] AND b[127:0]) == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-IF (((NOT a[127:0]) AND b[127:0]) == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-IF (ZF == 0 &amp;&amp; CF == 0)
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_test_all_zeros" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="mask" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and return 1 if the result is zero, otherwise return 0.</description>
-	<operation>
-IF ((a[127:0] AND mask[127:0]) == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-dst := ZF
-	</operation>
-	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_test_mix_ones_zeros" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="mask" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "mask", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0.</description>
-	<operation>
-IF ((a[127:0] AND mask[127:0]) == 0)
-	ZF := 1
-ELSE
-	ZF := 0
-FI
-IF (((NOT a[127:0]) AND mask[127:0]) == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-IF (ZF == 0 &amp;&amp; CF == 0)
-	dst := 1
-ELSE
-	dst := 0
-FI
-	</operation>
-	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_test_all_ones" sequence="TRUE" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<description>Compute the bitwise NOT of "a" and then AND with a 128-bit vector containing all 1's, and return 1 if the result is zero, otherwise return 0.</description>
-	<operation>
-FOR j := 0 to 127
-	tmp[j] := 1
-ENDFOR
-IF (((NOT a[127:0]) AND tmp[127:0]) == 0)
-	CF := 1
-ELSE
-	CF := 0
-FI
-dst := CF
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPEQD" xed="PCMPEQD_XMMdq_XMMdq" />
-	<instruction form="xmm, xmm" name="PTEST" xed="PTEST_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Logical</category>
-	</intrinsic>
-	<intrinsic name="_mm_minpos_epu16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="UI16" type="__m128i" varname="a" />
-	<description>Horizontally compute the minimum amongst the packed unsigned 16-bit integers in "a", store the minimum and index in "dst", and zero the remaining bits in "dst".</description>
-	<operation>
-index[2:0] := 0
-min[15:0] := a[15:0]
-FOR j := 0 to 7
-	i := j*16
-	IF a[i+15:i] &lt; min[15:0]
-		index[2:0] := j
-		min[15:0] := a[i+15:i]
-	FI
-ENDFOR
-dst[15:0] := min[15:0]
-dst[18:16] := index[2:0]
-dst[127:19] := 0
-	</operation>
-	<instruction form="xmm, xmm" name="PHMINPOSUW" xed="PHMINPOSUW_XMMdq_XMMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_stream_load_si128" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" memwidth="128" type="void*" varname="mem_addr" />
-	<description>Load 128-bits of integer data from memory into "dst" using a non-temporal memory hint.
-	"mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated.</description>
-	<operation>
-dst[127:0] := MEM[mem_addr+127:mem_addr]
-	</operation>
-	<instruction form="xmm, m128" name="MOVNTDQA" xed="MOVNTDQA_XMMdq_MEMdq" />
-	<CPUID>SSE4.1</CPUID>
-	<header>smmintrin.h</header>
-	<category>Load</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_cmpistrm" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated mask in "dst".
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF a[m+size-1:m] == 0
-			aInvalid := 1
-		FI
-		IF b[n+size-1:n] == 0
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-bInvalid := 0
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF b[n+size-1:n] == 0
-				bInvalid := 1
-			FI
-			IF bInvalid // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-IF imm8[6] // byte / word mask
-	FOR i := 0 to UpperBound
-		j := i*size
-		IF IntRes2[i]
-			dst[j+size-1:j] := (imm8[0] ? 0xFF : 0xFFFF)
-		ELSE
-			dst[j+size-1:j] := 0
-		FI
-	ENDFOR
-ELSE // bit mask
-	dst[UpperBound:0] := IntRes2[UpperBound:0]
-	dst[127:UpperBound+1] := 0
-FI
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPISTRM" xed="PCMPISTRM_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpistri" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated index in "dst".
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF a[m+size-1:m] == 0
-			aInvalid := 1
-		FI
-		IF b[n+size-1:n] == 0
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-bInvalid := 0
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF b[n+size-1:n] == 0
-				bInvalid := 1
-			FI
-			IF bInvalid // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-IF imm8[6] // most significant bit
-	tmp := UpperBound
-	dst := tmp
-	DO WHILE ((tmp &gt;= 0) AND a[tmp] == 0)
-		tmp := tmp - 1
-		dst := tmp
-	OD
-ELSE // least significant bit
-	tmp := 0
-	dst := tmp
-	DO WHILE ((tmp &lt;= UpperBound) AND a[tmp] == 0)
-		tmp := tmp + 1
-		dst := tmp
-	OD
-FI
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpistrz" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" hint="TRUE" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if any character in "b" was null, and 0 otherwise.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-bInvalid := 0
-FOR j := 0 to UpperBound
-	n := j*size
-	IF b[n+size-1:n] == 0
-		bInvalid := 1
-	FI
-ENDFOR
-dst := bInvalid
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpistrc" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if the resulting mask was non-zero, and 0 otherwise.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF a[m+size-1:m] == 0
-			aInvalid := 1
-		FI
-		IF b[n+size-1:n] == 0
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-bInvalid := 0
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF b[n+size-1:n] == 0
-				bInvalid := 1
-			FI
-			IF bInvalid // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-dst := (IntRes2 != 0)
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpistrs" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" hint="TRUE" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if any character in "a" was null, and 0 otherwise.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-aInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	IF a[m+size-1:m] == 0
-		aInvalid := 1
-	FI
-ENDFOR
-dst := aInvalid
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpistro" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns bit 0 of the resulting bit mask.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF a[m+size-1:m] == 0
-			aInvalid := 1
-		FI
-		IF b[n+size-1:n] == 0
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-bInvalid := 0
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF b[n+size-1:n] == 0
-				bInvalid := 1
-			FI
-			IF bInvalid // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-dst := IntRes2[0]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpistra" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if "b" did not contain a null character and the resulting mask was zero, and 0 otherwise.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF a[m+size-1:m] == 0
-			aInvalid := 1
-		FI
-		IF b[n+size-1:n] == 0
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-bInvalid := 0
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF b[n+size-1:n] == 0
-				bInvalid := 1
-			FI
-			IF bInvalid // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-dst := (IntRes2 == 0) AND bInvalid
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPISTRI" xed="PCMPISTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpestrm" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="M128" type="__m128i" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="int" varname="la" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="int" varname="lb" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated mask in "dst".
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF i == la
-			aInvalid := 1
-		FI
-		IF j == lb
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF i &gt;= lb // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-IF imm8[6] // byte / word mask
-	FOR i := 0 to UpperBound
-		j := i*size
-		IF IntRes2[i]
-			dst[j+size-1:j] := (imm8[0] ? 0xFF : 0xFFFF)
-		ELSE
-			dst[j+size-1:j] := 0
-		FI
-	ENDFOR
-ELSE // bit mask
-	dst[UpperBound:0] := IntRes2[UpperBound:0]
-	dst[127:UpperBound+1] := 0
-FI
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPESTRM" xed="PCMPESTRM_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpestri" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="int" varname="la" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="int" varname="lb" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated index in "dst".
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF i == la
-			aInvalid := 1
-		FI
-		IF j == lb
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF i &gt;= lb // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-IF imm8[6] // most significant bit
-	tmp := UpperBound
-	dst := tmp
-	DO WHILE ((tmp &gt;= 0) AND a[tmp] == 0)
-		tmp := tmp - 1
-		dst := tmp
-	OD
-ELSE // least significant bit
-	tmp := 0
-	dst := tmp
-	DO WHILE ((tmp &lt;= UpperBound) AND a[tmp] == 0)
-		tmp := tmp + 1
-		dst := tmp
-	OD
-FI
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpestrz" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" hint="TRUE" type="__m128i" varname="a" />
-	<parameter etype="UI32" hint="TRUE" type="int" varname="la" />
-	<parameter etype="M128" hint="TRUE" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="int" varname="lb" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if any character in "b" was null, and 0 otherwise.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-dst := (lb &lt;= UpperBound)
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpestrc" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="int" varname="la" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="int" varname="lb" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if the resulting mask was non-zero, and 0 otherwise.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF i == la
-			aInvalid := 1
-		FI
-		IF j == lb
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF i &gt;= lb // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-dst := (IntRes2 != 0)
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpestrs" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" hint="TRUE" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="int" varname="la" />
-	<parameter etype="M128" hint="TRUE" type="__m128i" varname="b" />
-	<parameter etype="UI32" hint="TRUE" type="int" varname="lb" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if any character in "a" was null, and 0 otherwise.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-dst := (la &lt;= UpperBound)
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpestro" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="int" varname="la" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="int" varname="lb" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns bit 0 of the resulting bit mask.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF i == la
-			aInvalid := 1
-		FI
-		IF j == lb
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF i &gt;= lb // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-dst := IntRes2[0]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpestra" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="int" varname="dst" />
-	<parameter etype="M128" type="__m128i" varname="a" />
-	<parameter etype="UI32" type="int" varname="la" />
-	<parameter etype="M128" type="__m128i" varname="b" />
-	<parameter etype="UI32" type="int" varname="lb" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="imm8" />
-	<description>Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if "b" did not contain a null character and the resulting mask was zero, and 0 otherwise.
-	[strcmp_note]</description>
-	<operation>
-size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters
-UpperBound := (128 / size) - 1
-BoolRes := 0
-// compare all characters
-aInvalid := 0
-bInvalid := 0
-FOR i := 0 to UpperBound
-	m := i*size
-	FOR j := 0 to UpperBound
-		n := j*size
-		BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0
-		
-		// invalidate characters after EOS
-		IF i == la
-			aInvalid := 1
-		FI
-		IF j == lb
-			bInvalid := 1
-		FI
-		
-		// override comparisons for invalid characters
-		CASE (imm8[3:2]) OF
-		0:  // equal any
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		1:  // ranges
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			FI
-		2:  // equal each
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		3:  // equal ordered
-			IF (!aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 0
-			ELSE IF (aInvalid &amp;&amp; !bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			ELSE IF (aInvalid &amp;&amp; bInvalid)
-				BoolRes.word[i].bit[j] := 1
-			FI
-		ESAC
-	ENDFOR
-ENDFOR
-// aggregate results
-CASE (imm8[3:2]) OF
-0:  // equal any
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j]
-		ENDFOR
-	ENDFOR
-1:  // ranges
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		FOR j := 0 to UpperBound
-			IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1])
-			j += 2
-		ENDFOR
-	ENDFOR
-2:  // equal each
-	IntRes1 := 0
-	FOR i := 0 to UpperBound
-		IntRes1[i] := BoolRes.word[i].bit[i]
-	ENDFOR
-3:  // equal ordered
-	IntRes1 := (imm8[0] ? 0xFF : 0xFFFF)
-	FOR i := 0 to UpperBound
-		k := i
-		FOR j := 0 to UpperBound-i
-			IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j]
-			k := k+1
-		ENDFOR
-	ENDFOR
-ESAC
-// optionally negate results
-FOR i := 0 to UpperBound
-	IF imm8[4]
-		IF imm8[5] // only negate valid
-			IF i &gt;= lb // invalid, don't negate
-				IntRes2[i] := IntRes1[i]
-			ELSE // valid, negate
-				IntRes2[i] := -1 XOR IntRes1[i]
-			FI
-		ELSE // negate all
-			IntRes2[i] := -1 XOR IntRes1[i]
-		FI
-	ELSE // don't negate
-		IntRes2[i] := IntRes1[i]
-	FI
-ENDFOR
-// output
-dst := (IntRes2 == 0) AND (lb &gt; UpperBound)
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PCMPESTRI" xed="PCMPESTRI_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>String Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_cmpgt_epi64" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI64" type="__m128i" varname="dst" />
-	<parameter etype="SI64" type="__m128i" varname="a" />
-	<parameter etype="SI64" type="__m128i" varname="b" />
-	<description>Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*64
-	dst[i+63:i] := ( a[i+63:i] &gt; b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PCMPGTQ" xed="PCMPGTQ_XMMdq_XMMdq" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Compare</category>
-	</intrinsic>
-	<intrinsic name="_mm_crc32_u8" tech="SSE_ALL">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="crc" />
-	<parameter etype="UI8" type="unsigned char" varname="v" />
-	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst".</description>
-	<operation>tmp1[7:0] := v[0:7] // bit reflection
-tmp2[31:0] := crc[0:31] // bit reflection
-tmp3[39:0] := tmp1[7:0] &lt;&lt; 32 
-tmp4[39:0] := tmp2[31:0] &lt;&lt; 8
-tmp5[39:0] := tmp3[39:0] XOR tmp4[39:0]
-tmp6[31:0] := MOD2(tmp5[39:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
-dst[31:0] := tmp6[0:31] // bit reflection
-	</operation>
-	<instruction form="r32, r8" name="CRC32" xed="CRC32_GPRyy_GPR8b" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_crc32_u16" tech="SSE_ALL">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="crc" />
-	<parameter etype="UI16" type="unsigned short" varname="v" />
-	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst".</description>
-	<operation>tmp1[15:0] := v[0:15] // bit reflection
-tmp2[31:0] := crc[0:31] // bit reflection
-tmp3[47:0] := tmp1[15:0] &lt;&lt; 32
-tmp4[47:0] := tmp2[31:0] &lt;&lt; 16
-tmp5[47:0] := tmp3[47:0] XOR tmp4[47:0]
-tmp6[31:0] := MOD2(tmp5[47:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
-dst[31:0] := tmp6[0:31] // bit reflection
-	</operation>
-	<instruction form="r32, r16" name="CRC32" xed="CRC32_GPRyy_GPRv" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_crc32_u32" tech="SSE_ALL">
-	<return etype="UI32" type="unsigned int" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="crc" />
-	<parameter etype="UI32" type="unsigned int" varname="v" />
-	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst".</description>
-	<operation>tmp1[31:0] := v[0:31] // bit reflection
-tmp2[31:0] := crc[0:31] // bit reflection
-tmp3[63:0] := tmp1[31:0] &lt;&lt; 32
-tmp4[63:0] := tmp2[31:0] &lt;&lt; 32
-tmp5[63:0] := tmp3[63:0] XOR tmp4[63:0]
-tmp6[31:0] := MOD2(tmp5[63:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
-dst[31:0] := tmp6[0:31] // bit reflection
-	</operation>
-	<instruction form="r32, r32" name="CRC32" xed="CRC32_GPRyy_GPRv" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm_crc32_u64" tech="SSE_ALL">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI64" type="unsigned __int64" varname="crc" />
-	<parameter etype="UI64" type="unsigned __int64" varname="v" />
-	<description>Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst".</description>
-	<operation>tmp1[63:0] := v[0:63] // bit reflection
-tmp2[31:0] := crc[0:31] // bit reflection
-tmp3[95:0] := tmp1[31:0] &lt;&lt; 32
-tmp4[95:0] := tmp2[63:0] &lt;&lt; 64
-tmp5[95:0] := tmp3[95:0] XOR tmp4[95:0]
-tmp6[31:0] := MOD2(tmp5[95:0], 0x11EDC6F41) // remainder from polynomial division modulus 2
-dst[31:0] := tmp6[0:31] // bit reflection
-	</operation>
-	<instruction form="r64, r64" name="CRC32" xed="CRC32_GPRyy_GPRv" />
-	<CPUID>SSE4.2</CPUID>
-	<header>nmmintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm_abs_pi8" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="SI8" type="__m64" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	dst[i+7:i] := ABS(Int(a[i+7:i]))
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PABSB" xed="PABSB_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_abs_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	dst[i+7:i] := ABS(a[i+7:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PABSB" xed="PABSB_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_abs_pi16" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := ABS(Int(a[i+15:i]))
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PABSW" xed="PABSW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_abs_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := ABS(a[i+15:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PABSW" xed="PABSW_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_abs_pi32" tech="SSE_ALL">
-	<return etype="UI32" type="__m64" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	dst[i+31:i] := ABS(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PABSD" xed="PABSD_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_abs_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<description>Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	dst[i+31:i] := ABS(a[i+31:i])
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PABSD" xed="PABSD_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Special Math Functions</category>
-	</intrinsic>
-	<intrinsic name="_mm_shuffle_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF b[i+7] == 1
-		dst[i+7:i] := 0
-	ELSE
-		index[3:0] := b[i+3:i]
-		dst[i+7:i] := a[index*8+7:index*8]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSHUFB" xed="PSHUFB_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_shuffle_pi8" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<description>Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	IF b[i+7] == 1
-		dst[i+7:i] := 0
-	ELSE
-		index[2:0] := b[i+2:i]
-		dst[i+7:i] := a[index*8+7:index*8]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSHUFB" xed="PSHUFB_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Swizzle</category>
-	</intrinsic>
-	<intrinsic name="_mm_alignr_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="UI8" type="__m128i" varname="b" />
-	<parameter etype="IMM" immwidth="5" type="int" varname="imm8" />
-	<description>Concatenate 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
-	<operation>
-tmp[255:0] := ((a[127:0] &lt;&lt; 128)[255:0] OR b[127:0]) &gt;&gt; (imm8*8)
-dst[127:0] := tmp[127:0]
-	</operation>
-	<instruction form="xmm, xmm, imm8" name="PALIGNR" xed="PALIGNR_XMMdq_XMMdq_IMMb" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_alignr_pi8" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="UI8" type="__m64" varname="b" />
-	<parameter etype="IMM" immwidth="4" type="int" varname="imm8" />
-	<description>Concatenate 8-byte blocks in "a" and "b" into a 16-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst".</description>
-	<operation>
-tmp[127:0] := ((a[63:0] &lt;&lt; 64)[127:0] OR b[63:0]) &gt;&gt; (imm8*8)
-dst[63:0] := tmp[63:0]
-	</operation>
-	<instruction form="mm, mm, imm8" name="PALIGNR" xed="PALIGNR_MMXq_MMXq_IMMb" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_mm_hadd_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := a[31:16] + a[15:0]
-dst[31:16] := a[63:48] + a[47:32]
-dst[47:32] := a[95:80] + a[79:64]
-dst[63:48] := a[127:112] + a[111:96]
-dst[79:64] := b[31:16] + b[15:0]
-dst[95:80] := b[63:48] + b[47:32]
-dst[111:96] := b[95:80] + b[79:64]
-dst[127:112] := b[127:112] + b[111:96]
-	</operation>
-	<instruction form="xmm, xmm" name="PHADDW" xed="PHADDW_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hadds_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[31:16] + a[15:0])
-dst[31:16] := Saturate16(a[63:48] + a[47:32])
-dst[47:32] := Saturate16(a[95:80] + a[79:64])
-dst[63:48] := Saturate16(a[127:112] + a[111:96])
-dst[79:64] := Saturate16(b[31:16] + b[15:0])
-dst[95:80] := Saturate16(b[63:48] + b[47:32])
-dst[111:96] := Saturate16(b[95:80] + b[79:64])
-dst[127:112] := Saturate16(b[127:112] + b[111:96])
-	</operation>
-	<instruction form="xmm, xmm" name="PHADDSW" xed="PHADDSW_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hadd_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32] + a[31:0]
-dst[63:32] := a[127:96] + a[95:64]
-dst[95:64] := b[63:32] + b[31:0]
-dst[127:96] := b[127:96] + b[95:64]
-	</operation>
-	<instruction form="xmm, xmm" name="PHADDD" xed="PHADDD_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hadd_pi16" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := a[31:16] + a[15:0]
-dst[31:16] := a[63:48] + a[47:32]
-dst[47:32] := b[31:16] + b[15:0]
-dst[63:48] := b[63:48] + b[47:32]
-	</operation>
-	<instruction form="mm, mm" name="PHADDW" xed="PHADDW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hadd_pi32" tech="SSE_ALL">
-	<return etype="SI32" type="__m64" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
-	<operation>
-dst[31:0] := a[63:32] + a[31:0]
-dst[63:32] := b[63:32] + b[31:0]
-	</operation>
-	<instruction form="mm, mm" name="PHADDW" xed="PHADDW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hadds_pi16" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[31:16] + a[15:0])
-dst[31:16] := Saturate16(a[63:48] + a[47:32])
-dst[47:32] := Saturate16(b[31:16] + b[15:0])
-dst[63:48] := Saturate16(b[63:48] + b[47:32])
-	</operation>
-	<instruction form="mm, mm" name="PHADDSW" xed="PHADDSW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hsub_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := a[15:0] - a[31:16]
-dst[31:16] := a[47:32] - a[63:48]
-dst[47:32] := a[79:64] - a[95:80]
-dst[63:48] := a[111:96] - a[127:112]
-dst[79:64] := b[15:0] - b[31:16]
-dst[95:80] := b[47:32] - b[63:48]
-dst[111:96] := b[79:64] - b[95:80]
-dst[127:112] := b[111:96] - b[127:112]
-	</operation>
-	<instruction form="xmm, xmm" name="PHSUBW" xed="PHSUBW_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hsubs_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[15:0] - a[31:16])
-dst[31:16] := Saturate16(a[47:32] - a[63:48])
-dst[47:32] := Saturate16(a[79:64] - a[95:80])
-dst[63:48] := Saturate16(a[111:96] - a[127:112])
-dst[79:64] := Saturate16(b[15:0] - b[31:16])
-dst[95:80] := Saturate16(b[47:32] - b[63:48])
-dst[111:96] := Saturate16(b[79:64] - b[95:80])
-dst[127:112] := Saturate16(b[111:96] - b[127:112])
-	</operation>
-	<instruction form="xmm, xmm" name="PHSUBSW" xed="PHSUBSW_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hsub_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] - a[63:32]
-dst[63:32] := a[95:64] - a[127:96]
-dst[95:64] := b[31:0] - b[63:32]
-dst[127:96] := b[95:64] - b[127:96]
-	</operation>
-	<instruction form="xmm, xmm" name="PHSUBD" xed="PHSUBD_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hsub_pi16" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := a[15:0] - a[31:16]
-dst[31:16] := a[47:32] - a[63:48]
-dst[47:32] := b[15:0] - b[31:16]
-dst[63:48] := b[47:32] - b[63:48]
-	</operation>
-	<instruction form="mm, mm" name="PHSUBW" xed="PHSUBW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hsub_pi32" tech="SSE_ALL">
-	<return etype="SI32" type="__m64" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst".</description>
-	<operation>
-dst[31:0] := a[31:0] - a[63:32]
-dst[63:32] := b[31:0] - b[63:32]
-	</operation>
-	<instruction form="mm, mm" name="PHSUBD" xed="PHSUBD_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_hsubs_pi16" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst".</description>
-	<operation>
-dst[15:0] := Saturate16(a[15:0] - a[31:16])
-dst[31:16] := Saturate16(a[47:32] - a[63:48])
-dst[47:32] := Saturate16(b[15:0] - b[31:16])
-dst[63:48] := Saturate16(b[47:32] - b[63:48])
-	</operation>
-	<instruction form="mm, mm" name="PHSUBSW" xed="PHSUBSW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maddubs_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="SI16" type="__m128i" varname="dst" />
-	<parameter etype="UI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMADDUBSW" xed="PMADDUBSW_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_maddubs_pi16" tech="SSE_ALL">
-	<return etype="SI16" type="__m64" varname="dst" />
-	<parameter etype="UI8" type="__m64" varname="a" />
-	<parameter etype="SI8" type="__m64" varname="b" />
-	<description>Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] )
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMADDUBSW" xed="PMADDUBSW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mulhrs_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-	dst[i+15:i] := tmp[16:1]
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PMULHRSW" xed="PMULHRSW_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_mulhrs_pi16" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst".</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) &gt;&gt; 14) + 1
-	dst[i+15:i] := tmp[16:1]
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PMULHRSW" xed="PMULHRSW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sign_epi8" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI8" type="__m128i" varname="dst" />
-	<parameter etype="SI8" type="__m128i" varname="a" />
-	<parameter etype="SI8" type="__m128i" varname="b" />
-	<description>Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 15
-	i := j*8
-	IF b[i+7:i] &lt; 0
-		dst[i+7:i] := -(a[i+7:i])
-	ELSE IF b[i+7:i] == 0
-		dst[i+7:i] := 0
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSIGNB" xed="PSIGNB_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sign_epi16" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI16" type="__m128i" varname="dst" />
-	<parameter etype="SI16" type="__m128i" varname="a" />
-	<parameter etype="SI16" type="__m128i" varname="b" />
-	<description>Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*16
-	IF b[i+15:i] &lt; 0
-		dst[i+15:i] := -(a[i+15:i])
-	ELSE IF b[i+15:i] == 0
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSIGNW" xed="PSIGNW_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sign_epi32" vexEq="TRUE" tech="SSE_ALL">
-	<return etype="UI32" type="__m128i" varname="dst" />
-	<parameter etype="SI32" type="__m128i" varname="a" />
-	<parameter etype="SI32" type="__m128i" varname="b" />
-	<description>Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*32
-	IF b[i+31:i] &lt; 0
-		dst[i+31:i] := -(a[i+31:i])
-	ELSE IF b[i+31:i] == 0
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="xmm, xmm" name="PSIGND" xed="PSIGND_XMMdq_XMMdq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sign_pi8" tech="SSE_ALL">
-	<return etype="UI8" type="__m64" varname="dst" />
-	<parameter etype="SI8" type="__m64" varname="a" />
-	<parameter etype="SI8" type="__m64" varname="b" />
-	<description>Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 7
-	i := j*8
-	IF b[i+7:i] &lt; 0
-		dst[i+7:i] := -(a[i+7:i])
-	ELSE IF b[i+7:i] == 0
-		dst[i+7:i] := 0
-	ELSE
-		dst[i+7:i] := a[i+7:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSIGNB" xed="PSIGNB_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sign_pi16" tech="SSE_ALL">
-	<return etype="UI16" type="__m64" varname="dst" />
-	<parameter etype="SI16" type="__m64" varname="a" />
-	<parameter etype="SI16" type="__m64" varname="b" />
-	<description>Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 3
-	i := j*16
-	IF b[i+15:i] &lt; 0
-		dst[i+15:i] := -(a[i+15:i])
-	ELSE IF b[i+15:i] == 0
-		dst[i+15:i] := 0
-	ELSE
-		dst[i+15:i] := a[i+15:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSIGNW" xed="PSIGNW_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	<intrinsic name="_mm_sign_pi32" tech="SSE_ALL">
-	<return etype="UI32" type="__m64" varname="dst" />
-	<parameter etype="SI32" type="__m64" varname="a" />
-	<parameter etype="SI32" type="__m64" varname="b" />
-	<description>Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero.</description>
-	<operation>
-FOR j := 0 to 1
-	i := j*32
-	IF b[i+31:i] &lt; 0
-		dst[i+31:i] := -(a[i+31:i])
-	ELSE IF b[i+31:i] == 0
-		dst[i+31:i] := 0
-	ELSE
-		dst[i+31:i] := a[i+31:i]
-	FI
-ENDFOR
-	</operation>
-	<instruction form="mm, mm" name="PSIGND" xed="PSIGND_MMXq_MMXq" />
-	<CPUID>SSSE3</CPUID>
-	<header>tmmintrin.h</header>
-	<category>Arithmetic</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_rdtsc" tech="Other">
-	<return etype="UI64" type="__int64" varname="dst" />
-	<parameter type="void" />
-	<description>Copy the current 64-bit value of the processor's time-stamp counter into "dst".</description>
-	<operation>dst[63:0] := TimeStampCounter
-	</operation>
-	<instruction name="RDTSC" xed="RDTSC" />
-	<CPUID>TSC</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_xsusldtrk" tech="Other">
-	<return type="void" />
-	<description>Mark the start of a TSX (HLE/RTM) suspend load address tracking region. If this is used inside a transactional region, subsequent loads are not added to the read set of the transaction. If this is used inside a suspend load address tracking region it will cause transaction abort. If this is used outside of a transactional region it behaves like a NOP.</description>
-	<instruction name="XSUSLDTRK" xed="XSUSLDTRK" />
-	<CPUID>TSXLDTRK</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_xresldtrk" tech="Other">
-	<return type="void" />
-	<description>Mark the end of a TSX (HLE/RTM) suspend load address tracking region. If this is used inside a suspend load address tracking region it will end the suspend region and all following load addresses will be added to the transaction read set. If this is used inside an active transaction but not in a suspend region it will cause transaction abort. If this is used outside of a transactional region it behaves like a NOP.</description>
-	<instruction name="XRESLDTRK" xed="XRESLDTRK" />
-	<CPUID>TSXLDTRK</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_clui" tech="Other">
-		<return type="void" />
-		<parameter type="void" />
-		<description>Clear the user interrupt flag (UIF).</description>
-		<instruction name="CLUI" xed="CLUI" />
-	<CPUID>UINTR</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_senduipi" tech="Other">
-		<return type="void" />
-		<parameter type="unsigned __int64" varname="__a" etype="UI64" />
-		<description>Send user interprocessor interrupts specified in unsigned 64-bit integer "__a".</description>
-		<instruction name="SENDUIPI" form="r32" xed="SENDUIPI_GPR32u32" />
-	<CPUID>UINTR</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_stui" tech="Other">
-		<return type="void" />
-		<parameter type="void" />
-		<description>Sets the user interrupt flag (UIF).</description>
-		<instruction name="STUI" xed="STUI" />
-	<CPUID>UINTR</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	<intrinsic name="_testui" tech="Other">
-		<return type="unsigned char" varname="dst" etype="UI8" />
-		<parameter type="void" />
-		<description>Store the current user interrupt flag (UIF) in unsigned 8-bit integer "dst".</description>
-		<instruction name="TESTUI" xed="TESTUI" />
-	<CPUID>UINTR</CPUID>
-	<header>immintrin.h</header>
-	<category>General Support</category>
-	</intrinsic>
-	
-<intrinsic name="_urdmsr" tech="Other">
-	<return type="unsigned __int64" etype="UI64"/>
-	<parameter type="unsigned __int64" varname="__A" etype="UI64" />
-	<description>Reads the contents of a 64-bit MSR specified in "__A" into "dst".</description>
-	<operation>DEST := MSR[__A]
-	</operation>
-	<instruction name="URDMSR" form="r64 r64" xed="URDMSR_GPR64u64_GPR64u64" />
-	<CPUID>USER_MSR</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>General Support</category>
-</intrinsic>
-<intrinsic name="_uwrmsr" tech="Other">
-	<return type="void"/>
-	<parameter type="unsigned __int64" varname="__A" etype="UI64" />
-	<parameter type="unsigned __int64" varname="__B" etype="UI64" />
-	<description>Writes the contents of "__B" into the 64-bit MSR specified in "__A".</description>
-	<operation>MSR[__A] := __B
-	</operation>
-	<instruction name="UWRMSR" form="r64 r64" xed="UWRMSR_GPR64u64_GPR64u64" />
-	<CPUID>USER_MSR</CPUID>
-	<header>x86gprintrin.h</header>
-	<category>General Support</category>
-</intrinsic>
-<intrinsic name="_mm256_aesenclast_epi128" tech="Other">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="M128" type="__m256i" varname="RoundKey" />
-	<description>Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
-	<operation>FOR j := 0 to 1
-	i := j*128
-	a[i+127:i] := ShiftRows(a[i+127:i])
-	a[i+127:i] := SubBytes(a[i+127:i])
-	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VAESENCLAST" xed="VAESENCLAST_YMMu128_YMMu128_YMMu128" />
-	<CPUID>VAES</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm256_aesenc_epi128" tech="Other">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="M128" type="__m256i" varname="RoundKey" />
-	<description>Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"."</description>
-	<operation>FOR j := 0 to 1
-	i := j*128
-	a[i+127:i] := ShiftRows(a[i+127:i])
-	a[i+127:i] := SubBytes(a[i+127:i])
-	a[i+127:i] := MixColumns(a[i+127:i])
-	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VAESENC" xed="VAESENC_YMMu128_YMMu128_YMMu128" />
-	<CPUID>VAES</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm256_aesdeclast_epi128" tech="Other">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="M128" type="__m256i" varname="RoundKey" />
-	<description>Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*128
-	a[i+127:i] := InvShiftRows(a[i+127:i])
-	a[i+127:i] := InvSubBytes(a[i+127:i])
-	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VAESDECLAST" xed="VAESDECLAST_YMMu128_YMMu128_YMMu128" />
-	<CPUID>VAES</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	<intrinsic name="_mm256_aesdec_epi128" tech="Other">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="a" />
-	<parameter etype="M128" type="__m256i" varname="RoundKey" />
-	<description>Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst".</description>
-	<operation>FOR j := 0 to 1
-	i := j*128
-	a[i+127:i] := InvShiftRows(a[i+127:i])
-	a[i+127:i] := InvSubBytes(a[i+127:i])
-	a[i+127:i] := InvMixColumns(a[i+127:i])
-	dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i]
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm" name="VAESDEC" xed="VAESDEC_YMMu128_YMMu128_YMMu128" />
-	<CPUID>VAES</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Cryptography</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm256_clmulepi64_epi128" tech="Other">
-	<return etype="M128" type="__m256i" varname="dst" />
-	<parameter etype="M128" type="__m256i" varname="b" />
-	<parameter etype="M128" type="__m256i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="Imm8" />
-	<description>Carry-less multiplication of one quadword of
-		'b' by one quadword of 'c', stores
-		the 128-bit result in 'dst'. The immediate 'Imm8' is
-		used to determine which quadwords of 'b'
-		and 'c' should be used.</description>
-	<operation>
-DEFINE PCLMUL128(X,Y) {
-	FOR i := 0 to 63
-		TMP[i] := X[ 0 ] and Y[ i ]
-		FOR j := 1 to i
-			TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ])
-		ENDFOR
-		DEST[ i ] := TMP[ i ]
-	ENDFOR
-	FOR i := 64 to 126
-		TMP[i] := 0
-		FOR j := i - 63 to 63
-			TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ])
-		ENDFOR
-		DEST[ i ] := TMP[ i ]
-	ENDFOR
-	DEST[127] := 0
-	RETURN DEST // 128b vector
-}
-FOR i := 0 to 1
-	IF Imm8[0] == 0
-		TEMP1 := b.m128[i].qword[0]
-	ELSE
-		TEMP1 := b.m128[i].qword[1]
-	FI
-	IF Imm8[4] == 0
-		TEMP2 := c.m128[i].qword[0]
-	ELSE
-		TEMP2 := c.m128[i].qword[1]
-	FI
-	dst.m128[i] := PCLMUL128(TEMP1, TEMP2)
-ENDFOR
-dst[MAX:256] := 0
-	</operation>
-	<instruction form="ymm, ymm, ymm, imm8" name="VPCLMULQDQ" xed="VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512" />
-	<CPUID>VPCLMULQDQ</CPUID>
-	<CPUID>AVX512VL</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_mm512_clmulepi64_epi128" tech="Other">
-	<return etype="M128" type="__m512i" varname="dst" />
-	<parameter etype="M128" type="__m512i" varname="b" />
-	<parameter etype="M128" type="__m512i" varname="c" />
-	<parameter etype="IMM" immwidth="8" type="const int" varname="Imm8" />
-	<description>Carry-less multiplication of one quadword of
-		'b' by one quadword of 'c', stores
-		the 128-bit result in 'dst'. The immediate 'Imm8' is
-		used to determine which quadwords of 'b'
-		and 'c' should be used.</description>
-	<operation>
-DEFINE PCLMUL128(X,Y) {
-	FOR i := 0 to 63
-		TMP[i] := X[ 0 ] and Y[ i ]
-		FOR j := 1 to i
-			TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ])
-		ENDFOR
-		DEST[ i ] := TMP[ i ]
-	ENDFOR
-	FOR i := 64 to 126
-		TMP[i] := 0
-		FOR j := i - 63 to 63
-			TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ])
-		ENDFOR
-		DEST[ i ] := TMP[ i ]
-	ENDFOR
-	DEST[127] := 0
-	RETURN DEST // 128b vector
-}
-FOR i := 0 to 3
-	IF Imm8[0] == 0
-		TEMP1 := b.m128[i].qword[0]
-	ELSE
-		TEMP1 := b.m128[i].qword[1]
-	FI
-	IF Imm8[4] == 0
-		TEMP2 := c.m128[i].qword[0]
-	ELSE
-		TEMP2 := c.m128[i].qword[1]
-	FI
-	dst.m128[i] := PCLMUL128(TEMP1, TEMP2)
-ENDFOR
-dst[MAX:512] := 0
-	</operation>
-	<instruction form="zmm, zmm, zmm, imm8" name="VPCLMULQDQ" xed="VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512" />
-	<CPUID>VPCLMULQDQ</CPUID>
-	<header>immintrin.h</header>
-	<category>Application-Targeted</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_tpause" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="ctrl" />
-	<parameter etype="UI64" type="unsigned __int64" varname="counter" />
-	<description>Directs the processor to enter an implementation-dependent optimized state until the TSC reaches or exceeds the value specified in "counter". Bit 0 of "ctrl" selects between a lower power (cleared) or faster wakeup (set) optimized state. Returns the carry flag (CF). If the processor that executed a UMWAIT instruction wakes due to the expiration of the operating system timelimit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.</description>
-	<instruction form="r32" name="TPAUSE" xed="TPAUSE_GPR32u32" />
-	<CPUID>WAITPKG</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_umwait" tech="Other">
-	<return etype="UI8" type="unsigned char" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="ctrl" />
-	<parameter etype="UI64" type="unsigned __int64" varname="counter" />
-	<description>Directs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The instruction wakes up when the TSC reaches or exceeds the value specified in "counter" (if the monitoring hardware did not trigger beforehand). Bit 0 of "ctrl" selects between a lower power (cleared) or faster wakeup (set) optimized state. Returns the carry flag (CF). If the processor that executed a UMWAIT instruction wakes due to the expiration of the operating system timelimit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.</description>
-	<instruction form="r32" name="UMWAIT" xed="UMWAIT_GPR32" />
-	<CPUID>WAITPKG</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	<intrinsic name="_umonitor" tech="Other">
-	<return type="void" />
-	<parameter type="void*" varname="a" />
-	<description>Sets up a linear address range to be
-		monitored by hardware and activates the
-		monitor. The address range should be a writeback
-		memory caching type. The address is
-		contained in "a".</description>
-	<instruction form="r16/r32/r64" name="UMONITOR" xed="UMONITOR_GPRa" />
-	<CPUID>WAITPKG</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_wbnoinvd" tech="Other">
-	<return type="void" />
-	<parameter type="void" />
-	<description>Write back and do not flush internal caches.
-		Initiate writing-back without flushing of external
-		caches.</description>
-	<instruction name="WBNOINVD" xed="WBNOINVD" />
-	<CPUID>WBNOINVD</CPUID>
-	<header>immintrin.h</header>
-	<category>Miscellaneous</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_xsavec" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
-	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsavec differs from xsave in that it uses compaction and that it may use init optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
-FOR i := 0 to 62
-	IF mask[i]
-		CASE (i) OF
-		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
-		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
-		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
-		ESAC
-		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XSAVEC" xed="XSAVEC_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<CPUID>XSAVEC</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xsavec64" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
-	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsavec differs from xsave in that it uses compaction and that it may use init optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
-FOR i := 0 to 62
-	IF mask[i]
-		CASE (i) OF
-		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
-		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
-		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
-		ESAC
-		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XSAVEC64" xed="XSAVEC64_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<CPUID>XSAVEC</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_xsaveopt" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
-	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. The hardware may optimize the manner in which data is saved. The performance of this instruction will be equal to or better than using the XSAVE instruction.</description>
-	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
-FOR i := 0 to 62
-	IF mask[i]
-		CASE (i) OF
-		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
-		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
-		2: mem_addr.EXT_SAVE_Area2[YMM] := ProcessorState[YMM]
-		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
-		ESAC
-		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XSAVEOPT" xed="XSAVEOPT_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<CPUID>XSAVEOPT</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xsaveopt64" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
-	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. The hardware may optimize the manner in which data is saved. The performance of this instruction will be equal to or better than using the XSAVE64 instruction.</description>
-	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
-FOR i := 0 to 62
-	IF mask[i]
-		CASE (i) OF
-		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
-		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
-		2: mem_addr.EXT_SAVE_Area2[YMM] := ProcessorState[YMM]
-		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
-		ESAC
-		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XSAVEOPT64" xed="XSAVEOPT64_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<CPUID>XSAVEOPT</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_xsaves" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
-	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsaves differs from xsave in that it can save state components corresponding to bits set in IA32_XSS MSR and that it may use the modified optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
-FOR i := 0 to 62
-	IF mask[i]
-		CASE (i) OF
-		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
-		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
-		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
-		ESAC
-		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XSAVES" xed="XSAVES_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<CPUID>XSS</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xsaves64" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
-	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsaves differs from xsave in that it can save state components corresponding to bits set in IA32_XSS MSR and that it may use the modified optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
-FOR i := 0 to 62
-	IF mask[i]
-		CASE (i) OF
-		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
-		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
-		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
-		ESAC
-		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XSAVEC64" xed="XSAVEC64_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<CPUID>XSS</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xrstors" tech="Other">
-	<return type="void" />
-	<parameter type="const void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="rs_mask" />
-	<description>Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". xrstors differs from xrstor in that it can restore state components corresponding to bits set in the IA32_XSS MSR; xrstors cannot restore from an xsave area in which the extended region is in the standard form. State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
-FOR i := 0 to 62
-	IF (rs_mask[i] AND XCR0[i])
-		IF st_mask[i]
-			CASE (i) OF
-			0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
-			1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
-			DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
-			ESAC
-		ELSE
-			// ProcessorExtendedState := Processor Supplied Values
-			CASE (i) OF
-			1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
-			ESAC
-		FI
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XRSTORS" xed="XRSTORS_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<CPUID>XSS</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xrstors64" tech="Other">
-	<return type="void" />
-	<parameter type="const void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="rs_mask" />
-	<description>Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". xrstors differs from xrstor in that it can restore state components corresponding to bits set in the IA32_XSS MSR; xrstors cannot restore from an xsave area in which the extended region is in the standard form. State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
-FOR i := 0 to 62
-	IF (rs_mask[i] AND XCR0[i])
-		IF st_mask[i]
-			CASE (i) OF
-			0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
-			1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
-			DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
-			ESAC
-		ELSE
-			// ProcessorExtendedState := Processor Supplied Values
-			CASE (i) OF
-			1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
-			ESAC
-		FI
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XRSTORS64" xed="XRSTORS64_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<CPUID>XSS</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	
-	
-<intrinsic name="_xgetbv" tech="Other">
-	<return etype="UI64" type="unsigned __int64" varname="dst" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<description>Copy up to 64-bits from the value of the extended control register (XCR) specified by "a" into "dst". Currently only XFEATURE_ENABLED_MASK XCR is supported.</description>
-	<operation>dst[63:0] := XCR[a]
-	</operation>
-	<instruction name="XGETBV" xed="XGETBV" />
-	<CPUID>XSAVE</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xrstor" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="rs_mask" />
-	<description>Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
-FOR i := 0 to 62
-	IF (rs_mask[i] AND XCR0[i])
-		IF st_mask[i]
-			CASE (i) OF
-			0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
-			1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
-			DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
-			ESAC
-		ELSE
-			// ProcessorExtendedState := Processor Supplied Values
-			CASE (i) OF
-			1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
-			ESAC
-		FI
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XRSTOR" xed="XRSTOR_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xrstor64" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="rs_mask" />
-	<description>Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>st_mask := mem_addr.HEADER.XSTATE_BV[62:0]
-FOR i := 0 to 62
-	IF (rs_mask[i] AND XCR0[i])
-		IF st_mask[i]
-			CASE (i) OF
-			0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU]
-			1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE]
-			DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i]
-			ESAC
-		ELSE
-			// ProcessorExtendedState := Processor Supplied Values
-			CASE (i) OF
-			1: MXCSR := mem_addr.FPUSSESave_Area[SSE]
-			ESAC
-		FI
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XRSTOR64" xed="XRSTOR64_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xsave" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
-	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
-FOR i := 0 to 62
-	IF mask[i]
-		CASE (i) OF
-		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
-		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
-		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
-		ESAC
-		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XSAVE" xed="XSAVE_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xsave64" tech="Other">
-	<return type="void" />
-	<parameter type="void *" varname="mem_addr" />
-	<parameter etype="UI64" type="unsigned __int64" varname="save_mask" />
-	<description>Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary.</description>
-	<operation>mask[62:0] := save_mask[62:0] AND XCR0[62:0]
-FOR i := 0 to 62
-	IF mask[i]
-		CASE (i) OF
-		0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU]
-		1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE]
-		DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i]
-		ESAC
-		mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i]
-	FI
-	i := i + 1
-ENDFOR
-	</operation>
-	<instruction form="m8" name="XSAVE64" xed="XSAVE64_MEMmxsave" />
-	<CPUID>XSAVE</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	<intrinsic name="_xsetbv" tech="Other">
-	<return type="void" />
-	<parameter etype="UI32" type="unsigned int" varname="a" />
-	<parameter etype="UI64" type="unsigned __int64" varname="val" />
-	<description>Copy 64-bits from "val" to the extended control register (XCR) specified by "a". Currently only XFEATURE_ENABLED_MASK XCR is supported.</description>
-	<operation>
-XCR[a] := val[63:0]
-	</operation>
-	<instruction name="XSETBV" xed="XSETBV" />
-	<CPUID>XSAVE</CPUID>
-	<header>immintrin.h</header>
-	<category>OS-Targeted</category>
-	</intrinsic>
-	
-	
-</intrinsics_list>
\ No newline at end of file

From 11375b9eab3beafc217c7a642f7a2924bb379fd6 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 15 Oct 2025 14:33:21 +0530
Subject: [PATCH 67/73] chore: move from random testing to testing only the
 first N intrinsics

---
 Cargo.lock                           | 77 +++-------------------------
 crates/intrinsic-test/Cargo.toml     |  1 -
 crates/intrinsic-test/src/x86/mod.rs | 10 +---
 3 files changed, 9 insertions(+), 79 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index e198e14ffe..70f09adf2c 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -282,18 +282,6 @@ dependencies = [
  "wasi",
 ]
 
-[[package]]
-name = "getrandom"
-version = "0.3.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "899def5c37c4fd7b2664648c28120ecec138e4d395b459e5ca34f9cce2dd77fd"
-dependencies = [
- "cfg-if",
- "libc",
- "r-efi",
- "wasip2",
-]
-
 [[package]]
 name = "hashbrown"
 version = "0.12.3"
@@ -360,7 +348,6 @@ dependencies = [
  "log",
  "pretty_env_logger",
  "quick-xml 0.37.5",
- "rand 0.9.2",
  "rayon",
  "regex",
  "serde",
@@ -486,7 +473,7 @@ checksum = "588f6378e4dd99458b60ec275b4477add41ce4fa9f64dcba6f15adccb19b50d6"
 dependencies = [
  "env_logger 0.8.4",
  "log",
- "rand 0.8.5",
+ "rand",
 ]
 
 [[package]]
@@ -498,12 +485,6 @@ dependencies = [
  "proc-macro2",
 ]
 
-[[package]]
-name = "r-efi"
-version = "5.3.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f"
-
 [[package]]
 name = "rand"
 version = "0.8.5"
@@ -511,18 +492,8 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "34af8d1a0e25924bc5b7c43c079c942339d8f0a8b57c39049bef581b46327404"
 dependencies = [
  "libc",
- "rand_chacha 0.3.1",
- "rand_core 0.6.4",
-]
-
-[[package]]
-name = "rand"
-version = "0.9.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6db2770f06117d490610c7488547d543617b21bfa07796d7a12f6f1bd53850d1"
-dependencies = [
- "rand_chacha 0.9.0",
- "rand_core 0.9.3",
+ "rand_chacha",
+ "rand_core",
 ]
 
 [[package]]
@@ -532,17 +503,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "e6c10a63a0fa32252be49d21e7709d4d4baf8d231c2dbce1eaa8141b9b127d88"
 dependencies = [
  "ppv-lite86",
- "rand_core 0.6.4",
-]
-
-[[package]]
-name = "rand_chacha"
-version = "0.9.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d3022b5f1df60f26e1ffddd6c66e8aa15de382ae63b3a0c1bfc0e4d3e3f325cb"
-dependencies = [
- "ppv-lite86",
- "rand_core 0.9.3",
+ "rand_core",
 ]
 
 [[package]]
@@ -551,16 +512,7 @@ version = "0.6.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c"
 dependencies = [
- "getrandom 0.2.16",
-]
-
-[[package]]
-name = "rand_core"
-version = "0.9.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "99d9a13982dcf210057a8a78572b2217b667c3beacbf3a0d8b454f6f82837d38"
-dependencies = [
- "getrandom 0.3.4",
+ "getrandom",
 ]
 
 [[package]]
@@ -751,7 +703,7 @@ dependencies = [
 name = "stdarch-gen-loongarch"
 version = "0.1.0"
 dependencies = [
- "rand 0.8.5",
+ "rand",
 ]
 
 [[package]]
@@ -784,7 +736,7 @@ version = "0.0.0"
 dependencies = [
  "core_arch",
  "quickcheck",
- "rand 0.8.5",
+ "rand",
 ]
 
 [[package]]
@@ -867,15 +819,6 @@ version = "0.11.1+wasi-snapshot-preview1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b"
 
-[[package]]
-name = "wasip2"
-version = "1.0.1+wasi-0.2.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0562428422c63773dad2c345a1882263bbf4d65cf3f42e90921f787ef5ad58e7"
-dependencies = [
- "wit-bindgen",
-]
-
 [[package]]
 name = "wasmparser"
 version = "0.235.0"
@@ -1060,12 +1003,6 @@ version = "0.53.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486"
 
-[[package]]
-name = "wit-bindgen"
-version = "0.46.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f17a85883d4e6d00e8a97c586de764dabcc06133f7f1d55dce5cdc070ad7fe59"
-
 [[package]]
 name = "xml-rs"
 version = "0.8.27"
diff --git a/crates/intrinsic-test/Cargo.toml b/crates/intrinsic-test/Cargo.toml
index 9fb70f32f8..2c0f53897e 100644
--- a/crates/intrinsic-test/Cargo.toml
+++ b/crates/intrinsic-test/Cargo.toml
@@ -22,4 +22,3 @@ itertools = "0.14.0"
 quick-xml = { version = "0.37.5", features = ["serialize", "overlapped-lists"] }
 serde-xml-rs = "0.8.0"
 regex = "1.11.1"
-rand = "0.9.2"
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index ca5748e5fb..a28c8647fe 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -12,8 +12,6 @@ use crate::common::intrinsic::Intrinsic;
 use crate::common::intrinsic_helpers::TypeKind;
 use intrinsic::X86IntrinsicType;
 use itertools::Itertools;
-use rand::rng;
-use rand::seq::IndexedRandom;
 use xml_parser::get_xml_intrinsics;
 
 pub struct X86ArchitectureTest {
@@ -49,10 +47,9 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
         let intrinsics =
             get_xml_intrinsics(&cli_options.filename).expect("Error parsing input file");
 
-        let mut rng = rng();
         let sample_percentage: usize = cli_options.sample_percentage as usize;
 
-        let intrinsics = intrinsics
+        let mut intrinsics = intrinsics
             .into_iter()
             // Not sure how we would compare intrinsic that returns void.
             .filter(|i| i.results.kind() != TypeKind::Void)
@@ -68,10 +65,7 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
             .collect::<Vec<_>>();
 
         let sample_size = (intrinsics.len() * sample_percentage) / 100;
-        let mut intrinsics = intrinsics
-            .choose_multiple(&mut rng, sample_size)
-            .cloned()
-            .collect::<Vec<_>>();
+        intrinsics.truncate(sample_size);
 
         intrinsics.sort_by(|a, b| a.name.cmp(&b.name));
         Self {

From 2ecda3bdc1773d88a3b3e4f56ec973c4eadb6ca8 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 15 Oct 2025 15:04:04 +0530
Subject: [PATCH 68/73] chore: convert println! logging to trace! logging
 during compilation step

---
 crates/intrinsic-test/src/common/mod.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/crates/intrinsic-test/src/common/mod.rs b/crates/intrinsic-test/src/common/mod.rs
index 86a7876807..d8f06ae238 100644
--- a/crates/intrinsic-test/src/common/mod.rs
+++ b/crates/intrinsic-test/src/common/mod.rs
@@ -76,12 +76,12 @@ pub trait SupportedArchitectureTest {
                 //
                 // This is done because `cpp_compiler_wrapped` is None when
                 // the --generate-only flag is passed
-                println!("compiling mod_{i}.cpp");
+                trace!("compiling mod_{i}.cpp");
                 if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
                     let compile_output = cpp_compiler
                         .compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"));
 
-                    println!("finished compiling mod_{i}.cpp");
+                    trace!("finished compiling mod_{i}.cpp");
                     if let Err(compile_error) = compile_output {
                         return Err(format!("Error compiling mod_{i}.cpp: {compile_error:?}"));
                     }
@@ -104,7 +104,7 @@ pub trait SupportedArchitectureTest {
         // the --generate-only flag is passed
         if let Some(cpp_compiler) = cpp_compiler_wrapped.as_ref() {
             // compile this cpp file into a .o file
-            info!("compiling main.cpp");
+            trace!("compiling main.cpp");
             let output = cpp_compiler
                 .compile_object_file("main.cpp", "intrinsic-test-programs.o")
                 .unwrap();

From 106b510c767b70e610d4175ee180eabe6e1f5ebb Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Wed, 15 Oct 2025 20:54:11 +0530
Subject: [PATCH 69/73] feat: code cleanup 1. changing array bracket prefixes
 from &'static str to char 2. including variable names in template strings
 instead of passing them as arguments to macros

---
 crates/intrinsic-test/src/arm/types.rs        | 14 +++++-----
 crates/intrinsic-test/src/common/argument.rs  |  2 +-
 .../src/common/intrinsic_helpers.rs           | 28 +++++++++----------
 crates/intrinsic-test/src/x86/config.rs       |  2 +-
 crates/intrinsic-test/src/x86/types.rs        |  4 +--
 5 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/types.rs b/crates/intrinsic-test/src/arm/types.rs
index c798cbe42d..4be8d1e48b 100644
--- a/crates/intrinsic-test/src/arm/types.rs
+++ b/crates/intrinsic-test/src/arm/types.rs
@@ -14,10 +14,10 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
                 (None, None) => format!("{const_prefix}{prefix}{bit_len}_t"),
                 (Some(simd), None) => format!("{prefix}{bit_len}x{simd}_t"),
                 (Some(simd), Some(vec)) => format!("{prefix}{bit_len}x{simd}x{vec}_t"),
-                (None, Some(_)) => todo!("{:#?}", self), // Likely an invalid case
+                (None, Some(_)) => todo!("{self:#?}"), // Likely an invalid case
             }
         } else {
-            todo!("{:#?}", self)
+            todo!("{self:#?}")
         }
     }
 
@@ -58,14 +58,14 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
                     // The ACLE doesn't support 64-bit polynomial loads on Armv7
                     // if armv7 and bl == 64, use "s", else "p"
                     TypeKind::Poly => if choose_workaround && *bl == 64 {"s"} else {"p"},
-                    x => todo!("get_load_function TypeKind: {:#?}", x),
+                    x => todo!("get_load_function TypeKind: {x:#?}"),
                 },
                 size = bl,
                 quad = quad,
                 len = vec_len.unwrap_or(1),
             )
         } else {
-            todo!("get_load_function IntrinsicType: {:#?}", self)
+            todo!("get_load_function IntrinsicType: {self:#?}")
         }
     }
 
@@ -90,13 +90,13 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
                     TypeKind::Int(Sign::Signed) => "s",
                     TypeKind::Float => "f",
                     TypeKind::Poly => "p",
-                    x => todo!("get_load_function TypeKind: {:#?}", x),
+                    x => todo!("get_load_function TypeKind: {x:#?}"),
                 },
                 size = bl,
                 quad = quad,
             )
         } else {
-            todo!("get_lane_function IntrinsicType: {:#?}", self)
+            todo!("get_lane_function IntrinsicType: {self:#?}")
         }
     }
 
@@ -143,7 +143,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
                     TypeKind::Int(Sign::Signed) => format!("int{}_t", self.inner_size()),
                     TypeKind::Int(Sign::Unsigned) => format!("uint{}_t", self.inner_size()),
                     TypeKind::Poly => format!("poly{}_t", self.inner_size()),
-                    ty => todo!("print_result_c - Unknown type: {:#?}", ty),
+                    ty => todo!("print_result_c - Unknown type: {ty:#?}"),
                 },
                 promote = self.generate_final_type_cast(),
             )
diff --git a/crates/intrinsic-test/src/common/argument.rs b/crates/intrinsic-test/src/common/argument.rs
index 5963abef2f..5fb7d0f210 100644
--- a/crates/intrinsic-test/src/common/argument.rs
+++ b/crates/intrinsic-test/src/common/argument.rs
@@ -31,7 +31,7 @@ where
 
     pub fn to_c_type(&self) -> String {
         let prefix = if self.ty.constant { "const " } else { "" };
-        format!("{}{}", prefix, self.ty.c_type())
+        format!("{prefix}{}", self.ty.c_type())
     }
 
     pub fn generate_name(&self) -> String {
diff --git a/crates/intrinsic-test/src/common/intrinsic_helpers.rs b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
index aa8613206e..c2d66868ce 100644
--- a/crates/intrinsic-test/src/common/intrinsic_helpers.rs
+++ b/crates/intrinsic-test/src/common/intrinsic_helpers.rs
@@ -80,7 +80,7 @@ impl TypeKind {
             Self::Poly => "poly",
             Self::Char(Sign::Signed) => "char",
             Self::Vector => "int",
-            _ => unreachable!("Not used: {:#?}", self),
+            _ => unreachable!("Not used: {self:#?}"),
         }
     }
 
@@ -94,7 +94,7 @@ impl TypeKind {
             Self::Poly => "u",
             Self::Char(Sign::Unsigned) => "u",
             Self::Char(Sign::Signed) => "i",
-            _ => unreachable!("Unused type kind: {:#?}", self),
+            _ => unreachable!("Unused type kind: {self:#?}"),
         }
     }
 }
@@ -134,7 +134,7 @@ impl IntrinsicType {
         if let Some(bl) = self.bit_len {
             cmp::max(bl, 8)
         } else {
-            unreachable!("{:#?}", self)
+            unreachable!("{self:#?}")
         }
     }
 
@@ -225,8 +225,8 @@ impl IntrinsicType {
                 ..
             } => {
                 let (prefix, suffix) = match language {
-                    Language::Rust => ("[", "]"),
-                    Language::C => ("{", "}"),
+                    Language::Rust => ('[', ']'),
+                    Language::C => ('{', '}'),
                 };
                 let body_indentation = indentation.nested();
                 format!(
@@ -262,12 +262,12 @@ impl IntrinsicType {
                 ..
             } => {
                 let (prefix, cast_prefix, cast_suffix, suffix) = match (language, bit_len) {
-                    (&Language::Rust, 16) => ("[", "f16::from_bits(", ")", "]"),
-                    (&Language::Rust, 32) => ("[", "f32::from_bits(", ")", "]"),
-                    (&Language::Rust, 64) => ("[", "f64::from_bits(", ")", "]"),
-                    (&Language::C, 16) => ("{", "cast<float16_t, uint16_t>(", ")", "}"),
-                    (&Language::C, 32) => ("{", "cast<float, uint32_t>(", ")", "}"),
-                    (&Language::C, 64) => ("{", "cast<double, uint64_t>(", ")", "}"),
+                    (&Language::Rust, 16) => ('[', "f16::from_bits(", ")", ']'),
+                    (&Language::Rust, 32) => ('[', "f32::from_bits(", ")", ']'),
+                    (&Language::Rust, 64) => ('[', "f64::from_bits(", ")", ']'),
+                    (&Language::C, 16) => ('{', "cast<float16_t, uint16_t>(", ")", '}'),
+                    (&Language::C, 32) => ('{', "cast<float, uint32_t>(", ")", '}'),
+                    (&Language::C, 64) => ('{', "cast<double, uint64_t>(", ")", '}'),
                     _ => unreachable!(),
                 };
                 format!(
@@ -288,8 +288,8 @@ impl IntrinsicType {
                 ..
             } => {
                 let (prefix, suffix) = match language {
-                    Language::Rust => ("[", "]"),
-                    Language::C => ("{", "}"),
+                    Language::Rust => ('[', ']'),
+                    Language::C => ('{', '}'),
                 };
                 let body_indentation = indentation.nested();
                 let effective_bit_len = 32;
@@ -317,7 +317,7 @@ impl IntrinsicType {
                         })
                 )
             }
-            _ => unimplemented!("populate random: {:#?}", self),
+            _ => unimplemented!("populate random: {self:#?}"),
         }
     }
 
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 6be3f1b133..6d913acca7 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -213,7 +213,7 @@ trait DebugAs<T> {
 
 impl<T: core::fmt::Display> DebugAs<T> for T {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "{}", self)
+        write!(f, "{self}")
     }
 }
 
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index cdfc6bfa98..be15b6dccd 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -219,11 +219,11 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
                     TypeKind::Float if self.inner_size() == 32 => "float".to_string(),
                     TypeKind::Mask => format!(
                         "__mmask{}",
-                        self.bit_len.expect(format!("self: {:#?}", self).as_str())
+                        self.bit_len.expect(format!("self: {self:#?}").as_str())
                     ),
                     TypeKind::Vector => format!(
                         "__m{}i",
-                        self.bit_len.expect(format!("self: {:#?}", self).as_str())
+                        self.bit_len.expect(format!("self: {self:#?}").as_str())
                     ),
                     _ => self.c_scalar_type(),
                 },

From 19a6292a44aad22987e30c0d999e4bbfdcabb2bf Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 16 Oct 2025 09:47:17 +0530
Subject: [PATCH 70/73] chore: make names in config.rs files uniform across
 architectures

---
 crates/intrinsic-test/src/arm/config.rs | 8 ++++----
 crates/intrinsic-test/src/arm/mod.rs    | 8 ++++----
 crates/intrinsic-test/src/x86/config.rs | 4 ++--
 crates/intrinsic-test/src/x86/mod.rs    | 4 ++--
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/crates/intrinsic-test/src/arm/config.rs b/crates/intrinsic-test/src/arm/config.rs
index e2bc501127..a634645969 100644
--- a/crates/intrinsic-test/src/arm/config.rs
+++ b/crates/intrinsic-test/src/arm/config.rs
@@ -3,7 +3,7 @@ pub const NOTICE: &str = "\
 // test are derived from a JSON specification, published under the same license as the
 // `intrinsic-test` crate.\n";
 
-pub const POLY128_OSTREAM_DECL: &str = r#"
+pub const PLATFORM_C_FORWARD_DECLARATIONS: &str = r#"
 #ifdef __aarch64__
 std::ostream& operator<<(std::ostream& os, poly128_t value);
 #endif
@@ -20,7 +20,7 @@ template<typename T1, typename T2> T1 cast(T2 x) {
 }
 "#;
 
-pub const POLY128_OSTREAM_DEF: &str = r#"
+pub const PLATFORM_C_DEFINITIONS: &str = r#"
 #ifdef __aarch64__
 std::ostream& operator<<(std::ostream& os, poly128_t value) {
     std::stringstream temp;
@@ -53,7 +53,7 @@ std::ostream& operator<<(std::ostream& os, uint8_t value) {
 "#;
 
 // Format f16 values (and vectors containing them) in a way that is consistent with C.
-pub const F16_FORMATTING_DEF: &str = r#"
+pub const PLATFORM_RUST_DEFINITIONS: &str = r#"
 /// Used to continue `Debug`ging SIMD types as `MySimd(1, 2, 3, 4)`, as they
 /// were before moving to array-based simd.
 #[inline]
@@ -139,7 +139,7 @@ impl DebugHexF16 for float16x8x4_t {
 }
  "#;
 
-pub const AARCH_CONFIGURATIONS: &str = r#"
+pub const PLATFORM_RUST_CFGS: &str = r#"
 #![cfg_attr(target_arch = "arm", feature(stdarch_arm_neon_intrinsics))]
 #![cfg_attr(target_arch = "arm", feature(stdarch_aarch32_crc32))]
 #![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fcma))]
diff --git a/crates/intrinsic-test/src/arm/mod.rs b/crates/intrinsic-test/src/arm/mod.rs
index 08dc2d3870..7fa5062e86 100644
--- a/crates/intrinsic-test/src/arm/mod.rs
+++ b/crates/intrinsic-test/src/arm/mod.rs
@@ -32,11 +32,11 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
     const NOTICE: &str = config::NOTICE;
 
     const PLATFORM_C_HEADERS: &[&str] = &["arm_neon.h", "arm_acle.h", "arm_fp16.h"];
-    const PLATFORM_C_DEFINITIONS: &str = config::POLY128_OSTREAM_DEF;
-    const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::POLY128_OSTREAM_DECL;
+    const PLATFORM_C_DEFINITIONS: &str = config::PLATFORM_C_DEFINITIONS;
+    const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::PLATFORM_C_FORWARD_DECLARATIONS;
 
-    const PLATFORM_RUST_DEFINITIONS: &str = config::F16_FORMATTING_DEF;
-    const PLATFORM_RUST_CFGS: &str = config::AARCH_CONFIGURATIONS;
+    const PLATFORM_RUST_DEFINITIONS: &str = config::PLATFORM_RUST_DEFINITIONS;
+    const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS;
 
     fn cpp_compilation(&self) -> Option<CppCompilation> {
         compile::build_cpp_compilation(&self.cli_options)
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index 6d913acca7..d7770189eb 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -4,7 +4,7 @@ pub const NOTICE: &str = "\
 // `intrinsic-test` crate.\n";
 
 // Format f16 values (and vectors containing them) in a way that is consistent with C.
-pub const F16_FORMATTING_DEF: &str = r#"
+pub const PLATFORM_RUST_DEFINITIONS: &str = r#"
 use std::arch::x86_64::*;
 
 #[inline]
@@ -392,7 +392,7 @@ std::ostream& operator<<(std::ostream& os, __mmask8 value) {
 }
 "#;
 
-pub const X86_CONFIGURATIONS: &str = r#"
+pub const PLATFORM_RUST_CFGS: &str = r#"
 #![cfg_attr(target_arch = "x86", feature(avx))]
 #![cfg_attr(target_arch = "x86", feature(sse))]
 #![cfg_attr(target_arch = "x86", feature(sse2))]
diff --git a/crates/intrinsic-test/src/x86/mod.rs b/crates/intrinsic-test/src/x86/mod.rs
index a28c8647fe..956e51836f 100644
--- a/crates/intrinsic-test/src/x86/mod.rs
+++ b/crates/intrinsic-test/src/x86/mod.rs
@@ -40,8 +40,8 @@ impl SupportedArchitectureTest for X86ArchitectureTest {
     const PLATFORM_C_DEFINITIONS: &str = config::PLATFORM_C_DEFINITIONS;
     const PLATFORM_C_FORWARD_DECLARATIONS: &str = config::PLATFORM_C_FORWARD_DECLARATIONS;
 
-    const PLATFORM_RUST_DEFINITIONS: &str = config::F16_FORMATTING_DEF;
-    const PLATFORM_RUST_CFGS: &str = config::X86_CONFIGURATIONS;
+    const PLATFORM_RUST_DEFINITIONS: &str = config::PLATFORM_RUST_DEFINITIONS;
+    const PLATFORM_RUST_CFGS: &str = config::PLATFORM_RUST_CFGS;
 
     fn create(cli_options: ProcessedCli) -> Self {
         let intrinsics =

From a80eff1a38b62c4f120e45c64e4cd7925fabfb9a Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Fri, 17 Oct 2025 22:26:59 +0530
Subject: [PATCH 71/73] fix: remove the PATH update in ci/run.sh

---
 ci/run.sh                                   | 2 --
 crates/intrinsic-test/src/common/compare.rs | 4 ++--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/ci/run.sh b/ci/run.sh
index bd0e06687f..48dfe2a77d 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -96,8 +96,6 @@ case ${TARGET} in
         TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
         TEST_SAMPLE_INTRINSICS_PERCENTAGE=5
         export STDARCH_DISABLE_ASSERT_INSTR=1
-        PATH="$PATH":"$(pwd)"/c_programs
-        export PATH
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
         cargo_test "${PROFILE}"
diff --git a/crates/intrinsic-test/src/common/compare.rs b/crates/intrinsic-test/src/common/compare.rs
index 89e5f965bc..902df94283 100644
--- a/crates/intrinsic-test/src/common/compare.rs
+++ b/crates/intrinsic-test/src/common/compare.rs
@@ -15,13 +15,13 @@ pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target:
         .par_iter()
         .filter_map(|intrinsic_name| {
             let c = runner_command(runner)
-                .arg("intrinsic-test-programs")
+                .arg("./intrinsic-test-programs")
                 .arg(intrinsic_name)
                 .current_dir("c_programs")
                 .output();
 
             let rust = runner_command(runner)
-                .arg(format!("target/{target}/release/intrinsic-test-programs"))
+                .arg(format!("./target/{target}/release/intrinsic-test-programs"))
                 .arg(intrinsic_name)
                 .current_dir("rust_programs")
                 .output();

From ce179da6118ed81ac938db3ca3ab274606647d2d Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Thu, 23 Oct 2025 10:17:33 +0530
Subject: [PATCH 72/73] feat: fixing Rust's print mechanism for _mm512_conj_pch

---
 crates/intrinsic-test/missing_x86.txt   | 2 +-
 crates/intrinsic-test/src/x86/config.rs | 3 +++
 crates/intrinsic-test/src/x86/types.rs  | 6 ++++++
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/crates/intrinsic-test/missing_x86.txt b/crates/intrinsic-test/missing_x86.txt
index e546799740..58e37b92a1 100644
--- a/crates/intrinsic-test/missing_x86.txt
+++ b/crates/intrinsic-test/missing_x86.txt
@@ -890,7 +890,7 @@ _mm256_extract_epi16
 _mm256_extract_epi8
 _mm512_castsi128_si512
 _mm512_castsi256_si512
-_mm512_conj_pch
+# _mm512_conj_pch
 _mm512_mask_reduce_max_pd
 _mm512_mask_reduce_max_ps
 _mm512_mask_reduce_min_pd
diff --git a/crates/intrinsic-test/src/x86/config.rs b/crates/intrinsic-test/src/x86/config.rs
index d7770189eb..7c349e4482 100644
--- a/crates/intrinsic-test/src/x86/config.rs
+++ b/crates/intrinsic-test/src/x86/config.rs
@@ -235,6 +235,9 @@ macro_rules! impl_debug_as {
 impl_debug_as!(__m128i, "__m128i", 128, [u8, i8, u16, i16, u32, i32, u64, i64]);
 impl_debug_as!(__m256i, "__m256i", 256, [u8, i8, u16, i16, u32, i32, u64, i64]);
 impl_debug_as!(__m512i, "__m512i", 512, [u8, i8, u16, i16, u32, i32, u64, i64]);
+impl_debug_as!(__m128h, "__m128h", 128, [f32]);
+impl_debug_as!(__m256h, "__m256h", 256, [f32]);
+impl_debug_as!(__m512h, "__m512h", 512, [f32]);
 
 fn debug_as<V, T>(x: V) -> impl core::fmt::Debug 
 where V: DebugAs<T>
diff --git a/crates/intrinsic-test/src/x86/types.rs b/crates/intrinsic-test/src/x86/types.rs
index be15b6dccd..87932fcb3e 100644
--- a/crates/intrinsic-test/src/x86/types.rs
+++ b/crates/intrinsic-test/src/x86/types.rs
@@ -290,6 +290,12 @@ impl IntrinsicTypeDefinition for X86IntrinsicType {
     fn print_result_rust(&self) -> String {
         let return_value = match self.kind() {
             TypeKind::Float if self.inner_size() == 16 => "debug_f16(__return_value)".to_string(),
+            TypeKind::Float
+                if self.inner_size() == 32
+                    && ["__m512h"].contains(&self.param.type_data.as_str()) =>
+            {
+                "debug_as::<_, f32>(__return_value)".to_string()
+            }
             TypeKind::Int(_)
                 if ["__m128i", "__m256i", "__m512i"].contains(&self.param.type_data.as_str()) =>
             {

From 41357a0a542d124c9a23064e6a182596a955c8d1 Mon Sep 17 00:00:00 2001
From: Madhav Madhusoodanan <madhavmadhusoodanan@gmail.com>
Date: Sun, 26 Oct 2025 18:19:45 +0530
Subject: [PATCH 73/73] feat: added x86_64-unknown-linux-gnu to the test matrix
 of `intrinsic-test`

---
 .github/workflows/main.yml |  1 +
 ci/intrinsic-test.sh       | 24 ++++++++++++++++++++++++
 ci/run.sh                  |  5 -----
 3 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index b852110a32..28c15cf473 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -260,6 +260,7 @@ jobs:
           - aarch64_be-unknown-linux-gnu
           - armv7-unknown-linux-gnueabihf
           - arm-unknown-linux-gnueabihf
+          - x86_64-unknown-linux-gnu
         profile: [dev, release]
         include:
           - target: aarch64_be-unknown-linux-gnu
diff --git a/ci/intrinsic-test.sh b/ci/intrinsic-test.sh
index 469e9e21c7..e14a824b2a 100755
--- a/ci/intrinsic-test.sh
+++ b/ci/intrinsic-test.sh
@@ -66,6 +66,14 @@ case ${TARGET} in
         TEST_CXX_COMPILER="clang++"
         TEST_RUNNER="${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}"
         ;;
+
+    x86_64-unknown-linux-gnu*)
+        TEST_CPPFLAGS="-fuse-ld=lld -I/usr/include/x86_64-linux-gnu/"
+        TEST_CXX_COMPILER="clang++"
+        TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
+        TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
+        TEST_SAMPLE_INTRINSICS_PERCENTAGE=5
+        ;;
     *)
         ;;
 
@@ -94,6 +102,22 @@ case "${TARGET}" in
             --linker "${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_LINKER}" \
             --cxx-toolchain-dir "${AARCH64_BE_TOOLCHAIN}"
         ;;
+
+    x86_64-unknown-linux-gnu*)
+        # `CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER` is not necessary for `intrinsic-test`
+        # because the binary needs to run directly on the host.
+        # Hence the use of `env -u`.
+        env -u CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER \
+            CPPFLAGS="${TEST_CPPFLAGS}" RUSTFLAGS="${HOST_RUSTFLAGS}" \
+            RUST_LOG=warn RUST_BACKTRACE=1 \
+            cargo run "${INTRINSIC_TEST}" "${PROFILE}"  \
+            --bin intrinsic-test -- intrinsics_data/x86-intel.xml \
+            --runner "${TEST_RUNNER}" \
+            --skip "${TEST_SKIP_INTRINSICS}" \
+            --cppcompiler "${TEST_CXX_COMPILER}" \
+            --target "${TARGET}" \
+            --sample-percentage "${TEST_SAMPLE_INTRINSICS_PERCENTAGE}"
+        ;;
      *)
         ;;
 esac
diff --git a/ci/run.sh b/ci/run.sh
index 48dfe2a77d..2bb77bae25 100755
--- a/ci/run.sh
+++ b/ci/run.sh
@@ -90,11 +90,6 @@ fi
 # Test targets compiled with extra features.
 case ${TARGET} in
     x86_64-unknown-linux-gnu)
-        TEST_CPPFLAGS="-fuse-ld=lld -I/usr/include/x86_64-linux-gnu/"
-        TEST_CXX_COMPILER="clang++"
-        TEST_RUNNER="${CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER}"
-        TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_x86.txt
-        TEST_SAMPLE_INTRINSICS_PERCENTAGE=5
         export STDARCH_DISABLE_ASSERT_INSTR=1
 
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"